HWSVMR0.cpp@ 3197

Last change on this file since 3197 was 3197, checked in by vboxsync, 17 years ago
IO handling updates
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1	/* $Id: HWSVMR0.cpp 3197 2007-06-21 08:19:41Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include "HWSVMR0.h"
45
46	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
47
48	/**
49	* Sets up and activates SVM
50	*
51	* @returns VBox status code.
52	* @param pVM The VM to operate on.
53	*/
54	HWACCMR0DECL(int) SVMR0Setup(PVM pVM)
55	{
56	int rc = VINF_SUCCESS;
57	SVM_VMCB *pVMCB;
58
59	if (pVM == NULL)
60	return VERR_INVALID_PARAMETER;
61
62	/* Setup AMD SVM. */
63	Assert(pVM->hwaccm.s.svm.fSupported);
64
65	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
66	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
67
68	/* Program the control fields. Most of them never have to be changed again. */
69	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
70	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
71	pVMCB->ctrl.u16InterceptRdCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
72
73	/*
74	* CR0/3/4 writes must be intercepted for obvious reasons.
75	*/
76	pVMCB->ctrl.u16InterceptWrCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
77
78	/* Intercept all DRx reads and writes. */
79	pVMCB->ctrl.u16InterceptRdDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
80	pVMCB->ctrl.u16InterceptWrDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
81
82	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
83	* All breakpoints are automatically cleared when the VM exits.
84	*/
85
86	/** @todo nested paging */
87	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
88	* pagefaults that need our attention).
89	*/
90	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
91
92	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
93	\| SVM_CTRL1_INTERCEPT_VINTR
94	\| SVM_CTRL1_INTERCEPT_NMI
95	\| SVM_CTRL1_INTERCEPT_SMI
96	\| SVM_CTRL1_INTERCEPT_INIT
97	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
98	\| SVM_CTRL1_INTERCEPT_RDPMC
99	\| SVM_CTRL1_INTERCEPT_CPUID
100	\| SVM_CTRL1_INTERCEPT_RSM
101	\| SVM_CTRL1_INTERCEPT_HLT
102	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
103	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
104	\| SVM_CTRL1_INTERCEPT_INVLPG
105	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
106	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
107	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
108	;
109	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
110	\| SVM_CTRL2_INTERCEPT_VMMCALL
111	\| SVM_CTRL2_INTERCEPT_VMLOAD
112	\| SVM_CTRL2_INTERCEPT_VMSAVE
113	\| SVM_CTRL2_INTERCEPT_STGI
114	\| SVM_CTRL2_INTERCEPT_CLGI
115	\| SVM_CTRL2_INTERCEPT_SKINIT
116	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
117	;
118	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
119	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
120	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
121
122	/* Virtualize masking of INTR interrupts. */
123	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
124
125	/* Set IO and MSR bitmap addresses. */
126	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
127	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
128
129	/* Enable nested paging. */
130	/** @todo how to detect support for this?? */
131	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
132
133	/* No LBR virtualization. */
134	pVMCB->ctrl.u64LBRVirt = 0;
135
136	return rc;
137	}
138
139
140	/**
141	* Injects an event (trap or external interrupt)
142	*
143	* @param pVM The VM to operate on.
144	* @param pVMCB SVM control block
145	* @param pCtx CPU Context
146	* @param pIntInfo SVM interrupt info
147	*/
148	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
149	{
150	#ifdef VBOX_STRICT
151	if (pEvent->n.u8Vector == 0xE)
152	Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
153	else
154	if (pEvent->n.u8Vector < 0x20)
155	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
156	else
157	{
158	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
159	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
160	Assert(pCtx->eflags.u32 & X86_EFL_IF);
161	}
162	#endif
163
164	/* Set event injection state. */
165	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
166	}
167
168
169	/**
170	* Checks for pending guest interrupts and injects them
171	*
172	* @returns VBox status code.
173	* @param pVM The VM to operate on.
174	* @param pVMCB SVM control block
175	* @param pCtx CPU Context
176	*/
177	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
178	{
179	int rc;
180
181	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
182	if (pVM->hwaccm.s.Event.fPending)
183	{
184	SVM_EVENT Event;
185
186	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
187	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
188	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
189	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
190
191	pVM->hwaccm.s.Event.fPending = false;
192	return VINF_SUCCESS;
193	}
194
195	/* When external interrupts are pending, we should exit the VM when IF is set. */
196	if ( !TRPMHasTrap(pVM)
197	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
198	{
199	if (!(pCtx->eflags.u32 & X86_EFL_IF))
200	{
201	Log2(("Enable irq window exit!\n"));
202	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
203	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
204	//// AssertRC(rc);
205	}
206	else
207	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
208	{
209	uint8_t u8Interrupt;
210
211	rc = PDMGetInterrupt(pVM, &u8Interrupt);
212	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
213	if (VBOX_SUCCESS(rc))
214	{
215	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
216	AssertRC(rc);
217	}
218	else
219	{
220	/* can't happen... */
221	AssertFailed();
222	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
223	return VINF_EM_RAW_INTERRUPT_PENDING;
224	}
225	}
226	else
227	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
228	}
229
230	#ifdef VBOX_STRICT
231	if (TRPMHasTrap(pVM))
232	{
233	uint8_t u8Vector;
234	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
235	AssertRC(rc);
236	}
237	#endif
238
239	if ( pCtx->eflags.u32 & X86_EFL_IF
240	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
241	&& TRPMHasTrap(pVM)
242	)
243	{
244	uint8_t u8Vector;
245	int rc;
246	TRPMEVENT enmType;
247	SVM_EVENT Event;
248	uint32_t u32ErrorCode;
249
250	Event.au64[0] = 0;
251
252	/* If a new event is pending, then dispatch it now. */
253	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
254	AssertRC(rc);
255	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
256	Assert(enmType != TRPM_SOFTWARE_INT);
257
258	/* Clear the pending trap. */
259	rc = TRPMResetTrap(pVM);
260	AssertRC(rc);
261
262	Event.n.u8Vector = u8Vector;
263	Event.n.u1Valid = 1;
264	Event.n.u32ErrorCode = u32ErrorCode;
265
266	if (enmType == TRPM_TRAP)
267	{
268	switch (u8Vector) {
269	case 8:
270	case 10:
271	case 11:
272	case 12:
273	case 13:
274	case 14:
275	case 17:
276	/* Valid error codes. */
277	Event.n.u1ErrorCodeValid = 1;
278	break;
279	default:
280	break;
281	}
282	if (u8Vector == X86_XCPT_NMI)
283	Event.n.u3Type = SVM_EVENT_NMI;
284	else
285	Event.n.u3Type = SVM_EVENT_EXCEPTION;
286	}
287	else
288	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
289
290	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
291	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
292	} /* if (interrupts can be dispatched) */
293
294	return VINF_SUCCESS;
295	}
296
297
298	/**
299	* Loads the guest state
300	*
301	* @returns VBox status code.
302	* @param pVM The VM to operate on.
303	* @param pCtx Guest context
304	*/
305	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
306	{
307	RTGCUINTPTR val;
308	SVM_VMCB *pVMCB;
309
310	if (pVM == NULL)
311	return VERR_INVALID_PARAMETER;
312
313	/* Setup AMD SVM. */
314	Assert(pVM->hwaccm.s.svm.fSupported);
315
316	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
317	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
318
319	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
320	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
321	{
322	SVM_WRITE_SELREG(CS, cs);
323	SVM_WRITE_SELREG(SS, ss);
324	SVM_WRITE_SELREG(DS, ds);
325	SVM_WRITE_SELREG(ES, es);
326	SVM_WRITE_SELREG(FS, fs);
327	SVM_WRITE_SELREG(GS, gs);
328	}
329
330	/* Guest CPU context: LDTR. */
331	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
332	{
333	SVM_WRITE_SELREG(LDTR, ldtr);
334	}
335
336	/* Guest CPU context: TR. */
337	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
338	{
339	SVM_WRITE_SELREG(TR, tr);
340	}
341
342	/* Guest CPU context: GDTR. */
343	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
344	{
345	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
346	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
347	}
348
349	/* Guest CPU context: IDTR. */
350	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
351	{
352	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
353	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
354	}
355
356	/*
357	* Sysenter MSRs
358	*/
359	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
360	{
361	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
362	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
363	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
364	}
365
366	/* Control registers */
367	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
368	{
369	val = pCtx->cr0;
370	if (CPUMIsGuestFPUStateActive(pVM) == false)
371	{
372	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
373	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
374	}
375	else
376	{
377	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
378	/** @todo check if we support the old style mess correctly. */
379	if (!(val & X86_CR0_NE))
380	{
381	Log(("Forcing X86_CR0_NE!!!\n"));
382
383	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
384	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
385	{
386	pVMCB->ctrl.u32InterceptException \|= BIT(16);
387	pVM->hwaccm.s.fFPUOldStyleOverride = true;
388	}
389	}
390	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
391	}
392	if (!(val & X86_CR0_CD))
393	val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
394
395	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
396	pVMCB->guest.u64CR0 = val;
397	}
398	/* CR2 as well */
399	pVMCB->guest.u64CR2 = pCtx->cr2;
400
401	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
402	{
403	/* Save our shadow CR3 register. */
404	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
405	}
406
407	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
408	{
409	val = pCtx->cr4;
410	switch(pVM->hwaccm.s.enmShadowMode)
411	{
412	case PGMMODE_REAL:
413	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
414	AssertFailed();
415	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
416
417	case PGMMODE_32_BIT: /* 32-bit paging. */
418	break;
419
420	case PGMMODE_PAE: /* PAE paging. */
421	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
422	/** @todo use normal 32 bits paging */
423	val \|= X86_CR4_PAE;
424	break;
425
426	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
427	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
428	AssertFailed();
429	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
430
431	default: /* shut up gcc */
432	AssertFailed();
433	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
434	}
435	pVMCB->guest.u64CR4 = val;
436	}
437
438	/* Debug registers. */
439	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
440	{
441	/** @todo DR0-6 */
442	val = pCtx->dr7;
443	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
444	val \|= 0x400; /* must be one */
445	#ifdef VBOX_STRICT
446	val = 0x400;
447	#endif
448	pVMCB->guest.u64DR7 = val;
449
450	pVMCB->guest.u64DR6 = pCtx->dr6;
451	}
452
453	/* EIP, ESP and EFLAGS */
454	pVMCB->guest.u64RIP = pCtx->eip;
455	pVMCB->guest.u64RSP = pCtx->esp;
456	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
457
458	/* Set CPL */
459	pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
460
461	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
462	pVMCB->guest.u64RAX = pCtx->eax;
463
464	/* vmrun will fail otherwise. */
465	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
466
467	/** @note We can do more complex things with tagged TLBs. */
468	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
469
470	/** TSC offset. */
471	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
472	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
473	else
474	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
475
476	/** @todo 64 bits stuff (?):
477	* - STAR
478	* - LSTAR
479	* - CSTAR
480	* - SFMASK
481	* - KernelGSBase
482	*/
483
484	#ifdef DEBUG
485	/* Intercept X86_XCPT_DB if stepping is enabled */
486	if (DBGFIsStepping(pVM))
487	pVMCB->ctrl.u32InterceptException \|= BIT(1);
488	else
489	pVMCB->ctrl.u32InterceptException &= ~BIT(1);
490	#endif
491
492	/* Done. */
493	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
494
495	return VINF_SUCCESS;
496	}
497
498
499	/**
500	* Runs guest code in an SVM VM.
501	*
502	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
503	*
504	* @returns VBox status code.
505	* @param pVM The VM to operate on.
506	* @param pCtx Guest context
507	*/
508	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
509	{
510	int rc = VINF_SUCCESS;
511	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
512	SVM_VMCB *pVMCB;
513	bool fForceTLBFlush = false;
514	bool fGuestStateSynced = false;
515
516	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
517
518	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
519	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
520
521	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
522	*/
523	ResumeExecution:
524
525	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
526	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
527	{
528	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
529	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
530	{
531	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
532	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
533	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
534	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
535	*/
536	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
537	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
538	pVMCB->ctrl.u64IntShadow = 0;
539	}
540	}
541	else
542	{
543	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
544	pVMCB->ctrl.u64IntShadow = 0;
545	}
546
547	/* Check for pending actions that force us to go back to ring 3. */
548	#ifdef DEBUG
549	/* Intercept X86_XCPT_DB if stepping is enabled */
550	if (!DBGFIsStepping(pVM))
551	#endif
552	{
553	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
554	{
555	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
556	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
557	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
558	rc = VINF_EM_RAW_TO_R3;
559	goto end;
560	}
561	}
562
563	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
564	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
565	{
566	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
567	rc = VINF_EM_PENDING_REQUEST;
568	goto end;
569	}
570
571	/* When external interrupts are pending, we should exit the VM when IF is set. */
572	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
573	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
574	if (VBOX_FAILURE(rc))
575	{
576	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
577	goto end;
578	}
579
580	/* Load the guest state */
581	rc = SVMR0LoadGuestState(pVM, pCtx);
582	if (rc != VINF_SUCCESS)
583	{
584	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
585	goto end;
586	}
587	fGuestStateSynced = true;
588
589	/* All done! Let's start VM execution. */
590	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
591
592	/** Erratum #170 -> must force a TLB flush */
593	/** @todo supposed to be fixed in future by AMD */
594	fForceTLBFlush = true;
595
596	if ( pVM->hwaccm.s.svm.fResumeVM == false
597	\|\| fForceTLBFlush)
598	{
599	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
600	}
601	else
602	{
603	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
604	}
605	/* In case we execute a goto ResumeExecution later on. */
606	pVM->hwaccm.s.svm.fResumeVM = true;
607	fForceTLBFlush = false;
608
609	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
610	Assert(pVMCB->ctrl.u32InterceptCtrl1 == ( SVM_CTRL1_INTERCEPT_INTR
611	\| SVM_CTRL1_INTERCEPT_VINTR
612	\| SVM_CTRL1_INTERCEPT_NMI
613	\| SVM_CTRL1_INTERCEPT_SMI
614	\| SVM_CTRL1_INTERCEPT_INIT
615	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
616	\| SVM_CTRL1_INTERCEPT_RDPMC
617	\| SVM_CTRL1_INTERCEPT_CPUID
618	\| SVM_CTRL1_INTERCEPT_RSM
619	\| SVM_CTRL1_INTERCEPT_HLT
620	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
621	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
622	\| SVM_CTRL1_INTERCEPT_INVLPG
623	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
624	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
625	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE /* Legacy FPU FERR handling. */
626	));
627	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
628	\| SVM_CTRL2_INTERCEPT_VMMCALL
629	\| SVM_CTRL2_INTERCEPT_VMLOAD
630	\| SVM_CTRL2_INTERCEPT_VMSAVE
631	\| SVM_CTRL2_INTERCEPT_STGI
632	\| SVM_CTRL2_INTERCEPT_CLGI
633	\| SVM_CTRL2_INTERCEPT_SKINIT
634	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
635	));
636	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
637	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
638	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
639	Assert(pVMCB->ctrl.u64NestedPaging == 0);
640	Assert(pVMCB->ctrl.u64LBRVirt == 0);
641
642	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
643	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
644
645	/**
646	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
647	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
648	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
649	*/
650
651	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
652
653	/* Reason for the VM exit */
654	exitCode = pVMCB->ctrl.u64ExitCode;
655
656	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
657	{
658	HWACCMDumpRegs(pCtx);
659	#ifdef DEBUG
660	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
661	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
662	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
663	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
664	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
665	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
666	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
667	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
668	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
669	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
670
671	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
672	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
673	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
674	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
675
676	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
677	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
678	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
679	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
680	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
681	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
682	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
683	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
684	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
685	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
686
687	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
688	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
689	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
690	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
691	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
692	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
693	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
694	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
695	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
696	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
697	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
698	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
699	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
700	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
701	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
702	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
703	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
704
705	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
706	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
707
708	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
709	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
710	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
711	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
712	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
713	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
714	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
715	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
716	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
717	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
718	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
719	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
720	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
721	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
722	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
723	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
724	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
725	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
726	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
727	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
728
729	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
730	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
731
732	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
733	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
734	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
735	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
736
737	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
738	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
739
740	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
741	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
742	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
743	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
744
745	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
746	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
747	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
748	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
749	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
750	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
751	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
752
753	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
754	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
755	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
756	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
757
758	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
759	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
760	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
761
762	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
763	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
764	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
765	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
766	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
767	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
768	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
769	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
770	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
771	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
772	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
773	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
774
775	#endif
776	rc = VERR_SVM_UNABLE_TO_START_VM;
777	goto end;
778	}
779
780	/* Let's first sync back eip, esp, and eflags. */
781	pCtx->eip = pVMCB->guest.u64RIP;
782	pCtx->esp = pVMCB->guest.u64RSP;
783	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
784	/* eax is saved/restore across the vmrun instruction */
785	pCtx->eax = pVMCB->guest.u64RAX;
786
787	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
788	SVM_READ_SELREG(SS, ss);
789	SVM_READ_SELREG(CS, cs);
790	SVM_READ_SELREG(DS, ds);
791	SVM_READ_SELREG(ES, es);
792	SVM_READ_SELREG(FS, fs);
793	SVM_READ_SELREG(GS, gs);
794
795	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
796
797	/** @note NOW IT'S SAFE FOR LOGGING! */
798
799	/* Take care of instruction fusing (sti, mov ss) */
800	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
801	{
802	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
803	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
804	}
805	else
806	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
807
808	Log2(("exitCode = %x\n", exitCode));
809
810	/* Check if an injected event was interrupted prematurely. */
811	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
812	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
813	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
814	{
815	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
816	pVM->hwaccm.s.Event.fPending = true;
817	/* Error code present? (redundant) */
818	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
819	{
820	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
821	}
822	else
823	pVM->hwaccm.s.Event.errCode = 0;
824	}
825	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
826
827	/* Deal with the reason of the VM-exit. */
828	switch (exitCode)
829	{
830	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
831	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
832	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
833	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
834	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
835	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
836	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
837	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
838	{
839	/* Pending trap. */
840	SVM_EVENT Event;
841	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
842
843	Log2(("Hardware/software interrupt %d\n", vector));
844	switch (vector)
845	{
846	#ifdef DEBUG
847	case X86_XCPT_DB:
848	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
849	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
850	break;
851	#endif
852
853	case X86_XCPT_NM:
854	{
855	uint32_t oldCR0;
856
857	Log(("#NM fault at %VGv\n", pCtx->eip));
858
859	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
860	oldCR0 = ASMGetCR0();
861	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
862	rc = CPUMHandleLazyFPU(pVM);
863	if (rc == VINF_SUCCESS)
864	{
865	Assert(CPUMIsGuestFPUStateActive(pVM));
866
867	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
868	ASMSetCR0(oldCR0);
869
870	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
871
872	/* Continue execution. */
873	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
874	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
875
876	goto ResumeExecution;
877	}
878
879	Log(("Forward #NM fault to the guest\n"));
880	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
881
882	Event.au64[0] = 0;
883	Event.n.u3Type = SVM_EVENT_EXCEPTION;
884	Event.n.u1Valid = 1;
885	Event.n.u8Vector = X86_XCPT_NM;
886
887	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
888	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
889	goto ResumeExecution;
890	}
891
892	case X86_XCPT_PF: /* Page fault */
893	{
894	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
895	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
896
897	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
898	/* Exit qualification contains the linear address of the page fault. */
899	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
900	TRPMSetErrorCode(pVM, errCode);
901	TRPMSetFaultAddress(pVM, uFaultAddress);
902
903	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
904	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
905	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
906	if (rc == VINF_SUCCESS)
907	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
908	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
909	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
910
911	TRPMResetTrap(pVM);
912
913	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
914	goto ResumeExecution;
915	}
916	else
917	if (rc == VINF_EM_RAW_GUEST_TRAP)
918	{ /* A genuine pagefault.
919	* Forward the trap to the guest by injecting the exception and resuming execution.
920	*/
921	Log2(("Forward page fault to the guest\n"));
922	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
923	/* The error code might have been changed. */
924	errCode = TRPMGetErrorCode(pVM);
925
926	TRPMResetTrap(pVM);
927
928	/* Now we must update CR2. */
929	pCtx->cr2 = uFaultAddress;
930
931	Event.au64[0] = 0;
932	Event.n.u3Type = SVM_EVENT_EXCEPTION;
933	Event.n.u1Valid = 1;
934	Event.n.u8Vector = X86_XCPT_PF;
935	Event.n.u1ErrorCodeValid = 1;
936	Event.n.u32ErrorCode = errCode;
937
938	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
939
940	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
941	goto ResumeExecution;
942	}
943	#ifdef VBOX_STRICT
944	if (rc != VINF_EM_RAW_EMULATE_INSTR)
945	Log(("PGMTrap0eHandler failed with %d\n", rc));
946	#endif
947	/* Need to go back to the recompiler to emulate the instruction. */
948	TRPMResetTrap(pVM);
949	break;
950	}
951
952	case X86_XCPT_MF: /* Floating point exception. */
953	{
954	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
955	if (!(pCtx->cr0 & X86_CR0_NE))
956	{
957	/* old style FPU error reporting needs some extra work. */
958	/** @todo don't fall back to the recompiler, but do it manually. */
959	rc = VINF_EM_RAW_EMULATE_INSTR;
960	break;
961	}
962	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
963
964	Event.au64[0] = 0;
965	Event.n.u3Type = SVM_EVENT_EXCEPTION;
966	Event.n.u1Valid = 1;
967	Event.n.u8Vector = X86_XCPT_MF;
968
969	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
970
971	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
972	goto ResumeExecution;
973	}
974
975	#ifdef VBOX_STRICT
976	case X86_XCPT_GP: /* General protection failure exception.*/
977	case X86_XCPT_UD: /* Unknown opcode exception. */
978	case X86_XCPT_DE: /* Debug exception. */
979	case X86_XCPT_SS: /* Stack segment exception. */
980	case X86_XCPT_NP: /* Segment not present exception. */
981	{
982	Event.au64[0] = 0;
983	Event.n.u3Type = SVM_EVENT_EXCEPTION;
984	Event.n.u1Valid = 1;
985	Event.n.u8Vector = vector;
986
987	switch(vector)
988	{
989	case X86_XCPT_GP:
990	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
991	Event.n.u1ErrorCodeValid = 1;
992	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
993	break;
994	case X86_XCPT_DE:
995	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
996	break;
997	case X86_XCPT_UD:
998	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
999	break;
1000	case X86_XCPT_SS:
1001	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1002	Event.n.u1ErrorCodeValid = 1;
1003	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1004	break;
1005	case X86_XCPT_NP:
1006	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1007	Event.n.u1ErrorCodeValid = 1;
1008	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1009	break;
1010	}
1011	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1012	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1013
1014	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1015	goto ResumeExecution;
1016	}
1017	#endif
1018	default:
1019	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1020	rc = VERR_EM_INTERNAL_ERROR;
1021	break;
1022
1023	} /* switch (vector) */
1024	break;
1025	}
1026
1027	case SVM_EXIT_FERR_FREEZE:
1028	case SVM_EXIT_INTR:
1029	case SVM_EXIT_NMI:
1030	case SVM_EXIT_SMI:
1031	case SVM_EXIT_INIT:
1032	case SVM_EXIT_VINTR:
1033	/* External interrupt; leave to allow it to be dispatched again. */
1034	rc = VINF_EM_RAW_INTERRUPT;
1035	break;
1036
1037	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1038	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1039	/* Skip instruction and continue directly. */
1040	pCtx->eip += 2; /** @note hardcoded opcode size! */
1041	/* Continue execution.*/
1042	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1043	goto ResumeExecution;
1044
1045	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1046	{
1047	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1048	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1049	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1050	if (rc == VINF_SUCCESS)
1051	{
1052	/* Update EIP and continue execution. */
1053	pCtx->eip += 2; /** @note hardcoded opcode size! */
1054	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1055	goto ResumeExecution;
1056	}
1057	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1058	rc = VINF_EM_RAW_EMULATE_INSTR;
1059	break;
1060	}
1061
1062	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1063	{
1064	Log2(("SVM: Rdtsc\n"));
1065	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1066	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1067	if (rc == VINF_SUCCESS)
1068	{
1069	/* Update EIP and continue execution. */
1070	pCtx->eip += 2; /** @note hardcoded opcode size! */
1071	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1072	goto ResumeExecution;
1073	}
1074	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1075	rc = VINF_EM_RAW_EMULATE_INSTR;
1076	break;
1077	}
1078
1079	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1080	{
1081	Log2(("SVM: invlpg\n"));
1082	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1083
1084	/* Truly a pita. Why can't SVM give the same information as VMX? */
1085	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1086	break;
1087	}
1088
1089	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1090	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1091	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1092	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1093	{
1094	uint32_t cbSize;
1095
1096	Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1097	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1098	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1099
1100	switch (exitCode - SVM_EXIT_WRITE_CR0)
1101	{
1102	case 0:
1103	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1104	break;
1105	case 2:
1106	break;
1107	case 3:
1108	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1109	break;
1110	case 4:
1111	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1112	break;
1113	default:
1114	AssertFailed();
1115	}
1116	/* Check if a sync operation is pending. */
1117	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1118	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1119	{
1120	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1121	AssertRC(rc);
1122
1123	/** @note Force a TLB flush. SVM requires us to do it manually. */
1124	fForceTLBFlush = true;
1125	}
1126	if (rc == VINF_SUCCESS)
1127	{
1128	/* EIP has been updated already. */
1129
1130	/* Only resume if successful. */
1131	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1132	goto ResumeExecution;
1133	}
1134	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1135	if (rc == VERR_EM_INTERPRETER)
1136	rc = VINF_EM_RAW_EMULATE_INSTR;
1137	break;
1138	}
1139
1140	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1141	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1142	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1143	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1144	{
1145	uint32_t cbSize;
1146
1147	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1148	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1149	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1150	if (rc == VINF_SUCCESS)
1151	{
1152	/* EIP has been updated already. */
1153
1154	/* Only resume if successful. */
1155	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1156	goto ResumeExecution;
1157	}
1158	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1159	if (rc == VERR_EM_INTERPRETER)
1160	rc = VINF_EM_RAW_EMULATE_INSTR;
1161	break;
1162	}
1163
1164	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1165	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1166	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1167	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1168	{
1169	uint32_t cbSize;
1170
1171	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1172	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1173	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1174	if (rc == VINF_SUCCESS)
1175	{
1176	/* EIP has been updated already. */
1177
1178	/* Only resume if successful. */
1179	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1180	goto ResumeExecution;
1181	}
1182	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1183	if (rc == VERR_EM_INTERPRETER)
1184	rc = VINF_EM_RAW_EMULATE_INSTR;
1185	break;
1186	}
1187
1188	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1189	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1190	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1191	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1192	{
1193	uint32_t cbSize;
1194
1195	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1196	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1197	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1198	if (rc == VINF_SUCCESS)
1199	{
1200	/* EIP has been updated already. */
1201
1202	/* Only resume if successful. */
1203	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1204	goto ResumeExecution;
1205	}
1206	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1207	if (rc == VERR_EM_INTERPRETER)
1208	rc = VINF_EM_RAW_EMULATE_INSTR;
1209	break;
1210	}
1211
1212	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1213	case SVM_EXIT_IOIO: /* I/O instruction. */
1214	{
1215	SVM_IOIO_EXIT IoExitInfo;
1216	uint32_t uIOSize, uAndVal;
1217
1218	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1219
1220	/** @todo could use a lookup table here */
1221	if (IoExitInfo.n.u1OP8)
1222	{
1223	uIOSize = 1;
1224	uAndVal = 0xff;
1225	}
1226	else
1227	if (IoExitInfo.n.u1OP16)
1228	{
1229	uIOSize = 2;
1230	uAndVal = 0xffff;
1231	}
1232	else
1233	if (IoExitInfo.n.u1OP32)
1234	{
1235	uIOSize = 4;
1236	uAndVal = 0xffffffff;
1237	}
1238	else
1239	{
1240	AssertFailed(); /* should be fatal. */
1241	rc = VINF_EM_RAW_EMULATE_INSTR;
1242	break;
1243	}
1244
1245	if (IoExitInfo.n.u1STR)
1246	{
1247	/* ins/outs */
1248	uint32_t prefix = 0;
1249	if (IoExitInfo.n.u1REP)
1250	prefix \|= PREFIX_REP;
1251
1252	if (IoExitInfo.n.u1Type == 0)
1253	{
1254	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1255	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1256	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1257	}
1258	else
1259	{
1260	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1261	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1262	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1263	}
1264	}
1265	else
1266	{
1267	/* normal in/out */
1268	Assert(!IoExitInfo.n.u1REP);
1269
1270	if (IoExitInfo.n.u1Type == 0)
1271	{
1272	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1273	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1274	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1275	}
1276	else
1277	{
1278	uint32_t u32Val = 0;
1279
1280	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1281	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1282	if (IOM_SUCCESS(rc))
1283	{
1284	/* Write back to the EAX register. */
1285	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1286	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1287	}
1288	}
1289	}
1290	/*
1291	* Handled the I/O return codes.
1292	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1293	*/
1294	if (IOM_SUCCESS(rc))
1295	{
1296	/* Update EIP and continue execution. */
1297	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1298	if (RT_LIKELY(rc == VINF_SUCCESS))
1299	{
1300	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1301	goto ResumeExecution;
1302	}
1303	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1304	break;
1305	}
1306	if (rc == VINF_EM_RAW_EMULATE_INSTR)
1307	{
1308	/* First attempt to emulate directly before falling back to the recompiler */
1309	rc = (IoExitInfo.n.u1Type == 0) ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1310	}
1311
1312	#ifdef VBOX_STRICT
1313	if (rc == VINF_IOM_HC_IOPORT_READ)
1314	Assert(IoExitInfo.n.u1Type != 0);
1315	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1316	Assert(IoExitInfo.n.u1Type == 0);
1317	else
1318	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1319	#endif
1320	Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1321	break;
1322	}
1323
1324	case SVM_EXIT_HLT:
1325	/** Check if external interrupts are pending; if so, don't switch back. */
1326	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1327	{
1328	pCtx->eip++; /* skip hlt */
1329	goto ResumeExecution;
1330	}
1331
1332	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1333	break;
1334
1335	case SVM_EXIT_RDPMC:
1336	case SVM_EXIT_RSM:
1337	case SVM_EXIT_INVLPGA:
1338	case SVM_EXIT_VMRUN:
1339	case SVM_EXIT_VMMCALL:
1340	case SVM_EXIT_VMLOAD:
1341	case SVM_EXIT_VMSAVE:
1342	case SVM_EXIT_STGI:
1343	case SVM_EXIT_CLGI:
1344	case SVM_EXIT_SKINIT:
1345	case SVM_EXIT_RDTSCP:
1346	{
1347	/* Unsupported instructions. */
1348	SVM_EVENT Event;
1349
1350	Event.au64[0] = 0;
1351	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1352	Event.n.u1Valid = 1;
1353	Event.n.u8Vector = X86_XCPT_UD;
1354
1355	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1356	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1357
1358	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1359	goto ResumeExecution;
1360	}
1361
1362	/* Emulate RDMSR & WRMSR in ring 3. */
1363	case SVM_EXIT_MSR:
1364	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1365	break;
1366
1367	case SVM_EXIT_NPF:
1368	AssertFailed(); /* unexpected */
1369	break;
1370
1371	case SVM_EXIT_SHUTDOWN:
1372	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1373	break;
1374
1375	case SVM_EXIT_PAUSE:
1376	case SVM_EXIT_IDTR_READ:
1377	case SVM_EXIT_GDTR_READ:
1378	case SVM_EXIT_LDTR_READ:
1379	case SVM_EXIT_TR_READ:
1380	case SVM_EXIT_IDTR_WRITE:
1381	case SVM_EXIT_GDTR_WRITE:
1382	case SVM_EXIT_LDTR_WRITE:
1383	case SVM_EXIT_TR_WRITE:
1384	case SVM_EXIT_CR0_SEL_WRITE:
1385	default:
1386	/* Unexpected exit codes. */
1387	rc = VERR_EM_INTERNAL_ERROR;
1388	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1389	break;
1390	}
1391
1392	end:
1393	if (fGuestStateSynced)
1394	{
1395	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1396	SVM_READ_SELREG(LDTR, ldtr);
1397	SVM_READ_SELREG(TR, tr);
1398
1399	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1400	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1401
1402	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1403	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1404
1405	/*
1406	* System MSRs
1407	*/
1408	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1409	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1410	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1411	}
1412
1413	/* Signal changes for the recompiler. */
1414	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1415
1416	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1417	if (exitCode == SVM_EXIT_INTR)
1418	{
1419	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1420	/* On the next entry we'll only sync the host context. */
1421	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1422	}
1423	else
1424	{
1425	/* On the next entry we'll sync everything. */
1426	/** @todo we can do better than this */
1427	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1428	}
1429
1430	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1431	return rc;
1432	}
1433
1434	/**
1435	* Enable SVM
1436	*
1437	* @returns VBox status code.
1438	* @param pVM The VM to operate on.
1439	*/
1440	HWACCMR0DECL(int) SVMR0Enable(PVM pVM)
1441	{
1442	uint64_t val;
1443
1444	Assert(pVM->hwaccm.s.svm.fSupported);
1445
1446	/* We must turn on SVM and setup the host state physical address, as those MSRs are per-cpu/core. */
1447
1448	/* Turn on SVM in the EFER MSR. */
1449	val = ASMRdMsr(MSR_K6_EFER);
1450	if (!(val & MSR_K6_EFER_SVME))
1451	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
1452
1453	/* Write the physical page address where the CPU will store the host state while executing the VM. */
1454	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pVM->hwaccm.s.svm.pHStatePhys);
1455
1456	/* Force a TLB flush on VM entry. */
1457	pVM->hwaccm.s.svm.fResumeVM = false;
1458
1459	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1460	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1461
1462	return VINF_SUCCESS;
1463	}
1464
1465
1466	/**
1467	* Disable SVM
1468	*
1469	* @returns VBox status code.
1470	* @param pVM The VM to operate on.
1471	*/
1472	HWACCMR0DECL(int) SVMR0Disable(PVM pVM)
1473	{
1474	/** @todo hopefully this is not very expensive. */
1475
1476	/* Turn off SVM in the EFER MSR. */
1477	uint64_t val = ASMRdMsr(MSR_K6_EFER);
1478	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
1479
1480	/* Invalidate host state physical address. */
1481	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
1482
1483	Assert(pVM->hwaccm.s.svm.fSupported);
1484	return VINF_SUCCESS;
1485	}
1486
1487
1488	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1489	{
1490	OP_PARAMVAL param1;
1491	RTGCPTR addr;
1492
1493	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1494	if(VBOX_FAILURE(rc))
1495	return VERR_EM_INTERPRETER;
1496
1497	switch(param1.type)
1498	{
1499	case PARMTYPE_IMMEDIATE:
1500	case PARMTYPE_ADDRESS:
1501	if(!(param1.flags & PARAM_VAL32))
1502	return VERR_EM_INTERPRETER;
1503	addr = (RTGCPTR)param1.val.val32;
1504	break;
1505
1506	default:
1507	return VERR_EM_INTERPRETER;
1508	}
1509
1510	/** @todo is addr always a flat linear address or ds based
1511	* (in absence of segment override prefixes)????
1512	*/
1513	rc = PGMInvalidatePage(pVM, addr);
1514	if (VBOX_SUCCESS(rc))
1515	{
1516	/* Manually invalidate the page for the VM's TLB. */
1517	SVMInvlpgA(addr, uASID);
1518	return VINF_SUCCESS;
1519	}
1520	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1521	return VERR_EM_INTERPRETER;
1522	}
1523
1524	/**
1525	* Interprets INVLPG
1526	*
1527	* @returns VBox status code.
1528	* @retval VINF_* Scheduling instructions.
1529	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1530	* @retval VERR_* Fatal errors.
1531	*
1532	* @param pVM The VM handle.
1533	* @param pRegFrame The register frame.
1534	* @param ASID Tagged TLB id for the guest
1535	*
1536	* Updates the EIP if an instruction was executed successfully.
1537	*/
1538	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1539	{
1540	/*
1541	* Only allow 32-bit code.
1542	*/
1543	if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1544	{
1545	RTGCPTR pbCode;
1546	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1547	if (VBOX_SUCCESS(rc))
1548	{
1549	uint32_t cbOp;
1550	DISCPUSTATE Cpu;
1551
1552	Cpu.mode = CPUMODE_32BIT;
1553	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1554	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1555	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1556	{
1557	Assert(cbOp == Cpu.opsize);
1558	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1559	if (VBOX_SUCCESS(rc))
1560	{
1561	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1562	}
1563	return rc;
1564	}
1565	}
1566	}
1567	return VERR_EM_INTERPRETER;
1568	}
1569

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 3197

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