VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 32963

Last change on this file since 32963 was 32847, checked in by vboxsync, 14 years ago

Clear VMCPU_FF_TO_R3 on the way out
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1/* $Id: HWSVMR0.cpp 32847 2010-09-30 14:18:37Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/hwaccm.h>
23#include <VBox/pgm.h>
24#include <VBox/selm.h>
25#include <VBox/iom.h>
26#include <VBox/dbgf.h>
27#include <VBox/tm.h>
28#include <VBox/pdmapi.h>
29#include "HWACCMInternal.h"
30#include <VBox/vm.h>
31#include <VBox/x86.h>
32#include <VBox/hwacc_svm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/dis.h>
36#include <VBox/disopcode.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/asm-amd64-x86.h>
41#include <iprt/cpuset.h>
42#include <iprt/mp.h>
43#include <iprt/time.h>
44#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
45# include <iprt/thread.h>
46#endif
47#include "HWSVMR0.h"
48
49/*******************************************************************************
50* Internal Functions *
51*******************************************************************************/
52static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
53static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
54static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
55
56/*******************************************************************************
57* Global Variables *
58*******************************************************************************/
59
60/**
61 * Sets up and activates AMD-V on the current CPU
62 *
63 * @returns VBox status code.
64 * @param pCpu CPU info struct
65 * @param pVM The VM to operate on. (can be NULL after a resume!!)
66 * @param pvPageCpu Pointer to the global cpu page
67 * @param pPageCpuPhys Physical address of the global cpu page
68 */
69VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
70{
71 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
72 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
73
74 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
75 uint64_t val = ASMRdMsr(MSR_K6_EFER);
76 if (val & MSR_K6_EFER_SVME)
77 {
78 /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we blindly use AMD-V. */
79 if ( pVM
80 && pVM->hwaccm.s.svm.fIgnoreInUseError)
81 {
82 pCpu->fIgnoreAMDVInUseError = true;
83 }
84
85 if (!pCpu->fIgnoreAMDVInUseError)
86 return VERR_SVM_IN_USE;
87 }
88
89 /* Turn on AMD-V in the EFER MSR. */
90 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
91
92 /* Write the physical page address where the CPU will store the host state while executing the VM. */
93 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
94
95 return VINF_SUCCESS;
96}
97
98/**
99 * Deactivates AMD-V on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pvPageCpu Pointer to the global cpu page
104 * @param pPageCpuPhys Physical address of the global cpu page
105 */
106VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
107{
108 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
109 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
110
111 /* Turn off AMD-V in the EFER MSR. */
112 uint64_t val = ASMRdMsr(MSR_K6_EFER);
113 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
114
115 /* Invalidate host state physical address. */
116 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
117
118 return VINF_SUCCESS;
119}
120
121/**
122 * Does Ring-0 per VM AMD-V init.
123 *
124 * @returns VBox status code.
125 * @param pVM The VM to operate on.
126 */
127VMMR0DECL(int) SVMR0InitVM(PVM pVM)
128{
129 int rc;
130
131 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
132
133 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
134 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
135 if (RT_FAILURE(rc))
136 return rc;
137
138 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
139 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
140 /* Set all bits to intercept all IO accesses. */
141 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
142
143 /* Erratum 170 which requires a forced TLB flush for each world switch:
144 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
145 *
146 * All BH-G1/2 and DH-G1/2 models include a fix:
147 * Athlon X2: 0x6b 1/2
148 * 0x68 1/2
149 * Athlon 64: 0x7f 1
150 * 0x6f 2
151 * Sempron: 0x7f 1/2
152 * 0x6f 2
153 * 0x6c 2
154 * 0x7c 2
155 * Turion 64: 0x68 2
156 *
157 */
158 uint32_t u32Dummy;
159 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
160 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
161 u32BaseFamily= (u32Version >> 8) & 0xf;
162 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
163 u32Model = ((u32Version >> 4) & 0xf);
164 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
165 u32Stepping = u32Version & 0xf;
166 if ( u32Family == 0xf
167 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
168 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
169 {
170 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
171 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
172 }
173
174 /* Allocate VMCBs for all guest CPUs. */
175 for (VMCPUID i = 0; i < pVM->cCpus; i++)
176 {
177 PVMCPU pVCpu = &pVM->aCpus[i];
178
179 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
180 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
181 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
182
183 /* Allocate one page for the host context */
184 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185 if (RT_FAILURE(rc))
186 return rc;
187
188 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
189 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
190 Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
191 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
192
193 /* Allocate one page for the VM control block (VMCB). */
194 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
195 if (RT_FAILURE(rc))
196 return rc;
197
198 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
199 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
200 Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
201 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
202
203 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
204 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
209 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
210 /* Set all bits to intercept all MSR accesses. */
211 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
212 }
213
214 return VINF_SUCCESS;
215}
216
217/**
218 * Does Ring-0 per VM AMD-V termination.
219 *
220 * @returns VBox status code.
221 * @param pVM The VM to operate on.
222 */
223VMMR0DECL(int) SVMR0TermVM(PVM pVM)
224{
225 for (VMCPUID i = 0; i < pVM->cCpus; i++)
226 {
227 PVMCPU pVCpu = &pVM->aCpus[i];
228
229 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
230 {
231 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
232 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
233 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
234 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
235 }
236
237 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
238 {
239 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
240 pVCpu->hwaccm.s.svm.pVMCB = 0;
241 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
242 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
243 }
244 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
245 {
246 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
247 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
248 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
249 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
250 }
251 }
252 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
253 {
254 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
255 pVM->hwaccm.s.svm.pIOBitmap = 0;
256 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
257 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
258 }
259 return VINF_SUCCESS;
260}
261
262/**
263 * Sets up AMD-V for the specified VM
264 *
265 * @returns VBox status code.
266 * @param pVM The VM to operate on.
267 */
268VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
269{
270 int rc = VINF_SUCCESS;
271
272 AssertReturn(pVM, VERR_INVALID_PARAMETER);
273
274 Assert(pVM->hwaccm.s.svm.fSupported);
275
276 for (VMCPUID i = 0; i < pVM->cCpus; i++)
277 {
278 PVMCPU pVCpu = &pVM->aCpus[i];
279 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
280
281 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
282
283 /* Program the control fields. Most of them never have to be changed again. */
284 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
285 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
286 if (!pVM->hwaccm.s.fNestedPaging)
287 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
288 else
289 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
290
291 /*
292 * CR0/3/4 writes must be intercepted for obvious reasons.
293 */
294 if (!pVM->hwaccm.s.fNestedPaging)
295 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
296 else
297 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4);
298
299 /* Intercept all DRx reads and writes by default. Changed later on. */
300 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
301 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
302
303 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
304 * All breakpoints are automatically cleared when the VM exits.
305 */
306
307 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
308#ifndef DEBUG
309 if (pVM->hwaccm.s.fNestedPaging)
310 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
311#endif
312
313 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
314 | SVM_CTRL1_INTERCEPT_VINTR
315 | SVM_CTRL1_INTERCEPT_NMI
316 | SVM_CTRL1_INTERCEPT_SMI
317 | SVM_CTRL1_INTERCEPT_INIT
318 | SVM_CTRL1_INTERCEPT_RDPMC
319 | SVM_CTRL1_INTERCEPT_CPUID
320 | SVM_CTRL1_INTERCEPT_RSM
321 | SVM_CTRL1_INTERCEPT_HLT
322 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
323 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
324 | SVM_CTRL1_INTERCEPT_INVLPG
325 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
326 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
327 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
328 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
329 ;
330 /* With nested paging we don't care about invlpg anymore. */
331 if (pVM->hwaccm.s.fNestedPaging)
332 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
333
334 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
335 | SVM_CTRL2_INTERCEPT_VMMCALL
336 | SVM_CTRL2_INTERCEPT_VMLOAD
337 | SVM_CTRL2_INTERCEPT_VMSAVE
338 | SVM_CTRL2_INTERCEPT_STGI
339 | SVM_CTRL2_INTERCEPT_CLGI
340 | SVM_CTRL2_INTERCEPT_SKINIT
341 | SVM_CTRL2_INTERCEPT_WBINVD
342 | SVM_CTRL2_INTERCEPT_MONITOR
343 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
344 ;
345 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
346 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
347 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
348
349 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
350 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
351 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
352 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
353
354 /* Set IO and MSR bitmap addresses. */
355 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
356 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
357
358 /* No LBR virtualization. */
359 pVMCB->ctrl.u64LBRVirt = 0;
360
361 /** The ASID must start at 1; the host uses 0. */
362 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
363
364 /** Setup the PAT msr (nested paging only) */
365 /* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB, so choose type 6 for all PAT slots. */
366 pVMCB->guest.u64GPAT = 0x0006060606060606ULL;
367
368 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
369 * to modify them directly.
370 */
371 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
372 svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
373 svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
374 svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
375 svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
376 svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
377 svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
378 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
379 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
380 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
381 }
382
383 return rc;
384}
385
386
387/**
388 * Sets the permission bits for the specified MSR
389 *
390 * @param pVCpu The VMCPU to operate on.
391 * @param ulMSR MSR value
392 * @param fRead Reading allowed/disallowed
393 * @param fWrite Writing allowed/disallowed
394 */
395static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
396{
397 unsigned ulBit;
398 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
399
400 if (ulMSR <= 0x00001FFF)
401 {
402 /* Pentium-compatible MSRs */
403 ulBit = ulMSR * 2;
404 }
405 else
406 if ( ulMSR >= 0xC0000000
407 && ulMSR <= 0xC0001FFF)
408 {
409 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
410 ulBit = (ulMSR - 0xC0000000) * 2;
411 pMSRBitmap += 0x800;
412 }
413 else
414 if ( ulMSR >= 0xC0010000
415 && ulMSR <= 0xC0011FFF)
416 {
417 /* AMD Seventh and Eighth Generation Processor MSRs */
418 ulBit = (ulMSR - 0xC0001000) * 2;
419 pMSRBitmap += 0x1000;
420 }
421 else
422 {
423 AssertFailed();
424 return;
425 }
426 Assert(ulBit < 16 * 1024 - 1);
427 if (fRead)
428 ASMBitClear(pMSRBitmap, ulBit);
429 else
430 ASMBitSet(pMSRBitmap, ulBit);
431
432 if (fWrite)
433 ASMBitClear(pMSRBitmap, ulBit + 1);
434 else
435 ASMBitSet(pMSRBitmap, ulBit + 1);
436}
437
438/**
439 * Injects an event (trap or external interrupt)
440 *
441 * @param pVCpu The VMCPU to operate on.
442 * @param pVMCB SVM control block
443 * @param pCtx CPU Context
444 * @param pIntInfo SVM interrupt info
445 */
446inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
447{
448#ifdef VBOX_WITH_STATISTICS
449 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
450#endif
451
452#ifdef VBOX_STRICT
453 if (pEvent->n.u8Vector == 0xE)
454 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
455 else
456 if (pEvent->n.u8Vector < 0x20)
457 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
458 else
459 {
460 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
461 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
462 Assert(pCtx->eflags.u32 & X86_EFL_IF);
463 }
464#endif
465
466 /* Set event injection state. */
467 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
468}
469
470
471/**
472 * Checks for pending guest interrupts and injects them
473 *
474 * @returns VBox status code.
475 * @param pVM The VM to operate on.
476 * @param pVCpu The VM CPU to operate on.
477 * @param pVMCB SVM control block
478 * @param pCtx CPU Context
479 */
480static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
481{
482 int rc;
483
484 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
485 if (pVCpu->hwaccm.s.Event.fPending)
486 {
487 SVM_EVENT Event;
488
489 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
490 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
491 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
492 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
493
494 pVCpu->hwaccm.s.Event.fPending = false;
495 return VINF_SUCCESS;
496 }
497
498 /* If an active trap is already pending, then we must forward it first! */
499 if (!TRPMHasTrap(pVCpu))
500 {
501 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
502 {
503 SVM_EVENT Event;
504
505 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
506 Event.n.u8Vector = X86_XCPT_NMI;
507 Event.n.u1Valid = 1;
508 Event.n.u32ErrorCode = 0;
509 Event.n.u3Type = SVM_EVENT_NMI;
510
511 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
512 return VINF_SUCCESS;
513 }
514
515 /* @todo SMI interrupts. */
516
517 /* When external interrupts are pending, we should exit the VM when IF is set. */
518 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
519 {
520 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
521 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
522 {
523 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
524 {
525 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
526 LogFlow(("Enable irq window exit!\n"));
527 else
528 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
529
530 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
531 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
532 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
533 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
534 }
535 }
536 else
537 {
538 uint8_t u8Interrupt;
539
540 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
541 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
542 if (RT_SUCCESS(rc))
543 {
544 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
545 AssertRC(rc);
546 }
547 else
548 {
549 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
550 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
551 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
552 /* Just continue */
553 }
554 }
555 }
556 }
557
558#ifdef VBOX_STRICT
559 if (TRPMHasTrap(pVCpu))
560 {
561 uint8_t u8Vector;
562 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
563 AssertRC(rc);
564 }
565#endif
566
567 if ( (pCtx->eflags.u32 & X86_EFL_IF)
568 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
569 && TRPMHasTrap(pVCpu)
570 )
571 {
572 uint8_t u8Vector;
573 TRPMEVENT enmType;
574 SVM_EVENT Event;
575 RTGCUINT u32ErrorCode;
576
577 Event.au64[0] = 0;
578
579 /* If a new event is pending, then dispatch it now. */
580 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
581 AssertRC(rc);
582 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
583 Assert(enmType != TRPM_SOFTWARE_INT);
584
585 /* Clear the pending trap. */
586 rc = TRPMResetTrap(pVCpu);
587 AssertRC(rc);
588
589 Event.n.u8Vector = u8Vector;
590 Event.n.u1Valid = 1;
591 Event.n.u32ErrorCode = u32ErrorCode;
592
593 if (enmType == TRPM_TRAP)
594 {
595 switch (u8Vector) {
596 case 8:
597 case 10:
598 case 11:
599 case 12:
600 case 13:
601 case 14:
602 case 17:
603 /* Valid error codes. */
604 Event.n.u1ErrorCodeValid = 1;
605 break;
606 default:
607 break;
608 }
609 if (u8Vector == X86_XCPT_NMI)
610 Event.n.u3Type = SVM_EVENT_NMI;
611 else
612 Event.n.u3Type = SVM_EVENT_EXCEPTION;
613 }
614 else
615 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
616
617 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
618 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
619 } /* if (interrupts can be dispatched) */
620
621 return VINF_SUCCESS;
622}
623
624/**
625 * Save the host state
626 *
627 * @returns VBox status code.
628 * @param pVM The VM to operate on.
629 * @param pVCpu The VM CPU to operate on.
630 */
631VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
632{
633 NOREF(pVM);
634 NOREF(pVCpu);
635 /* Nothing to do here. */
636 return VINF_SUCCESS;
637}
638
639/**
640 * Loads the guest state
641 *
642 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
643 *
644 * @returns VBox status code.
645 * @param pVM The VM to operate on.
646 * @param pVCpu The VM CPU to operate on.
647 * @param pCtx Guest context
648 */
649VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
650{
651 RTGCUINTPTR val;
652 SVM_VMCB *pVMCB;
653
654 if (pVM == NULL)
655 return VERR_INVALID_PARAMETER;
656
657 /* Setup AMD SVM. */
658 Assert(pVM->hwaccm.s.svm.fSupported);
659
660 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
661 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
662
663 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
664 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
665 {
666 SVM_WRITE_SELREG(CS, cs);
667 SVM_WRITE_SELREG(SS, ss);
668 SVM_WRITE_SELREG(DS, ds);
669 SVM_WRITE_SELREG(ES, es);
670 SVM_WRITE_SELREG(FS, fs);
671 SVM_WRITE_SELREG(GS, gs);
672 }
673
674 /* Guest CPU context: LDTR. */
675 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
676 {
677 SVM_WRITE_SELREG(LDTR, ldtr);
678 }
679
680 /* Guest CPU context: TR. */
681 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
682 {
683 SVM_WRITE_SELREG(TR, tr);
684 }
685
686 /* Guest CPU context: GDTR. */
687 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
688 {
689 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
690 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
691 }
692
693 /* Guest CPU context: IDTR. */
694 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
695 {
696 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
697 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
698 }
699
700 /*
701 * Sysenter MSRs (unconditional)
702 */
703 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
704 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
705 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
706
707 /* Control registers */
708 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
709 {
710 val = pCtx->cr0;
711 if (!CPUMIsGuestFPUStateActive(pVCpu))
712 {
713 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
714 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
715 }
716 else
717 {
718 /** @todo check if we support the old style mess correctly. */
719 if (!(val & X86_CR0_NE))
720 {
721 Log(("Forcing X86_CR0_NE!!!\n"));
722
723 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
724 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
725 {
726 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
727 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
728 }
729 }
730 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
731 }
732 /* Always enable caching. */
733 val &= ~(X86_CR0_CD|X86_CR0_NW);
734
735 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
736 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
737 if (!pVM->hwaccm.s.fNestedPaging)
738 {
739 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
740 val |= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
741 }
742 pVMCB->guest.u64CR0 = val;
743 }
744 /* CR2 as well */
745 pVMCB->guest.u64CR2 = pCtx->cr2;
746
747 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
748 {
749 /* Save our shadow CR3 register. */
750 if (pVM->hwaccm.s.fNestedPaging)
751 {
752 PGMMODE enmShwPagingMode;
753
754#if HC_ARCH_BITS == 32
755 if (CPUMIsGuestInLongModeEx(pCtx))
756 enmShwPagingMode = PGMMODE_AMD64_NX;
757 else
758#endif
759 enmShwPagingMode = PGMGetHostMode(pVM);
760
761 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
762 Assert(pVMCB->ctrl.u64NestedPagingCR3);
763 pVMCB->guest.u64CR3 = pCtx->cr3;
764 }
765 else
766 {
767 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
768 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
769 }
770 }
771
772 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
773 {
774 val = pCtx->cr4;
775 if (!pVM->hwaccm.s.fNestedPaging)
776 {
777 switch(pVCpu->hwaccm.s.enmShadowMode)
778 {
779 case PGMMODE_REAL:
780 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
781 AssertFailed();
782 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
783
784 case PGMMODE_32_BIT: /* 32-bit paging. */
785 val &= ~X86_CR4_PAE;
786 break;
787
788 case PGMMODE_PAE: /* PAE paging. */
789 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
790 /** Must use PAE paging as we could use physical memory > 4 GB */
791 val |= X86_CR4_PAE;
792 break;
793
794 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
795 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
796#ifdef VBOX_ENABLE_64_BITS_GUESTS
797 break;
798#else
799 AssertFailed();
800 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
801#endif
802
803 default: /* shut up gcc */
804 AssertFailed();
805 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
806 }
807 }
808 pVMCB->guest.u64CR4 = val;
809 }
810
811 /* Debug registers. */
812 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
813 {
814 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
815 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
816
817 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
818 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
819 pCtx->dr[7] |= 0x400; /* must be one */
820
821 pVMCB->guest.u64DR7 = pCtx->dr[7];
822 pVMCB->guest.u64DR6 = pCtx->dr[6];
823
824#ifdef DEBUG
825 /* Sync the hypervisor debug state now if any breakpoint is armed. */
826 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
827 && !CPUMIsHyperDebugStateActive(pVCpu)
828 && !DBGFIsStepping(pVCpu))
829 {
830 /* Save the host and load the hypervisor debug state. */
831 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
832 AssertRC(rc);
833
834 /* DRx intercepts remain enabled. */
835
836 /* Override dr6 & dr7 with the hypervisor values. */
837 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
838 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
839 }
840 else
841#endif
842 /* Sync the debug state now if any breakpoint is armed. */
843 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
844 && !CPUMIsGuestDebugStateActive(pVCpu)
845 && !DBGFIsStepping(pVCpu))
846 {
847 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
848
849 /* Disable drx move intercepts. */
850 pVMCB->ctrl.u16InterceptRdDRx = 0;
851 pVMCB->ctrl.u16InterceptWrDRx = 0;
852
853 /* Save the host and load the guest debug state. */
854 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
855 AssertRC(rc);
856 }
857 }
858
859 /* EIP, ESP and EFLAGS */
860 pVMCB->guest.u64RIP = pCtx->rip;
861 pVMCB->guest.u64RSP = pCtx->rsp;
862 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
863
864 /* Set CPL */
865 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
866
867 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
868 pVMCB->guest.u64RAX = pCtx->rax;
869
870 /* vmrun will fail without MSR_K6_EFER_SVME. */
871 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
872
873 /* 64 bits guest mode? */
874 if (CPUMIsGuestInLongModeEx(pCtx))
875 {
876#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
877 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
878#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
879 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
880#else
881# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
882 if (!pVM->hwaccm.s.fAllow64BitGuests)
883 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
884# endif
885 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
886#endif
887 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
888 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
889 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
890 }
891 else
892 {
893 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
894 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
895
896 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
897 }
898
899 /* TSC offset. */
900 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
901 {
902 uint64_t u64CurTSC = ASMReadTSC();
903 if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
904 {
905 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
906 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
907 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
908 }
909 else
910 {
911 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
912 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
913 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
914 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
915 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
916 }
917 }
918 else
919 {
920 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
921 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
922 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
923 }
924
925 /* Sync the various msrs for 64 bits mode. */
926 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
927 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
928 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
929 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
930 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
931
932#ifdef DEBUG
933 /* Intercept X86_XCPT_DB if stepping is enabled */
934 if ( DBGFIsStepping(pVCpu)
935 || CPUMIsHyperDebugStateActive(pVCpu))
936 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
937 else
938 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
939#endif
940
941 /* Done. */
942 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
943
944 return VINF_SUCCESS;
945}
946
947
948/**
949 * Runs guest code in an AMD-V VM.
950 *
951 * @returns VBox status code.
952 * @param pVM The VM to operate on.
953 * @param pVCpu The VM CPU to operate on.
954 * @param pCtx Guest context
955 */
956VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
957{
958 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
959 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit1);
960 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit2);
961
962 VBOXSTRICTRC rc = VINF_SUCCESS;
963 int rc2;
964 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
965 SVM_VMCB *pVMCB;
966 bool fSyncTPR = false;
967 unsigned cResume = 0;
968 uint8_t u8LastTPR;
969 PHWACCM_CPUINFO pCpu = 0;
970 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
971#ifdef VBOX_STRICT
972 RTCPUID idCpuCheck;
973#endif
974#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
975 uint64_t u64LastTime = RTTimeMilliTS();
976#endif
977
978 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
979 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
980
981 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
982 */
983ResumeExecution:
984 if (!STAM_PROFILE_ADV_IS_RUNNING(&pVCpu->hwaccm.s.StatEntry))
985 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit2, &pVCpu->hwaccm.s.StatEntry, x);
986 Assert(!HWACCMR0SuspendPending());
987
988 /* Safety precaution; looping for too long here can have a very bad effect on the host */
989 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
990 {
991 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
992 rc = VINF_EM_RAW_INTERRUPT;
993 goto end;
994 }
995
996 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
997 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
998 {
999 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
1000 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
1001 {
1002 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1003 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1004 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1005 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1006 */
1007 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1008 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1009 pVMCB->ctrl.u64IntShadow = 0;
1010 }
1011 }
1012 else
1013 {
1014 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1015 pVMCB->ctrl.u64IntShadow = 0;
1016 }
1017
1018#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1019 if (RT_UNLIKELY((cResume & 0xf) == 0))
1020 {
1021 uint64_t u64CurTime = RTTimeMilliTS();
1022
1023 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1024 {
1025 u64LastTime = u64CurTime;
1026 TMTimerPollVoid(pVM, pVCpu);
1027 }
1028 }
1029#endif
1030
1031 /* Check for pending actions that force us to go back to ring 3. */
1032 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
1033 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST))
1034 {
1035 /* Check if a sync operation is pending. */
1036 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1037 {
1038 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1039 AssertRC(VBOXSTRICTRC_VAL(rc));
1040 if (rc != VINF_SUCCESS)
1041 {
1042 Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", VBOXSTRICTRC_VAL(rc)));
1043 goto end;
1044 }
1045 }
1046
1047#ifdef DEBUG
1048 /* Intercept X86_XCPT_DB if stepping is enabled */
1049 if (!DBGFIsStepping(pVCpu))
1050#endif
1051 {
1052 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1053 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1054 {
1055 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1056 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1057 goto end;
1058 }
1059 }
1060
1061 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1062 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1063 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1064 {
1065 rc = VINF_EM_PENDING_REQUEST;
1066 goto end;
1067 }
1068
1069 /* Check if a pgm pool flush is in progress. */
1070 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
1071 {
1072 rc = VINF_PGM_POOL_FLUSH_PENDING;
1073 goto end;
1074 }
1075
1076 /* Check if DMA work is pending (2nd+ run). */
1077 if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA) && cResume > 1)
1078 {
1079 rc = VINF_EM_RAW_TO_R3;
1080 goto end;
1081 }
1082 }
1083
1084#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1085 /*
1086 * Exit to ring-3 preemption/work is pending.
1087 *
1088 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1089 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1090 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1091 *
1092 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1093 * shootdowns rely on this.
1094 */
1095 uOldEFlags = ASMIntDisableFlags();
1096 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1097 {
1098 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1099 rc = VINF_EM_RAW_INTERRUPT;
1100 goto end;
1101 }
1102 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1103#endif
1104
1105 /* When external interrupts are pending, we should exit the VM when IF is set. */
1106 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1107 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1108 if (RT_FAILURE(rc))
1109 goto end;
1110
1111 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1112 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1113 * @todo query and update the TPR only when it could have been changed (mmio access)
1114 */
1115 if (pVM->hwaccm.s.fHasIoApic)
1116 {
1117 bool fPending;
1118
1119 /* TPR caching in CR8 */
1120 rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1121 AssertRC(rc2);
1122
1123 if (pVM->hwaccm.s.fTPRPatchingActive)
1124 {
1125 /* Our patch code uses LSTAR for TPR caching. */
1126 pCtx->msrLSTAR = u8LastTPR;
1127
1128 if (fPending)
1129 {
1130 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1131 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1132 }
1133 else
1134 /* No interrupts are pending, so we don't need to be explicitely notified.
1135 * There are enough world switches for detecting pending interrupts.
1136 */
1137 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1138 }
1139 else
1140 {
1141 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1142
1143 if (fPending)
1144 {
1145 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1146 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1147 }
1148 else
1149 /* No interrupts are pending, so we don't need to be explicitely notified.
1150 * There are enough world switches for detecting pending interrupts.
1151 */
1152 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1153 }
1154 fSyncTPR = !fPending;
1155 }
1156
1157 /* All done! Let's start VM execution. */
1158
1159 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1160 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1161
1162#ifdef LOG_ENABLED
1163 pCpu = HWACCMR0GetCurrentCpu();
1164 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1165 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1166 {
1167 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1168 LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1169 else
1170 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1171 }
1172 if (pCpu->fFlushTLB)
1173 LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1174#endif
1175
1176 /*
1177 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1178 * (until the actual world switch)
1179 */
1180#ifdef VBOX_STRICT
1181 idCpuCheck = RTMpCpuId();
1182#endif
1183 VMMR0LogFlushDisable(pVCpu);
1184
1185 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1186 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1187 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1188 {
1189 VMMR0LogFlushEnable(pVCpu);
1190 goto end;
1191 }
1192
1193#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1194 /* Disable interrupts to make sure a poke will interrupt execution.
1195 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1196 */
1197 uOldEFlags = ASMIntDisableFlags();
1198 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1199#endif
1200 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatEntry, &pVCpu->hwaccm.s.StatInGC, x);
1201
1202 pCpu = HWACCMR0GetCurrentCpu();
1203 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1204 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1205 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1206 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1207 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1208 {
1209 /* Force a TLB flush on VM entry. */
1210 pVCpu->hwaccm.s.fForceTLBFlush = true;
1211 }
1212 else
1213 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1214
1215 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1216
1217 /** Set TLB flush state as checked until we return from the world switch. */
1218 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1219
1220 /* Check for tlb shootdown flushes. */
1221 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1222 pVCpu->hwaccm.s.fForceTLBFlush = true;
1223
1224 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1225 if ( pVCpu->hwaccm.s.fForceTLBFlush
1226 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1227 {
1228 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1229 || pCpu->fFlushTLB)
1230 {
1231 pCpu->fFlushTLB = false;
1232 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1233 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1234 pCpu->cTLBFlushes++;
1235 }
1236 else
1237 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1238
1239 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1240 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1241 }
1242 else
1243 {
1244 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1245
1246 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1247 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1248 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1249
1250 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1251 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1252
1253 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1254 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1255 {
1256 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1257 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1258 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1259 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1260 }
1261 }
1262 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1263 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1264
1265 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1266 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1267 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1268 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1269
1270#ifdef VBOX_WITH_STATISTICS
1271 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1272 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1273 else
1274 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1275#endif
1276
1277 /* In case we execute a goto ResumeExecution later on. */
1278 pVCpu->hwaccm.s.fResumeVM = true;
1279 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1280
1281 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1282 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1283 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1284 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1285 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1286
1287#ifdef VBOX_STRICT
1288 Assert(idCpuCheck == RTMpCpuId());
1289#endif
1290 TMNotifyStartOfExecution(pVCpu);
1291#ifdef VBOX_WITH_KERNEL_USING_XMM
1292 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1293#else
1294 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1295#endif
1296 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1297 ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExit);
1298 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1299 if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1300 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1301 TMNotifyEndOfExecution(pVCpu);
1302 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1303 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatInGC, &pVCpu->hwaccm.s.StatExit1, x);
1304 ASMSetFlags(uOldEFlags);
1305#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1306 uOldEFlags = ~(RTCCUINTREG)0;
1307#endif
1308
1309 /*
1310 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1311 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1312 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1313 */
1314
1315 /* Reason for the VM exit */
1316 exitCode = pVMCB->ctrl.u64ExitCode;
1317
1318 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1319 {
1320 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1321#ifdef DEBUG
1322 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1323 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1324 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1325 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1326 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1327 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1328 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1329 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1330 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1331 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1332
1333 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1334 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1335 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1336 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1337
1338 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1339 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1340 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1341 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1342 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1343 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1344 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1345 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1346 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1347 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1348
1349 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1350 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1351 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1352 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1353 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1354 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1355 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1356 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1357 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1358 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1359 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1360 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1361 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1362 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1363 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1364 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1365 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1366
1367 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1368 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1369
1370 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1371 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1372 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1373 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1374 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1375 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1376 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1377 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1378 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1379 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1380 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1381 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1382 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1383 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1384 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1385 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1386 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1387 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1388 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1389 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1390
1391 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1392 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1393
1394 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1395 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1396 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1397 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1398
1399 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1400 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1401
1402 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1403 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1404 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1405 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1406
1407 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1408 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1409 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1410 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1411 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1412 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1413 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1414
1415 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1416 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1417 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1418 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1419
1420 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1421 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1422 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1423
1424 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1425 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1426 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1427 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1428 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1429 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1430 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1431 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1432 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1433 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1434 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1435 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1436
1437#endif
1438 rc = VERR_SVM_UNABLE_TO_START_VM;
1439 VMMR0LogFlushEnable(pVCpu);
1440 goto end;
1441 }
1442
1443 /* Let's first sync back eip, esp, and eflags. */
1444 pCtx->rip = pVMCB->guest.u64RIP;
1445 pCtx->rsp = pVMCB->guest.u64RSP;
1446 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1447 /* eax is saved/restore across the vmrun instruction */
1448 pCtx->rax = pVMCB->guest.u64RAX;
1449
1450 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1451 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1452 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1453 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1454 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1455 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1456 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1457 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1458 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1459
1460 /* Can be updated behind our back in the nested paging case. */
1461 pCtx->cr2 = pVMCB->guest.u64CR2;
1462
1463 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1464 SVM_READ_SELREG(SS, ss);
1465 SVM_READ_SELREG(CS, cs);
1466 SVM_READ_SELREG(DS, ds);
1467 SVM_READ_SELREG(ES, es);
1468 SVM_READ_SELREG(FS, fs);
1469 SVM_READ_SELREG(GS, gs);
1470
1471 /* Correct the hidden CS granularity flag. Haven't seen it being wrong in
1472 any other register (yet). */
1473 if ( !pCtx->csHid.Attr.n.u1Granularity
1474 && pCtx->csHid.Attr.n.u1Present
1475 && pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1476 {
1477 Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1478 pCtx->csHid.Attr.n.u1Granularity = 1;
1479 }
1480#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1481 AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1482 || ( pCtx->reg##Hid.Attr.n.u1Granularity \
1483 ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1484 : pCtx->reg##Hid.u32Limit <= 0xfffff), \
1485 ("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1486 SVM_ASSERT_SEL_GRANULARITY(ss);
1487 SVM_ASSERT_SEL_GRANULARITY(cs);
1488 SVM_ASSERT_SEL_GRANULARITY(ds);
1489 SVM_ASSERT_SEL_GRANULARITY(es);
1490 SVM_ASSERT_SEL_GRANULARITY(fs);
1491 SVM_ASSERT_SEL_GRANULARITY(gs);
1492#undef SVM_ASSERT_SEL_GRANULARITY
1493
1494 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1495 SVM_READ_SELREG(LDTR, ldtr);
1496 SVM_READ_SELREG(TR, tr);
1497
1498 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1499 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1500
1501 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1502 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1503
1504 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1505 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1506 if ( pVM->hwaccm.s.fNestedPaging
1507 && pCtx->cr3 != pVMCB->guest.u64CR3)
1508 {
1509 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1510 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1511 }
1512
1513 /* Note! NOW IT'S SAFE FOR LOGGING! */
1514 VMMR0LogFlushEnable(pVCpu);
1515
1516 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1517 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1518 {
1519 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1520 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1521 }
1522 else
1523 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1524
1525 Log2(("exitCode = %x\n", exitCode));
1526
1527 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1528 pCtx->dr[6] = pVMCB->guest.u64DR6;
1529 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1530 pCtx->dr[7] = pVMCB->guest.u64DR7;
1531
1532 /* Check if an injected event was interrupted prematurely. */
1533 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1534 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1535 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1536 {
1537 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1538
1539#ifdef LOG_ENABLED
1540 SVM_EVENT Event;
1541 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1542
1543 if ( exitCode == SVM_EXIT_EXCEPTION_E
1544 && Event.n.u8Vector == 0xE)
1545 {
1546 Log(("Double fault!\n"));
1547 }
1548#endif
1549
1550 pVCpu->hwaccm.s.Event.fPending = true;
1551 /* Error code present? (redundant) */
1552 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1553 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1554 else
1555 pVCpu->hwaccm.s.Event.errCode = 0;
1556 }
1557#ifdef VBOX_WITH_STATISTICS
1558 if (exitCode == SVM_EXIT_NPF)
1559 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1560 else
1561 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1562#endif
1563
1564 /* Sync back the TPR if it was changed. */
1565 if (fSyncTPR)
1566 {
1567 if (pVM->hwaccm.s.fTPRPatchingActive)
1568 {
1569 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1570 {
1571 /* Our patch code uses LSTAR for TPR caching. */
1572 rc2 = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1573 AssertRC(rc2);
1574 }
1575 }
1576 else
1577 {
1578 if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1579 {
1580 rc2 = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1581 AssertRC(rc2);
1582 }
1583 }
1584 }
1585
1586 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit1, &pVCpu->hwaccm.s.StatExit2, x);
1587
1588 /* Deal with the reason of the VM-exit. */
1589 switch (exitCode)
1590 {
1591 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1592 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1593 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1594 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1595 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1596 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1597 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1598 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1599 {
1600 /* Pending trap. */
1601 SVM_EVENT Event;
1602 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1603
1604 Log2(("Hardware/software interrupt %d\n", vector));
1605 switch (vector)
1606 {
1607 case X86_XCPT_DB:
1608 {
1609 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1610
1611 /* Note that we don't support guest and host-initiated debugging at the same time. */
1612 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1613
1614 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1615 if (rc == VINF_EM_RAW_GUEST_TRAP)
1616 {
1617 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1618
1619 /* Reinject the exception. */
1620 Event.au64[0] = 0;
1621 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1622 Event.n.u1Valid = 1;
1623 Event.n.u8Vector = X86_XCPT_DB;
1624
1625 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1626 goto ResumeExecution;
1627 }
1628 /* Return to ring 3 to deal with the debug exit code. */
1629 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1630 break;
1631 }
1632
1633 case X86_XCPT_NM:
1634 {
1635 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1636
1637 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1638 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1639 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1640 if (rc == VINF_SUCCESS)
1641 {
1642 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1643 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1644
1645 /* Continue execution. */
1646 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1647
1648 goto ResumeExecution;
1649 }
1650
1651 Log(("Forward #NM fault to the guest\n"));
1652 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1653
1654 Event.au64[0] = 0;
1655 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1656 Event.n.u1Valid = 1;
1657 Event.n.u8Vector = X86_XCPT_NM;
1658
1659 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1660 goto ResumeExecution;
1661 }
1662
1663 case X86_XCPT_PF: /* Page fault */
1664 {
1665 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1666 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1667
1668#ifdef DEBUG
1669 if (pVM->hwaccm.s.fNestedPaging)
1670 { /* A genuine pagefault.
1671 * Forward the trap to the guest by injecting the exception and resuming execution.
1672 */
1673 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1674 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1675
1676 /* Now we must update CR2. */
1677 pCtx->cr2 = uFaultAddress;
1678
1679 Event.au64[0] = 0;
1680 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1681 Event.n.u1Valid = 1;
1682 Event.n.u8Vector = X86_XCPT_PF;
1683 Event.n.u1ErrorCodeValid = 1;
1684 Event.n.u32ErrorCode = errCode;
1685
1686 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1687 goto ResumeExecution;
1688 }
1689#endif
1690 Assert(!pVM->hwaccm.s.fNestedPaging);
1691
1692#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1693 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1694 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1695 && (uFaultAddress & 0xfff) == 0x080
1696 && !(errCode & X86_TRAP_PF_P) /* not present */
1697 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1698 && !CPUMIsGuestInLongModeEx(pCtx)
1699 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1700 {
1701 RTGCPHYS GCPhysApicBase, GCPhys;
1702 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1703 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1704
1705 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1706 if ( rc == VINF_SUCCESS
1707 && GCPhys == GCPhysApicBase)
1708 {
1709 /* Only attempt to patch the instruction once. */
1710 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1711 if (!pPatch)
1712 {
1713 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1714 break;
1715 }
1716 }
1717 }
1718#endif
1719
1720 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1721 /* Exit qualification contains the linear address of the page fault. */
1722 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1723 TRPMSetErrorCode(pVCpu, errCode);
1724 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1725
1726 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1727 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1728 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1729 if (rc == VINF_SUCCESS)
1730 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1731 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1732 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1733
1734 TRPMResetTrap(pVCpu);
1735 goto ResumeExecution;
1736 }
1737 else
1738 if (rc == VINF_EM_RAW_GUEST_TRAP)
1739 { /* A genuine pagefault.
1740 * Forward the trap to the guest by injecting the exception and resuming execution.
1741 */
1742 Log2(("Forward page fault to the guest\n"));
1743 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1744 /* The error code might have been changed. */
1745 errCode = TRPMGetErrorCode(pVCpu);
1746
1747 TRPMResetTrap(pVCpu);
1748
1749 /* Now we must update CR2. */
1750 pCtx->cr2 = uFaultAddress;
1751
1752 Event.au64[0] = 0;
1753 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1754 Event.n.u1Valid = 1;
1755 Event.n.u8Vector = X86_XCPT_PF;
1756 Event.n.u1ErrorCodeValid = 1;
1757 Event.n.u32ErrorCode = errCode;
1758
1759 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1760 goto ResumeExecution;
1761 }
1762#ifdef VBOX_STRICT
1763 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1764 LogFlow(("PGMTrap0eHandler failed with %d\n", VBOXSTRICTRC_VAL(rc)));
1765#endif
1766 /* Need to go back to the recompiler to emulate the instruction. */
1767 TRPMResetTrap(pVCpu);
1768 break;
1769 }
1770
1771 case X86_XCPT_MF: /* Floating point exception. */
1772 {
1773 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1774 if (!(pCtx->cr0 & X86_CR0_NE))
1775 {
1776 /* old style FPU error reporting needs some extra work. */
1777 /** @todo don't fall back to the recompiler, but do it manually. */
1778 rc = VINF_EM_RAW_EMULATE_INSTR;
1779 break;
1780 }
1781 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1782
1783 Event.au64[0] = 0;
1784 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1785 Event.n.u1Valid = 1;
1786 Event.n.u8Vector = X86_XCPT_MF;
1787
1788 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1789 goto ResumeExecution;
1790 }
1791
1792#ifdef VBOX_STRICT
1793 case X86_XCPT_BP: /* Breakpoint. */
1794 case X86_XCPT_GP: /* General protection failure exception.*/
1795 case X86_XCPT_UD: /* Unknown opcode exception. */
1796 case X86_XCPT_DE: /* Divide error. */
1797 case X86_XCPT_SS: /* Stack segment exception. */
1798 case X86_XCPT_NP: /* Segment not present exception. */
1799 {
1800 Event.au64[0] = 0;
1801 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1802 Event.n.u1Valid = 1;
1803 Event.n.u8Vector = vector;
1804
1805 switch(vector)
1806 {
1807 case X86_XCPT_GP:
1808 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1809 Event.n.u1ErrorCodeValid = 1;
1810 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1811 break;
1812 case X86_XCPT_BP:
1813 /** Saves the wrong EIP on the stack (pointing to the int3 instead of the next instruction. */
1814 break;
1815 case X86_XCPT_DE:
1816 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1817 break;
1818 case X86_XCPT_UD:
1819 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1820 break;
1821 case X86_XCPT_SS:
1822 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1823 Event.n.u1ErrorCodeValid = 1;
1824 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1825 break;
1826 case X86_XCPT_NP:
1827 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1828 Event.n.u1ErrorCodeValid = 1;
1829 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1830 break;
1831 }
1832 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1833 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1834 goto ResumeExecution;
1835 }
1836#endif
1837 default:
1838 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1839 rc = VERR_EM_INTERNAL_ERROR;
1840 break;
1841
1842 } /* switch (vector) */
1843 break;
1844 }
1845
1846 case SVM_EXIT_NPF:
1847 {
1848 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1849 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1850 RTGCPHYS GCPhysFault = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1851 PGMMODE enmShwPagingMode;
1852
1853 Assert(pVM->hwaccm.s.fNestedPaging);
1854 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
1855
1856#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1857 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1858 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1859 && (GCPhysFault & PAGE_OFFSET_MASK) == 0x080
1860 && ( !(errCode & X86_TRAP_PF_P) /* not present */
1861 || (errCode & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P | X86_TRAP_PF_RSVD) /* mmio optimization */)
1862 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1863 && !CPUMIsGuestInLongModeEx(pCtx)
1864 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1865 {
1866 RTGCPHYS GCPhysApicBase;
1867 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1868 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1869
1870 if (GCPhysFault == GCPhysApicBase + 0x80)
1871 {
1872 /* Only attempt to patch the instruction once. */
1873 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1874 if (!pPatch)
1875 {
1876 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1877 break;
1878 }
1879 }
1880 }
1881#endif
1882
1883 /* Handle the pagefault trap for the nested shadow table. */
1884#if HC_ARCH_BITS == 32 /** @todo shadow this in a variable. */
1885 if (CPUMIsGuestInLongModeEx(pCtx))
1886 enmShwPagingMode = PGMMODE_AMD64_NX;
1887 else
1888#endif
1889 enmShwPagingMode = PGMGetHostMode(pVM);
1890
1891 /* MMIO optimization */
1892 Assert((errCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
1893 if ((errCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD | X86_TRAP_PF_P))
1894 {
1895 rc = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmShwPagingMode, CPUMCTX2CORE(pCtx), GCPhysFault, errCode);
1896 if (rc == VINF_SUCCESS)
1897 {
1898 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
1899 goto ResumeExecution;
1900 }
1901 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
1902 break;
1903 }
1904
1905 /* Exit qualification contains the linear address of the page fault. */
1906 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1907 TRPMSetErrorCode(pVCpu, errCode);
1908 TRPMSetFaultAddress(pVCpu, GCPhysFault);
1909
1910 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), GCPhysFault);
1911 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1912 if (rc == VINF_SUCCESS)
1913 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1914 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
1915 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1916
1917 TRPMResetTrap(pVCpu);
1918 goto ResumeExecution;
1919 }
1920
1921#ifdef VBOX_STRICT
1922 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1923 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", VBOXSTRICTRC_VAL(rc)));
1924#endif
1925 /* Need to go back to the recompiler to emulate the instruction. */
1926 TRPMResetTrap(pVCpu);
1927 break;
1928 }
1929
1930 case SVM_EXIT_VINTR:
1931 /* A virtual interrupt is about to be delivered, which means IF=1. */
1932 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1933 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1934 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1935 goto ResumeExecution;
1936
1937 case SVM_EXIT_FERR_FREEZE:
1938 case SVM_EXIT_INTR:
1939 case SVM_EXIT_NMI:
1940 case SVM_EXIT_SMI:
1941 case SVM_EXIT_INIT:
1942 /* External interrupt; leave to allow it to be dispatched again. */
1943 rc = VINF_EM_RAW_INTERRUPT;
1944 break;
1945
1946 case SVM_EXIT_WBINVD:
1947 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1948 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1949 /* Skip instruction and continue directly. */
1950 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1951 /* Continue execution.*/
1952 goto ResumeExecution;
1953
1954 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1955 {
1956 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1957 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1958 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1959 if (rc == VINF_SUCCESS)
1960 {
1961 /* Update EIP and continue execution. */
1962 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1963 goto ResumeExecution;
1964 }
1965 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1966 rc = VINF_EM_RAW_EMULATE_INSTR;
1967 break;
1968 }
1969
1970 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1971 {
1972 Log2(("SVM: Rdtsc\n"));
1973 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1974 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1975 if (rc == VINF_SUCCESS)
1976 {
1977 /* Update EIP and continue execution. */
1978 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1979 goto ResumeExecution;
1980 }
1981 rc = VINF_EM_RAW_EMULATE_INSTR;
1982 break;
1983 }
1984
1985 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1986 {
1987 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1988 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1989 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1990 if (rc == VINF_SUCCESS)
1991 {
1992 /* Update EIP and continue execution. */
1993 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1994 goto ResumeExecution;
1995 }
1996 rc = VINF_EM_RAW_EMULATE_INSTR;
1997 break;
1998 }
1999
2000 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
2001 {
2002 Log2(("SVM: Rdtscp\n"));
2003 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2004 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
2005 if (rc == VINF_SUCCESS)
2006 {
2007 /* Update EIP and continue execution. */
2008 pCtx->rip += 3; /* Note! hardcoded opcode size! */
2009 goto ResumeExecution;
2010 }
2011 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2012 rc = VINF_EM_RAW_EMULATE_INSTR;
2013 break;
2014 }
2015
2016 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
2017 {
2018 Log2(("SVM: invlpg\n"));
2019 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2020
2021 Assert(!pVM->hwaccm.s.fNestedPaging);
2022
2023 /* Truly a pita. Why can't SVM give the same information as VT-x? */
2024 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
2025 if (rc == VINF_SUCCESS)
2026 {
2027 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
2028 goto ResumeExecution; /* eip already updated */
2029 }
2030 break;
2031 }
2032
2033 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2034 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2035 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2036 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2037 {
2038 uint32_t cbSize;
2039
2040 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2041 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2042 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2043
2044 switch (exitCode - SVM_EXIT_WRITE_CR0)
2045 {
2046 case 0:
2047 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2048 break;
2049 case 2:
2050 break;
2051 case 3:
2052 Assert(!pVM->hwaccm.s.fNestedPaging);
2053 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2054 break;
2055 case 4:
2056 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2057 break;
2058 case 8:
2059 break;
2060 default:
2061 AssertFailed();
2062 }
2063 if (rc == VINF_SUCCESS)
2064 {
2065 /* EIP has been updated already. */
2066
2067 /* Only resume if successful. */
2068 goto ResumeExecution;
2069 }
2070 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2071 break;
2072 }
2073
2074 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2075 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2076 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2077 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2078 {
2079 uint32_t cbSize;
2080
2081 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2082 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2083 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2084 if (rc == VINF_SUCCESS)
2085 {
2086 /* EIP has been updated already. */
2087
2088 /* Only resume if successful. */
2089 goto ResumeExecution;
2090 }
2091 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2092 break;
2093 }
2094
2095 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2096 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2097 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2098 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2099 {
2100 uint32_t cbSize;
2101
2102 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2103 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2104
2105 if ( !DBGFIsStepping(pVCpu)
2106 && !CPUMIsHyperDebugStateActive(pVCpu))
2107 {
2108 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2109
2110 /* Disable drx move intercepts. */
2111 pVMCB->ctrl.u16InterceptRdDRx = 0;
2112 pVMCB->ctrl.u16InterceptWrDRx = 0;
2113
2114 /* Save the host and load the guest debug state. */
2115 rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2116 AssertRC(rc2);
2117 goto ResumeExecution;
2118 }
2119
2120 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2121 if (rc == VINF_SUCCESS)
2122 {
2123 /* EIP has been updated already. */
2124 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2125
2126 /* Only resume if successful. */
2127 goto ResumeExecution;
2128 }
2129 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2130 break;
2131 }
2132
2133 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2134 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2135 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2136 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2137 {
2138 uint32_t cbSize;
2139
2140 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2141 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2142
2143 if (!DBGFIsStepping(pVCpu))
2144 {
2145 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2146
2147 /* Disable drx move intercepts. */
2148 pVMCB->ctrl.u16InterceptRdDRx = 0;
2149 pVMCB->ctrl.u16InterceptWrDRx = 0;
2150
2151 /* Save the host and load the guest debug state. */
2152 rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2153 AssertRC(rc2);
2154 goto ResumeExecution;
2155 }
2156
2157 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2158 if (rc == VINF_SUCCESS)
2159 {
2160 /* EIP has been updated already. */
2161
2162 /* Only resume if successful. */
2163 goto ResumeExecution;
2164 }
2165 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2166 break;
2167 }
2168
2169 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2170 case SVM_EXIT_IOIO: /* I/O instruction. */
2171 {
2172 SVM_IOIO_EXIT IoExitInfo;
2173 uint32_t uIOSize, uAndVal;
2174
2175 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2176
2177 /** @todo could use a lookup table here */
2178 if (IoExitInfo.n.u1OP8)
2179 {
2180 uIOSize = 1;
2181 uAndVal = 0xff;
2182 }
2183 else
2184 if (IoExitInfo.n.u1OP16)
2185 {
2186 uIOSize = 2;
2187 uAndVal = 0xffff;
2188 }
2189 else
2190 if (IoExitInfo.n.u1OP32)
2191 {
2192 uIOSize = 4;
2193 uAndVal = 0xffffffff;
2194 }
2195 else
2196 {
2197 AssertFailed(); /* should be fatal. */
2198 rc = VINF_EM_RAW_EMULATE_INSTR;
2199 break;
2200 }
2201
2202 if (IoExitInfo.n.u1STR)
2203 {
2204 /* ins/outs */
2205 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2206
2207 /* Disassemble manually to deal with segment prefixes. */
2208 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2209 if (rc == VINF_SUCCESS)
2210 {
2211 if (IoExitInfo.n.u1Type == 0)
2212 {
2213 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2214 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2215 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2216 }
2217 else
2218 {
2219 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2220 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2221 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize);
2222 }
2223 }
2224 else
2225 rc = VINF_EM_RAW_EMULATE_INSTR;
2226 }
2227 else
2228 {
2229 /* normal in/out */
2230 Assert(!IoExitInfo.n.u1REP);
2231
2232 if (IoExitInfo.n.u1Type == 0)
2233 {
2234 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2235 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2236 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2237 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2238 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2239 }
2240 else
2241 {
2242 uint32_t u32Val = 0;
2243
2244 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2245 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2246 if (IOM_SUCCESS(rc))
2247 {
2248 /* Write back to the EAX register. */
2249 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2250 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2251 }
2252 else
2253 if (rc == VINF_IOM_HC_IOPORT_READ)
2254 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2255 }
2256 }
2257 /*
2258 * Handled the I/O return codes.
2259 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2260 */
2261 if (IOM_SUCCESS(rc))
2262 {
2263 /* Update EIP and continue execution. */
2264 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2265 if (RT_LIKELY(rc == VINF_SUCCESS))
2266 {
2267 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2268 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2269 {
2270 /* IO operation lookup arrays. */
2271 static uint32_t const aIOSize[4] = {1, 2, 0, 4};
2272
2273 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2274 for (unsigned i=0;i<4;i++)
2275 {
2276 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2277
2278 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2279 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2280 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2281 {
2282 SVM_EVENT Event;
2283
2284 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2285
2286 /* Clear all breakpoint status flags and set the one we just hit. */
2287 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2288 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2289
2290 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2291 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2292 * the contents have been read.
2293 */
2294 pVMCB->guest.u64DR6 = pCtx->dr[6];
2295
2296 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2297 pCtx->dr[7] &= ~X86_DR7_GD;
2298
2299 /* Paranoia. */
2300 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2301 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2302 pCtx->dr[7] |= 0x400; /* must be one */
2303
2304 pVMCB->guest.u64DR7 = pCtx->dr[7];
2305
2306 /* Inject the exception. */
2307 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2308
2309 Event.au64[0] = 0;
2310 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2311 Event.n.u1Valid = 1;
2312 Event.n.u8Vector = X86_XCPT_DB;
2313
2314 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2315 goto ResumeExecution;
2316 }
2317 }
2318 }
2319 goto ResumeExecution;
2320 }
2321 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, VBOXSTRICTRC_VAL(rc)));
2322 break;
2323 }
2324
2325#ifdef VBOX_STRICT
2326 if (rc == VINF_IOM_HC_IOPORT_READ)
2327 Assert(IoExitInfo.n.u1Type != 0);
2328 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2329 Assert(IoExitInfo.n.u1Type == 0);
2330 else
2331 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
2332#endif
2333 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2334 break;
2335 }
2336
2337 case SVM_EXIT_HLT:
2338 /** Check if external interrupts are pending; if so, don't switch back. */
2339 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2340 pCtx->rip++; /* skip hlt */
2341 if (EMShouldContinueAfterHalt(pVCpu, pCtx))
2342 goto ResumeExecution;
2343
2344 rc = VINF_EM_HALT;
2345 break;
2346
2347 case SVM_EXIT_MWAIT_UNCOND:
2348 Log2(("SVM: mwait\n"));
2349 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2350 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2351 if ( rc == VINF_EM_HALT
2352 || rc == VINF_SUCCESS)
2353 {
2354 /* Update EIP and continue execution. */
2355 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2356
2357 /** Check if external interrupts are pending; if so, don't switch back. */
2358 if ( rc == VINF_SUCCESS
2359 || ( rc == VINF_EM_HALT
2360 && EMShouldContinueAfterHalt(pVCpu, pCtx))
2361 )
2362 goto ResumeExecution;
2363 }
2364 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2365 break;
2366
2367 case SVM_EXIT_MONITOR:
2368 {
2369 Log2(("SVM: monitor\n"));
2370
2371 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMonitor);
2372 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2373 if (rc == VINF_SUCCESS)
2374 {
2375 /* Update EIP and continue execution. */
2376 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2377 goto ResumeExecution;
2378 }
2379 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2380 break;
2381 }
2382
2383
2384 case SVM_EXIT_VMMCALL:
2385 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2386 if (rc == VINF_SUCCESS)
2387 {
2388 goto ResumeExecution; /* rip already updated. */
2389 }
2390 /* no break */
2391
2392 case SVM_EXIT_RSM:
2393 case SVM_EXIT_INVLPGA:
2394 case SVM_EXIT_VMRUN:
2395 case SVM_EXIT_VMLOAD:
2396 case SVM_EXIT_VMSAVE:
2397 case SVM_EXIT_STGI:
2398 case SVM_EXIT_CLGI:
2399 case SVM_EXIT_SKINIT:
2400 {
2401 /* Unsupported instructions. */
2402 SVM_EVENT Event;
2403
2404 Event.au64[0] = 0;
2405 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2406 Event.n.u1Valid = 1;
2407 Event.n.u8Vector = X86_XCPT_UD;
2408
2409 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2410 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2411 goto ResumeExecution;
2412 }
2413
2414 /* Emulate in ring 3. */
2415 case SVM_EXIT_MSR:
2416 {
2417 uint32_t cbSize;
2418
2419 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2420 if ( pVM->hwaccm.s.fTPRPatchingActive
2421 && pCtx->ecx == MSR_K8_LSTAR
2422 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2423 {
2424 if ((pCtx->eax & 0xff) != u8LastTPR)
2425 {
2426 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2427
2428 /* Our patch code uses LSTAR for TPR caching. */
2429 rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2430 AssertRC(rc2);
2431 }
2432
2433 /* Skip the instruction and continue. */
2434 pCtx->rip += 2; /* wrmsr = [0F 30] */
2435
2436 /* Only resume if successful. */
2437 goto ResumeExecution;
2438 }
2439
2440 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2441 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2442 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2443 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2444 if (rc == VINF_SUCCESS)
2445 {
2446 /* EIP has been updated already. */
2447
2448 /* Only resume if successful. */
2449 goto ResumeExecution;
2450 }
2451 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", VBOXSTRICTRC_VAL(rc)));
2452 break;
2453 }
2454
2455 case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
2456 Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2457 if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
2458 && pVCpu->hwaccm.s.Event.fPending)
2459 {
2460 SVM_EVENT Event;
2461
2462 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2463
2464 /* Caused by an injected interrupt. */
2465 pVCpu->hwaccm.s.Event.fPending = false;
2466
2467 switch (Event.n.u3Type)
2468 {
2469 case SVM_EVENT_EXTERNAL_IRQ:
2470 case SVM_EVENT_NMI:
2471 Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2472 Assert(!Event.n.u1ErrorCodeValid);
2473 rc2 = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2474 AssertRC(rc2);
2475 break;
2476
2477 default:
2478 /* Exceptions and software interrupts can just be restarted. */
2479 break;
2480 }
2481 }
2482 rc = VERR_EM_INTERPRETER;
2483 break;
2484
2485 case SVM_EXIT_PAUSE:
2486 case SVM_EXIT_MWAIT_ARMED:
2487 rc = VERR_EM_INTERPRETER;
2488 break;
2489
2490 case SVM_EXIT_SHUTDOWN:
2491 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2492 break;
2493
2494 case SVM_EXIT_IDTR_READ:
2495 case SVM_EXIT_GDTR_READ:
2496 case SVM_EXIT_LDTR_READ:
2497 case SVM_EXIT_TR_READ:
2498 case SVM_EXIT_IDTR_WRITE:
2499 case SVM_EXIT_GDTR_WRITE:
2500 case SVM_EXIT_LDTR_WRITE:
2501 case SVM_EXIT_TR_WRITE:
2502 case SVM_EXIT_CR0_SEL_WRITE:
2503 default:
2504 /* Unexpected exit codes. */
2505 rc = VERR_EM_INTERNAL_ERROR;
2506 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2507 break;
2508 }
2509
2510end:
2511
2512 /* We now going back to ring-3, so clear the action flag. */
2513 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2514
2515 /* Signal changes for the recompiler. */
2516 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2517
2518 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2519 if (exitCode == SVM_EXIT_INTR)
2520 {
2521 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2522 /* On the next entry we'll only sync the host context. */
2523 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2524 }
2525 else
2526 {
2527 /* On the next entry we'll sync everything. */
2528 /** @todo we can do better than this */
2529 /* Not in the VINF_PGM_CHANGE_MODE though! */
2530 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2531 }
2532
2533 /* translate into a less severe return code */
2534 if (rc == VERR_EM_INTERPRETER)
2535 rc = VINF_EM_RAW_EMULATE_INSTR;
2536
2537 /* Just set the correct state here instead of trying to catch every goto above. */
2538 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2539
2540#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2541 /* Restore interrupts if we exitted after disabling them. */
2542 if (uOldEFlags != ~(RTCCUINTREG)0)
2543 ASMSetFlags(uOldEFlags);
2544#endif
2545
2546 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, x);
2547 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2548 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
2549 return VBOXSTRICTRC_TODO(rc);
2550}
2551
2552/**
2553 * Emulate simple mov tpr instruction
2554 *
2555 * @returns VBox status code.
2556 * @param pVM The VM to operate on.
2557 * @param pVCpu The VM CPU to operate on.
2558 * @param pCtx CPU context
2559 */
2560static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2561{
2562 int rc;
2563
2564 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2565
2566 while (true)
2567 {
2568 bool fPending;
2569 uint8_t u8Tpr;
2570
2571 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2572 if (!pPatch)
2573 break;
2574
2575 switch(pPatch->enmType)
2576 {
2577 case HWACCMTPRINSTR_READ:
2578 /* TPR caching in CR8 */
2579 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2580 AssertRC(rc);
2581
2582 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2583 AssertRC(rc);
2584
2585 LogFlow(("Emulated read successfully\n"));
2586 pCtx->rip += pPatch->cbOp;
2587 break;
2588
2589 case HWACCMTPRINSTR_WRITE_REG:
2590 case HWACCMTPRINSTR_WRITE_IMM:
2591 /* Fetch the new TPR value */
2592 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2593 {
2594 uint32_t val;
2595
2596 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2597 AssertRC(rc);
2598 u8Tpr = val;
2599 }
2600 else
2601 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2602
2603 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2604 AssertRC(rc);
2605 LogFlow(("Emulated write successfully\n"));
2606 pCtx->rip += pPatch->cbOp;
2607 break;
2608 default:
2609 AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_INTERNAL_ERROR);
2610 }
2611 }
2612 return VINF_SUCCESS;
2613}
2614
2615
2616/**
2617 * Enters the AMD-V session
2618 *
2619 * @returns VBox status code.
2620 * @param pVM The VM to operate on.
2621 * @param pVCpu The VM CPU to operate on.
2622 * @param pCpu CPU info struct
2623 */
2624VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2625{
2626 Assert(pVM->hwaccm.s.svm.fSupported);
2627
2628 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2629 pVCpu->hwaccm.s.fResumeVM = false;
2630
2631 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2632 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2633
2634 return VINF_SUCCESS;
2635}
2636
2637
2638/**
2639 * Leaves the AMD-V session
2640 *
2641 * @returns VBox status code.
2642 * @param pVM The VM to operate on.
2643 * @param pVCpu The VM CPU to operate on.
2644 * @param pCtx CPU context
2645 */
2646VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2647{
2648 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2649
2650 Assert(pVM->hwaccm.s.svm.fSupported);
2651
2652#ifdef DEBUG
2653 if (CPUMIsHyperDebugStateActive(pVCpu))
2654 {
2655 CPUMR0LoadHostDebugState(pVM, pVCpu);
2656 }
2657 else
2658#endif
2659 /* Save the guest debug state if necessary. */
2660 if (CPUMIsGuestDebugStateActive(pVCpu))
2661 {
2662 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2663
2664 /* Intercept all DRx reads and writes again. Changed later on. */
2665 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2666 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2667
2668 /* Resync the debug registers the next time. */
2669 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2670 }
2671 else
2672 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2673
2674 return VINF_SUCCESS;
2675}
2676
2677
2678static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2679{
2680 OP_PARAMVAL param1;
2681 RTGCPTR addr;
2682
2683 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2684 if(RT_FAILURE(rc))
2685 return VERR_EM_INTERPRETER;
2686
2687 switch(param1.type)
2688 {
2689 case PARMTYPE_IMMEDIATE:
2690 case PARMTYPE_ADDRESS:
2691 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2692 return VERR_EM_INTERPRETER;
2693 addr = param1.val.val64;
2694 break;
2695
2696 default:
2697 return VERR_EM_INTERPRETER;
2698 }
2699
2700 /** @todo is addr always a flat linear address or ds based
2701 * (in absence of segment override prefixes)????
2702 */
2703 rc = PGMInvalidatePage(pVCpu, addr);
2704 if (RT_SUCCESS(rc))
2705 return VINF_SUCCESS;
2706
2707 AssertRC(rc);
2708 return rc;
2709}
2710
2711/**
2712 * Interprets INVLPG
2713 *
2714 * @returns VBox status code.
2715 * @retval VINF_* Scheduling instructions.
2716 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2717 * @retval VERR_* Fatal errors.
2718 *
2719 * @param pVM The VM handle.
2720 * @param pRegFrame The register frame.
2721 * @param ASID Tagged TLB id for the guest
2722 *
2723 * Updates the EIP if an instruction was executed successfully.
2724 */
2725static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2726{
2727 /*
2728 * Only allow 32 & 64 bits code.
2729 */
2730 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2731 if (enmMode != CPUMODE_16BIT)
2732 {
2733 RTGCPTR pbCode;
2734 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
2735 &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2736 if (RT_SUCCESS(rc))
2737 {
2738 uint32_t cbOp;
2739 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2740
2741 pDis->mode = enmMode;
2742 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2743 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2744 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2745 {
2746 Assert(cbOp == pDis->opsize);
2747 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2748 if (RT_SUCCESS(rc))
2749 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2750
2751 return rc;
2752 }
2753 }
2754 }
2755 return VERR_EM_INTERPRETER;
2756}
2757
2758
2759/**
2760 * Invalidates a guest page
2761 *
2762 * @returns VBox status code.
2763 * @param pVM The VM to operate on.
2764 * @param pVCpu The VM CPU to operate on.
2765 * @param GCVirt Page to invalidate
2766 */
2767VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2768{
2769 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2770
2771 /* Skip it if a TLB flush is already pending. */
2772 if (!fFlushPending)
2773 {
2774 SVM_VMCB *pVMCB;
2775
2776 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2777 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2778 Assert(pVM->hwaccm.s.svm.fSupported);
2779
2780 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2781 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2782
2783#if HC_ARCH_BITS == 32
2784 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2785 if (CPUMIsGuestInLongMode(pVCpu))
2786 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2787 else
2788#endif
2789 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2790 }
2791 return VINF_SUCCESS;
2792}
2793
2794
2795#if 0 /* obsolete, but left here for clarification. */
2796/**
2797 * Invalidates a guest page by physical address
2798 *
2799 * @returns VBox status code.
2800 * @param pVM The VM to operate on.
2801 * @param pVCpu The VM CPU to operate on.
2802 * @param GCPhys Page to invalidate
2803 */
2804VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2805{
2806 Assert(pVM->hwaccm.s.fNestedPaging);
2807 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2808 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2809 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2810 return VINF_SUCCESS;
2811}
2812#endif
2813
2814#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2815/**
2816 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2817 *
2818 * @returns VBox status code.
2819 * @param pVMCBHostPhys Physical address of host VMCB.
2820 * @param pVMCBPhys Physical address of the VMCB.
2821 * @param pCtx Guest context.
2822 * @param pVM The VM to operate on.
2823 * @param pVCpu The VMCPU to operate on.
2824 */
2825DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2826{
2827 uint32_t aParam[4];
2828
2829 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2830 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2831 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2832 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2833
2834 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2835}
2836
2837/**
2838 * Executes the specified handler in 64 mode
2839 *
2840 * @returns VBox status code.
2841 * @param pVM The VM to operate on.
2842 * @param pVCpu The VMCPU to operate on.
2843 * @param pCtx Guest context
2844 * @param pfnHandler RC handler
2845 * @param cbParam Number of parameters
2846 * @param paParam Array of 32 bits parameters
2847 */
2848VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2849{
2850 int rc;
2851 RTHCUINTREG uOldEFlags;
2852
2853 Assert(pfnHandler);
2854
2855 /* Disable interrupts. */
2856 uOldEFlags = ASMIntDisableFlags();
2857
2858 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
2859 CPUMSetHyperEIP(pVCpu, pfnHandler);
2860 for (int i=(int)cbParam-1;i>=0;i--)
2861 CPUMPushHyper(pVCpu, paParam[i]);
2862
2863 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2864 /* Call switcher. */
2865 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
2866 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2867
2868 ASMSetFlags(uOldEFlags);
2869 return rc;
2870}
2871
2872#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
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