VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 39436

Last change on this file since 39436 was 39402, checked in by vboxsync, 13 years ago

VMM: don't use generic IPE status codes, use specific ones. Part 1.
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1/* $Id: HWSVMR0.cpp 39402 2011-11-23 16:25:04Z vboxsync $ */
2/** @file
3 * HM SVM (AMD-V) - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/vmm/hwaccm.h>
23#include <VBox/vmm/pgm.h>
24#include <VBox/vmm/selm.h>
25#include <VBox/vmm/iom.h>
26#include <VBox/vmm/dbgf.h>
27#include <VBox/vmm/tm.h>
28#include <VBox/vmm/pdmapi.h>
29#include "HWACCMInternal.h"
30#include <VBox/vmm/vm.h>
31#include <VBox/vmm/hwacc_svm.h>
32#include <VBox/err.h>
33#include <VBox/log.h>
34#include <VBox/dis.h>
35#include <VBox/disopcode.h>
36#include <iprt/param.h>
37#include <iprt/assert.h>
38#include <iprt/asm.h>
39#include <iprt/asm-amd64-x86.h>
40#include <iprt/cpuset.h>
41#include <iprt/mp.h>
42#include <iprt/time.h>
43#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
44# include <iprt/thread.h>
45#endif
46#include <iprt/x86.h>
47#include "HWSVMR0.h"
48
49/*******************************************************************************
50* Internal Functions *
51*******************************************************************************/
52static int hmR0SvmInterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
53static int hmR0SvmEmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
54static void hmR0SvmSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
55
56/*******************************************************************************
57* Global Variables *
58*******************************************************************************/
59
60/**
61 * Sets up and activates AMD-V on the current CPU
62 *
63 * @returns VBox status code.
64 * @param pCpu CPU info struct
65 * @param pVM The VM to operate on. (can be NULL after a resume!!)
66 * @param pvCpuPage Pointer to the global cpu page.
67 * @param HCPhysCpuPage Physical address of the global cpu page.
68 */
69VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
70{
71 AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
72 AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
73
74 /* We must turn on AMD-V and setup the host state physical address, as
75 those MSRs are per-cpu/core. */
76 uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
77 if (fEfer & MSR_K6_EFER_SVME)
78 {
79 /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we
80 blindly use AMD-V. */
81 if ( pVM
82 && pVM->hwaccm.s.svm.fIgnoreInUseError)
83 pCpu->fIgnoreAMDVInUseError = true;
84 if (!pCpu->fIgnoreAMDVInUseError)
85 return VERR_SVM_IN_USE;
86 }
87
88 /* Turn on AMD-V in the EFER MSR. */
89 ASMWrMsr(MSR_K6_EFER, fEfer | MSR_K6_EFER_SVME);
90
91 /* Write the physical page address where the CPU will store the host state
92 while executing the VM. */
93 ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
94
95 return VINF_SUCCESS;
96}
97
98/**
99 * Deactivates AMD-V on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pvCpuPage Pointer to the global cpu page.
104 * @param HCPhysCpuPage Physical address of the global cpu page.
105 */
106VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
107{
108 AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
109 AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
110 NOREF(pCpu);
111
112 /* Turn off AMD-V in the EFER MSR. */
113 uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
114 ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
115
116 /* Invalidate host state physical address. */
117 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
118
119 return VINF_SUCCESS;
120}
121
122/**
123 * Does Ring-0 per VM AMD-V init.
124 *
125 * @returns VBox status code.
126 * @param pVM The VM to operate on.
127 */
128VMMR0DECL(int) SVMR0InitVM(PVM pVM)
129{
130 int rc;
131
132 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
133
134 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
135 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
136 if (RT_FAILURE(rc))
137 return rc;
138
139 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
140 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
141 /* Set all bits to intercept all IO accesses. */
142 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
143
144 /* Erratum 170 which requires a forced TLB flush for each world switch:
145 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
146 *
147 * All BH-G1/2 and DH-G1/2 models include a fix:
148 * Athlon X2: 0x6b 1/2
149 * 0x68 1/2
150 * Athlon 64: 0x7f 1
151 * 0x6f 2
152 * Sempron: 0x7f 1/2
153 * 0x6f 2
154 * 0x6c 2
155 * 0x7c 2
156 * Turion 64: 0x68 2
157 *
158 */
159 uint32_t u32Dummy;
160 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
161 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
162 u32BaseFamily= (u32Version >> 8) & 0xf;
163 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
164 u32Model = ((u32Version >> 4) & 0xf);
165 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
166 u32Stepping = u32Version & 0xf;
167 if ( u32Family == 0xf
168 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
169 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
170 {
171 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
172 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
173 }
174
175 /* Allocate VMCBs for all guest CPUs. */
176 for (VMCPUID i = 0; i < pVM->cCpus; i++)
177 {
178 PVMCPU pVCpu = &pVM->aCpus[i];
179
180 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
181 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
182 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
183
184 /* Allocate one page for the host context */
185 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
186 if (RT_FAILURE(rc))
187 return rc;
188
189 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
190 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
191 Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
192 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
193
194 /* Allocate one page for the VM control block (VMCB). */
195 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
196 if (RT_FAILURE(rc))
197 return rc;
198
199 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
200 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
201 Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
202 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
203
204 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
205 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
206 if (RT_FAILURE(rc))
207 return rc;
208
209 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
210 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
211 /* Set all bits to intercept all MSR accesses. */
212 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
213 }
214
215 return VINF_SUCCESS;
216}
217
218/**
219 * Does Ring-0 per VM AMD-V termination.
220 *
221 * @returns VBox status code.
222 * @param pVM The VM to operate on.
223 */
224VMMR0DECL(int) SVMR0TermVM(PVM pVM)
225{
226 for (VMCPUID i = 0; i < pVM->cCpus; i++)
227 {
228 PVMCPU pVCpu = &pVM->aCpus[i];
229
230 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
231 {
232 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
233 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
234 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
235 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
236 }
237
238 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
239 {
240 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
241 pVCpu->hwaccm.s.svm.pVMCB = 0;
242 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
243 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
244 }
245 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
246 {
247 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
248 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
249 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
250 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
251 }
252 }
253 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
254 {
255 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
256 pVM->hwaccm.s.svm.pIOBitmap = 0;
257 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
258 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
259 }
260 return VINF_SUCCESS;
261}
262
263/**
264 * Sets up AMD-V for the specified VM
265 *
266 * @returns VBox status code.
267 * @param pVM The VM to operate on.
268 */
269VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
270{
271 int rc = VINF_SUCCESS;
272
273 AssertReturn(pVM, VERR_INVALID_PARAMETER);
274
275 Assert(pVM->hwaccm.s.svm.fSupported);
276
277 for (VMCPUID i = 0; i < pVM->cCpus; i++)
278 {
279 PVMCPU pVCpu = &pVM->aCpus[i];
280 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
281
282 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_HMSVM_INVALID_PVMCB);
283
284 /* Program the control fields. Most of them never have to be changed again. */
285 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
286 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
287 if (!pVM->hwaccm.s.fNestedPaging)
288 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
289 else
290 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
291
292 /*
293 * CR0/3/4 writes must be intercepted for obvious reasons.
294 */
295 if (!pVM->hwaccm.s.fNestedPaging)
296 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
297 else
298 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4);
299
300 /* Intercept all DRx reads and writes by default. Changed later on. */
301 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
302 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
303
304 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
305 * All breakpoints are automatically cleared when the VM exits.
306 */
307
308 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
309#ifndef DEBUG
310 if (pVM->hwaccm.s.fNestedPaging)
311 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
312#endif
313
314 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
315 | SVM_CTRL1_INTERCEPT_VINTR
316 | SVM_CTRL1_INTERCEPT_NMI
317 | SVM_CTRL1_INTERCEPT_SMI
318 | SVM_CTRL1_INTERCEPT_INIT
319 | SVM_CTRL1_INTERCEPT_RDPMC
320 | SVM_CTRL1_INTERCEPT_CPUID
321 | SVM_CTRL1_INTERCEPT_RSM
322 | SVM_CTRL1_INTERCEPT_HLT
323 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
324 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
325 | SVM_CTRL1_INTERCEPT_INVLPG
326 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
327 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
328 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
329 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
330 ;
331 /* With nested paging we don't care about invlpg anymore. */
332 if (pVM->hwaccm.s.fNestedPaging)
333 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
334
335 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
336 | SVM_CTRL2_INTERCEPT_VMMCALL
337 | SVM_CTRL2_INTERCEPT_VMLOAD
338 | SVM_CTRL2_INTERCEPT_VMSAVE
339 | SVM_CTRL2_INTERCEPT_STGI
340 | SVM_CTRL2_INTERCEPT_CLGI
341 | SVM_CTRL2_INTERCEPT_SKINIT
342 | SVM_CTRL2_INTERCEPT_WBINVD
343 | SVM_CTRL2_INTERCEPT_MONITOR
344 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
345 ;
346 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
347 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
348 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
349
350 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
351 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
352 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
353 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
354
355 /* Set IO and MSR bitmap addresses. */
356 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
357 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
358
359 /* No LBR virtualization. */
360 pVMCB->ctrl.u64LBRVirt = 0;
361
362 /** The ASID must start at 1; the host uses 0. */
363 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
364
365 /** Setup the PAT msr (nested paging only) */
366 /* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB, so choose type 6 for all PAT slots. */
367 pVMCB->guest.u64GPAT = 0x0006060606060606ULL;
368
369 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
370 * to modify them directly.
371 */
372 hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
373 hmR0SvmSetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
374 hmR0SvmSetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
375 hmR0SvmSetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
376 hmR0SvmSetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
377 hmR0SvmSetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
378 hmR0SvmSetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
379 hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
380 hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
381 hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
382 }
383
384 return rc;
385}
386
387
388/**
389 * Sets the permission bits for the specified MSR
390 *
391 * @param pVCpu The VMCPU to operate on.
392 * @param ulMSR MSR value
393 * @param fRead Reading allowed/disallowed
394 * @param fWrite Writing allowed/disallowed
395 */
396static void hmR0SvmSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
397{
398 unsigned ulBit;
399 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
400
401 if (ulMSR <= 0x00001FFF)
402 {
403 /* Pentium-compatible MSRs */
404 ulBit = ulMSR * 2;
405 }
406 else
407 if ( ulMSR >= 0xC0000000
408 && ulMSR <= 0xC0001FFF)
409 {
410 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
411 ulBit = (ulMSR - 0xC0000000) * 2;
412 pMSRBitmap += 0x800;
413 }
414 else
415 if ( ulMSR >= 0xC0010000
416 && ulMSR <= 0xC0011FFF)
417 {
418 /* AMD Seventh and Eighth Generation Processor MSRs */
419 ulBit = (ulMSR - 0xC0001000) * 2;
420 pMSRBitmap += 0x1000;
421 }
422 else
423 {
424 AssertFailed();
425 return;
426 }
427 Assert(ulBit < 16 * 1024 - 1);
428 if (fRead)
429 ASMBitClear(pMSRBitmap, ulBit);
430 else
431 ASMBitSet(pMSRBitmap, ulBit);
432
433 if (fWrite)
434 ASMBitClear(pMSRBitmap, ulBit + 1);
435 else
436 ASMBitSet(pMSRBitmap, ulBit + 1);
437}
438
439/**
440 * Injects an event (trap or external interrupt)
441 *
442 * @param pVCpu The VMCPU to operate on.
443 * @param pVMCB SVM control block
444 * @param pCtx CPU Context
445 * @param pIntInfo SVM interrupt info
446 */
447DECLINLINE(void) hmR0SvmInjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT *pEvent)
448{
449#ifdef VBOX_WITH_STATISTICS
450 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
451#endif
452
453#ifdef VBOX_STRICT
454 if (pEvent->n.u8Vector == 0xE)
455 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
456 else
457 if (pEvent->n.u8Vector < 0x20)
458 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
459 else
460 {
461 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
462 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
463 Assert(pCtx->eflags.u32 & X86_EFL_IF);
464 }
465#endif
466
467 /* Set event injection state. */
468 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
469}
470
471
472/**
473 * Checks for pending guest interrupts and injects them
474 *
475 * @returns VBox status code.
476 * @param pVM The VM to operate on.
477 * @param pVCpu The VM CPU to operate on.
478 * @param pVMCB SVM control block
479 * @param pCtx CPU Context
480 */
481static int hmR0SvmCheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
482{
483 int rc;
484 NOREF(pVM);
485
486 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
487 if (pVCpu->hwaccm.s.Event.fPending)
488 {
489 SVM_EVENT Event;
490
491 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
492 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
493 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
494 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
495
496 pVCpu->hwaccm.s.Event.fPending = false;
497 return VINF_SUCCESS;
498 }
499
500 /* If an active trap is already pending, then we must forward it first! */
501 if (!TRPMHasTrap(pVCpu))
502 {
503 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
504 {
505 SVM_EVENT Event;
506
507 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
508 Event.n.u8Vector = X86_XCPT_NMI;
509 Event.n.u1Valid = 1;
510 Event.n.u32ErrorCode = 0;
511 Event.n.u3Type = SVM_EVENT_NMI;
512
513 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
514 return VINF_SUCCESS;
515 }
516
517 /* @todo SMI interrupts. */
518
519 /* When external interrupts are pending, we should exit the VM when IF is set. */
520 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
521 {
522 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
523 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
524 {
525 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
526 {
527 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
528 LogFlow(("Enable irq window exit!\n"));
529 else
530 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
531
532 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
533 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
534 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
535 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
536 }
537 }
538 else
539 {
540 uint8_t u8Interrupt;
541
542 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
543 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
544 if (RT_SUCCESS(rc))
545 {
546 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
547 AssertRC(rc);
548 }
549 else
550 {
551 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
552 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
553 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
554 /* Just continue */
555 }
556 }
557 }
558 }
559
560#ifdef VBOX_STRICT
561 if (TRPMHasTrap(pVCpu))
562 {
563 uint8_t u8Vector;
564 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
565 AssertRC(rc);
566 }
567#endif
568
569 if ( (pCtx->eflags.u32 & X86_EFL_IF)
570 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
571 && TRPMHasTrap(pVCpu)
572 )
573 {
574 uint8_t u8Vector;
575 TRPMEVENT enmType;
576 SVM_EVENT Event;
577 RTGCUINT u32ErrorCode;
578
579 Event.au64[0] = 0;
580
581 /* If a new event is pending, then dispatch it now. */
582 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
583 AssertRC(rc);
584 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
585 Assert(enmType != TRPM_SOFTWARE_INT);
586
587 /* Clear the pending trap. */
588 rc = TRPMResetTrap(pVCpu);
589 AssertRC(rc);
590
591 Event.n.u8Vector = u8Vector;
592 Event.n.u1Valid = 1;
593 Event.n.u32ErrorCode = u32ErrorCode;
594
595 if (enmType == TRPM_TRAP)
596 {
597 switch (u8Vector) {
598 case 8:
599 case 10:
600 case 11:
601 case 12:
602 case 13:
603 case 14:
604 case 17:
605 /* Valid error codes. */
606 Event.n.u1ErrorCodeValid = 1;
607 break;
608 default:
609 break;
610 }
611 if (u8Vector == X86_XCPT_NMI)
612 Event.n.u3Type = SVM_EVENT_NMI;
613 else
614 Event.n.u3Type = SVM_EVENT_EXCEPTION;
615 }
616 else
617 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
618
619 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
620 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
621 } /* if (interrupts can be dispatched) */
622
623 return VINF_SUCCESS;
624}
625
626/**
627 * Save the host state
628 *
629 * @returns VBox status code.
630 * @param pVM The VM to operate on.
631 * @param pVCpu The VM CPU to operate on.
632 */
633VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
634{
635 NOREF(pVM);
636 NOREF(pVCpu);
637 /* Nothing to do here. */
638 return VINF_SUCCESS;
639}
640
641/**
642 * Loads the guest state
643 *
644 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
645 *
646 * @returns VBox status code.
647 * @param pVM The VM to operate on.
648 * @param pVCpu The VM CPU to operate on.
649 * @param pCtx Guest context
650 */
651VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
652{
653 RTGCUINTPTR val;
654 SVM_VMCB *pVMCB;
655
656 if (pVM == NULL)
657 return VERR_INVALID_PARAMETER;
658
659 /* Setup AMD SVM. */
660 Assert(pVM->hwaccm.s.svm.fSupported);
661
662 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
663 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_HMSVM_INVALID_PVMCB);
664
665 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
666 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
667 {
668 SVM_WRITE_SELREG(CS, cs);
669 SVM_WRITE_SELREG(SS, ss);
670 SVM_WRITE_SELREG(DS, ds);
671 SVM_WRITE_SELREG(ES, es);
672 SVM_WRITE_SELREG(FS, fs);
673 SVM_WRITE_SELREG(GS, gs);
674 }
675
676 /* Guest CPU context: LDTR. */
677 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
678 {
679 SVM_WRITE_SELREG(LDTR, ldtr);
680 }
681
682 /* Guest CPU context: TR. */
683 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
684 {
685 SVM_WRITE_SELREG(TR, tr);
686 }
687
688 /* Guest CPU context: GDTR. */
689 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
690 {
691 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
692 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
693 }
694
695 /* Guest CPU context: IDTR. */
696 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
697 {
698 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
699 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
700 }
701
702 /*
703 * Sysenter MSRs (unconditional)
704 */
705 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
706 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
707 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
708
709 /* Control registers */
710 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
711 {
712 val = pCtx->cr0;
713 if (!CPUMIsGuestFPUStateActive(pVCpu))
714 {
715 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
716 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
717 }
718 else
719 {
720 /** @todo check if we support the old style mess correctly. */
721 if (!(val & X86_CR0_NE))
722 {
723 Log(("Forcing X86_CR0_NE!!!\n"));
724
725 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
726 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
727 {
728 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
729 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
730 }
731 }
732 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
733 }
734 /* Always enable caching. */
735 val &= ~(X86_CR0_CD|X86_CR0_NW);
736
737 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
738 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
739 if (!pVM->hwaccm.s.fNestedPaging)
740 {
741 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
742 val |= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
743 }
744 pVMCB->guest.u64CR0 = val;
745 }
746 /* CR2 as well */
747 pVMCB->guest.u64CR2 = pCtx->cr2;
748
749 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
750 {
751 /* Save our shadow CR3 register. */
752 if (pVM->hwaccm.s.fNestedPaging)
753 {
754 PGMMODE enmShwPagingMode;
755
756#if HC_ARCH_BITS == 32
757 if (CPUMIsGuestInLongModeEx(pCtx))
758 enmShwPagingMode = PGMMODE_AMD64_NX;
759 else
760#endif
761 enmShwPagingMode = PGMGetHostMode(pVM);
762
763 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
764 Assert(pVMCB->ctrl.u64NestedPagingCR3);
765 pVMCB->guest.u64CR3 = pCtx->cr3;
766 }
767 else
768 {
769 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
770 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
771 }
772 }
773
774 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
775 {
776 val = pCtx->cr4;
777 if (!pVM->hwaccm.s.fNestedPaging)
778 {
779 switch(pVCpu->hwaccm.s.enmShadowMode)
780 {
781 case PGMMODE_REAL:
782 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
783 AssertFailed();
784 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
785
786 case PGMMODE_32_BIT: /* 32-bit paging. */
787 val &= ~X86_CR4_PAE;
788 break;
789
790 case PGMMODE_PAE: /* PAE paging. */
791 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
792 /** Must use PAE paging as we could use physical memory > 4 GB */
793 val |= X86_CR4_PAE;
794 break;
795
796 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
797 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
798#ifdef VBOX_ENABLE_64_BITS_GUESTS
799 break;
800#else
801 AssertFailed();
802 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
803#endif
804
805 default: /* shut up gcc */
806 AssertFailed();
807 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
808 }
809 }
810 pVMCB->guest.u64CR4 = val;
811 }
812
813 /* Debug registers. */
814 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
815 {
816 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
817 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
818
819 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
820 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
821 pCtx->dr[7] |= 0x400; /* must be one */
822
823 pVMCB->guest.u64DR7 = pCtx->dr[7];
824 pVMCB->guest.u64DR6 = pCtx->dr[6];
825
826#ifdef DEBUG
827 /* Sync the hypervisor debug state now if any breakpoint is armed. */
828 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
829 && !CPUMIsHyperDebugStateActive(pVCpu)
830 && !DBGFIsStepping(pVCpu))
831 {
832 /* Save the host and load the hypervisor debug state. */
833 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
834 AssertRC(rc);
835
836 /* DRx intercepts remain enabled. */
837
838 /* Override dr6 & dr7 with the hypervisor values. */
839 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
840 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
841 }
842 else
843#endif
844 /* Sync the debug state now if any breakpoint is armed. */
845 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
846 && !CPUMIsGuestDebugStateActive(pVCpu)
847 && !DBGFIsStepping(pVCpu))
848 {
849 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
850
851 /* Disable drx move intercepts. */
852 pVMCB->ctrl.u16InterceptRdDRx = 0;
853 pVMCB->ctrl.u16InterceptWrDRx = 0;
854
855 /* Save the host and load the guest debug state. */
856 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
857 AssertRC(rc);
858 }
859 }
860
861 /* EIP, ESP and EFLAGS */
862 pVMCB->guest.u64RIP = pCtx->rip;
863 pVMCB->guest.u64RSP = pCtx->rsp;
864 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
865
866 /* Set CPL */
867 pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
868
869 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
870 pVMCB->guest.u64RAX = pCtx->rax;
871
872 /* vmrun will fail without MSR_K6_EFER_SVME. */
873 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
874
875 /* 64 bits guest mode? */
876 if (CPUMIsGuestInLongModeEx(pCtx))
877 {
878#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
879 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
880#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
881 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
882#else
883# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
884 if (!pVM->hwaccm.s.fAllow64BitGuests)
885 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
886# endif
887 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
888#endif
889 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
890 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
891 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
892 }
893 else
894 {
895 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
896 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
897
898 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
899 }
900
901 /* TSC offset. */
902 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
903 {
904 uint64_t u64CurTSC = ASMReadTSC();
905 if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
906 {
907 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
908 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
909 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
910 }
911 else
912 {
913 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
914 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
915 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
916 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
917 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
918 }
919 }
920 else
921 {
922 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
923 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
924 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
925 }
926
927 /* Sync the various msrs for 64 bits mode. */
928 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
929 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
930 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
931 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
932 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
933
934#ifdef DEBUG
935 /* Intercept X86_XCPT_DB if stepping is enabled */
936 if ( DBGFIsStepping(pVCpu)
937 || CPUMIsHyperDebugStateActive(pVCpu))
938 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
939 else
940 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
941#endif
942
943 /* Done. */
944 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
945
946 return VINF_SUCCESS;
947}
948
949
950/**
951 * Runs guest code in an AMD-V VM.
952 *
953 * @returns VBox status code.
954 * @param pVM The VM to operate on.
955 * @param pVCpu The VM CPU to operate on.
956 * @param pCtx Guest context
957 */
958VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
959{
960 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
961 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit1);
962 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit2);
963
964 VBOXSTRICTRC rc = VINF_SUCCESS;
965 int rc2;
966 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
967 SVM_VMCB *pVMCB;
968 bool fSyncTPR = false;
969 unsigned cResume = 0;
970 uint8_t u8LastTPR = 0; /* Initialized for potentially stupid compilers. */
971 PHMGLOBLCPUINFO pCpu = 0;
972 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
973#ifdef VBOX_STRICT
974 RTCPUID idCpuCheck;
975#endif
976#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
977 uint64_t u64LastTime = RTTimeMilliTS();
978#endif
979
980 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
981 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_HMSVM_INVALID_PVMCB);
982
983 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
984 */
985ResumeExecution:
986 if (!STAM_PROFILE_ADV_IS_RUNNING(&pVCpu->hwaccm.s.StatEntry))
987 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit2, &pVCpu->hwaccm.s.StatEntry, x);
988 Assert(!HWACCMR0SuspendPending());
989
990 /* Safety precaution; looping for too long here can have a very bad effect on the host */
991 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
992 {
993 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
994 rc = VINF_EM_RAW_INTERRUPT;
995 goto end;
996 }
997
998 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
999 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1000 {
1001 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
1002 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
1003 {
1004 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1005 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1006 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1007 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1008 */
1009 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1010 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1011 pVMCB->ctrl.u64IntShadow = 0;
1012 }
1013 }
1014 else
1015 {
1016 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1017 pVMCB->ctrl.u64IntShadow = 0;
1018 }
1019
1020#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1021 if (RT_UNLIKELY((cResume & 0xf) == 0))
1022 {
1023 uint64_t u64CurTime = RTTimeMilliTS();
1024
1025 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1026 {
1027 u64LastTime = u64CurTime;
1028 TMTimerPollVoid(pVM, pVCpu);
1029 }
1030 }
1031#endif
1032
1033 /* Check for pending actions that force us to go back to ring 3. */
1034 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING | VM_FF_PDM_DMA)
1035 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST))
1036 {
1037 /* Check if a sync operation is pending. */
1038 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1039 {
1040 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1041 AssertRC(VBOXSTRICTRC_VAL(rc));
1042 if (rc != VINF_SUCCESS)
1043 {
1044 Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", VBOXSTRICTRC_VAL(rc)));
1045 goto end;
1046 }
1047 }
1048
1049#ifdef DEBUG
1050 /* Intercept X86_XCPT_DB if stepping is enabled */
1051 if (!DBGFIsStepping(pVCpu))
1052#endif
1053 {
1054 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1055 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1056 {
1057 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1058 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1059 goto end;
1060 }
1061 }
1062
1063 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1064 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1065 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1066 {
1067 rc = VINF_EM_PENDING_REQUEST;
1068 goto end;
1069 }
1070
1071 /* Check if a pgm pool flush is in progress. */
1072 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
1073 {
1074 rc = VINF_PGM_POOL_FLUSH_PENDING;
1075 goto end;
1076 }
1077
1078 /* Check if DMA work is pending (2nd+ run). */
1079 if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA) && cResume > 1)
1080 {
1081 rc = VINF_EM_RAW_TO_R3;
1082 goto end;
1083 }
1084 }
1085
1086#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1087 /*
1088 * Exit to ring-3 preemption/work is pending.
1089 *
1090 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1091 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1092 * further down, but hmR0SvmCheckPendingInterrupt makes that impossible.)
1093 *
1094 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1095 * shootdowns rely on this.
1096 */
1097 uOldEFlags = ASMIntDisableFlags();
1098 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1099 {
1100 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1101 rc = VINF_EM_RAW_INTERRUPT;
1102 goto end;
1103 }
1104 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1105#endif
1106
1107 /* When external interrupts are pending, we should exit the VM when IF is set. */
1108 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1109 rc = hmR0SvmCheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1110 if (RT_FAILURE(rc))
1111 goto end;
1112
1113 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1114 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1115 */
1116 /** @todo query and update the TPR only when it could have been changed (mmio access)
1117 */
1118 if (pVM->hwaccm.s.fHasIoApic)
1119 {
1120 /* TPR caching in CR8 */
1121 bool fPending;
1122 rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1123 AssertRC(rc2);
1124
1125 if (pVM->hwaccm.s.fTPRPatchingActive)
1126 {
1127 /* Our patch code uses LSTAR for TPR caching. */
1128 pCtx->msrLSTAR = u8LastTPR;
1129
1130 if (fPending)
1131 {
1132 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1133 hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1134 }
1135 else
1136 /* No interrupts are pending, so we don't need to be explicitely notified.
1137 * There are enough world switches for detecting pending interrupts.
1138 */
1139 hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1140 }
1141 else
1142 {
1143 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1144
1145 if (fPending)
1146 {
1147 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1148 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1149 }
1150 else
1151 /* No interrupts are pending, so we don't need to be explicitely notified.
1152 * There are enough world switches for detecting pending interrupts.
1153 */
1154 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1155 }
1156 fSyncTPR = !fPending;
1157 }
1158
1159 /* All done! Let's start VM execution. */
1160
1161 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1162 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1163
1164#ifdef LOG_ENABLED
1165 pCpu = HWACCMR0GetCurrentCpu();
1166 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1167 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1168 {
1169 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1170 LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1171 else
1172 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1173 }
1174 if (pCpu->fFlushTLB)
1175 LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1176#endif
1177
1178 /*
1179 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1180 * (until the actual world switch)
1181 */
1182#ifdef VBOX_STRICT
1183 idCpuCheck = RTMpCpuId();
1184#endif
1185 VMMR0LogFlushDisable(pVCpu);
1186
1187 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1188 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1189 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1190 {
1191 VMMR0LogFlushEnable(pVCpu);
1192 goto end;
1193 }
1194
1195#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1196 /* Disable interrupts to make sure a poke will interrupt execution.
1197 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1198 */
1199 uOldEFlags = ASMIntDisableFlags();
1200 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1201#endif
1202 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatEntry, &pVCpu->hwaccm.s.StatInGC, x);
1203
1204 pCpu = HWACCMR0GetCurrentCpu();
1205 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1206 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1207 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1208 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1209 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1210 {
1211 /* Force a TLB flush on VM entry. */
1212 pVCpu->hwaccm.s.fForceTLBFlush = true;
1213 }
1214 else
1215 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1216
1217 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1218
1219 /* Set TLB flush state as checked until we return from the world switch. */
1220 ASMAtomicWriteBool(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1221
1222 /* Check for tlb shootdown flushes. */
1223 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1224 pVCpu->hwaccm.s.fForceTLBFlush = true;
1225
1226 /* Make sure we flush the TLB when required. Switch ASID to achieve the
1227 same thing, but without actually flushing the whole TLB (which is
1228 expensive). */
1229 if ( pVCpu->hwaccm.s.fForceTLBFlush
1230 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1231 {
1232 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1233 || pCpu->fFlushTLB)
1234 {
1235 pCpu->fFlushTLB = false;
1236 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1237 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1238 pCpu->cTLBFlushes++;
1239 }
1240 else
1241 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1242
1243 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1244 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1245 }
1246 else
1247 {
1248 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1249
1250 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1251 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1252 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1253
1254 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1255 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1256
1257 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1258 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1259 {
1260 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1261 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1262 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1263 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1264 }
1265 }
1266 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1267 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1268
1269 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1270 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1271 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1272 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1273
1274#ifdef VBOX_WITH_STATISTICS
1275 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1276 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1277 else
1278 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1279#endif
1280
1281 /* In case we execute a goto ResumeExecution later on. */
1282 pVCpu->hwaccm.s.fResumeVM = true;
1283 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1284
1285 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1286 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1287 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1288 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1289 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1290
1291#ifdef VBOX_STRICT
1292 Assert(idCpuCheck == RTMpCpuId());
1293#endif
1294 TMNotifyStartOfExecution(pVCpu);
1295#ifdef VBOX_WITH_KERNEL_USING_XMM
1296 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1297#else
1298 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1299#endif
1300 ASMAtomicWriteBool(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1301 ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExits);
1302 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1303 if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1304 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1305 TMNotifyEndOfExecution(pVCpu);
1306 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1307 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatInGC, &pVCpu->hwaccm.s.StatExit1, x);
1308 ASMSetFlags(uOldEFlags);
1309#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1310 uOldEFlags = ~(RTCCUINTREG)0;
1311#endif
1312
1313 /*
1314 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1315 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1316 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1317 */
1318
1319 /* Reason for the VM exit */
1320 exitCode = pVMCB->ctrl.u64ExitCode;
1321
1322 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1323 {
1324 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1325#ifdef DEBUG
1326 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1327 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1328 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1329 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1330 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1331 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1332 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1333 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1334 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1335 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1336
1337 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1338 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1339 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1340 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1341
1342 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1343 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1344 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1345 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1346 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1347 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1348 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1349 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1350 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1351 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1352
1353 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1354 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1355 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1356 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1357 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1358 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1359 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1360 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1361 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1362 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1363 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1364 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1365 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1366 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1367 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1368 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1369 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1370
1371 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1372 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1373
1374 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1375 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1376 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1377 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1378 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1379 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1380 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1381 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1382 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1383 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1384 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1385 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1386 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1387 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1388 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1389 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1390 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1391 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1392 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1393 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1394
1395 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1396 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1397
1398 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1399 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1400 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1401 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1402
1403 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1404 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1405
1406 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1407 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1408 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1409 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1410
1411 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1412 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1413 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1414 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1415 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1416 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1417 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1418
1419 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1420 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1421 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1422 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1423
1424 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1425 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1426 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1427
1428 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1429 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1430 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1431 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1432 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1433 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1434 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1435 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1436 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1437 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1438 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1439 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1440
1441#endif
1442 rc = VERR_SVM_UNABLE_TO_START_VM;
1443 VMMR0LogFlushEnable(pVCpu);
1444 goto end;
1445 }
1446
1447 /* Let's first sync back eip, esp, and eflags. */
1448 pCtx->rip = pVMCB->guest.u64RIP;
1449 pCtx->rsp = pVMCB->guest.u64RSP;
1450 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1451 /* eax is saved/restore across the vmrun instruction */
1452 pCtx->rax = pVMCB->guest.u64RAX;
1453
1454 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1455 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1456 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1457 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1458 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1459 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1460 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1461 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1462 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1463
1464 /* Can be updated behind our back in the nested paging case. */
1465 pCtx->cr2 = pVMCB->guest.u64CR2;
1466
1467 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1468 SVM_READ_SELREG(SS, ss);
1469 SVM_READ_SELREG(CS, cs);
1470 SVM_READ_SELREG(DS, ds);
1471 SVM_READ_SELREG(ES, es);
1472 SVM_READ_SELREG(FS, fs);
1473 SVM_READ_SELREG(GS, gs);
1474
1475 /* Correct the hidden CS granularity flag. Haven't seen it being wrong in
1476 any other register (yet). */
1477 if ( !pCtx->csHid.Attr.n.u1Granularity
1478 && pCtx->csHid.Attr.n.u1Present
1479 && pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1480 {
1481 Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1482 pCtx->csHid.Attr.n.u1Granularity = 1;
1483 }
1484#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1485 AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1486 || ( pCtx->reg##Hid.Attr.n.u1Granularity \
1487 ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1488 : pCtx->reg##Hid.u32Limit <= 0xfffff), \
1489 ("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1490 SVM_ASSERT_SEL_GRANULARITY(ss);
1491 SVM_ASSERT_SEL_GRANULARITY(cs);
1492 SVM_ASSERT_SEL_GRANULARITY(ds);
1493 SVM_ASSERT_SEL_GRANULARITY(es);
1494 SVM_ASSERT_SEL_GRANULARITY(fs);
1495 SVM_ASSERT_SEL_GRANULARITY(gs);
1496#undef SVM_ASSERT_SEL_GRANULARITY
1497
1498 /*
1499 * Correct the hidden SS DPL field. It can be wrong on certain CPUs
1500 * sometimes (seen it on AMD Fusion APUs with 64bit guests). The CPU
1501 * always uses the CPL field in the VMCB instead of the DPL in the hidden
1502 * SS (chapter 15.5.1 Basic operation).
1503 */
1504 Assert(!(pVMCB->guest.u8CPL & ~0x3));
1505 pCtx->ssHid.Attr.n.u2Dpl = pVMCB->guest.u8CPL & 0x3;
1506
1507 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1508 SVM_READ_SELREG(LDTR, ldtr);
1509 SVM_READ_SELREG(TR, tr);
1510
1511 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1512 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1513
1514 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1515 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1516
1517 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1518 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1519 if ( pVM->hwaccm.s.fNestedPaging
1520 && pCtx->cr3 != pVMCB->guest.u64CR3)
1521 {
1522 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1523 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1524 }
1525
1526 /* Note! NOW IT'S SAFE FOR LOGGING! */
1527 VMMR0LogFlushEnable(pVCpu);
1528
1529 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1530 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1531 {
1532 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1533 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1534 }
1535 else
1536 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1537
1538 Log2(("exitCode = %x\n", exitCode));
1539
1540 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1541 pCtx->dr[6] = pVMCB->guest.u64DR6;
1542 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1543 pCtx->dr[7] = pVMCB->guest.u64DR7;
1544
1545 /* Check if an injected event was interrupted prematurely. */
1546 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1547 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1548 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1549 {
1550 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1551
1552#ifdef LOG_ENABLED
1553 SVM_EVENT Event;
1554 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1555
1556 if ( exitCode == SVM_EXIT_EXCEPTION_E
1557 && Event.n.u8Vector == 0xE)
1558 {
1559 Log(("Double fault!\n"));
1560 }
1561#endif
1562
1563 pVCpu->hwaccm.s.Event.fPending = true;
1564 /* Error code present? (redundant) */
1565 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1566 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1567 else
1568 pVCpu->hwaccm.s.Event.errCode = 0;
1569 }
1570#ifdef VBOX_WITH_STATISTICS
1571 if (exitCode == SVM_EXIT_NPF)
1572 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1573 else
1574 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1575#endif
1576
1577 /* Sync back the TPR if it was changed. */
1578 if (fSyncTPR)
1579 {
1580 if (pVM->hwaccm.s.fTPRPatchingActive)
1581 {
1582 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1583 {
1584 /* Our patch code uses LSTAR for TPR caching. */
1585 rc2 = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1586 AssertRC(rc2);
1587 }
1588 }
1589 else
1590 {
1591 if ((uint8_t)(u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1592 {
1593 rc2 = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1594 AssertRC(rc2);
1595 }
1596 }
1597 }
1598
1599 STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit1, &pVCpu->hwaccm.s.StatExit2, x);
1600
1601 /* Deal with the reason of the VM-exit. */
1602 switch (exitCode)
1603 {
1604 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1605 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1606 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1607 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1608 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1609 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1610 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1611 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1612 {
1613 /* Pending trap. */
1614 SVM_EVENT Event;
1615 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1616
1617 Log2(("Hardware/software interrupt %d\n", vector));
1618 switch (vector)
1619 {
1620 case X86_XCPT_DB:
1621 {
1622 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1623
1624 /* Note that we don't support guest and host-initiated debugging at the same time. */
1625 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1626
1627 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1628 if (rc == VINF_EM_RAW_GUEST_TRAP)
1629 {
1630 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1631
1632 /* Reinject the exception. */
1633 Event.au64[0] = 0;
1634 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1635 Event.n.u1Valid = 1;
1636 Event.n.u8Vector = X86_XCPT_DB;
1637
1638 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1639 goto ResumeExecution;
1640 }
1641 /* Return to ring 3 to deal with the debug exit code. */
1642 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1643 break;
1644 }
1645
1646 case X86_XCPT_NM:
1647 {
1648 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1649
1650 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1651 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1652 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1653 if (rc == VINF_SUCCESS)
1654 {
1655 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1656 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1657
1658 /* Continue execution. */
1659 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1660
1661 goto ResumeExecution;
1662 }
1663
1664 Log(("Forward #NM fault to the guest\n"));
1665 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1666
1667 Event.au64[0] = 0;
1668 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1669 Event.n.u1Valid = 1;
1670 Event.n.u8Vector = X86_XCPT_NM;
1671
1672 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1673 goto ResumeExecution;
1674 }
1675
1676 case X86_XCPT_PF: /* Page fault */
1677 {
1678 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1679 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1680
1681#ifdef DEBUG
1682 if (pVM->hwaccm.s.fNestedPaging)
1683 { /* A genuine pagefault.
1684 * Forward the trap to the guest by injecting the exception and resuming execution.
1685 */
1686 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1687 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1688
1689 /* Now we must update CR2. */
1690 pCtx->cr2 = uFaultAddress;
1691
1692 Event.au64[0] = 0;
1693 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1694 Event.n.u1Valid = 1;
1695 Event.n.u8Vector = X86_XCPT_PF;
1696 Event.n.u1ErrorCodeValid = 1;
1697 Event.n.u32ErrorCode = errCode;
1698
1699 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1700 goto ResumeExecution;
1701 }
1702#endif
1703 Assert(!pVM->hwaccm.s.fNestedPaging);
1704
1705#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1706 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1707 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1708 && (uFaultAddress & 0xfff) == 0x080
1709 && !(errCode & X86_TRAP_PF_P) /* not present */
1710 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1711 && !CPUMIsGuestInLongModeEx(pCtx)
1712 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1713 {
1714 RTGCPHYS GCPhysApicBase, GCPhys;
1715 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1716 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1717
1718 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1719 if ( rc == VINF_SUCCESS
1720 && GCPhys == GCPhysApicBase)
1721 {
1722 /* Only attempt to patch the instruction once. */
1723 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1724 if (!pPatch)
1725 {
1726 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1727 break;
1728 }
1729 }
1730 }
1731#endif
1732
1733 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1734 /* Exit qualification contains the linear address of the page fault. */
1735 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1736 TRPMSetErrorCode(pVCpu, errCode);
1737 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1738
1739 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1740 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1741 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1742 if (rc == VINF_SUCCESS)
1743 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1744 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1745 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1746
1747 TRPMResetTrap(pVCpu);
1748 goto ResumeExecution;
1749 }
1750 else
1751 if (rc == VINF_EM_RAW_GUEST_TRAP)
1752 { /* A genuine pagefault.
1753 * Forward the trap to the guest by injecting the exception and resuming execution.
1754 */
1755 Log2(("Forward page fault to the guest\n"));
1756 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1757 /* The error code might have been changed. */
1758 errCode = TRPMGetErrorCode(pVCpu);
1759
1760 TRPMResetTrap(pVCpu);
1761
1762 /* Now we must update CR2. */
1763 pCtx->cr2 = uFaultAddress;
1764
1765 Event.au64[0] = 0;
1766 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1767 Event.n.u1Valid = 1;
1768 Event.n.u8Vector = X86_XCPT_PF;
1769 Event.n.u1ErrorCodeValid = 1;
1770 Event.n.u32ErrorCode = errCode;
1771
1772 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1773 goto ResumeExecution;
1774 }
1775#ifdef VBOX_STRICT
1776 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1777 LogFlow(("PGMTrap0eHandler failed with %d\n", VBOXSTRICTRC_VAL(rc)));
1778#endif
1779 /* Need to go back to the recompiler to emulate the instruction. */
1780 TRPMResetTrap(pVCpu);
1781 break;
1782 }
1783
1784 case X86_XCPT_MF: /* Floating point exception. */
1785 {
1786 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1787 if (!(pCtx->cr0 & X86_CR0_NE))
1788 {
1789 /* old style FPU error reporting needs some extra work. */
1790 /** @todo don't fall back to the recompiler, but do it manually. */
1791 rc = VINF_EM_RAW_EMULATE_INSTR;
1792 break;
1793 }
1794 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1795
1796 Event.au64[0] = 0;
1797 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1798 Event.n.u1Valid = 1;
1799 Event.n.u8Vector = X86_XCPT_MF;
1800
1801 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1802 goto ResumeExecution;
1803 }
1804
1805#ifdef VBOX_STRICT
1806 case X86_XCPT_BP: /* Breakpoint. */
1807 case X86_XCPT_GP: /* General protection failure exception.*/
1808 case X86_XCPT_UD: /* Unknown opcode exception. */
1809 case X86_XCPT_DE: /* Divide error. */
1810 case X86_XCPT_SS: /* Stack segment exception. */
1811 case X86_XCPT_NP: /* Segment not present exception. */
1812 {
1813 Event.au64[0] = 0;
1814 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1815 Event.n.u1Valid = 1;
1816 Event.n.u8Vector = vector;
1817
1818 switch(vector)
1819 {
1820 case X86_XCPT_GP:
1821 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1822 Event.n.u1ErrorCodeValid = 1;
1823 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1824 break;
1825 case X86_XCPT_BP:
1826 /** Saves the wrong EIP on the stack (pointing to the int3 instead of the next instruction. */
1827 break;
1828 case X86_XCPT_DE:
1829 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1830 break;
1831 case X86_XCPT_UD:
1832 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1833 break;
1834 case X86_XCPT_SS:
1835 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1836 Event.n.u1ErrorCodeValid = 1;
1837 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1838 break;
1839 case X86_XCPT_NP:
1840 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1841 Event.n.u1ErrorCodeValid = 1;
1842 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1843 break;
1844 }
1845 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1846 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
1847 goto ResumeExecution;
1848 }
1849#endif
1850 default:
1851 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1852 rc = VERR_HMSVM_UNEXPECTED_XCPT_EXIT;
1853 break;
1854
1855 } /* switch (vector) */
1856 break;
1857 }
1858
1859 case SVM_EXIT_NPF:
1860 {
1861 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1862 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1863 RTGCPHYS GCPhysFault = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1864 PGMMODE enmShwPagingMode;
1865
1866 Assert(pVM->hwaccm.s.fNestedPaging);
1867 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
1868
1869#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1870 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1871 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1872 && (GCPhysFault & PAGE_OFFSET_MASK) == 0x080
1873 && ( !(errCode & X86_TRAP_PF_P) /* not present */
1874 || (errCode & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P | X86_TRAP_PF_RSVD) /* mmio optimization */)
1875 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1876 && !CPUMIsGuestInLongModeEx(pCtx)
1877 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1878 {
1879 RTGCPHYS GCPhysApicBase;
1880 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1881 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1882
1883 if (GCPhysFault == GCPhysApicBase + 0x80)
1884 {
1885 /* Only attempt to patch the instruction once. */
1886 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1887 if (!pPatch)
1888 {
1889 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1890 break;
1891 }
1892 }
1893 }
1894#endif
1895
1896 /* Handle the pagefault trap for the nested shadow table. */
1897#if HC_ARCH_BITS == 32 /** @todo shadow this in a variable. */
1898 if (CPUMIsGuestInLongModeEx(pCtx))
1899 enmShwPagingMode = PGMMODE_AMD64_NX;
1900 else
1901#endif
1902 enmShwPagingMode = PGMGetHostMode(pVM);
1903
1904 /* MMIO optimization */
1905 Assert((errCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
1906 if ((errCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD | X86_TRAP_PF_P))
1907 {
1908 rc = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmShwPagingMode, CPUMCTX2CORE(pCtx), GCPhysFault, errCode);
1909 if (rc == VINF_SUCCESS)
1910 {
1911 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
1912 goto ResumeExecution;
1913 }
1914 Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
1915 break;
1916 }
1917
1918 /* Exit qualification contains the linear address of the page fault. */
1919 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1920 TRPMSetErrorCode(pVCpu, errCode);
1921 TRPMSetFaultAddress(pVCpu, GCPhysFault);
1922
1923 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), GCPhysFault);
1924 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1925 if (rc == VINF_SUCCESS)
1926 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1927 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
1928 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1929
1930 TRPMResetTrap(pVCpu);
1931 goto ResumeExecution;
1932 }
1933
1934#ifdef VBOX_STRICT
1935 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1936 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", VBOXSTRICTRC_VAL(rc)));
1937#endif
1938 /* Need to go back to the recompiler to emulate the instruction. */
1939 TRPMResetTrap(pVCpu);
1940 break;
1941 }
1942
1943 case SVM_EXIT_VINTR:
1944 /* A virtual interrupt is about to be delivered, which means IF=1. */
1945 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1946 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1947 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1948 goto ResumeExecution;
1949
1950 case SVM_EXIT_FERR_FREEZE:
1951 case SVM_EXIT_INTR:
1952 case SVM_EXIT_NMI:
1953 case SVM_EXIT_SMI:
1954 case SVM_EXIT_INIT:
1955 /* External interrupt; leave to allow it to be dispatched again. */
1956 rc = VINF_EM_RAW_INTERRUPT;
1957 break;
1958
1959 case SVM_EXIT_WBINVD:
1960 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1961 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1962 /* Skip instruction and continue directly. */
1963 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1964 /* Continue execution.*/
1965 goto ResumeExecution;
1966
1967 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1968 {
1969 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1970 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1971 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1972 if (rc == VINF_SUCCESS)
1973 {
1974 /* Update EIP and continue execution. */
1975 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1976 goto ResumeExecution;
1977 }
1978 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
1979 rc = VINF_EM_RAW_EMULATE_INSTR;
1980 break;
1981 }
1982
1983 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1984 {
1985 Log2(("SVM: Rdtsc\n"));
1986 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1987 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1988 if (rc == VINF_SUCCESS)
1989 {
1990 /* Update EIP and continue execution. */
1991 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1992 goto ResumeExecution;
1993 }
1994 rc = VINF_EM_RAW_EMULATE_INSTR;
1995 break;
1996 }
1997
1998 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1999 {
2000 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
2001 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
2002 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2003 if (rc == VINF_SUCCESS)
2004 {
2005 /* Update EIP and continue execution. */
2006 pCtx->rip += 2; /* Note! hardcoded opcode size! */
2007 goto ResumeExecution;
2008 }
2009 rc = VINF_EM_RAW_EMULATE_INSTR;
2010 break;
2011 }
2012
2013 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
2014 {
2015 Log2(("SVM: Rdtscp\n"));
2016 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2017 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
2018 if (rc == VINF_SUCCESS)
2019 {
2020 /* Update EIP and continue execution. */
2021 pCtx->rip += 3; /* Note! hardcoded opcode size! */
2022 goto ResumeExecution;
2023 }
2024 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2025 rc = VINF_EM_RAW_EMULATE_INSTR;
2026 break;
2027 }
2028
2029 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
2030 {
2031 Log2(("SVM: invlpg\n"));
2032 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2033
2034 Assert(!pVM->hwaccm.s.fNestedPaging);
2035
2036 /* Truly a pita. Why can't SVM give the same information as VT-x? */
2037 rc = hmR0SvmInterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
2038 if (rc == VINF_SUCCESS)
2039 {
2040 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
2041 goto ResumeExecution; /* eip already updated */
2042 }
2043 break;
2044 }
2045
2046 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2047 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2048 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2049 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2050 {
2051 uint32_t cbSize;
2052
2053 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2054 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2055 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2056
2057 switch (exitCode - SVM_EXIT_WRITE_CR0)
2058 {
2059 case 0:
2060 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2061 break;
2062 case 2:
2063 break;
2064 case 3:
2065 Assert(!pVM->hwaccm.s.fNestedPaging);
2066 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2067 break;
2068 case 4:
2069 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2070 break;
2071 case 8:
2072 break;
2073 default:
2074 AssertFailed();
2075 }
2076 if (rc == VINF_SUCCESS)
2077 {
2078 /* EIP has been updated already. */
2079
2080 /* Only resume if successful. */
2081 goto ResumeExecution;
2082 }
2083 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2084 break;
2085 }
2086
2087 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2088 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2089 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2090 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2091 {
2092 uint32_t cbSize;
2093
2094 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2095 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2096 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2097 if (rc == VINF_SUCCESS)
2098 {
2099 /* EIP has been updated already. */
2100
2101 /* Only resume if successful. */
2102 goto ResumeExecution;
2103 }
2104 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2105 break;
2106 }
2107
2108 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2109 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2110 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2111 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2112 {
2113 uint32_t cbSize;
2114
2115 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2116 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2117
2118 if ( !DBGFIsStepping(pVCpu)
2119 && !CPUMIsHyperDebugStateActive(pVCpu))
2120 {
2121 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2122
2123 /* Disable drx move intercepts. */
2124 pVMCB->ctrl.u16InterceptRdDRx = 0;
2125 pVMCB->ctrl.u16InterceptWrDRx = 0;
2126
2127 /* Save the host and load the guest debug state. */
2128 rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2129 AssertRC(rc2);
2130 goto ResumeExecution;
2131 }
2132
2133 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2134 if (rc == VINF_SUCCESS)
2135 {
2136 /* EIP has been updated already. */
2137 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2138
2139 /* Only resume if successful. */
2140 goto ResumeExecution;
2141 }
2142 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2143 break;
2144 }
2145
2146 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2147 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2148 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2149 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2150 {
2151 uint32_t cbSize;
2152
2153 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2154 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2155
2156 if (!DBGFIsStepping(pVCpu))
2157 {
2158 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2159
2160 /* Disable drx move intercepts. */
2161 pVMCB->ctrl.u16InterceptRdDRx = 0;
2162 pVMCB->ctrl.u16InterceptWrDRx = 0;
2163
2164 /* Save the host and load the guest debug state. */
2165 rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2166 AssertRC(rc2);
2167 goto ResumeExecution;
2168 }
2169
2170 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2171 if (rc == VINF_SUCCESS)
2172 {
2173 /* EIP has been updated already. */
2174
2175 /* Only resume if successful. */
2176 goto ResumeExecution;
2177 }
2178 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2179 break;
2180 }
2181
2182 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2183 case SVM_EXIT_IOIO: /* I/O instruction. */
2184 {
2185 SVM_IOIO_EXIT IoExitInfo;
2186 uint32_t uIOSize, uAndVal;
2187
2188 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2189
2190 /** @todo could use a lookup table here */
2191 if (IoExitInfo.n.u1OP8)
2192 {
2193 uIOSize = 1;
2194 uAndVal = 0xff;
2195 }
2196 else
2197 if (IoExitInfo.n.u1OP16)
2198 {
2199 uIOSize = 2;
2200 uAndVal = 0xffff;
2201 }
2202 else
2203 if (IoExitInfo.n.u1OP32)
2204 {
2205 uIOSize = 4;
2206 uAndVal = 0xffffffff;
2207 }
2208 else
2209 {
2210 AssertFailed(); /* should be fatal. */
2211 rc = VINF_EM_RAW_EMULATE_INSTR;
2212 break;
2213 }
2214
2215 if (IoExitInfo.n.u1STR)
2216 {
2217 /* ins/outs */
2218 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2219
2220 /* Disassemble manually to deal with segment prefixes. */
2221 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2222 if (rc == VINF_SUCCESS)
2223 {
2224 if (IoExitInfo.n.u1Type == 0)
2225 {
2226 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2227 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2228 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, pDis->addrmode, uIOSize);
2229 }
2230 else
2231 {
2232 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2233 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2234 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, pDis->addrmode, uIOSize);
2235 }
2236 }
2237 else
2238 rc = VINF_EM_RAW_EMULATE_INSTR;
2239 }
2240 else
2241 {
2242 /* normal in/out */
2243 Assert(!IoExitInfo.n.u1REP);
2244
2245 if (IoExitInfo.n.u1Type == 0)
2246 {
2247 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2248 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2249 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2250 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2251 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2252 }
2253 else
2254 {
2255 uint32_t u32Val = 0;
2256
2257 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2258 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2259 if (IOM_SUCCESS(rc))
2260 {
2261 /* Write back to the EAX register. */
2262 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2263 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2264 }
2265 else
2266 if (rc == VINF_IOM_HC_IOPORT_READ)
2267 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2268 }
2269 }
2270 /*
2271 * Handled the I/O return codes.
2272 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2273 */
2274 if (IOM_SUCCESS(rc))
2275 {
2276 /* Update EIP and continue execution. */
2277 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2278 if (RT_LIKELY(rc == VINF_SUCCESS))
2279 {
2280 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2281 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2282 {
2283 /* IO operation lookup arrays. */
2284 static uint32_t const aIOSize[4] = {1, 2, 0, 4};
2285
2286 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2287 for (unsigned i=0;i<4;i++)
2288 {
2289 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2290
2291 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2292 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2293 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2294 {
2295 SVM_EVENT Event;
2296
2297 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2298
2299 /* Clear all breakpoint status flags and set the one we just hit. */
2300 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2301 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2302
2303 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2304 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2305 * the contents have been read.
2306 */
2307 pVMCB->guest.u64DR6 = pCtx->dr[6];
2308
2309 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2310 pCtx->dr[7] &= ~X86_DR7_GD;
2311
2312 /* Paranoia. */
2313 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2314 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2315 pCtx->dr[7] |= 0x400; /* must be one */
2316
2317 pVMCB->guest.u64DR7 = pCtx->dr[7];
2318
2319 /* Inject the exception. */
2320 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2321
2322 Event.au64[0] = 0;
2323 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2324 Event.n.u1Valid = 1;
2325 Event.n.u8Vector = X86_XCPT_DB;
2326
2327 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
2328 goto ResumeExecution;
2329 }
2330 }
2331 }
2332 goto ResumeExecution;
2333 }
2334 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, VBOXSTRICTRC_VAL(rc)));
2335 break;
2336 }
2337
2338#ifdef VBOX_STRICT
2339 if (rc == VINF_IOM_HC_IOPORT_READ)
2340 Assert(IoExitInfo.n.u1Type != 0);
2341 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2342 Assert(IoExitInfo.n.u1Type == 0);
2343 else
2344 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
2345#endif
2346 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2347 break;
2348 }
2349
2350 case SVM_EXIT_HLT:
2351 /** Check if external interrupts are pending; if so, don't switch back. */
2352 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2353 pCtx->rip++; /* skip hlt */
2354 if (EMShouldContinueAfterHalt(pVCpu, pCtx))
2355 goto ResumeExecution;
2356
2357 rc = VINF_EM_HALT;
2358 break;
2359
2360 case SVM_EXIT_MWAIT_UNCOND:
2361 Log2(("SVM: mwait\n"));
2362 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2363 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2364 if ( rc == VINF_EM_HALT
2365 || rc == VINF_SUCCESS)
2366 {
2367 /* Update EIP and continue execution. */
2368 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2369
2370 /** Check if external interrupts are pending; if so, don't switch back. */
2371 if ( rc == VINF_SUCCESS
2372 || ( rc == VINF_EM_HALT
2373 && EMShouldContinueAfterHalt(pVCpu, pCtx))
2374 )
2375 goto ResumeExecution;
2376 }
2377 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2378 break;
2379
2380 case SVM_EXIT_MONITOR:
2381 {
2382 Log2(("SVM: monitor\n"));
2383
2384 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMonitor);
2385 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2386 if (rc == VINF_SUCCESS)
2387 {
2388 /* Update EIP and continue execution. */
2389 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2390 goto ResumeExecution;
2391 }
2392 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2393 break;
2394 }
2395
2396
2397 case SVM_EXIT_VMMCALL:
2398 rc = hmR0SvmEmulateTprVMMCall(pVM, pVCpu, pCtx);
2399 if (rc == VINF_SUCCESS)
2400 {
2401 goto ResumeExecution; /* rip already updated. */
2402 }
2403 /* no break */
2404
2405 case SVM_EXIT_RSM:
2406 case SVM_EXIT_INVLPGA:
2407 case SVM_EXIT_VMRUN:
2408 case SVM_EXIT_VMLOAD:
2409 case SVM_EXIT_VMSAVE:
2410 case SVM_EXIT_STGI:
2411 case SVM_EXIT_CLGI:
2412 case SVM_EXIT_SKINIT:
2413 {
2414 /* Unsupported instructions. */
2415 SVM_EVENT Event;
2416
2417 Event.au64[0] = 0;
2418 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2419 Event.n.u1Valid = 1;
2420 Event.n.u8Vector = X86_XCPT_UD;
2421
2422 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2423 hmR0SvmInjectEvent(pVCpu, pVMCB, pCtx, &Event);
2424 goto ResumeExecution;
2425 }
2426
2427 /* Emulate in ring 3. */
2428 case SVM_EXIT_MSR:
2429 {
2430 uint32_t cbSize;
2431
2432 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2433 if ( pVM->hwaccm.s.fTPRPatchingActive
2434 && pCtx->ecx == MSR_K8_LSTAR
2435 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2436 {
2437 if ((pCtx->eax & 0xff) != u8LastTPR)
2438 {
2439 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2440
2441 /* Our patch code uses LSTAR for TPR caching. */
2442 rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2443 AssertRC(rc2);
2444 }
2445
2446 /* Skip the instruction and continue. */
2447 pCtx->rip += 2; /* wrmsr = [0F 30] */
2448
2449 /* Only resume if successful. */
2450 goto ResumeExecution;
2451 }
2452
2453 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2454 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2455 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2456 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2457 if (rc == VINF_SUCCESS)
2458 {
2459 /* EIP has been updated already. */
2460
2461 /* Only resume if successful. */
2462 goto ResumeExecution;
2463 }
2464 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", VBOXSTRICTRC_VAL(rc)));
2465 break;
2466 }
2467
2468 case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
2469 Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2470 if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
2471 && pVCpu->hwaccm.s.Event.fPending)
2472 {
2473 SVM_EVENT Event;
2474
2475 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2476
2477 /* Caused by an injected interrupt. */
2478 pVCpu->hwaccm.s.Event.fPending = false;
2479
2480 switch (Event.n.u3Type)
2481 {
2482 case SVM_EVENT_EXTERNAL_IRQ:
2483 case SVM_EVENT_NMI:
2484 Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2485 Assert(!Event.n.u1ErrorCodeValid);
2486 rc2 = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2487 AssertRC(rc2);
2488 break;
2489
2490 default:
2491 /* Exceptions and software interrupts can just be restarted. */
2492 break;
2493 }
2494 }
2495 rc = VERR_EM_INTERPRETER;
2496 break;
2497
2498 case SVM_EXIT_PAUSE:
2499 case SVM_EXIT_MWAIT_ARMED:
2500 rc = VERR_EM_INTERPRETER;
2501 break;
2502
2503 case SVM_EXIT_SHUTDOWN:
2504 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2505 break;
2506
2507 case SVM_EXIT_IDTR_READ:
2508 case SVM_EXIT_GDTR_READ:
2509 case SVM_EXIT_LDTR_READ:
2510 case SVM_EXIT_TR_READ:
2511 case SVM_EXIT_IDTR_WRITE:
2512 case SVM_EXIT_GDTR_WRITE:
2513 case SVM_EXIT_LDTR_WRITE:
2514 case SVM_EXIT_TR_WRITE:
2515 case SVM_EXIT_CR0_SEL_WRITE:
2516 default:
2517 /* Unexpected exit codes. */
2518 rc = VERR_HMSVM_UNEXPECTED_EXIT;
2519 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2520 break;
2521 }
2522
2523end:
2524
2525 /* We now going back to ring-3, so clear the action flag. */
2526 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2527
2528 /* Signal changes for the recompiler. */
2529 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2530
2531 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2532 if (exitCode == SVM_EXIT_INTR)
2533 {
2534 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2535 /* On the next entry we'll only sync the host context. */
2536 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2537 }
2538 else
2539 {
2540 /* On the next entry we'll sync everything. */
2541 /** @todo we can do better than this */
2542 /* Not in the VINF_PGM_CHANGE_MODE though! */
2543 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2544 }
2545
2546 /* translate into a less severe return code */
2547 if (rc == VERR_EM_INTERPRETER)
2548 rc = VINF_EM_RAW_EMULATE_INSTR;
2549
2550 /* Just set the correct state here instead of trying to catch every goto above. */
2551 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2552
2553#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2554 /* Restore interrupts if we exitted after disabling them. */
2555 if (uOldEFlags != ~(RTCCUINTREG)0)
2556 ASMSetFlags(uOldEFlags);
2557#endif
2558
2559 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, x);
2560 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2561 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
2562 return VBOXSTRICTRC_TODO(rc);
2563}
2564
2565/**
2566 * Emulate simple mov tpr instruction
2567 *
2568 * @returns VBox status code.
2569 * @param pVM The VM to operate on.
2570 * @param pVCpu The VM CPU to operate on.
2571 * @param pCtx CPU context
2572 */
2573static int hmR0SvmEmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2574{
2575 int rc;
2576
2577 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2578
2579 while (true)
2580 {
2581 bool fPending;
2582 uint8_t u8Tpr;
2583
2584 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2585 if (!pPatch)
2586 break;
2587
2588 switch(pPatch->enmType)
2589 {
2590 case HWACCMTPRINSTR_READ:
2591 /* TPR caching in CR8 */
2592 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2593 AssertRC(rc);
2594
2595 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2596 AssertRC(rc);
2597
2598 LogFlow(("Emulated read successfully\n"));
2599 pCtx->rip += pPatch->cbOp;
2600 break;
2601
2602 case HWACCMTPRINSTR_WRITE_REG:
2603 case HWACCMTPRINSTR_WRITE_IMM:
2604 /* Fetch the new TPR value */
2605 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2606 {
2607 uint32_t val;
2608
2609 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2610 AssertRC(rc);
2611 u8Tpr = val;
2612 }
2613 else
2614 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2615
2616 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2617 AssertRC(rc);
2618 LogFlow(("Emulated write successfully\n"));
2619 pCtx->rip += pPatch->cbOp;
2620 break;
2621 default:
2622 AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_HMSVM_UNEXPECTED_PATCH_TYPE);
2623 }
2624 }
2625 return VINF_SUCCESS;
2626}
2627
2628
2629/**
2630 * Enters the AMD-V session
2631 *
2632 * @returns VBox status code.
2633 * @param pVM The VM to operate on.
2634 * @param pVCpu The VM CPU to operate on.
2635 * @param pCpu CPU info struct
2636 */
2637VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
2638{
2639 Assert(pVM->hwaccm.s.svm.fSupported);
2640
2641 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2642 pVCpu->hwaccm.s.fResumeVM = false;
2643
2644 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2645 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2646
2647 return VINF_SUCCESS;
2648}
2649
2650
2651/**
2652 * Leaves the AMD-V session
2653 *
2654 * @returns VBox status code.
2655 * @param pVM The VM to operate on.
2656 * @param pVCpu The VM CPU to operate on.
2657 * @param pCtx CPU context
2658 */
2659VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2660{
2661 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2662
2663 Assert(pVM->hwaccm.s.svm.fSupported);
2664
2665#ifdef DEBUG
2666 if (CPUMIsHyperDebugStateActive(pVCpu))
2667 {
2668 CPUMR0LoadHostDebugState(pVM, pVCpu);
2669 }
2670 else
2671#endif
2672 /* Save the guest debug state if necessary. */
2673 if (CPUMIsGuestDebugStateActive(pVCpu))
2674 {
2675 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2676
2677 /* Intercept all DRx reads and writes again. Changed later on. */
2678 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2679 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2680
2681 /* Resync the debug registers the next time. */
2682 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2683 }
2684 else
2685 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2686
2687 return VINF_SUCCESS;
2688}
2689
2690
2691static int hmR0svmInterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2692{
2693 OP_PARAMVAL param1;
2694 RTGCPTR addr;
2695 NOREF(uASID);
2696
2697 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2698 if(RT_FAILURE(rc))
2699 return VERR_EM_INTERPRETER;
2700
2701 switch(param1.type)
2702 {
2703 case PARMTYPE_IMMEDIATE:
2704 case PARMTYPE_ADDRESS:
2705 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2706 return VERR_EM_INTERPRETER;
2707 addr = param1.val.val64;
2708 break;
2709
2710 default:
2711 return VERR_EM_INTERPRETER;
2712 }
2713
2714 /** @todo is addr always a flat linear address or ds based
2715 * (in absence of segment override prefixes)????
2716 */
2717 rc = PGMInvalidatePage(pVCpu, addr);
2718 if (RT_SUCCESS(rc))
2719 return VINF_SUCCESS;
2720
2721 AssertRC(rc);
2722 return rc;
2723}
2724
2725/**
2726 * Interprets INVLPG
2727 *
2728 * @returns VBox status code.
2729 * @retval VINF_* Scheduling instructions.
2730 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2731 * @retval VERR_* Fatal errors.
2732 *
2733 * @param pVM The VM handle.
2734 * @param pRegFrame The register frame.
2735 * @param ASID Tagged TLB id for the guest
2736 *
2737 * Updates the EIP if an instruction was executed successfully.
2738 */
2739static int hmR0SvmInterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2740{
2741 /*
2742 * Only allow 32 & 64 bits code.
2743 */
2744 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2745 if (enmMode != CPUMODE_16BIT)
2746 {
2747 RTGCPTR pbCode;
2748 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
2749 &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2750 if (RT_SUCCESS(rc))
2751 {
2752 uint32_t cbOp;
2753 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2754
2755 pDis->mode = enmMode;
2756 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2757 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2758 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2759 {
2760 Assert(cbOp == pDis->opsize);
2761 rc = hmR0svmInterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2762 if (RT_SUCCESS(rc))
2763 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2764
2765 return rc;
2766 }
2767 }
2768 }
2769 return VERR_EM_INTERPRETER;
2770}
2771
2772
2773/**
2774 * Invalidates a guest page
2775 *
2776 * @returns VBox status code.
2777 * @param pVM The VM to operate on.
2778 * @param pVCpu The VM CPU to operate on.
2779 * @param GCVirt Page to invalidate
2780 */
2781VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2782{
2783 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2784
2785 /* Skip it if a TLB flush is already pending. */
2786 if (!fFlushPending)
2787 {
2788 SVM_VMCB *pVMCB;
2789
2790 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2791 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2792 Assert(pVM->hwaccm.s.svm.fSupported);
2793
2794 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2795 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_HMSVM_INVALID_PVMCB);
2796
2797#if HC_ARCH_BITS == 32
2798 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2799 if (CPUMIsGuestInLongMode(pVCpu))
2800 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2801 else
2802#endif
2803 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2804 }
2805 return VINF_SUCCESS;
2806}
2807
2808
2809#if 0 /* obsolete, but left here for clarification. */
2810/**
2811 * Invalidates a guest page by physical address
2812 *
2813 * @returns VBox status code.
2814 * @param pVM The VM to operate on.
2815 * @param pVCpu The VM CPU to operate on.
2816 * @param GCPhys Page to invalidate
2817 */
2818VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2819{
2820 Assert(pVM->hwaccm.s.fNestedPaging);
2821 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2822 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2823 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2824 return VINF_SUCCESS;
2825}
2826#endif
2827
2828#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2829/**
2830 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2831 *
2832 * @returns VBox status code.
2833 * @param pVMCBHostPhys Physical address of host VMCB.
2834 * @param pVMCBPhys Physical address of the VMCB.
2835 * @param pCtx Guest context.
2836 * @param pVM The VM to operate on.
2837 * @param pVCpu The VMCPU to operate on.
2838 */
2839DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2840{
2841 uint32_t aParam[4];
2842
2843 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2844 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2845 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2846 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2847
2848 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2849}
2850
2851/**
2852 * Executes the specified handler in 64 mode
2853 *
2854 * @returns VBox status code.
2855 * @param pVM The VM to operate on.
2856 * @param pVCpu The VMCPU to operate on.
2857 * @param pCtx Guest context
2858 * @param pfnHandler RC handler
2859 * @param cbParam Number of parameters
2860 * @param paParam Array of 32 bits parameters
2861 */
2862VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2863{
2864 int rc;
2865 RTHCUINTREG uOldEFlags;
2866
2867 Assert(pfnHandler);
2868
2869 /* Disable interrupts. */
2870 uOldEFlags = ASMIntDisableFlags();
2871
2872 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
2873 CPUMSetHyperEIP(pVCpu, pfnHandler);
2874 for (int i=(int)cbParam-1;i>=0;i--)
2875 CPUMPushHyper(pVCpu, paParam[i]);
2876
2877 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2878 /* Call switcher. */
2879 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
2880 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2881
2882 ASMSetFlags(uOldEFlags);
2883 return rc;
2884}
2885
2886#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
2887
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