VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 8868

Last change on this file since 8868 was 8868, checked in by vboxsync, 17 years ago

Base & extended model corrections.
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File size: 68.4 KB
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1/* $Id: HWSVMR0.cpp 8868 2008-05-16 07:43:10Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include "HWSVMR0.h"
45
46static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
47
48/**
49 * Sets up and activates AMD-V on the current CPU
50 *
51 * @returns VBox status code.
52 * @param idCpu The identifier for the CPU the function is called on.
53 * @param pVM The VM to operate on.
54 * @param pvPageCpu Pointer to the global cpu page
55 * @param pPageCpuPhys Physical address of the global cpu page
56 */
57HWACCMR0DECL(int) SVMR0EnableCpu(RTCPUID idCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
58{
59 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
60 AssertReturn(pVM, VERR_INVALID_PARAMETER);
61 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
62
63 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
64
65 /* Turn on AMD-V in the EFER MSR. */
66 uint64_t val = ASMRdMsr(MSR_K6_EFER);
67 if (!(val & MSR_K6_EFER_SVME))
68 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
69
70 /* Write the physical page address where the CPU will store the host state while executing the VM. */
71 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
72 return VINF_SUCCESS;
73}
74
75/**
76 * Deactivates AMD-V on the current CPU
77 *
78 * @returns VBox status code.
79 * @param idCpu The identifier for the CPU the function is called on.
80 * @param pvPageCpu Pointer to the global cpu page
81 * @param pPageCpuPhys Physical address of the global cpu page
82 */
83HWACCMR0DECL(int) SVMR0DisableCpu(RTCPUID idCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
84{
85 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
86 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
87
88 /* Turn off AMD-V in the EFER MSR. */
89 uint64_t val = ASMRdMsr(MSR_K6_EFER);
90 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
91
92 /* Invalidate host state physical address. */
93 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
94 return VINF_SUCCESS;
95}
96
97/**
98 * Does Ring-0 per VM AMD-V init.
99 *
100 * @returns VBox status code.
101 * @param pVM The VM to operate on.
102 */
103HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
104{
105 int rc;
106
107 /* Allocate one page for the VM control block (VMCB). */
108 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
109 if (RT_FAILURE(rc))
110 return rc;
111
112 pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
113 pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
114 ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
115
116 /* Allocate one page for the host context */
117 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
118 if (RT_FAILURE(rc))
119 return rc;
120
121 pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
122 pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
123 ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
124
125 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
126 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
127 if (RT_FAILURE(rc))
128 return rc;
129
130 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
131 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
132 /* Set all bits to intercept all IO accesses. */
133 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
134
135 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
136 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
137 if (RT_FAILURE(rc))
138 return rc;
139
140 pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
141 pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
142 /* Set all bits to intercept all MSR accesses. */
143 ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
144
145 /* Erratum 170 which requires a forced TLB flush for each world switch:
146 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
147 *
148 * All BH-G1/2 and DH-G1/2 models include a fix:
149 * Athlon X2: 0x6b 1/2
150 * 0x68 1/2
151 * Athlon 64: 0x7f 1
152 * 0x6f 2
153 * Sempron: 0x7f 1/2
154 * 0x6f 2
155 * 0x6c 2
156 * 0x7c 2
157 * Turion 64: 0x68 2
158 *
159 */
160 uint32_t u32Dummy;
161 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
162 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
163 u32BaseFamily= (u32Version >> 8) & 0xf;
164 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
165 u32Model = ((u32Version >> 4) & 0xf);
166 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
167 u32Stepping = u32Version & 0xf;
168 if ( u32Family == 0xf
169 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
170 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
171 {
172 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
173 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
174 }
175
176 return VINF_SUCCESS;
177}
178
179/**
180 * Does Ring-0 per VM AMD-V termination.
181 *
182 * @returns VBox status code.
183 * @param pVM The VM to operate on.
184 */
185HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
186{
187 if (pVM->hwaccm.s.svm.pMemObjVMCB)
188 {
189 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
190 pVM->hwaccm.s.svm.pVMCB = 0;
191 pVM->hwaccm.s.svm.pVMCBPhys = 0;
192 pVM->hwaccm.s.svm.pMemObjVMCB = 0;
193 }
194 if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
195 {
196 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
197 pVM->hwaccm.s.svm.pVMCBHost = 0;
198 pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
199 pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
200 }
201 if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
202 {
203 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
204 pVM->hwaccm.s.svm.pIOBitmap = 0;
205 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
206 pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
207 }
208 if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
209 {
210 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
211 pVM->hwaccm.s.svm.pMSRBitmap = 0;
212 pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
213 pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
214 }
215 return VINF_SUCCESS;
216}
217
218/**
219 * Sets up AMD-V for the specified VM
220 *
221 * @returns VBox status code.
222 * @param pVM The VM to operate on.
223 */
224HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
225{
226 int rc = VINF_SUCCESS;
227 SVM_VMCB *pVMCB;
228
229 AssertReturn(pVM, VERR_INVALID_PARAMETER);
230
231 Assert(pVM->hwaccm.s.svm.fSupported);
232
233 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
234 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
235
236 /* Program the control fields. Most of them never have to be changed again. */
237 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
238 /** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
239 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
240
241 /*
242 * CR0/3/4 writes must be intercepted for obvious reasons.
243 */
244 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
245
246 /* Intercept all DRx reads and writes. */
247 pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
248 pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
249
250 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
251 * All breakpoints are automatically cleared when the VM exits.
252 */
253
254 /** @todo nested paging */
255 /* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
256 * pagefaults that need our attention).
257 */
258 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
259
260 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
261 | SVM_CTRL1_INTERCEPT_VINTR
262 | SVM_CTRL1_INTERCEPT_NMI
263 | SVM_CTRL1_INTERCEPT_SMI
264 | SVM_CTRL1_INTERCEPT_INIT
265 | SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
266 | SVM_CTRL1_INTERCEPT_RDPMC
267 | SVM_CTRL1_INTERCEPT_CPUID
268 | SVM_CTRL1_INTERCEPT_RSM
269 | SVM_CTRL1_INTERCEPT_HLT
270 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
271 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
272 | SVM_CTRL1_INTERCEPT_INVLPG
273 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
274 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
275 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
276 ;
277 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
278 | SVM_CTRL2_INTERCEPT_VMMCALL
279 | SVM_CTRL2_INTERCEPT_VMLOAD
280 | SVM_CTRL2_INTERCEPT_VMSAVE
281 | SVM_CTRL2_INTERCEPT_STGI
282 | SVM_CTRL2_INTERCEPT_CLGI
283 | SVM_CTRL2_INTERCEPT_SKINIT
284 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
285 ;
286 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
287 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
288 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
289
290 /* Virtualize masking of INTR interrupts. */
291 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
292
293 /* Set IO and MSR bitmap addresses. */
294 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
295 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
296
297 /* Enable nested paging. */
298 /** @todo how to detect support for this?? */
299 pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
300
301 /* No LBR virtualization. */
302 pVMCB->ctrl.u64LBRVirt = 0;
303
304 return rc;
305}
306
307
308/**
309 * Injects an event (trap or external interrupt)
310 *
311 * @param pVM The VM to operate on.
312 * @param pVMCB SVM control block
313 * @param pCtx CPU Context
314 * @param pIntInfo SVM interrupt info
315 */
316inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
317{
318#ifdef VBOX_STRICT
319 if (pEvent->n.u8Vector == 0xE)
320 Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
321 else
322 if (pEvent->n.u8Vector < 0x20)
323 Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
324 else
325 {
326 Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
327 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
328 Assert(pCtx->eflags.u32 & X86_EFL_IF);
329 }
330#endif
331
332 /* Set event injection state. */
333 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
334}
335
336
337/**
338 * Checks for pending guest interrupts and injects them
339 *
340 * @returns VBox status code.
341 * @param pVM The VM to operate on.
342 * @param pVMCB SVM control block
343 * @param pCtx CPU Context
344 */
345static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
346{
347 int rc;
348
349 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
350 if (pVM->hwaccm.s.Event.fPending)
351 {
352 SVM_EVENT Event;
353
354 Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
355 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
356 Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
357 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
358
359 pVM->hwaccm.s.Event.fPending = false;
360 return VINF_SUCCESS;
361 }
362
363 /* When external interrupts are pending, we should exit the VM when IF is set. */
364 if ( !TRPMHasTrap(pVM)
365 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
366 {
367 if (!(pCtx->eflags.u32 & X86_EFL_IF))
368 {
369 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
370 {
371 Log(("Enable irq window exit!\n"));
372 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
373 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
374 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
375 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; /* ignore the priority in the TPR; just deliver it */
376 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
377 }
378 }
379 else
380 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
381 {
382 uint8_t u8Interrupt;
383
384 rc = PDMGetInterrupt(pVM, &u8Interrupt);
385 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
386 if (VBOX_SUCCESS(rc))
387 {
388 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
389 AssertRC(rc);
390 }
391 else
392 {
393 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
394 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
395 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
396 /* Just continue */
397 }
398 }
399 else
400 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
401 }
402
403#ifdef VBOX_STRICT
404 if (TRPMHasTrap(pVM))
405 {
406 uint8_t u8Vector;
407 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
408 AssertRC(rc);
409 }
410#endif
411
412 if ( pCtx->eflags.u32 & X86_EFL_IF
413 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
414 && TRPMHasTrap(pVM)
415 )
416 {
417 uint8_t u8Vector;
418 int rc;
419 TRPMEVENT enmType;
420 SVM_EVENT Event;
421 uint32_t u32ErrorCode;
422
423 Event.au64[0] = 0;
424
425 /* If a new event is pending, then dispatch it now. */
426 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
427 AssertRC(rc);
428 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
429 Assert(enmType != TRPM_SOFTWARE_INT);
430
431 /* Clear the pending trap. */
432 rc = TRPMResetTrap(pVM);
433 AssertRC(rc);
434
435 Event.n.u8Vector = u8Vector;
436 Event.n.u1Valid = 1;
437 Event.n.u32ErrorCode = u32ErrorCode;
438
439 if (enmType == TRPM_TRAP)
440 {
441 switch (u8Vector) {
442 case 8:
443 case 10:
444 case 11:
445 case 12:
446 case 13:
447 case 14:
448 case 17:
449 /* Valid error codes. */
450 Event.n.u1ErrorCodeValid = 1;
451 break;
452 default:
453 break;
454 }
455 if (u8Vector == X86_XCPT_NMI)
456 Event.n.u3Type = SVM_EVENT_NMI;
457 else
458 Event.n.u3Type = SVM_EVENT_EXCEPTION;
459 }
460 else
461 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
462
463 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
464 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
465 } /* if (interrupts can be dispatched) */
466
467 return VINF_SUCCESS;
468}
469
470
471/**
472 * Loads the guest state
473 *
474 * @returns VBox status code.
475 * @param pVM The VM to operate on.
476 * @param pCtx Guest context
477 */
478HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
479{
480 RTGCUINTPTR val;
481 SVM_VMCB *pVMCB;
482
483 if (pVM == NULL)
484 return VERR_INVALID_PARAMETER;
485
486 /* Setup AMD SVM. */
487 Assert(pVM->hwaccm.s.svm.fSupported);
488
489 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
490 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
491
492 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
493 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
494 {
495 SVM_WRITE_SELREG(CS, cs);
496 SVM_WRITE_SELREG(SS, ss);
497 SVM_WRITE_SELREG(DS, ds);
498 SVM_WRITE_SELREG(ES, es);
499 SVM_WRITE_SELREG(FS, fs);
500 SVM_WRITE_SELREG(GS, gs);
501 }
502
503 /* Guest CPU context: LDTR. */
504 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
505 {
506 SVM_WRITE_SELREG(LDTR, ldtr);
507 }
508
509 /* Guest CPU context: TR. */
510 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
511 {
512 SVM_WRITE_SELREG(TR, tr);
513 }
514
515 /* Guest CPU context: GDTR. */
516 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
517 {
518 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
519 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
520 }
521
522 /* Guest CPU context: IDTR. */
523 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
524 {
525 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
526 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
527 }
528
529 /*
530 * Sysenter MSRs
531 */
532 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
533 {
534 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
535 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
536 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
537 }
538
539 /* Control registers */
540 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
541 {
542 val = pCtx->cr0;
543 if (CPUMIsGuestFPUStateActive(pVM) == false)
544 {
545 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
546 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
547 }
548 else
549 {
550 Assert(pVM->hwaccm.s.svm.fResumeVM == true);
551 /** @todo check if we support the old style mess correctly. */
552 if (!(val & X86_CR0_NE))
553 {
554 Log(("Forcing X86_CR0_NE!!!\n"));
555
556 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
557 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
558 {
559 pVMCB->ctrl.u32InterceptException |= RT_BIT(16);
560 pVM->hwaccm.s.fFPUOldStyleOverride = true;
561 }
562 }
563 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
564 }
565 if (!(val & X86_CR0_CD))
566 val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
567
568 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
569 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
570 pVMCB->guest.u64CR0 = val;
571 }
572 /* CR2 as well */
573 pVMCB->guest.u64CR2 = pCtx->cr2;
574
575 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
576 {
577 /* Save our shadow CR3 register. */
578 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
579 }
580
581 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
582 {
583 val = pCtx->cr4;
584 switch(pVM->hwaccm.s.enmShadowMode)
585 {
586 case PGMMODE_REAL:
587 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
588 AssertFailed();
589 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
590
591 case PGMMODE_32_BIT: /* 32-bit paging. */
592 break;
593
594 case PGMMODE_PAE: /* PAE paging. */
595 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
596 /** @todo use normal 32 bits paging */
597 val |= X86_CR4_PAE;
598 break;
599
600 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
601 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
602 AssertFailed();
603 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
604
605 default: /* shut up gcc */
606 AssertFailed();
607 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
608 }
609 pVMCB->guest.u64CR4 = val;
610 }
611
612 /* Debug registers. */
613 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
614 {
615 /** @todo DR0-6 */
616 val = pCtx->dr7;
617 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
618 val |= 0x400; /* must be one */
619#ifdef VBOX_STRICT
620 val = 0x400;
621#endif
622 pVMCB->guest.u64DR7 = val;
623
624 pVMCB->guest.u64DR6 = pCtx->dr6;
625 }
626
627 /* EIP, ESP and EFLAGS */
628 pVMCB->guest.u64RIP = pCtx->eip;
629 pVMCB->guest.u64RSP = pCtx->esp;
630 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
631
632 /* Set CPL */
633 pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
634
635 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
636 pVMCB->guest.u64RAX = pCtx->eax;
637
638 /* vmrun will fail otherwise. */
639 pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
640
641 /** @note We can do more complex things with tagged TLBs. */
642 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
643
644 /** TSC offset. */
645 if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
646 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
647 else
648 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
649
650 /** @todo 64 bits stuff (?):
651 * - STAR
652 * - LSTAR
653 * - CSTAR
654 * - SFMASK
655 * - KernelGSBase
656 */
657
658#ifdef DEBUG
659 /* Intercept X86_XCPT_DB if stepping is enabled */
660 if (DBGFIsStepping(pVM))
661 pVMCB->ctrl.u32InterceptException |= RT_BIT(1);
662 else
663 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
664#endif
665
666 /* Done. */
667 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
668
669 return VINF_SUCCESS;
670}
671
672
673/**
674 * Runs guest code in an SVM VM.
675 *
676 * @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
677 *
678 * @returns VBox status code.
679 * @param pVM The VM to operate on.
680 * @param pCtx Guest context
681 */
682HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
683{
684 int rc = VINF_SUCCESS;
685 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
686 SVM_VMCB *pVMCB;
687 bool fGuestStateSynced = false;
688 unsigned cResume = 0;
689
690 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
691
692 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
693 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
694
695 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
696 */
697ResumeExecution:
698 /* Safety precaution; looping for too long here can have a very bad effect on the host */
699 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
700 {
701 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
702 rc = VINF_EM_RAW_INTERRUPT;
703 goto end;
704 }
705
706 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
707 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
708 {
709 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
710 if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
711 {
712 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
713 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
714 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
715 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
716 */
717 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
718 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
719 pVMCB->ctrl.u64IntShadow = 0;
720 }
721 }
722 else
723 {
724 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
725 pVMCB->ctrl.u64IntShadow = 0;
726 }
727
728 /* Check for pending actions that force us to go back to ring 3. */
729#ifdef DEBUG
730 /* Intercept X86_XCPT_DB if stepping is enabled */
731 if (!DBGFIsStepping(pVM))
732#endif
733 {
734 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
735 {
736 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
737 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
738 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
739 rc = VINF_EM_RAW_TO_R3;
740 goto end;
741 }
742 }
743
744 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
745 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
746 {
747 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
748 rc = VINF_EM_PENDING_REQUEST;
749 goto end;
750 }
751
752 /* When external interrupts are pending, we should exit the VM when IF is set. */
753 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
754 rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
755 if (VBOX_FAILURE(rc))
756 {
757 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
758 goto end;
759 }
760
761 /* Load the guest state */
762 rc = SVMR0LoadGuestState(pVM, pCtx);
763 if (rc != VINF_SUCCESS)
764 {
765 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
766 goto end;
767 }
768 fGuestStateSynced = true;
769
770 /* All done! Let's start VM execution. */
771 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
772
773 /* Make sure we flush the TLB when required. */
774 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
775#ifdef VBOX_WITH_STATISTICS
776 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
777 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
778 else
779 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
780#endif
781
782 /* In case we execute a goto ResumeExecution later on. */
783 pVM->hwaccm.s.svm.fResumeVM = true;
784 pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
785
786 Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
787 Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
788 | SVM_CTRL2_INTERCEPT_VMMCALL
789 | SVM_CTRL2_INTERCEPT_VMLOAD
790 | SVM_CTRL2_INTERCEPT_VMSAVE
791 | SVM_CTRL2_INTERCEPT_STGI
792 | SVM_CTRL2_INTERCEPT_CLGI
793 | SVM_CTRL2_INTERCEPT_SKINIT
794 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
795 ));
796 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
797 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
798 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
799 Assert(pVMCB->ctrl.u64NestedPaging == 0);
800 Assert(pVMCB->ctrl.u64LBRVirt == 0);
801
802 SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
803 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
804
805 /**
806 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
807 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
808 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
809 */
810
811 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
812
813 /* Reason for the VM exit */
814 exitCode = pVMCB->ctrl.u64ExitCode;
815
816 if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
817 {
818 HWACCMDumpRegs(pCtx);
819#ifdef DEBUG
820 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
821 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
822 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
823 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
824 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
825 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
826 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
827 Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
828 Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
829 Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
830
831 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
832 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
833 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
834 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
835
836 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
837 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
838 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
839 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
840 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
841 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
842 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
843 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
844 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
845 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
846
847 Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
848 Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
849 Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
850 Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
851 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
852 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
853 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
854 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
855 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
856 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
857 Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
858 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
859 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
860 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
861 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
862 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
863 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
864
865 Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
866 Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
867
868 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
869 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
870 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
871 Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
872 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
873 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
874 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
875 Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
876 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
877 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
878 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
879 Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
880 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
881 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
882 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
883 Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
884 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
885 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
886 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
887 Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
888
889 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
890 Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
891
892 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
893 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
894 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
895 Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
896
897 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
898 Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
899
900 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
901 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
902 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
903 Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
904
905 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
906 Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
907 Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
908 Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
909 Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
910 Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
911 Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
912
913 Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
914 Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
915 Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
916 Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
917
918 Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
919 Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
920 Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
921
922 Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
923 Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
924 Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
925 Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
926 Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
927 Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
928 Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
929 Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
930 Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
931 Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
932 Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
933 Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
934
935#endif
936 rc = VERR_SVM_UNABLE_TO_START_VM;
937 goto end;
938 }
939
940 /* Let's first sync back eip, esp, and eflags. */
941 pCtx->eip = pVMCB->guest.u64RIP;
942 pCtx->esp = pVMCB->guest.u64RSP;
943 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
944 /* eax is saved/restore across the vmrun instruction */
945 pCtx->eax = pVMCB->guest.u64RAX;
946
947 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
948 SVM_READ_SELREG(SS, ss);
949 SVM_READ_SELREG(CS, cs);
950 SVM_READ_SELREG(DS, ds);
951 SVM_READ_SELREG(ES, es);
952 SVM_READ_SELREG(FS, fs);
953 SVM_READ_SELREG(GS, gs);
954
955 /** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
956
957 /** @note NOW IT'S SAFE FOR LOGGING! */
958
959 /* Take care of instruction fusing (sti, mov ss) */
960 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
961 {
962 Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
963 EMSetInhibitInterruptsPC(pVM, pCtx->eip);
964 }
965 else
966 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
967
968 Log2(("exitCode = %x\n", exitCode));
969
970 /* Check if an injected event was interrupted prematurely. */
971 pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
972 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
973 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
974 {
975 Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
976 pVM->hwaccm.s.Event.fPending = true;
977 /* Error code present? (redundant) */
978 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
979 {
980 pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
981 }
982 else
983 pVM->hwaccm.s.Event.errCode = 0;
984 }
985 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
986
987 /* Deal with the reason of the VM-exit. */
988 switch (exitCode)
989 {
990 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
991 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
992 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
993 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
994 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
995 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
996 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
997 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
998 {
999 /* Pending trap. */
1000 SVM_EVENT Event;
1001 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1002
1003 Log2(("Hardware/software interrupt %d\n", vector));
1004 switch (vector)
1005 {
1006#ifdef DEBUG
1007 case X86_XCPT_DB:
1008 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1009 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1010 break;
1011#endif
1012
1013 case X86_XCPT_NM:
1014 {
1015 uint32_t oldCR0;
1016
1017 Log(("#NM fault at %VGv\n", pCtx->eip));
1018
1019 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1020 oldCR0 = ASMGetCR0();
1021 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1022 rc = CPUMHandleLazyFPU(pVM);
1023 if (rc == VINF_SUCCESS)
1024 {
1025 Assert(CPUMIsGuestFPUStateActive(pVM));
1026
1027 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
1028 ASMSetCR0(oldCR0);
1029
1030 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1031
1032 /* Continue execution. */
1033 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1034 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1035
1036 goto ResumeExecution;
1037 }
1038
1039 Log(("Forward #NM fault to the guest\n"));
1040 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1041
1042 Event.au64[0] = 0;
1043 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1044 Event.n.u1Valid = 1;
1045 Event.n.u8Vector = X86_XCPT_NM;
1046
1047 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1048 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1049 goto ResumeExecution;
1050 }
1051
1052 case X86_XCPT_PF: /* Page fault */
1053 {
1054 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1055 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1056
1057 Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1058 /* Exit qualification contains the linear address of the page fault. */
1059 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1060 TRPMSetErrorCode(pVM, errCode);
1061 TRPMSetFaultAddress(pVM, uFaultAddress);
1062
1063 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1064 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1065 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1066 if (rc == VINF_SUCCESS)
1067 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1068 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1069 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1070
1071 TRPMResetTrap(pVM);
1072
1073 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1074 goto ResumeExecution;
1075 }
1076 else
1077 if (rc == VINF_EM_RAW_GUEST_TRAP)
1078 { /* A genuine pagefault.
1079 * Forward the trap to the guest by injecting the exception and resuming execution.
1080 */
1081 Log2(("Forward page fault to the guest\n"));
1082 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1083 /* The error code might have been changed. */
1084 errCode = TRPMGetErrorCode(pVM);
1085
1086 TRPMResetTrap(pVM);
1087
1088 /* Now we must update CR2. */
1089 pCtx->cr2 = uFaultAddress;
1090
1091 Event.au64[0] = 0;
1092 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1093 Event.n.u1Valid = 1;
1094 Event.n.u8Vector = X86_XCPT_PF;
1095 Event.n.u1ErrorCodeValid = 1;
1096 Event.n.u32ErrorCode = errCode;
1097
1098 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1099
1100 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1101 goto ResumeExecution;
1102 }
1103#ifdef VBOX_STRICT
1104 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1105 Log(("PGMTrap0eHandler failed with %d\n", rc));
1106#endif
1107 /* Need to go back to the recompiler to emulate the instruction. */
1108 TRPMResetTrap(pVM);
1109 break;
1110 }
1111
1112 case X86_XCPT_MF: /* Floating point exception. */
1113 {
1114 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1115 if (!(pCtx->cr0 & X86_CR0_NE))
1116 {
1117 /* old style FPU error reporting needs some extra work. */
1118 /** @todo don't fall back to the recompiler, but do it manually. */
1119 rc = VINF_EM_RAW_EMULATE_INSTR;
1120 break;
1121 }
1122 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1123
1124 Event.au64[0] = 0;
1125 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1126 Event.n.u1Valid = 1;
1127 Event.n.u8Vector = X86_XCPT_MF;
1128
1129 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1130
1131 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1132 goto ResumeExecution;
1133 }
1134
1135#ifdef VBOX_STRICT
1136 case X86_XCPT_GP: /* General protection failure exception.*/
1137 case X86_XCPT_UD: /* Unknown opcode exception. */
1138 case X86_XCPT_DE: /* Debug exception. */
1139 case X86_XCPT_SS: /* Stack segment exception. */
1140 case X86_XCPT_NP: /* Segment not present exception. */
1141 {
1142 Event.au64[0] = 0;
1143 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1144 Event.n.u1Valid = 1;
1145 Event.n.u8Vector = vector;
1146
1147 switch(vector)
1148 {
1149 case X86_XCPT_GP:
1150 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1151 Event.n.u1ErrorCodeValid = 1;
1152 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1153 break;
1154 case X86_XCPT_DE:
1155 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1156 break;
1157 case X86_XCPT_UD:
1158 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1159 break;
1160 case X86_XCPT_SS:
1161 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1162 Event.n.u1ErrorCodeValid = 1;
1163 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1164 break;
1165 case X86_XCPT_NP:
1166 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1167 Event.n.u1ErrorCodeValid = 1;
1168 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1169 break;
1170 }
1171 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1172 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1173
1174 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1175 goto ResumeExecution;
1176 }
1177#endif
1178 default:
1179 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1180 rc = VERR_EM_INTERNAL_ERROR;
1181 break;
1182
1183 } /* switch (vector) */
1184 break;
1185 }
1186
1187 case SVM_EXIT_VINTR:
1188 /* A virtual interrupt is about to be delivered, which means IF=1. */
1189 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1190 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1191 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 0;
1192 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1193 goto ResumeExecution;
1194
1195 case SVM_EXIT_FERR_FREEZE:
1196 case SVM_EXIT_INTR:
1197 case SVM_EXIT_NMI:
1198 case SVM_EXIT_SMI:
1199 case SVM_EXIT_INIT:
1200 /* External interrupt; leave to allow it to be dispatched again. */
1201 rc = VINF_EM_RAW_INTERRUPT;
1202 break;
1203
1204 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1205 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1206 /* Skip instruction and continue directly. */
1207 pCtx->eip += 2; /** @note hardcoded opcode size! */
1208 /* Continue execution.*/
1209 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1210 goto ResumeExecution;
1211
1212 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1213 {
1214 Log2(("SVM: Cpuid %x\n", pCtx->eax));
1215 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1216 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1217 if (rc == VINF_SUCCESS)
1218 {
1219 /* Update EIP and continue execution. */
1220 pCtx->eip += 2; /** @note hardcoded opcode size! */
1221 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1222 goto ResumeExecution;
1223 }
1224 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1225 rc = VINF_EM_RAW_EMULATE_INSTR;
1226 break;
1227 }
1228
1229 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1230 {
1231 Log2(("SVM: Rdtsc\n"));
1232 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1233 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1234 if (rc == VINF_SUCCESS)
1235 {
1236 /* Update EIP and continue execution. */
1237 pCtx->eip += 2; /** @note hardcoded opcode size! */
1238 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1239 goto ResumeExecution;
1240 }
1241 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1242 rc = VINF_EM_RAW_EMULATE_INSTR;
1243 break;
1244 }
1245
1246 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1247 {
1248 Log2(("SVM: invlpg\n"));
1249 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1250
1251 /* Truly a pita. Why can't SVM give the same information as VMX? */
1252 rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1253 if (rc == VINF_SUCCESS)
1254 {
1255 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1256 goto ResumeExecution; /* eip already updated */
1257 }
1258 break;
1259 }
1260
1261 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1262 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1263 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1264 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1265 {
1266 uint32_t cbSize;
1267
1268 Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1269 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1270 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1271
1272 switch (exitCode - SVM_EXIT_WRITE_CR0)
1273 {
1274 case 0:
1275 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1276 break;
1277 case 2:
1278 break;
1279 case 3:
1280 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1281 break;
1282 case 4:
1283 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1284 break;
1285 default:
1286 AssertFailed();
1287 }
1288 /* Check if a sync operation is pending. */
1289 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1290 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1291 {
1292 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1293 AssertRC(rc);
1294
1295 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1296
1297 /** @note Force a TLB flush. SVM requires us to do it manually. */
1298 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1299 }
1300 if (rc == VINF_SUCCESS)
1301 {
1302 /* EIP has been updated already. */
1303
1304 /* Only resume if successful. */
1305 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1306 goto ResumeExecution;
1307 }
1308 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1309 break;
1310 }
1311
1312 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1313 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1314 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1315 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1316 {
1317 uint32_t cbSize;
1318
1319 Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1320 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1321 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1322 if (rc == VINF_SUCCESS)
1323 {
1324 /* EIP has been updated already. */
1325
1326 /* Only resume if successful. */
1327 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1328 goto ResumeExecution;
1329 }
1330 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1331 break;
1332 }
1333
1334 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1335 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1336 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1337 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1338 {
1339 uint32_t cbSize;
1340
1341 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1342 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1343 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1344 if (rc == VINF_SUCCESS)
1345 {
1346 /* EIP has been updated already. */
1347
1348 /* Only resume if successful. */
1349 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1350 goto ResumeExecution;
1351 }
1352 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1353 break;
1354 }
1355
1356 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1357 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1358 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1359 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1360 {
1361 uint32_t cbSize;
1362
1363 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1364 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1365 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1366 if (rc == VINF_SUCCESS)
1367 {
1368 /* EIP has been updated already. */
1369
1370 /* Only resume if successful. */
1371 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1372 goto ResumeExecution;
1373 }
1374 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1375 break;
1376 }
1377
1378 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1379 case SVM_EXIT_IOIO: /* I/O instruction. */
1380 {
1381 SVM_IOIO_EXIT IoExitInfo;
1382 uint32_t uIOSize, uAndVal;
1383
1384 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1385
1386 /** @todo could use a lookup table here */
1387 if (IoExitInfo.n.u1OP8)
1388 {
1389 uIOSize = 1;
1390 uAndVal = 0xff;
1391 }
1392 else
1393 if (IoExitInfo.n.u1OP16)
1394 {
1395 uIOSize = 2;
1396 uAndVal = 0xffff;
1397 }
1398 else
1399 if (IoExitInfo.n.u1OP32)
1400 {
1401 uIOSize = 4;
1402 uAndVal = 0xffffffff;
1403 }
1404 else
1405 {
1406 AssertFailed(); /* should be fatal. */
1407 rc = VINF_EM_RAW_EMULATE_INSTR;
1408 break;
1409 }
1410
1411 if (IoExitInfo.n.u1STR)
1412 {
1413 /* ins/outs */
1414 uint32_t prefix = 0;
1415 if (IoExitInfo.n.u1REP)
1416 prefix |= PREFIX_REP;
1417
1418 if (IoExitInfo.n.u1Type == 0)
1419 {
1420 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1421 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1422 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1423 }
1424 else
1425 {
1426 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1427 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1428 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1429 }
1430 }
1431 else
1432 {
1433 /* normal in/out */
1434 Assert(!IoExitInfo.n.u1REP);
1435
1436 if (IoExitInfo.n.u1Type == 0)
1437 {
1438 Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1439 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1440 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1441 }
1442 else
1443 {
1444 uint32_t u32Val = 0;
1445
1446 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1447 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1448 if (IOM_SUCCESS(rc))
1449 {
1450 /* Write back to the EAX register. */
1451 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1452 Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1453 }
1454 }
1455 }
1456 /*
1457 * Handled the I/O return codes.
1458 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1459 */
1460 if (IOM_SUCCESS(rc))
1461 {
1462 /* Update EIP and continue execution. */
1463 pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1464 if (RT_LIKELY(rc == VINF_SUCCESS))
1465 {
1466 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1467 goto ResumeExecution;
1468 }
1469 Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1470 break;
1471 }
1472
1473#ifdef VBOX_STRICT
1474 if (rc == VINF_IOM_HC_IOPORT_READ)
1475 Assert(IoExitInfo.n.u1Type != 0);
1476 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1477 Assert(IoExitInfo.n.u1Type == 0);
1478 else
1479 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1480#endif
1481 Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1482 break;
1483 }
1484
1485 case SVM_EXIT_HLT:
1486 /** Check if external interrupts are pending; if so, don't switch back. */
1487 if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
1488 {
1489 pCtx->eip++; /* skip hlt */
1490 goto ResumeExecution;
1491 }
1492
1493 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1494 break;
1495
1496 case SVM_EXIT_RDPMC:
1497 case SVM_EXIT_RSM:
1498 case SVM_EXIT_INVLPGA:
1499 case SVM_EXIT_VMRUN:
1500 case SVM_EXIT_VMMCALL:
1501 case SVM_EXIT_VMLOAD:
1502 case SVM_EXIT_VMSAVE:
1503 case SVM_EXIT_STGI:
1504 case SVM_EXIT_CLGI:
1505 case SVM_EXIT_SKINIT:
1506 case SVM_EXIT_RDTSCP:
1507 {
1508 /* Unsupported instructions. */
1509 SVM_EVENT Event;
1510
1511 Event.au64[0] = 0;
1512 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1513 Event.n.u1Valid = 1;
1514 Event.n.u8Vector = X86_XCPT_UD;
1515
1516 Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1517 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1518
1519 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1520 goto ResumeExecution;
1521 }
1522
1523 /* Emulate RDMSR & WRMSR in ring 3. */
1524 case SVM_EXIT_MSR:
1525 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1526 break;
1527
1528 case SVM_EXIT_NPF:
1529 AssertFailed(); /* unexpected */
1530 break;
1531
1532 case SVM_EXIT_SHUTDOWN:
1533 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1534 break;
1535
1536 case SVM_EXIT_PAUSE:
1537 case SVM_EXIT_IDTR_READ:
1538 case SVM_EXIT_GDTR_READ:
1539 case SVM_EXIT_LDTR_READ:
1540 case SVM_EXIT_TR_READ:
1541 case SVM_EXIT_IDTR_WRITE:
1542 case SVM_EXIT_GDTR_WRITE:
1543 case SVM_EXIT_LDTR_WRITE:
1544 case SVM_EXIT_TR_WRITE:
1545 case SVM_EXIT_CR0_SEL_WRITE:
1546 default:
1547 /* Unexpected exit codes. */
1548 rc = VERR_EM_INTERNAL_ERROR;
1549 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1550 break;
1551 }
1552
1553end:
1554 if (fGuestStateSynced)
1555 {
1556 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1557 SVM_READ_SELREG(LDTR, ldtr);
1558 SVM_READ_SELREG(TR, tr);
1559
1560 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1561 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1562
1563 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1564 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1565
1566 /*
1567 * System MSRs
1568 */
1569 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1570 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1571 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1572 }
1573
1574 /* Signal changes for the recompiler. */
1575 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
1576
1577 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1578 if (exitCode == SVM_EXIT_INTR)
1579 {
1580 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1581 /* On the next entry we'll only sync the host context. */
1582 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
1583 }
1584 else
1585 {
1586 /* On the next entry we'll sync everything. */
1587 /** @todo we can do better than this */
1588 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
1589 }
1590
1591 /* translate into a less severe return code */
1592 if (rc == VERR_EM_INTERPRETER)
1593 rc = VINF_EM_RAW_EMULATE_INSTR;
1594
1595 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1596 return rc;
1597}
1598
1599/**
1600 * Enters the AMD-V session
1601 *
1602 * @returns VBox status code.
1603 * @param pVM The VM to operate on.
1604 */
1605HWACCMR0DECL(int) SVMR0Enter(PVM pVM)
1606{
1607 Assert(pVM->hwaccm.s.svm.fSupported);
1608
1609 /* Force a TLB flush on VM entry. */
1610 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1611
1612 pVM->hwaccm.s.svm.fResumeVM = false;
1613
1614 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1615 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
1616
1617 return VINF_SUCCESS;
1618}
1619
1620
1621/**
1622 * Leaves the AMD-V session
1623 *
1624 * @returns VBox status code.
1625 * @param pVM The VM to operate on.
1626 */
1627HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1628{
1629 Assert(pVM->hwaccm.s.svm.fSupported);
1630 return VINF_SUCCESS;
1631}
1632
1633
1634static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1635{
1636 OP_PARAMVAL param1;
1637 RTGCPTR addr;
1638
1639 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1640 if(VBOX_FAILURE(rc))
1641 return VERR_EM_INTERPRETER;
1642
1643 switch(param1.type)
1644 {
1645 case PARMTYPE_IMMEDIATE:
1646 case PARMTYPE_ADDRESS:
1647 if(!(param1.flags & PARAM_VAL32))
1648 return VERR_EM_INTERPRETER;
1649 addr = (RTGCPTR)param1.val.val32;
1650 break;
1651
1652 default:
1653 return VERR_EM_INTERPRETER;
1654 }
1655
1656 /** @todo is addr always a flat linear address or ds based
1657 * (in absence of segment override prefixes)????
1658 */
1659 rc = PGMInvalidatePage(pVM, addr);
1660 if (VBOX_SUCCESS(rc))
1661 {
1662 /* Manually invalidate the page for the VM's TLB. */
1663 Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1664 SVMInvlpgA(addr, uASID);
1665 return VINF_SUCCESS;
1666 }
1667 Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1668 return rc;
1669}
1670
1671/**
1672 * Interprets INVLPG
1673 *
1674 * @returns VBox status code.
1675 * @retval VINF_* Scheduling instructions.
1676 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1677 * @retval VERR_* Fatal errors.
1678 *
1679 * @param pVM The VM handle.
1680 * @param pRegFrame The register frame.
1681 * @param ASID Tagged TLB id for the guest
1682 *
1683 * Updates the EIP if an instruction was executed successfully.
1684 */
1685static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1686{
1687 /*
1688 * Only allow 32-bit code.
1689 */
1690 if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1691 {
1692 RTGCPTR pbCode;
1693 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1694 if (VBOX_SUCCESS(rc))
1695 {
1696 uint32_t cbOp;
1697 DISCPUSTATE Cpu;
1698
1699 Cpu.mode = CPUMODE_32BIT;
1700 rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1701 Assert(VBOX_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);
1702 if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1703 {
1704 Assert(cbOp == Cpu.opsize);
1705 rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1706 if (VBOX_SUCCESS(rc))
1707 {
1708 pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1709 }
1710 return rc;
1711 }
1712 }
1713 }
1714 return VERR_EM_INTERPRETER;
1715}
1716
1717
1718/**
1719 * Invalidates a guest page
1720 *
1721 * @returns VBox status code.
1722 * @param pVM The VM to operate on.
1723 * @param GCVirt Page to invalidate
1724 */
1725HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
1726{
1727 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | pVM->hwaccm.s.svm.fForceTLBFlush;
1728
1729 /* Skip it if a TLB flush is already pending. */
1730 if (!fFlushPending)
1731 {
1732 SVM_VMCB *pVMCB;
1733
1734 Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
1735 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1736 Assert(pVM->hwaccm.s.svm.fSupported);
1737
1738 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
1739 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
1740
1741 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
1742 SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
1743 }
1744 return VINF_SUCCESS;
1745}
1746
1747/**
1748 * Flushes the guest TLB
1749 *
1750 * @returns VBox status code.
1751 * @param pVM The VM to operate on.
1752 */
1753HWACCMR0DECL(int) SVMR0FlushTLB(PVM pVM)
1754{
1755 Log2(("SVMR0FlushTLB\n"));
1756 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1757 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBManual);
1758 return VINF_SUCCESS;
1759}
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