VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 8871

Last change on this file since 8871 was 8871, checked in by vboxsync, 17 years ago

Updated assertion
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1/* $Id: HWSVMR0.cpp 8871 2008-05-16 08:29:00Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include "HWSVMR0.h"
45
46static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
47
48/**
49 * Sets up and activates AMD-V on the current CPU
50 *
51 * @returns VBox status code.
52 * @param idCpu The identifier for the CPU the function is called on.
53 * @param pVM The VM to operate on.
54 * @param pvPageCpu Pointer to the global cpu page
55 * @param pPageCpuPhys Physical address of the global cpu page
56 */
57HWACCMR0DECL(int) SVMR0EnableCpu(RTCPUID idCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
58{
59 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
60 AssertReturn(pVM, VERR_INVALID_PARAMETER);
61 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
62
63 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
64
65 /* Turn on AMD-V in the EFER MSR. */
66 uint64_t val = ASMRdMsr(MSR_K6_EFER);
67 if (!(val & MSR_K6_EFER_SVME))
68 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
69
70 /* Write the physical page address where the CPU will store the host state while executing the VM. */
71 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
72 return VINF_SUCCESS;
73}
74
75/**
76 * Deactivates AMD-V on the current CPU
77 *
78 * @returns VBox status code.
79 * @param idCpu The identifier for the CPU the function is called on.
80 * @param pvPageCpu Pointer to the global cpu page
81 * @param pPageCpuPhys Physical address of the global cpu page
82 */
83HWACCMR0DECL(int) SVMR0DisableCpu(RTCPUID idCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
84{
85 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
86 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
87
88 /* Turn off AMD-V in the EFER MSR. */
89 uint64_t val = ASMRdMsr(MSR_K6_EFER);
90 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
91
92 /* Invalidate host state physical address. */
93 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
94 return VINF_SUCCESS;
95}
96
97/**
98 * Does Ring-0 per VM AMD-V init.
99 *
100 * @returns VBox status code.
101 * @param pVM The VM to operate on.
102 */
103HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
104{
105 int rc;
106
107 /* Allocate one page for the VM control block (VMCB). */
108 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
109 if (RT_FAILURE(rc))
110 return rc;
111
112 pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
113 pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
114 ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
115
116 /* Allocate one page for the host context */
117 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
118 if (RT_FAILURE(rc))
119 return rc;
120
121 pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
122 pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
123 ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
124
125 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
126 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
127 if (RT_FAILURE(rc))
128 return rc;
129
130 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
131 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
132 /* Set all bits to intercept all IO accesses. */
133 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
134
135 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
136 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
137 if (RT_FAILURE(rc))
138 return rc;
139
140 pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
141 pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
142 /* Set all bits to intercept all MSR accesses. */
143 ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
144
145 /* Erratum 170 which requires a forced TLB flush for each world switch:
146 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
147 *
148 * All BH-G1/2 and DH-G1/2 models include a fix:
149 * Athlon X2: 0x6b 1/2
150 * 0x68 1/2
151 * Athlon 64: 0x7f 1
152 * 0x6f 2
153 * Sempron: 0x7f 1/2
154 * 0x6f 2
155 * 0x6c 2
156 * 0x7c 2
157 * Turion 64: 0x68 2
158 *
159 */
160 uint32_t u32Dummy;
161 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
162 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
163 u32BaseFamily= (u32Version >> 8) & 0xf;
164 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
165 u32Model = ((u32Version >> 4) & 0xf);
166 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
167 u32Stepping = u32Version & 0xf;
168 if ( u32Family == 0xf
169 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
170 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
171 {
172 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
173 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
174 }
175
176 return VINF_SUCCESS;
177}
178
179/**
180 * Does Ring-0 per VM AMD-V termination.
181 *
182 * @returns VBox status code.
183 * @param pVM The VM to operate on.
184 */
185HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
186{
187 if (pVM->hwaccm.s.svm.pMemObjVMCB)
188 {
189 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
190 pVM->hwaccm.s.svm.pVMCB = 0;
191 pVM->hwaccm.s.svm.pVMCBPhys = 0;
192 pVM->hwaccm.s.svm.pMemObjVMCB = 0;
193 }
194 if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
195 {
196 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
197 pVM->hwaccm.s.svm.pVMCBHost = 0;
198 pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
199 pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
200 }
201 if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
202 {
203 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
204 pVM->hwaccm.s.svm.pIOBitmap = 0;
205 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
206 pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
207 }
208 if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
209 {
210 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
211 pVM->hwaccm.s.svm.pMSRBitmap = 0;
212 pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
213 pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
214 }
215 return VINF_SUCCESS;
216}
217
218/**
219 * Sets up AMD-V for the specified VM
220 *
221 * @returns VBox status code.
222 * @param pVM The VM to operate on.
223 */
224HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
225{
226 int rc = VINF_SUCCESS;
227 SVM_VMCB *pVMCB;
228
229 AssertReturn(pVM, VERR_INVALID_PARAMETER);
230
231 Assert(pVM->hwaccm.s.svm.fSupported);
232
233 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
234 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
235
236 /* Program the control fields. Most of them never have to be changed again. */
237 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
238 /** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
239 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
240
241 /*
242 * CR0/3/4 writes must be intercepted for obvious reasons.
243 */
244 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
245
246 /* Intercept all DRx reads and writes. */
247 pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
248 pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
249
250 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
251 * All breakpoints are automatically cleared when the VM exits.
252 */
253
254 /** @todo nested paging */
255 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
256
257 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
258 | SVM_CTRL1_INTERCEPT_VINTR
259 | SVM_CTRL1_INTERCEPT_NMI
260 | SVM_CTRL1_INTERCEPT_SMI
261 | SVM_CTRL1_INTERCEPT_INIT
262 | SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
263 | SVM_CTRL1_INTERCEPT_RDPMC
264 | SVM_CTRL1_INTERCEPT_CPUID
265 | SVM_CTRL1_INTERCEPT_RSM
266 | SVM_CTRL1_INTERCEPT_HLT
267 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
268 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
269 | SVM_CTRL1_INTERCEPT_INVLPG
270 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
271 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
272 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
273 ;
274 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
275 | SVM_CTRL2_INTERCEPT_VMMCALL
276 | SVM_CTRL2_INTERCEPT_VMLOAD
277 | SVM_CTRL2_INTERCEPT_VMSAVE
278 | SVM_CTRL2_INTERCEPT_STGI
279 | SVM_CTRL2_INTERCEPT_CLGI
280 | SVM_CTRL2_INTERCEPT_SKINIT
281 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
282 | SVM_CTRL2_INTERCEPT_WBINVD
283 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
284 ;
285 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
286 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
287 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
288
289 /* Virtualize masking of INTR interrupts. */
290 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
291
292 /* Set IO and MSR bitmap addresses. */
293 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
294 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
295
296 /* Enable nested paging. */
297 /** @todo how to detect support for this?? */
298 pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
299
300 /* No LBR virtualization. */
301 pVMCB->ctrl.u64LBRVirt = 0;
302
303 return rc;
304}
305
306
307/**
308 * Injects an event (trap or external interrupt)
309 *
310 * @param pVM The VM to operate on.
311 * @param pVMCB SVM control block
312 * @param pCtx CPU Context
313 * @param pIntInfo SVM interrupt info
314 */
315inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
316{
317#ifdef VBOX_STRICT
318 if (pEvent->n.u8Vector == 0xE)
319 Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
320 else
321 if (pEvent->n.u8Vector < 0x20)
322 Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
323 else
324 {
325 Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
326 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
327 Assert(pCtx->eflags.u32 & X86_EFL_IF);
328 }
329#endif
330
331 /* Set event injection state. */
332 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
333}
334
335
336/**
337 * Checks for pending guest interrupts and injects them
338 *
339 * @returns VBox status code.
340 * @param pVM The VM to operate on.
341 * @param pVMCB SVM control block
342 * @param pCtx CPU Context
343 */
344static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
345{
346 int rc;
347
348 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
349 if (pVM->hwaccm.s.Event.fPending)
350 {
351 SVM_EVENT Event;
352
353 Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
354 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
355 Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
356 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
357
358 pVM->hwaccm.s.Event.fPending = false;
359 return VINF_SUCCESS;
360 }
361
362 /* When external interrupts are pending, we should exit the VM when IF is set. */
363 if ( !TRPMHasTrap(pVM)
364 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
365 {
366 if (!(pCtx->eflags.u32 & X86_EFL_IF))
367 {
368 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
369 {
370 Log(("Enable irq window exit!\n"));
371 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
372 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
373 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
374 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; /* ignore the priority in the TPR; just deliver it */
375 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
376 }
377 }
378 else
379 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
380 {
381 uint8_t u8Interrupt;
382
383 rc = PDMGetInterrupt(pVM, &u8Interrupt);
384 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
385 if (VBOX_SUCCESS(rc))
386 {
387 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
388 AssertRC(rc);
389 }
390 else
391 {
392 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
393 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
394 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
395 /* Just continue */
396 }
397 }
398 else
399 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
400 }
401
402#ifdef VBOX_STRICT
403 if (TRPMHasTrap(pVM))
404 {
405 uint8_t u8Vector;
406 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
407 AssertRC(rc);
408 }
409#endif
410
411 if ( pCtx->eflags.u32 & X86_EFL_IF
412 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
413 && TRPMHasTrap(pVM)
414 )
415 {
416 uint8_t u8Vector;
417 int rc;
418 TRPMEVENT enmType;
419 SVM_EVENT Event;
420 uint32_t u32ErrorCode;
421
422 Event.au64[0] = 0;
423
424 /* If a new event is pending, then dispatch it now. */
425 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
426 AssertRC(rc);
427 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
428 Assert(enmType != TRPM_SOFTWARE_INT);
429
430 /* Clear the pending trap. */
431 rc = TRPMResetTrap(pVM);
432 AssertRC(rc);
433
434 Event.n.u8Vector = u8Vector;
435 Event.n.u1Valid = 1;
436 Event.n.u32ErrorCode = u32ErrorCode;
437
438 if (enmType == TRPM_TRAP)
439 {
440 switch (u8Vector) {
441 case 8:
442 case 10:
443 case 11:
444 case 12:
445 case 13:
446 case 14:
447 case 17:
448 /* Valid error codes. */
449 Event.n.u1ErrorCodeValid = 1;
450 break;
451 default:
452 break;
453 }
454 if (u8Vector == X86_XCPT_NMI)
455 Event.n.u3Type = SVM_EVENT_NMI;
456 else
457 Event.n.u3Type = SVM_EVENT_EXCEPTION;
458 }
459 else
460 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
461
462 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
463 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
464 } /* if (interrupts can be dispatched) */
465
466 return VINF_SUCCESS;
467}
468
469
470/**
471 * Loads the guest state
472 *
473 * @returns VBox status code.
474 * @param pVM The VM to operate on.
475 * @param pCtx Guest context
476 */
477HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
478{
479 RTGCUINTPTR val;
480 SVM_VMCB *pVMCB;
481
482 if (pVM == NULL)
483 return VERR_INVALID_PARAMETER;
484
485 /* Setup AMD SVM. */
486 Assert(pVM->hwaccm.s.svm.fSupported);
487
488 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
489 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
490
491 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
492 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
493 {
494 SVM_WRITE_SELREG(CS, cs);
495 SVM_WRITE_SELREG(SS, ss);
496 SVM_WRITE_SELREG(DS, ds);
497 SVM_WRITE_SELREG(ES, es);
498 SVM_WRITE_SELREG(FS, fs);
499 SVM_WRITE_SELREG(GS, gs);
500 }
501
502 /* Guest CPU context: LDTR. */
503 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
504 {
505 SVM_WRITE_SELREG(LDTR, ldtr);
506 }
507
508 /* Guest CPU context: TR. */
509 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
510 {
511 SVM_WRITE_SELREG(TR, tr);
512 }
513
514 /* Guest CPU context: GDTR. */
515 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
516 {
517 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
518 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
519 }
520
521 /* Guest CPU context: IDTR. */
522 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
523 {
524 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
525 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
526 }
527
528 /*
529 * Sysenter MSRs
530 */
531 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
532 {
533 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
534 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
535 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
536 }
537
538 /* Control registers */
539 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
540 {
541 val = pCtx->cr0;
542 if (CPUMIsGuestFPUStateActive(pVM) == false)
543 {
544 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
545 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
546 }
547 else
548 {
549 Assert(pVM->hwaccm.s.svm.fResumeVM == true);
550 /** @todo check if we support the old style mess correctly. */
551 if (!(val & X86_CR0_NE))
552 {
553 Log(("Forcing X86_CR0_NE!!!\n"));
554
555 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
556 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
557 {
558 pVMCB->ctrl.u32InterceptException |= RT_BIT(16);
559 pVM->hwaccm.s.fFPUOldStyleOverride = true;
560 }
561 }
562 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
563 }
564 if (!(val & X86_CR0_CD))
565 val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
566
567 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
568 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
569 pVMCB->guest.u64CR0 = val;
570 }
571 /* CR2 as well */
572 pVMCB->guest.u64CR2 = pCtx->cr2;
573
574 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
575 {
576 /* Save our shadow CR3 register. */
577 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
578 }
579
580 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
581 {
582 val = pCtx->cr4;
583 switch(pVM->hwaccm.s.enmShadowMode)
584 {
585 case PGMMODE_REAL:
586 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
587 AssertFailed();
588 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
589
590 case PGMMODE_32_BIT: /* 32-bit paging. */
591 break;
592
593 case PGMMODE_PAE: /* PAE paging. */
594 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
595 /** @todo use normal 32 bits paging */
596 val |= X86_CR4_PAE;
597 break;
598
599 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
600 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
601 AssertFailed();
602 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
603
604 default: /* shut up gcc */
605 AssertFailed();
606 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
607 }
608 pVMCB->guest.u64CR4 = val;
609 }
610
611 /* Debug registers. */
612 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
613 {
614 /** @todo DR0-6 */
615 val = pCtx->dr7;
616 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
617 val |= 0x400; /* must be one */
618#ifdef VBOX_STRICT
619 val = 0x400;
620#endif
621 pVMCB->guest.u64DR7 = val;
622
623 pVMCB->guest.u64DR6 = pCtx->dr6;
624 }
625
626 /* EIP, ESP and EFLAGS */
627 pVMCB->guest.u64RIP = pCtx->eip;
628 pVMCB->guest.u64RSP = pCtx->esp;
629 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
630
631 /* Set CPL */
632 pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
633
634 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
635 pVMCB->guest.u64RAX = pCtx->eax;
636
637 /* vmrun will fail otherwise. */
638 pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
639
640 /** @note We can do more complex things with tagged TLBs. */
641 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
642
643 /** TSC offset. */
644 if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
645 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
646 else
647 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
648
649 /** @todo 64 bits stuff (?):
650 * - STAR
651 * - LSTAR
652 * - CSTAR
653 * - SFMASK
654 * - KernelGSBase
655 */
656
657#ifdef DEBUG
658 /* Intercept X86_XCPT_DB if stepping is enabled */
659 if (DBGFIsStepping(pVM))
660 pVMCB->ctrl.u32InterceptException |= RT_BIT(1);
661 else
662 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
663#endif
664
665 /* Done. */
666 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
667
668 return VINF_SUCCESS;
669}
670
671
672/**
673 * Runs guest code in an SVM VM.
674 *
675 * @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
676 *
677 * @returns VBox status code.
678 * @param pVM The VM to operate on.
679 * @param pCtx Guest context
680 */
681HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
682{
683 int rc = VINF_SUCCESS;
684 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
685 SVM_VMCB *pVMCB;
686 bool fGuestStateSynced = false;
687 unsigned cResume = 0;
688
689 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
690
691 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
692 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
693
694 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
695 */
696ResumeExecution:
697 /* Safety precaution; looping for too long here can have a very bad effect on the host */
698 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
699 {
700 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
701 rc = VINF_EM_RAW_INTERRUPT;
702 goto end;
703 }
704
705 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
706 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
707 {
708 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
709 if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
710 {
711 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
712 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
713 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
714 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
715 */
716 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
717 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
718 pVMCB->ctrl.u64IntShadow = 0;
719 }
720 }
721 else
722 {
723 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
724 pVMCB->ctrl.u64IntShadow = 0;
725 }
726
727 /* Check for pending actions that force us to go back to ring 3. */
728#ifdef DEBUG
729 /* Intercept X86_XCPT_DB if stepping is enabled */
730 if (!DBGFIsStepping(pVM))
731#endif
732 {
733 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
734 {
735 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
736 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
737 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
738 rc = VINF_EM_RAW_TO_R3;
739 goto end;
740 }
741 }
742
743 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
744 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
745 {
746 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
747 rc = VINF_EM_PENDING_REQUEST;
748 goto end;
749 }
750
751 /* When external interrupts are pending, we should exit the VM when IF is set. */
752 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
753 rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
754 if (VBOX_FAILURE(rc))
755 {
756 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
757 goto end;
758 }
759
760 /* Load the guest state */
761 rc = SVMR0LoadGuestState(pVM, pCtx);
762 if (rc != VINF_SUCCESS)
763 {
764 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
765 goto end;
766 }
767 fGuestStateSynced = true;
768
769 /* All done! Let's start VM execution. */
770 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
771
772 /* Make sure we flush the TLB when required. */
773 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
774#ifdef VBOX_WITH_STATISTICS
775 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
776 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
777 else
778 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
779#endif
780
781 /* In case we execute a goto ResumeExecution later on. */
782 pVM->hwaccm.s.svm.fResumeVM = true;
783 pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
784
785 Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
786 Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
787 | SVM_CTRL2_INTERCEPT_VMMCALL
788 | SVM_CTRL2_INTERCEPT_VMLOAD
789 | SVM_CTRL2_INTERCEPT_VMSAVE
790 | SVM_CTRL2_INTERCEPT_STGI
791 | SVM_CTRL2_INTERCEPT_CLGI
792 | SVM_CTRL2_INTERCEPT_SKINIT
793 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
794 | SVM_CTRL2_INTERCEPT_WBINVD
795 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
796 ));
797 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
798 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
799 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
800 Assert(pVMCB->ctrl.u64NestedPaging == 0);
801 Assert(pVMCB->ctrl.u64LBRVirt == 0);
802
803 SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
804 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
805
806 /**
807 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
808 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
809 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
810 */
811
812 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
813
814 /* Reason for the VM exit */
815 exitCode = pVMCB->ctrl.u64ExitCode;
816
817 if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
818 {
819 HWACCMDumpRegs(pCtx);
820#ifdef DEBUG
821 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
822 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
823 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
824 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
825 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
826 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
827 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
828 Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
829 Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
830 Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
831
832 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
833 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
834 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
835 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
836
837 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
838 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
839 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
840 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
841 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
842 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
843 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
844 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
845 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
846 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
847
848 Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
849 Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
850 Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
851 Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
852 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
853 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
854 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
855 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
856 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
857 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
858 Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
859 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
860 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
861 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
862 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
863 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
864 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
865
866 Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
867 Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
868
869 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
870 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
871 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
872 Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
873 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
874 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
875 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
876 Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
877 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
878 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
879 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
880 Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
881 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
882 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
883 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
884 Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
885 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
886 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
887 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
888 Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
889
890 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
891 Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
892
893 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
894 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
895 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
896 Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
897
898 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
899 Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
900
901 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
902 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
903 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
904 Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
905
906 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
907 Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
908 Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
909 Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
910 Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
911 Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
912 Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
913
914 Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
915 Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
916 Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
917 Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
918
919 Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
920 Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
921 Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
922
923 Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
924 Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
925 Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
926 Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
927 Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
928 Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
929 Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
930 Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
931 Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
932 Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
933 Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
934 Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
935
936#endif
937 rc = VERR_SVM_UNABLE_TO_START_VM;
938 goto end;
939 }
940
941 /* Let's first sync back eip, esp, and eflags. */
942 pCtx->eip = pVMCB->guest.u64RIP;
943 pCtx->esp = pVMCB->guest.u64RSP;
944 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
945 /* eax is saved/restore across the vmrun instruction */
946 pCtx->eax = pVMCB->guest.u64RAX;
947
948 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
949 SVM_READ_SELREG(SS, ss);
950 SVM_READ_SELREG(CS, cs);
951 SVM_READ_SELREG(DS, ds);
952 SVM_READ_SELREG(ES, es);
953 SVM_READ_SELREG(FS, fs);
954 SVM_READ_SELREG(GS, gs);
955
956 /** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
957
958 /** @note NOW IT'S SAFE FOR LOGGING! */
959
960 /* Take care of instruction fusing (sti, mov ss) */
961 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
962 {
963 Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
964 EMSetInhibitInterruptsPC(pVM, pCtx->eip);
965 }
966 else
967 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
968
969 Log2(("exitCode = %x\n", exitCode));
970
971 /* Check if an injected event was interrupted prematurely. */
972 pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
973 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
974 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
975 {
976 Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
977 pVM->hwaccm.s.Event.fPending = true;
978 /* Error code present? (redundant) */
979 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
980 {
981 pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
982 }
983 else
984 pVM->hwaccm.s.Event.errCode = 0;
985 }
986 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
987
988 /* Deal with the reason of the VM-exit. */
989 switch (exitCode)
990 {
991 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
992 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
993 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
994 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
995 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
996 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
997 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
998 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
999 {
1000 /* Pending trap. */
1001 SVM_EVENT Event;
1002 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1003
1004 Log2(("Hardware/software interrupt %d\n", vector));
1005 switch (vector)
1006 {
1007#ifdef DEBUG
1008 case X86_XCPT_DB:
1009 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1010 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1011 break;
1012#endif
1013
1014 case X86_XCPT_NM:
1015 {
1016 uint32_t oldCR0;
1017
1018 Log(("#NM fault at %VGv\n", pCtx->eip));
1019
1020 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1021 oldCR0 = ASMGetCR0();
1022 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1023 rc = CPUMHandleLazyFPU(pVM);
1024 if (rc == VINF_SUCCESS)
1025 {
1026 Assert(CPUMIsGuestFPUStateActive(pVM));
1027
1028 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
1029 ASMSetCR0(oldCR0);
1030
1031 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1032
1033 /* Continue execution. */
1034 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1035 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1036
1037 goto ResumeExecution;
1038 }
1039
1040 Log(("Forward #NM fault to the guest\n"));
1041 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1042
1043 Event.au64[0] = 0;
1044 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1045 Event.n.u1Valid = 1;
1046 Event.n.u8Vector = X86_XCPT_NM;
1047
1048 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1049 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1050 goto ResumeExecution;
1051 }
1052
1053 case X86_XCPT_PF: /* Page fault */
1054 {
1055 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1056 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1057
1058 Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1059 /* Exit qualification contains the linear address of the page fault. */
1060 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1061 TRPMSetErrorCode(pVM, errCode);
1062 TRPMSetFaultAddress(pVM, uFaultAddress);
1063
1064 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1065 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1066 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1067 if (rc == VINF_SUCCESS)
1068 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1069 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1070 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1071
1072 TRPMResetTrap(pVM);
1073
1074 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1075 goto ResumeExecution;
1076 }
1077 else
1078 if (rc == VINF_EM_RAW_GUEST_TRAP)
1079 { /* A genuine pagefault.
1080 * Forward the trap to the guest by injecting the exception and resuming execution.
1081 */
1082 Log2(("Forward page fault to the guest\n"));
1083 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1084 /* The error code might have been changed. */
1085 errCode = TRPMGetErrorCode(pVM);
1086
1087 TRPMResetTrap(pVM);
1088
1089 /* Now we must update CR2. */
1090 pCtx->cr2 = uFaultAddress;
1091
1092 Event.au64[0] = 0;
1093 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1094 Event.n.u1Valid = 1;
1095 Event.n.u8Vector = X86_XCPT_PF;
1096 Event.n.u1ErrorCodeValid = 1;
1097 Event.n.u32ErrorCode = errCode;
1098
1099 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1100
1101 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1102 goto ResumeExecution;
1103 }
1104#ifdef VBOX_STRICT
1105 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1106 Log(("PGMTrap0eHandler failed with %d\n", rc));
1107#endif
1108 /* Need to go back to the recompiler to emulate the instruction. */
1109 TRPMResetTrap(pVM);
1110 break;
1111 }
1112
1113 case X86_XCPT_MF: /* Floating point exception. */
1114 {
1115 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1116 if (!(pCtx->cr0 & X86_CR0_NE))
1117 {
1118 /* old style FPU error reporting needs some extra work. */
1119 /** @todo don't fall back to the recompiler, but do it manually. */
1120 rc = VINF_EM_RAW_EMULATE_INSTR;
1121 break;
1122 }
1123 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1124
1125 Event.au64[0] = 0;
1126 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1127 Event.n.u1Valid = 1;
1128 Event.n.u8Vector = X86_XCPT_MF;
1129
1130 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1131
1132 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1133 goto ResumeExecution;
1134 }
1135
1136#ifdef VBOX_STRICT
1137 case X86_XCPT_GP: /* General protection failure exception.*/
1138 case X86_XCPT_UD: /* Unknown opcode exception. */
1139 case X86_XCPT_DE: /* Debug exception. */
1140 case X86_XCPT_SS: /* Stack segment exception. */
1141 case X86_XCPT_NP: /* Segment not present exception. */
1142 {
1143 Event.au64[0] = 0;
1144 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1145 Event.n.u1Valid = 1;
1146 Event.n.u8Vector = vector;
1147
1148 switch(vector)
1149 {
1150 case X86_XCPT_GP:
1151 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1152 Event.n.u1ErrorCodeValid = 1;
1153 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1154 break;
1155 case X86_XCPT_DE:
1156 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1157 break;
1158 case X86_XCPT_UD:
1159 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1160 break;
1161 case X86_XCPT_SS:
1162 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1163 Event.n.u1ErrorCodeValid = 1;
1164 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1165 break;
1166 case X86_XCPT_NP:
1167 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1168 Event.n.u1ErrorCodeValid = 1;
1169 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1170 break;
1171 }
1172 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1173 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1174
1175 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1176 goto ResumeExecution;
1177 }
1178#endif
1179 default:
1180 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1181 rc = VERR_EM_INTERNAL_ERROR;
1182 break;
1183
1184 } /* switch (vector) */
1185 break;
1186 }
1187
1188 case SVM_EXIT_VINTR:
1189 /* A virtual interrupt is about to be delivered, which means IF=1. */
1190 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1191 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1192 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 0;
1193 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1194 goto ResumeExecution;
1195
1196 case SVM_EXIT_FERR_FREEZE:
1197 case SVM_EXIT_INTR:
1198 case SVM_EXIT_NMI:
1199 case SVM_EXIT_SMI:
1200 case SVM_EXIT_INIT:
1201 /* External interrupt; leave to allow it to be dispatched again. */
1202 rc = VINF_EM_RAW_INTERRUPT;
1203 break;
1204
1205 case SVM_EXIT_WBINVD:
1206 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1207 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1208 /* Skip instruction and continue directly. */
1209 pCtx->eip += 2; /** @note hardcoded opcode size! */
1210 /* Continue execution.*/
1211 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1212 goto ResumeExecution;
1213
1214 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1215 {
1216 Log2(("SVM: Cpuid %x\n", pCtx->eax));
1217 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1218 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1219 if (rc == VINF_SUCCESS)
1220 {
1221 /* Update EIP and continue execution. */
1222 pCtx->eip += 2; /** @note hardcoded opcode size! */
1223 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1224 goto ResumeExecution;
1225 }
1226 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1227 rc = VINF_EM_RAW_EMULATE_INSTR;
1228 break;
1229 }
1230
1231 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1232 {
1233 Log2(("SVM: Rdtsc\n"));
1234 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1235 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1236 if (rc == VINF_SUCCESS)
1237 {
1238 /* Update EIP and continue execution. */
1239 pCtx->eip += 2; /** @note hardcoded opcode size! */
1240 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1241 goto ResumeExecution;
1242 }
1243 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1244 rc = VINF_EM_RAW_EMULATE_INSTR;
1245 break;
1246 }
1247
1248 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1249 {
1250 Log2(("SVM: invlpg\n"));
1251 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1252
1253 /* Truly a pita. Why can't SVM give the same information as VMX? */
1254 rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1255 if (rc == VINF_SUCCESS)
1256 {
1257 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1258 goto ResumeExecution; /* eip already updated */
1259 }
1260 break;
1261 }
1262
1263 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1264 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1265 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1266 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1267 {
1268 uint32_t cbSize;
1269
1270 Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1271 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1272 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1273
1274 switch (exitCode - SVM_EXIT_WRITE_CR0)
1275 {
1276 case 0:
1277 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1278 break;
1279 case 2:
1280 break;
1281 case 3:
1282 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1283 break;
1284 case 4:
1285 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1286 break;
1287 default:
1288 AssertFailed();
1289 }
1290 /* Check if a sync operation is pending. */
1291 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1292 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1293 {
1294 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1295 AssertRC(rc);
1296
1297 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1298
1299 /** @note Force a TLB flush. SVM requires us to do it manually. */
1300 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1301 }
1302 if (rc == VINF_SUCCESS)
1303 {
1304 /* EIP has been updated already. */
1305
1306 /* Only resume if successful. */
1307 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1308 goto ResumeExecution;
1309 }
1310 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1311 break;
1312 }
1313
1314 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1315 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1316 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1317 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1318 {
1319 uint32_t cbSize;
1320
1321 Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1322 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1323 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1324 if (rc == VINF_SUCCESS)
1325 {
1326 /* EIP has been updated already. */
1327
1328 /* Only resume if successful. */
1329 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1330 goto ResumeExecution;
1331 }
1332 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1333 break;
1334 }
1335
1336 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1337 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1338 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1339 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1340 {
1341 uint32_t cbSize;
1342
1343 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1344 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1345 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1346 if (rc == VINF_SUCCESS)
1347 {
1348 /* EIP has been updated already. */
1349
1350 /* Only resume if successful. */
1351 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1352 goto ResumeExecution;
1353 }
1354 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1355 break;
1356 }
1357
1358 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1359 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1360 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1361 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1362 {
1363 uint32_t cbSize;
1364
1365 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1366 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1367 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1368 if (rc == VINF_SUCCESS)
1369 {
1370 /* EIP has been updated already. */
1371
1372 /* Only resume if successful. */
1373 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1374 goto ResumeExecution;
1375 }
1376 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1377 break;
1378 }
1379
1380 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1381 case SVM_EXIT_IOIO: /* I/O instruction. */
1382 {
1383 SVM_IOIO_EXIT IoExitInfo;
1384 uint32_t uIOSize, uAndVal;
1385
1386 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1387
1388 /** @todo could use a lookup table here */
1389 if (IoExitInfo.n.u1OP8)
1390 {
1391 uIOSize = 1;
1392 uAndVal = 0xff;
1393 }
1394 else
1395 if (IoExitInfo.n.u1OP16)
1396 {
1397 uIOSize = 2;
1398 uAndVal = 0xffff;
1399 }
1400 else
1401 if (IoExitInfo.n.u1OP32)
1402 {
1403 uIOSize = 4;
1404 uAndVal = 0xffffffff;
1405 }
1406 else
1407 {
1408 AssertFailed(); /* should be fatal. */
1409 rc = VINF_EM_RAW_EMULATE_INSTR;
1410 break;
1411 }
1412
1413 if (IoExitInfo.n.u1STR)
1414 {
1415 /* ins/outs */
1416 uint32_t prefix = 0;
1417 if (IoExitInfo.n.u1REP)
1418 prefix |= PREFIX_REP;
1419
1420 if (IoExitInfo.n.u1Type == 0)
1421 {
1422 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1423 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1424 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1425 }
1426 else
1427 {
1428 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1429 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1430 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1431 }
1432 }
1433 else
1434 {
1435 /* normal in/out */
1436 Assert(!IoExitInfo.n.u1REP);
1437
1438 if (IoExitInfo.n.u1Type == 0)
1439 {
1440 Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1441 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1442 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1443 }
1444 else
1445 {
1446 uint32_t u32Val = 0;
1447
1448 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1449 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1450 if (IOM_SUCCESS(rc))
1451 {
1452 /* Write back to the EAX register. */
1453 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1454 Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1455 }
1456 }
1457 }
1458 /*
1459 * Handled the I/O return codes.
1460 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1461 */
1462 if (IOM_SUCCESS(rc))
1463 {
1464 /* Update EIP and continue execution. */
1465 pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1466 if (RT_LIKELY(rc == VINF_SUCCESS))
1467 {
1468 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1469 goto ResumeExecution;
1470 }
1471 Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1472 break;
1473 }
1474
1475#ifdef VBOX_STRICT
1476 if (rc == VINF_IOM_HC_IOPORT_READ)
1477 Assert(IoExitInfo.n.u1Type != 0);
1478 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1479 Assert(IoExitInfo.n.u1Type == 0);
1480 else
1481 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1482#endif
1483 Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1484 break;
1485 }
1486
1487 case SVM_EXIT_HLT:
1488 /** Check if external interrupts are pending; if so, don't switch back. */
1489 if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
1490 {
1491 pCtx->eip++; /* skip hlt */
1492 goto ResumeExecution;
1493 }
1494
1495 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1496 break;
1497
1498 case SVM_EXIT_RSM:
1499 case SVM_EXIT_INVLPGA:
1500 case SVM_EXIT_VMRUN:
1501 case SVM_EXIT_VMMCALL:
1502 case SVM_EXIT_VMLOAD:
1503 case SVM_EXIT_VMSAVE:
1504 case SVM_EXIT_STGI:
1505 case SVM_EXIT_CLGI:
1506 case SVM_EXIT_SKINIT:
1507 case SVM_EXIT_RDTSCP:
1508 {
1509 /* Unsupported instructions. */
1510 SVM_EVENT Event;
1511
1512 Event.au64[0] = 0;
1513 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1514 Event.n.u1Valid = 1;
1515 Event.n.u8Vector = X86_XCPT_UD;
1516
1517 Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1518 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1519
1520 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1521 goto ResumeExecution;
1522 }
1523
1524 /* Emulate in ring 3. */
1525 case SVM_EXIT_MONITOR:
1526 case SVM_EXIT_RDPMC:
1527 case SVM_EXIT_PAUSE:
1528 case SVM_EXIT_MWAIT_UNCOND:
1529 case SVM_EXIT_MWAIT_ARMED:
1530 case SVM_EXIT_MSR:
1531 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1532 break;
1533
1534 case SVM_EXIT_NPF:
1535 AssertFailed(); /* unexpected */
1536 break;
1537
1538 case SVM_EXIT_SHUTDOWN:
1539 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1540 break;
1541
1542 case SVM_EXIT_IDTR_READ:
1543 case SVM_EXIT_GDTR_READ:
1544 case SVM_EXIT_LDTR_READ:
1545 case SVM_EXIT_TR_READ:
1546 case SVM_EXIT_IDTR_WRITE:
1547 case SVM_EXIT_GDTR_WRITE:
1548 case SVM_EXIT_LDTR_WRITE:
1549 case SVM_EXIT_TR_WRITE:
1550 case SVM_EXIT_CR0_SEL_WRITE:
1551 default:
1552 /* Unexpected exit codes. */
1553 rc = VERR_EM_INTERNAL_ERROR;
1554 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1555 break;
1556 }
1557
1558end:
1559 if (fGuestStateSynced)
1560 {
1561 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1562 SVM_READ_SELREG(LDTR, ldtr);
1563 SVM_READ_SELREG(TR, tr);
1564
1565 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1566 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1567
1568 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1569 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1570
1571 /*
1572 * System MSRs
1573 */
1574 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1575 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1576 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1577 }
1578
1579 /* Signal changes for the recompiler. */
1580 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
1581
1582 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1583 if (exitCode == SVM_EXIT_INTR)
1584 {
1585 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1586 /* On the next entry we'll only sync the host context. */
1587 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
1588 }
1589 else
1590 {
1591 /* On the next entry we'll sync everything. */
1592 /** @todo we can do better than this */
1593 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
1594 }
1595
1596 /* translate into a less severe return code */
1597 if (rc == VERR_EM_INTERPRETER)
1598 rc = VINF_EM_RAW_EMULATE_INSTR;
1599
1600 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1601 return rc;
1602}
1603
1604/**
1605 * Enters the AMD-V session
1606 *
1607 * @returns VBox status code.
1608 * @param pVM The VM to operate on.
1609 */
1610HWACCMR0DECL(int) SVMR0Enter(PVM pVM)
1611{
1612 Assert(pVM->hwaccm.s.svm.fSupported);
1613
1614 /* Force a TLB flush on VM entry. */
1615 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1616
1617 pVM->hwaccm.s.svm.fResumeVM = false;
1618
1619 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1620 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
1621
1622 return VINF_SUCCESS;
1623}
1624
1625
1626/**
1627 * Leaves the AMD-V session
1628 *
1629 * @returns VBox status code.
1630 * @param pVM The VM to operate on.
1631 */
1632HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1633{
1634 Assert(pVM->hwaccm.s.svm.fSupported);
1635 return VINF_SUCCESS;
1636}
1637
1638
1639static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1640{
1641 OP_PARAMVAL param1;
1642 RTGCPTR addr;
1643
1644 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1645 if(VBOX_FAILURE(rc))
1646 return VERR_EM_INTERPRETER;
1647
1648 switch(param1.type)
1649 {
1650 case PARMTYPE_IMMEDIATE:
1651 case PARMTYPE_ADDRESS:
1652 if(!(param1.flags & PARAM_VAL32))
1653 return VERR_EM_INTERPRETER;
1654 addr = (RTGCPTR)param1.val.val32;
1655 break;
1656
1657 default:
1658 return VERR_EM_INTERPRETER;
1659 }
1660
1661 /** @todo is addr always a flat linear address or ds based
1662 * (in absence of segment override prefixes)????
1663 */
1664 rc = PGMInvalidatePage(pVM, addr);
1665 if (VBOX_SUCCESS(rc))
1666 {
1667 /* Manually invalidate the page for the VM's TLB. */
1668 Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1669 SVMInvlpgA(addr, uASID);
1670 return VINF_SUCCESS;
1671 }
1672 Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1673 return rc;
1674}
1675
1676/**
1677 * Interprets INVLPG
1678 *
1679 * @returns VBox status code.
1680 * @retval VINF_* Scheduling instructions.
1681 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1682 * @retval VERR_* Fatal errors.
1683 *
1684 * @param pVM The VM handle.
1685 * @param pRegFrame The register frame.
1686 * @param ASID Tagged TLB id for the guest
1687 *
1688 * Updates the EIP if an instruction was executed successfully.
1689 */
1690static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1691{
1692 /*
1693 * Only allow 32-bit code.
1694 */
1695 if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1696 {
1697 RTGCPTR pbCode;
1698 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1699 if (VBOX_SUCCESS(rc))
1700 {
1701 uint32_t cbOp;
1702 DISCPUSTATE Cpu;
1703
1704 Cpu.mode = CPUMODE_32BIT;
1705 rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1706 Assert(VBOX_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);
1707 if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1708 {
1709 Assert(cbOp == Cpu.opsize);
1710 rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1711 if (VBOX_SUCCESS(rc))
1712 {
1713 pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1714 }
1715 return rc;
1716 }
1717 }
1718 }
1719 return VERR_EM_INTERPRETER;
1720}
1721
1722
1723/**
1724 * Invalidates a guest page
1725 *
1726 * @returns VBox status code.
1727 * @param pVM The VM to operate on.
1728 * @param GCVirt Page to invalidate
1729 */
1730HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
1731{
1732 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | pVM->hwaccm.s.svm.fForceTLBFlush;
1733
1734 /* Skip it if a TLB flush is already pending. */
1735 if (!fFlushPending)
1736 {
1737 SVM_VMCB *pVMCB;
1738
1739 Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
1740 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1741 Assert(pVM->hwaccm.s.svm.fSupported);
1742
1743 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
1744 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
1745
1746 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
1747 SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
1748 }
1749 return VINF_SUCCESS;
1750}
1751
1752/**
1753 * Flushes the guest TLB
1754 *
1755 * @returns VBox status code.
1756 * @param pVM The VM to operate on.
1757 */
1758HWACCMR0DECL(int) SVMR0FlushTLB(PVM pVM)
1759{
1760 Log2(("SVMR0FlushTLB\n"));
1761 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1762 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBManual);
1763 return VINF_SUCCESS;
1764}
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