VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 8881

Last change on this file since 8881 was 8881, checked in by vboxsync, 17 years ago

Wrong assertion
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1/* $Id: HWSVMR0.cpp 8881 2008-05-16 11:17:35Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include "HWSVMR0.h"
47
48static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50/**
51 * Sets up and activates AMD-V on the current CPU
52 *
53 * @returns VBox status code.
54 * @param pCpu CPU info struct
55 * @param pVM The VM to operate on.
56 * @param pvPageCpu Pointer to the global cpu page
57 * @param pPageCpuPhys Physical address of the global cpu page
58 */
59HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60{
61 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62 AssertReturn(pVM, VERR_INVALID_PARAMETER);
63 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67#ifdef LOG_ENABLED
68 SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69#endif
70
71 /* Turn on AMD-V in the EFER MSR. */
72 uint64_t val = ASMRdMsr(MSR_K6_EFER);
73 if (!(val & MSR_K6_EFER_SVME))
74 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
75
76 /* Write the physical page address where the CPU will store the host state while executing the VM. */
77 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79 pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80 return VINF_SUCCESS;
81}
82
83/**
84 * Deactivates AMD-V on the current CPU
85 *
86 * @returns VBox status code.
87 * @param pCpu CPU info struct
88 * @param pvPageCpu Pointer to the global cpu page
89 * @param pPageCpuPhys Physical address of the global cpu page
90 */
91HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
92{
93 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
94 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
95
96#ifdef LOG_ENABLED
97 SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
98#endif
99
100 /* Turn off AMD-V in the EFER MSR. */
101 uint64_t val = ASMRdMsr(MSR_K6_EFER);
102 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
103
104 /* Invalidate host state physical address. */
105 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
106 pCpu->uCurrentASID = 0;
107
108 return VINF_SUCCESS;
109}
110
111/**
112 * Does Ring-0 per VM AMD-V init.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
118{
119 int rc;
120
121 /* Allocate one page for the VM control block (VMCB). */
122 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
123 if (RT_FAILURE(rc))
124 return rc;
125
126 pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
127 pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
128 ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
129
130 /* Allocate one page for the host context */
131 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
132 if (RT_FAILURE(rc))
133 return rc;
134
135 pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
136 pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
137 ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
138
139 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
140 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
141 if (RT_FAILURE(rc))
142 return rc;
143
144 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
145 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
146 /* Set all bits to intercept all IO accesses. */
147 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
148
149 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
150 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
151 if (RT_FAILURE(rc))
152 return rc;
153
154 pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
155 pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
156 /* Set all bits to intercept all MSR accesses. */
157 ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
158
159 /* Erratum 170 which requires a forced TLB flush for each world switch:
160 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
161 *
162 * All BH-G1/2 and DH-G1/2 models include a fix:
163 * Athlon X2: 0x6b 1/2
164 * 0x68 1/2
165 * Athlon 64: 0x7f 1
166 * 0x6f 2
167 * Sempron: 0x7f 1/2
168 * 0x6f 2
169 * 0x6c 2
170 * 0x7c 2
171 * Turion 64: 0x68 2
172 *
173 */
174 uint32_t u32Dummy;
175 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
176 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
177 u32BaseFamily= (u32Version >> 8) & 0xf;
178 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
179 u32Model = ((u32Version >> 4) & 0xf);
180 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
181 u32Stepping = u32Version & 0xf;
182 if ( u32Family == 0xf
183 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
184 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
185 {
186 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
187 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
188 }
189
190 /* Invalidate the last cpu we were running on. */
191 pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
192 return VINF_SUCCESS;
193}
194
195/**
196 * Does Ring-0 per VM AMD-V termination.
197 *
198 * @returns VBox status code.
199 * @param pVM The VM to operate on.
200 */
201HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
202{
203 if (pVM->hwaccm.s.svm.pMemObjVMCB)
204 {
205 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
206 pVM->hwaccm.s.svm.pVMCB = 0;
207 pVM->hwaccm.s.svm.pVMCBPhys = 0;
208 pVM->hwaccm.s.svm.pMemObjVMCB = 0;
209 }
210 if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
211 {
212 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
213 pVM->hwaccm.s.svm.pVMCBHost = 0;
214 pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
215 pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
216 }
217 if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
218 {
219 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
220 pVM->hwaccm.s.svm.pIOBitmap = 0;
221 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
222 pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
223 }
224 if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
225 {
226 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
227 pVM->hwaccm.s.svm.pMSRBitmap = 0;
228 pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
229 pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
230 }
231 return VINF_SUCCESS;
232}
233
234/**
235 * Sets up AMD-V for the specified VM
236 *
237 * @returns VBox status code.
238 * @param pVM The VM to operate on.
239 */
240HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
241{
242 int rc = VINF_SUCCESS;
243 SVM_VMCB *pVMCB;
244
245 AssertReturn(pVM, VERR_INVALID_PARAMETER);
246
247 Assert(pVM->hwaccm.s.svm.fSupported);
248
249 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
250 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
251
252 /* Program the control fields. Most of them never have to be changed again. */
253 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
254 /** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
255 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
256
257 /*
258 * CR0/3/4 writes must be intercepted for obvious reasons.
259 */
260 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
261
262 /* Intercept all DRx reads and writes. */
263 pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
264 pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
265
266 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
267 * All breakpoints are automatically cleared when the VM exits.
268 */
269
270 /** @todo nested paging */
271 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
272
273 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
274 | SVM_CTRL1_INTERCEPT_VINTR
275 | SVM_CTRL1_INTERCEPT_NMI
276 | SVM_CTRL1_INTERCEPT_SMI
277 | SVM_CTRL1_INTERCEPT_INIT
278 | SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
279 | SVM_CTRL1_INTERCEPT_RDPMC
280 | SVM_CTRL1_INTERCEPT_CPUID
281 | SVM_CTRL1_INTERCEPT_RSM
282 | SVM_CTRL1_INTERCEPT_HLT
283 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
284 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
285 | SVM_CTRL1_INTERCEPT_INVLPG
286 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
287 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
288 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
289 ;
290 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
291 | SVM_CTRL2_INTERCEPT_VMMCALL
292 | SVM_CTRL2_INTERCEPT_VMLOAD
293 | SVM_CTRL2_INTERCEPT_VMSAVE
294 | SVM_CTRL2_INTERCEPT_STGI
295 | SVM_CTRL2_INTERCEPT_CLGI
296 | SVM_CTRL2_INTERCEPT_SKINIT
297 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
298 | SVM_CTRL2_INTERCEPT_WBINVD
299 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
300 ;
301 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
302 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
303 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
304
305 /* Virtualize masking of INTR interrupts. */
306 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
307
308 /* Set IO and MSR bitmap addresses. */
309 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
310 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
311
312 /* Enable nested paging. */
313 /** @todo how to detect support for this?? */
314 pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
315
316 /* No LBR virtualization. */
317 pVMCB->ctrl.u64LBRVirt = 0;
318
319 /** The ASID must start at 1; the host uses 0. */
320 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
321
322 return rc;
323}
324
325
326/**
327 * Injects an event (trap or external interrupt)
328 *
329 * @param pVM The VM to operate on.
330 * @param pVMCB SVM control block
331 * @param pCtx CPU Context
332 * @param pIntInfo SVM interrupt info
333 */
334inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
335{
336#ifdef VBOX_STRICT
337 if (pEvent->n.u8Vector == 0xE)
338 Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
339 else
340 if (pEvent->n.u8Vector < 0x20)
341 Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
342 else
343 {
344 Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
345 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
346 Assert(pCtx->eflags.u32 & X86_EFL_IF);
347 }
348#endif
349
350 /* Set event injection state. */
351 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
352}
353
354
355/**
356 * Checks for pending guest interrupts and injects them
357 *
358 * @returns VBox status code.
359 * @param pVM The VM to operate on.
360 * @param pVMCB SVM control block
361 * @param pCtx CPU Context
362 */
363static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
364{
365 int rc;
366
367 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
368 if (pVM->hwaccm.s.Event.fPending)
369 {
370 SVM_EVENT Event;
371
372 Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
373 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
374 Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
375 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
376
377 pVM->hwaccm.s.Event.fPending = false;
378 return VINF_SUCCESS;
379 }
380
381 /* When external interrupts are pending, we should exit the VM when IF is set. */
382 if ( !TRPMHasTrap(pVM)
383 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
384 {
385 if (!(pCtx->eflags.u32 & X86_EFL_IF))
386 {
387 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
388 {
389 Log(("Enable irq window exit!\n"));
390 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
391 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
392 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
393 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; /* ignore the priority in the TPR; just deliver it */
394 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
395 }
396 }
397 else
398 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
399 {
400 uint8_t u8Interrupt;
401
402 rc = PDMGetInterrupt(pVM, &u8Interrupt);
403 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
404 if (VBOX_SUCCESS(rc))
405 {
406 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
407 AssertRC(rc);
408 }
409 else
410 {
411 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
412 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
413 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
414 /* Just continue */
415 }
416 }
417 else
418 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
419 }
420
421#ifdef VBOX_STRICT
422 if (TRPMHasTrap(pVM))
423 {
424 uint8_t u8Vector;
425 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
426 AssertRC(rc);
427 }
428#endif
429
430 if ( pCtx->eflags.u32 & X86_EFL_IF
431 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
432 && TRPMHasTrap(pVM)
433 )
434 {
435 uint8_t u8Vector;
436 int rc;
437 TRPMEVENT enmType;
438 SVM_EVENT Event;
439 uint32_t u32ErrorCode;
440
441 Event.au64[0] = 0;
442
443 /* If a new event is pending, then dispatch it now. */
444 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
445 AssertRC(rc);
446 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
447 Assert(enmType != TRPM_SOFTWARE_INT);
448
449 /* Clear the pending trap. */
450 rc = TRPMResetTrap(pVM);
451 AssertRC(rc);
452
453 Event.n.u8Vector = u8Vector;
454 Event.n.u1Valid = 1;
455 Event.n.u32ErrorCode = u32ErrorCode;
456
457 if (enmType == TRPM_TRAP)
458 {
459 switch (u8Vector) {
460 case 8:
461 case 10:
462 case 11:
463 case 12:
464 case 13:
465 case 14:
466 case 17:
467 /* Valid error codes. */
468 Event.n.u1ErrorCodeValid = 1;
469 break;
470 default:
471 break;
472 }
473 if (u8Vector == X86_XCPT_NMI)
474 Event.n.u3Type = SVM_EVENT_NMI;
475 else
476 Event.n.u3Type = SVM_EVENT_EXCEPTION;
477 }
478 else
479 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
480
481 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
482 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
483 } /* if (interrupts can be dispatched) */
484
485 return VINF_SUCCESS;
486}
487
488
489/**
490 * Loads the guest state
491 *
492 * @returns VBox status code.
493 * @param pVM The VM to operate on.
494 * @param pCtx Guest context
495 */
496HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
497{
498 RTGCUINTPTR val;
499 SVM_VMCB *pVMCB;
500
501 if (pVM == NULL)
502 return VERR_INVALID_PARAMETER;
503
504 /* Setup AMD SVM. */
505 Assert(pVM->hwaccm.s.svm.fSupported);
506
507 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
508 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
509
510 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
511 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
512 {
513 SVM_WRITE_SELREG(CS, cs);
514 SVM_WRITE_SELREG(SS, ss);
515 SVM_WRITE_SELREG(DS, ds);
516 SVM_WRITE_SELREG(ES, es);
517 SVM_WRITE_SELREG(FS, fs);
518 SVM_WRITE_SELREG(GS, gs);
519 }
520
521 /* Guest CPU context: LDTR. */
522 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
523 {
524 SVM_WRITE_SELREG(LDTR, ldtr);
525 }
526
527 /* Guest CPU context: TR. */
528 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
529 {
530 SVM_WRITE_SELREG(TR, tr);
531 }
532
533 /* Guest CPU context: GDTR. */
534 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
535 {
536 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
537 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
538 }
539
540 /* Guest CPU context: IDTR. */
541 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
542 {
543 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
544 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
545 }
546
547 /*
548 * Sysenter MSRs
549 */
550 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
551 {
552 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
553 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
554 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
555 }
556
557 /* Control registers */
558 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
559 {
560 val = pCtx->cr0;
561 if (CPUMIsGuestFPUStateActive(pVM) == false)
562 {
563 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
564 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
565 }
566 else
567 {
568 Assert(pVM->hwaccm.s.svm.fResumeVM == true);
569 /** @todo check if we support the old style mess correctly. */
570 if (!(val & X86_CR0_NE))
571 {
572 Log(("Forcing X86_CR0_NE!!!\n"));
573
574 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
575 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
576 {
577 pVMCB->ctrl.u32InterceptException |= RT_BIT(16);
578 pVM->hwaccm.s.fFPUOldStyleOverride = true;
579 }
580 }
581 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
582 }
583 if (!(val & X86_CR0_CD))
584 val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
585
586 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
587 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
588 pVMCB->guest.u64CR0 = val;
589 }
590 /* CR2 as well */
591 pVMCB->guest.u64CR2 = pCtx->cr2;
592
593 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
594 {
595 /* Save our shadow CR3 register. */
596 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
597 }
598
599 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
600 {
601 val = pCtx->cr4;
602 switch(pVM->hwaccm.s.enmShadowMode)
603 {
604 case PGMMODE_REAL:
605 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
606 AssertFailed();
607 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
608
609 case PGMMODE_32_BIT: /* 32-bit paging. */
610 break;
611
612 case PGMMODE_PAE: /* PAE paging. */
613 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
614 /** @todo use normal 32 bits paging */
615 val |= X86_CR4_PAE;
616 break;
617
618 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
619 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
620 AssertFailed();
621 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
622
623 default: /* shut up gcc */
624 AssertFailed();
625 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
626 }
627 pVMCB->guest.u64CR4 = val;
628 }
629
630 /* Debug registers. */
631 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
632 {
633 /** @todo DR0-6 */
634 val = pCtx->dr7;
635 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
636 val |= 0x400; /* must be one */
637#ifdef VBOX_STRICT
638 val = 0x400;
639#endif
640 pVMCB->guest.u64DR7 = val;
641
642 pVMCB->guest.u64DR6 = pCtx->dr6;
643 }
644
645 /* EIP, ESP and EFLAGS */
646 pVMCB->guest.u64RIP = pCtx->eip;
647 pVMCB->guest.u64RSP = pCtx->esp;
648 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
649
650 /* Set CPL */
651 pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
652
653 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
654 pVMCB->guest.u64RAX = pCtx->eax;
655
656 /* vmrun will fail otherwise. */
657 pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
658
659 /** TSC offset. */
660 if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
661 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
662 else
663 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
664
665 /** @todo 64 bits stuff (?):
666 * - STAR
667 * - LSTAR
668 * - CSTAR
669 * - SFMASK
670 * - KernelGSBase
671 */
672
673#ifdef DEBUG
674 /* Intercept X86_XCPT_DB if stepping is enabled */
675 if (DBGFIsStepping(pVM))
676 pVMCB->ctrl.u32InterceptException |= RT_BIT(1);
677 else
678 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
679#endif
680
681 /* Done. */
682 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
683
684 return VINF_SUCCESS;
685}
686
687
688/**
689 * Runs guest code in an SVM VM.
690 *
691 * @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
692 *
693 * @returns VBox status code.
694 * @param pVM The VM to operate on.
695 * @param pCtx Guest context
696 * @param pCpu CPU info struct
697 */
698HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
699{
700 int rc = VINF_SUCCESS;
701 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
702 SVM_VMCB *pVMCB;
703 bool fGuestStateSynced = false;
704 unsigned cResume = 0;
705
706 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
707
708 AssertReturn(pCpu->fSVMConfigured, VERR_EM_INTERNAL_ERROR);
709
710 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
711 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
712
713 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
714 */
715ResumeExecution:
716 /* Safety precaution; looping for too long here can have a very bad effect on the host */
717 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
718 {
719 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
720 rc = VINF_EM_RAW_INTERRUPT;
721 goto end;
722 }
723
724 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
725 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
726 {
727 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
728 if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
729 {
730 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
731 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
732 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
733 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
734 */
735 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
736 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
737 pVMCB->ctrl.u64IntShadow = 0;
738 }
739 }
740 else
741 {
742 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
743 pVMCB->ctrl.u64IntShadow = 0;
744 }
745
746 /* Check for pending actions that force us to go back to ring 3. */
747#ifdef DEBUG
748 /* Intercept X86_XCPT_DB if stepping is enabled */
749 if (!DBGFIsStepping(pVM))
750#endif
751 {
752 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
753 {
754 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
755 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
756 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
757 rc = VINF_EM_RAW_TO_R3;
758 goto end;
759 }
760 }
761
762 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
763 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
764 {
765 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
766 rc = VINF_EM_PENDING_REQUEST;
767 goto end;
768 }
769
770 /* When external interrupts are pending, we should exit the VM when IF is set. */
771 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
772 rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
773 if (VBOX_FAILURE(rc))
774 {
775 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
776 goto end;
777 }
778
779 /* Load the guest state */
780 rc = SVMR0LoadGuestState(pVM, pCtx);
781 if (rc != VINF_SUCCESS)
782 {
783 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
784 goto end;
785 }
786 fGuestStateSynced = true;
787
788 /* All done! Let's start VM execution. */
789 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
790
791 /* Make sure we flush the TLB when required. */
792 if ( pVM->hwaccm.s.svm.fForceTLBFlush
793 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
794 {
795 if (++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID)
796 {
797 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
798 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
799 }
800 else
801 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
802 }
803 else
804 {
805 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
806 }
807
808 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
809 pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
810
811#ifdef VBOX_WITH_STATISTICS
812 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
813 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
814 else
815 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
816#endif
817
818 /* In case we execute a goto ResumeExecution later on. */
819 pVM->hwaccm.s.svm.fResumeVM = true;
820 pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
821
822 Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
823 Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
824 | SVM_CTRL2_INTERCEPT_VMMCALL
825 | SVM_CTRL2_INTERCEPT_VMLOAD
826 | SVM_CTRL2_INTERCEPT_VMSAVE
827 | SVM_CTRL2_INTERCEPT_STGI
828 | SVM_CTRL2_INTERCEPT_CLGI
829 | SVM_CTRL2_INTERCEPT_SKINIT
830 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
831 | SVM_CTRL2_INTERCEPT_WBINVD
832 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
833 ));
834 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
835 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
836 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
837 Assert(pVMCB->ctrl.u64NestedPaging == 0);
838 Assert(pVMCB->ctrl.u64LBRVirt == 0);
839
840 SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
841 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
842
843 /**
844 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
845 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
846 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
847 */
848
849 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
850
851 /* Reason for the VM exit */
852 exitCode = pVMCB->ctrl.u64ExitCode;
853
854 if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
855 {
856 HWACCMDumpRegs(pCtx);
857#ifdef DEBUG
858 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
859 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
860 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
861 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
862 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
863 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
864 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
865 Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
866 Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
867 Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
868
869 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
870 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
871 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
872 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
873
874 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
875 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
876 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
877 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
878 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
879 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
880 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
881 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
882 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
883 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
884
885 Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
886 Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
887 Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
888 Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
889 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
890 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
891 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
892 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
893 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
894 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
895 Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
896 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
897 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
898 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
899 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
900 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
901 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
902
903 Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
904 Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
905
906 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
907 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
908 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
909 Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
910 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
911 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
912 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
913 Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
914 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
915 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
916 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
917 Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
918 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
919 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
920 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
921 Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
922 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
923 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
924 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
925 Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
926
927 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
928 Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
929
930 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
931 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
932 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
933 Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
934
935 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
936 Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
937
938 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
939 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
940 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
941 Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
942
943 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
944 Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
945 Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
946 Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
947 Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
948 Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
949 Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
950
951 Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
952 Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
953 Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
954 Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
955
956 Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
957 Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
958 Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
959
960 Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
961 Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
962 Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
963 Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
964 Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
965 Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
966 Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
967 Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
968 Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
969 Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
970 Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
971 Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
972
973#endif
974 rc = VERR_SVM_UNABLE_TO_START_VM;
975 goto end;
976 }
977
978 /* Let's first sync back eip, esp, and eflags. */
979 pCtx->eip = pVMCB->guest.u64RIP;
980 pCtx->esp = pVMCB->guest.u64RSP;
981 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
982 /* eax is saved/restore across the vmrun instruction */
983 pCtx->eax = pVMCB->guest.u64RAX;
984
985 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
986 SVM_READ_SELREG(SS, ss);
987 SVM_READ_SELREG(CS, cs);
988 SVM_READ_SELREG(DS, ds);
989 SVM_READ_SELREG(ES, es);
990 SVM_READ_SELREG(FS, fs);
991 SVM_READ_SELREG(GS, gs);
992
993 /** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
994
995 /** @note NOW IT'S SAFE FOR LOGGING! */
996
997 /* Take care of instruction fusing (sti, mov ss) */
998 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
999 {
1000 Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
1001 EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1002 }
1003 else
1004 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1005
1006 Log2(("exitCode = %x\n", exitCode));
1007
1008 /* Check if an injected event was interrupted prematurely. */
1009 pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1010 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1011 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1012 {
1013 Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
1014 pVM->hwaccm.s.Event.fPending = true;
1015 /* Error code present? (redundant) */
1016 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1017 {
1018 pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1019 }
1020 else
1021 pVM->hwaccm.s.Event.errCode = 0;
1022 }
1023 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1024
1025 /* Deal with the reason of the VM-exit. */
1026 switch (exitCode)
1027 {
1028 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1029 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1030 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1031 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1032 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1033 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1034 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1035 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1036 {
1037 /* Pending trap. */
1038 SVM_EVENT Event;
1039 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1040
1041 Log2(("Hardware/software interrupt %d\n", vector));
1042 switch (vector)
1043 {
1044#ifdef DEBUG
1045 case X86_XCPT_DB:
1046 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1047 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1048 break;
1049#endif
1050
1051 case X86_XCPT_NM:
1052 {
1053 uint32_t oldCR0;
1054
1055 Log(("#NM fault at %VGv\n", pCtx->eip));
1056
1057 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1058 oldCR0 = ASMGetCR0();
1059 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1060 rc = CPUMHandleLazyFPU(pVM);
1061 if (rc == VINF_SUCCESS)
1062 {
1063 Assert(CPUMIsGuestFPUStateActive(pVM));
1064
1065 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
1066 ASMSetCR0(oldCR0);
1067
1068 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1069
1070 /* Continue execution. */
1071 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1072 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1073
1074 goto ResumeExecution;
1075 }
1076
1077 Log(("Forward #NM fault to the guest\n"));
1078 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1079
1080 Event.au64[0] = 0;
1081 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1082 Event.n.u1Valid = 1;
1083 Event.n.u8Vector = X86_XCPT_NM;
1084
1085 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1086 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1087 goto ResumeExecution;
1088 }
1089
1090 case X86_XCPT_PF: /* Page fault */
1091 {
1092 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1093 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1094
1095 Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1096 /* Exit qualification contains the linear address of the page fault. */
1097 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1098 TRPMSetErrorCode(pVM, errCode);
1099 TRPMSetFaultAddress(pVM, uFaultAddress);
1100
1101 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1102 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1103 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1104 if (rc == VINF_SUCCESS)
1105 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1106 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1107 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1108
1109 TRPMResetTrap(pVM);
1110
1111 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1112 goto ResumeExecution;
1113 }
1114 else
1115 if (rc == VINF_EM_RAW_GUEST_TRAP)
1116 { /* A genuine pagefault.
1117 * Forward the trap to the guest by injecting the exception and resuming execution.
1118 */
1119 Log2(("Forward page fault to the guest\n"));
1120 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1121 /* The error code might have been changed. */
1122 errCode = TRPMGetErrorCode(pVM);
1123
1124 TRPMResetTrap(pVM);
1125
1126 /* Now we must update CR2. */
1127 pCtx->cr2 = uFaultAddress;
1128
1129 Event.au64[0] = 0;
1130 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1131 Event.n.u1Valid = 1;
1132 Event.n.u8Vector = X86_XCPT_PF;
1133 Event.n.u1ErrorCodeValid = 1;
1134 Event.n.u32ErrorCode = errCode;
1135
1136 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1137
1138 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1139 goto ResumeExecution;
1140 }
1141#ifdef VBOX_STRICT
1142 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1143 Log(("PGMTrap0eHandler failed with %d\n", rc));
1144#endif
1145 /* Need to go back to the recompiler to emulate the instruction. */
1146 TRPMResetTrap(pVM);
1147 break;
1148 }
1149
1150 case X86_XCPT_MF: /* Floating point exception. */
1151 {
1152 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1153 if (!(pCtx->cr0 & X86_CR0_NE))
1154 {
1155 /* old style FPU error reporting needs some extra work. */
1156 /** @todo don't fall back to the recompiler, but do it manually. */
1157 rc = VINF_EM_RAW_EMULATE_INSTR;
1158 break;
1159 }
1160 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1161
1162 Event.au64[0] = 0;
1163 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1164 Event.n.u1Valid = 1;
1165 Event.n.u8Vector = X86_XCPT_MF;
1166
1167 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1168
1169 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1170 goto ResumeExecution;
1171 }
1172
1173#ifdef VBOX_STRICT
1174 case X86_XCPT_GP: /* General protection failure exception.*/
1175 case X86_XCPT_UD: /* Unknown opcode exception. */
1176 case X86_XCPT_DE: /* Debug exception. */
1177 case X86_XCPT_SS: /* Stack segment exception. */
1178 case X86_XCPT_NP: /* Segment not present exception. */
1179 {
1180 Event.au64[0] = 0;
1181 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1182 Event.n.u1Valid = 1;
1183 Event.n.u8Vector = vector;
1184
1185 switch(vector)
1186 {
1187 case X86_XCPT_GP:
1188 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1189 Event.n.u1ErrorCodeValid = 1;
1190 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1191 break;
1192 case X86_XCPT_DE:
1193 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1194 break;
1195 case X86_XCPT_UD:
1196 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1197 break;
1198 case X86_XCPT_SS:
1199 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1200 Event.n.u1ErrorCodeValid = 1;
1201 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1202 break;
1203 case X86_XCPT_NP:
1204 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1205 Event.n.u1ErrorCodeValid = 1;
1206 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1207 break;
1208 }
1209 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1210 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1211
1212 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1213 goto ResumeExecution;
1214 }
1215#endif
1216 default:
1217 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1218 rc = VERR_EM_INTERNAL_ERROR;
1219 break;
1220
1221 } /* switch (vector) */
1222 break;
1223 }
1224
1225 case SVM_EXIT_VINTR:
1226 /* A virtual interrupt is about to be delivered, which means IF=1. */
1227 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1228 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1229 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 0;
1230 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1231 goto ResumeExecution;
1232
1233 case SVM_EXIT_FERR_FREEZE:
1234 case SVM_EXIT_INTR:
1235 case SVM_EXIT_NMI:
1236 case SVM_EXIT_SMI:
1237 case SVM_EXIT_INIT:
1238 /* External interrupt; leave to allow it to be dispatched again. */
1239 rc = VINF_EM_RAW_INTERRUPT;
1240 break;
1241
1242 case SVM_EXIT_WBINVD:
1243 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1244 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1245 /* Skip instruction and continue directly. */
1246 pCtx->eip += 2; /** @note hardcoded opcode size! */
1247 /* Continue execution.*/
1248 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1249 goto ResumeExecution;
1250
1251 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1252 {
1253 Log2(("SVM: Cpuid %x\n", pCtx->eax));
1254 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1255 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1256 if (rc == VINF_SUCCESS)
1257 {
1258 /* Update EIP and continue execution. */
1259 pCtx->eip += 2; /** @note hardcoded opcode size! */
1260 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1261 goto ResumeExecution;
1262 }
1263 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1264 rc = VINF_EM_RAW_EMULATE_INSTR;
1265 break;
1266 }
1267
1268 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1269 {
1270 Log2(("SVM: Rdtsc\n"));
1271 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1272 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1273 if (rc == VINF_SUCCESS)
1274 {
1275 /* Update EIP and continue execution. */
1276 pCtx->eip += 2; /** @note hardcoded opcode size! */
1277 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1278 goto ResumeExecution;
1279 }
1280 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1281 rc = VINF_EM_RAW_EMULATE_INSTR;
1282 break;
1283 }
1284
1285 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1286 {
1287 Log2(("SVM: invlpg\n"));
1288 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1289
1290 /* Truly a pita. Why can't SVM give the same information as VMX? */
1291 rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1292 if (rc == VINF_SUCCESS)
1293 {
1294 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1295 goto ResumeExecution; /* eip already updated */
1296 }
1297 break;
1298 }
1299
1300 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1301 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1302 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1303 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1304 {
1305 uint32_t cbSize;
1306
1307 Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1308 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1309 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1310
1311 switch (exitCode - SVM_EXIT_WRITE_CR0)
1312 {
1313 case 0:
1314 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1315 break;
1316 case 2:
1317 break;
1318 case 3:
1319 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1320 break;
1321 case 4:
1322 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1323 break;
1324 default:
1325 AssertFailed();
1326 }
1327 /* Check if a sync operation is pending. */
1328 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1329 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1330 {
1331 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1332 AssertRC(rc);
1333
1334 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1335
1336 /** @note Force a TLB flush. SVM requires us to do it manually. */
1337 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1338 }
1339 if (rc == VINF_SUCCESS)
1340 {
1341 /* EIP has been updated already. */
1342
1343 /* Only resume if successful. */
1344 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1345 goto ResumeExecution;
1346 }
1347 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1348 break;
1349 }
1350
1351 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1352 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1353 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1354 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1355 {
1356 uint32_t cbSize;
1357
1358 Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1359 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1360 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1361 if (rc == VINF_SUCCESS)
1362 {
1363 /* EIP has been updated already. */
1364
1365 /* Only resume if successful. */
1366 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1367 goto ResumeExecution;
1368 }
1369 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1370 break;
1371 }
1372
1373 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1374 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1375 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1376 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1377 {
1378 uint32_t cbSize;
1379
1380 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1381 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1382 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1383 if (rc == VINF_SUCCESS)
1384 {
1385 /* EIP has been updated already. */
1386
1387 /* Only resume if successful. */
1388 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1389 goto ResumeExecution;
1390 }
1391 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1392 break;
1393 }
1394
1395 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1396 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1397 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1398 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1399 {
1400 uint32_t cbSize;
1401
1402 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1403 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1404 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1405 if (rc == VINF_SUCCESS)
1406 {
1407 /* EIP has been updated already. */
1408
1409 /* Only resume if successful. */
1410 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1411 goto ResumeExecution;
1412 }
1413 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1414 break;
1415 }
1416
1417 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1418 case SVM_EXIT_IOIO: /* I/O instruction. */
1419 {
1420 SVM_IOIO_EXIT IoExitInfo;
1421 uint32_t uIOSize, uAndVal;
1422
1423 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1424
1425 /** @todo could use a lookup table here */
1426 if (IoExitInfo.n.u1OP8)
1427 {
1428 uIOSize = 1;
1429 uAndVal = 0xff;
1430 }
1431 else
1432 if (IoExitInfo.n.u1OP16)
1433 {
1434 uIOSize = 2;
1435 uAndVal = 0xffff;
1436 }
1437 else
1438 if (IoExitInfo.n.u1OP32)
1439 {
1440 uIOSize = 4;
1441 uAndVal = 0xffffffff;
1442 }
1443 else
1444 {
1445 AssertFailed(); /* should be fatal. */
1446 rc = VINF_EM_RAW_EMULATE_INSTR;
1447 break;
1448 }
1449
1450 if (IoExitInfo.n.u1STR)
1451 {
1452 /* ins/outs */
1453 uint32_t prefix = 0;
1454 if (IoExitInfo.n.u1REP)
1455 prefix |= PREFIX_REP;
1456
1457 if (IoExitInfo.n.u1Type == 0)
1458 {
1459 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1460 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1461 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1462 }
1463 else
1464 {
1465 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1466 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1467 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1468 }
1469 }
1470 else
1471 {
1472 /* normal in/out */
1473 Assert(!IoExitInfo.n.u1REP);
1474
1475 if (IoExitInfo.n.u1Type == 0)
1476 {
1477 Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1478 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1479 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1480 }
1481 else
1482 {
1483 uint32_t u32Val = 0;
1484
1485 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1486 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1487 if (IOM_SUCCESS(rc))
1488 {
1489 /* Write back to the EAX register. */
1490 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1491 Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1492 }
1493 }
1494 }
1495 /*
1496 * Handled the I/O return codes.
1497 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1498 */
1499 if (IOM_SUCCESS(rc))
1500 {
1501 /* Update EIP and continue execution. */
1502 pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1503 if (RT_LIKELY(rc == VINF_SUCCESS))
1504 {
1505 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1506 goto ResumeExecution;
1507 }
1508 Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1509 break;
1510 }
1511
1512#ifdef VBOX_STRICT
1513 if (rc == VINF_IOM_HC_IOPORT_READ)
1514 Assert(IoExitInfo.n.u1Type != 0);
1515 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1516 Assert(IoExitInfo.n.u1Type == 0);
1517 else
1518 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1519#endif
1520 Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1521 break;
1522 }
1523
1524 case SVM_EXIT_HLT:
1525 /** Check if external interrupts are pending; if so, don't switch back. */
1526 if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
1527 {
1528 pCtx->eip++; /* skip hlt */
1529 goto ResumeExecution;
1530 }
1531
1532 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1533 break;
1534
1535 case SVM_EXIT_RSM:
1536 case SVM_EXIT_INVLPGA:
1537 case SVM_EXIT_VMRUN:
1538 case SVM_EXIT_VMMCALL:
1539 case SVM_EXIT_VMLOAD:
1540 case SVM_EXIT_VMSAVE:
1541 case SVM_EXIT_STGI:
1542 case SVM_EXIT_CLGI:
1543 case SVM_EXIT_SKINIT:
1544 case SVM_EXIT_RDTSCP:
1545 {
1546 /* Unsupported instructions. */
1547 SVM_EVENT Event;
1548
1549 Event.au64[0] = 0;
1550 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1551 Event.n.u1Valid = 1;
1552 Event.n.u8Vector = X86_XCPT_UD;
1553
1554 Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1555 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1556
1557 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1558 goto ResumeExecution;
1559 }
1560
1561 /* Emulate in ring 3. */
1562 case SVM_EXIT_MONITOR:
1563 case SVM_EXIT_RDPMC:
1564 case SVM_EXIT_PAUSE:
1565 case SVM_EXIT_MWAIT_UNCOND:
1566 case SVM_EXIT_MWAIT_ARMED:
1567 case SVM_EXIT_MSR:
1568 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1569 break;
1570
1571 case SVM_EXIT_NPF:
1572 AssertFailed(); /* unexpected */
1573 break;
1574
1575 case SVM_EXIT_SHUTDOWN:
1576 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1577 break;
1578
1579 case SVM_EXIT_IDTR_READ:
1580 case SVM_EXIT_GDTR_READ:
1581 case SVM_EXIT_LDTR_READ:
1582 case SVM_EXIT_TR_READ:
1583 case SVM_EXIT_IDTR_WRITE:
1584 case SVM_EXIT_GDTR_WRITE:
1585 case SVM_EXIT_LDTR_WRITE:
1586 case SVM_EXIT_TR_WRITE:
1587 case SVM_EXIT_CR0_SEL_WRITE:
1588 default:
1589 /* Unexpected exit codes. */
1590 rc = VERR_EM_INTERNAL_ERROR;
1591 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1592 break;
1593 }
1594
1595end:
1596 if (fGuestStateSynced)
1597 {
1598 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1599 SVM_READ_SELREG(LDTR, ldtr);
1600 SVM_READ_SELREG(TR, tr);
1601
1602 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1603 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1604
1605 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1606 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1607
1608 /*
1609 * System MSRs
1610 */
1611 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1612 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1613 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1614 }
1615
1616 /* Signal changes for the recompiler. */
1617 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
1618
1619 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1620 if (exitCode == SVM_EXIT_INTR)
1621 {
1622 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1623 /* On the next entry we'll only sync the host context. */
1624 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
1625 }
1626 else
1627 {
1628 /* On the next entry we'll sync everything. */
1629 /** @todo we can do better than this */
1630 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
1631 }
1632
1633 /* translate into a less severe return code */
1634 if (rc == VERR_EM_INTERPRETER)
1635 rc = VINF_EM_RAW_EMULATE_INSTR;
1636
1637 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1638 return rc;
1639}
1640
1641/**
1642 * Enters the AMD-V session
1643 *
1644 * @returns VBox status code.
1645 * @param pVM The VM to operate on.
1646 * @param pCpu CPU info struct
1647 */
1648HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1649{
1650 Assert(pVM->hwaccm.s.svm.fSupported);
1651
1652 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1653 if (pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu)
1654 {
1655 /* Force a TLB flush on VM entry. */
1656 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1657 }
1658 pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
1659
1660 pVM->hwaccm.s.svm.fResumeVM = false;
1661
1662 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1663 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
1664
1665 return VINF_SUCCESS;
1666}
1667
1668
1669/**
1670 * Leaves the AMD-V session
1671 *
1672 * @returns VBox status code.
1673 * @param pVM The VM to operate on.
1674 */
1675HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1676{
1677 Assert(pVM->hwaccm.s.svm.fSupported);
1678 return VINF_SUCCESS;
1679}
1680
1681
1682static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1683{
1684 OP_PARAMVAL param1;
1685 RTGCPTR addr;
1686
1687 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1688 if(VBOX_FAILURE(rc))
1689 return VERR_EM_INTERPRETER;
1690
1691 switch(param1.type)
1692 {
1693 case PARMTYPE_IMMEDIATE:
1694 case PARMTYPE_ADDRESS:
1695 if(!(param1.flags & PARAM_VAL32))
1696 return VERR_EM_INTERPRETER;
1697 addr = (RTGCPTR)param1.val.val32;
1698 break;
1699
1700 default:
1701 return VERR_EM_INTERPRETER;
1702 }
1703
1704 /** @todo is addr always a flat linear address or ds based
1705 * (in absence of segment override prefixes)????
1706 */
1707 rc = PGMInvalidatePage(pVM, addr);
1708 if (VBOX_SUCCESS(rc))
1709 {
1710 /* Manually invalidate the page for the VM's TLB. */
1711 Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1712 SVMInvlpgA(addr, uASID);
1713 return VINF_SUCCESS;
1714 }
1715 Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1716 return rc;
1717}
1718
1719/**
1720 * Interprets INVLPG
1721 *
1722 * @returns VBox status code.
1723 * @retval VINF_* Scheduling instructions.
1724 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1725 * @retval VERR_* Fatal errors.
1726 *
1727 * @param pVM The VM handle.
1728 * @param pRegFrame The register frame.
1729 * @param ASID Tagged TLB id for the guest
1730 *
1731 * Updates the EIP if an instruction was executed successfully.
1732 */
1733static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1734{
1735 /*
1736 * Only allow 32-bit code.
1737 */
1738 if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1739 {
1740 RTGCPTR pbCode;
1741 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1742 if (VBOX_SUCCESS(rc))
1743 {
1744 uint32_t cbOp;
1745 DISCPUSTATE Cpu;
1746
1747 Cpu.mode = CPUMODE_32BIT;
1748 rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1749 Assert(VBOX_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);
1750 if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1751 {
1752 Assert(cbOp == Cpu.opsize);
1753 rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1754 if (VBOX_SUCCESS(rc))
1755 {
1756 pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1757 }
1758 return rc;
1759 }
1760 }
1761 }
1762 return VERR_EM_INTERPRETER;
1763}
1764
1765
1766/**
1767 * Invalidates a guest page
1768 *
1769 * @returns VBox status code.
1770 * @param pVM The VM to operate on.
1771 * @param GCVirt Page to invalidate
1772 */
1773HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
1774{
1775 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | pVM->hwaccm.s.svm.fForceTLBFlush;
1776
1777 /* Skip it if a TLB flush is already pending. */
1778 if (!fFlushPending)
1779 {
1780 SVM_VMCB *pVMCB;
1781
1782 Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
1783 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1784 Assert(pVM->hwaccm.s.svm.fSupported);
1785
1786 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
1787 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
1788
1789 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
1790 SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
1791 }
1792 return VINF_SUCCESS;
1793}
1794
1795/**
1796 * Flushes the guest TLB
1797 *
1798 * @returns VBox status code.
1799 * @param pVM The VM to operate on.
1800 */
1801HWACCMR0DECL(int) SVMR0FlushTLB(PVM pVM)
1802{
1803 Log2(("SVMR0FlushTLB\n"));
1804 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1805 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBManual);
1806 return VINF_SUCCESS;
1807}
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