HWSVMR0.cpp@ 9062

Last change on this file since 9062 was 9038, checked in by vboxsync, 17 years ago
Sync back the debug registers too (fixed gdb/dbx weirdness on solaris).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 74.3 KB

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1	/* $Id: HWSVMR0.cpp 9038 2008-05-21 20:54:25Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50	/**
51	* Sets up and activates AMD-V on the current CPU
52	*
53	* @returns VBox status code.
54	* @param pCpu CPU info struct
55	* @param pVM The VM to operate on.
56	* @param pvPageCpu Pointer to the global cpu page
57	* @param pPageCpuPhys Physical address of the global cpu page
58	*/
59	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60	{
61	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62	AssertReturn(pVM, VERR_INVALID_PARAMETER);
63	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67	#ifdef LOG_ENABLED
68	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69	#endif
70
71	/* Turn on AMD-V in the EFER MSR. */
72	uint64_t val = ASMRdMsr(MSR_K6_EFER);
73	if (!(val & MSR_K6_EFER_SVME))
74	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
75
76	/* Write the physical page address where the CPU will store the host state while executing the VM. */
77	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80	pCpu->cTLBFlushes = 0;
81	return VINF_SUCCESS;
82	}
83
84	/**
85	* Deactivates AMD-V on the current CPU
86	*
87	* @returns VBox status code.
88	* @param pCpu CPU info struct
89	* @param pvPageCpu Pointer to the global cpu page
90	* @param pPageCpuPhys Physical address of the global cpu page
91	*/
92	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93	{
94	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97	#ifdef LOG_ENABLED
98	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99	#endif
100
101	/* Turn off AMD-V in the EFER MSR. */
102	uint64_t val = ASMRdMsr(MSR_K6_EFER);
103	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105	/* Invalidate host state physical address. */
106	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107	pCpu->uCurrentASID = 0;
108
109	return VINF_SUCCESS;
110	}
111
112	/**
113	* Does Ring-0 per VM AMD-V init.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119	{
120	int rc;
121
122	/* Allocate one page for the VM control block (VMCB). */
123	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
124	if (RT_FAILURE(rc))
125	return rc;
126
127	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
128	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
129	ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
130
131	/* Allocate one page for the host context */
132	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133	if (RT_FAILURE(rc))
134	return rc;
135
136	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138	ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
139
140	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142	if (RT_FAILURE(rc))
143	return rc;
144
145	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152	if (RT_FAILURE(rc))
153	return rc;
154
155	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157	/* Set all bits to intercept all MSR accesses. */
158	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160	/* Erratum 170 which requires a forced TLB flush for each world switch:
161	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162	*
163	* All BH-G1/2 and DH-G1/2 models include a fix:
164	* Athlon X2: 0x6b 1/2
165	* 0x68 1/2
166	* Athlon 64: 0x7f 1
167	* 0x6f 2
168	* Sempron: 0x7f 1/2
169	* 0x6f 2
170	* 0x6c 2
171	* 0x7c 2
172	* Turion 64: 0x68 2
173	*
174	*/
175	uint32_t u32Dummy;
176	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178	u32BaseFamily= (u32Version >> 8) & 0xf;
179	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180	u32Model = ((u32Version >> 4) & 0xf);
181	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182	u32Stepping = u32Version & 0xf;
183	if ( u32Family == 0xf
184	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
185	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
186	{
187	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189	}
190
191	/* Invalidate the last cpu we were running on. */
192	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
193	return VINF_SUCCESS;
194	}
195
196	/**
197	* Does Ring-0 per VM AMD-V termination.
198	*
199	* @returns VBox status code.
200	* @param pVM The VM to operate on.
201	*/
202	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
203	{
204	if (pVM->hwaccm.s.svm.pMemObjVMCB)
205	{
206	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
207	pVM->hwaccm.s.svm.pVMCB = 0;
208	pVM->hwaccm.s.svm.pVMCBPhys = 0;
209	pVM->hwaccm.s.svm.pMemObjVMCB = 0;
210	}
211	if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
212	{
213	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
214	pVM->hwaccm.s.svm.pVMCBHost = 0;
215	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
216	pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
217	}
218	if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
219	{
220	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
221	pVM->hwaccm.s.svm.pIOBitmap = 0;
222	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
223	pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
224	}
225	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
226	{
227	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
228	pVM->hwaccm.s.svm.pMSRBitmap = 0;
229	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
230	pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
231	}
232	return VINF_SUCCESS;
233	}
234
235	/**
236	* Sets up AMD-V for the specified VM
237	*
238	* @returns VBox status code.
239	* @param pVM The VM to operate on.
240	*/
241	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
242	{
243	int rc = VINF_SUCCESS;
244	SVM_VMCB *pVMCB;
245
246	AssertReturn(pVM, VERR_INVALID_PARAMETER);
247
248	Assert(pVM->hwaccm.s.svm.fSupported);
249
250	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
251	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
252
253	/* Program the control fields. Most of them never have to be changed again. */
254	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
255	/* Note: CR8 reads will refer to V_TPR, so no need to catch them. */
256	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
257	if (!pVM->hwaccm.s.fNestedPaging)
258	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
259	else
260	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0);
261
262	/*
263	* CR0/3/4 writes must be intercepted for obvious reasons.
264	*/
265	if (!pVM->hwaccm.s.fNestedPaging)
266	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(8);
267	else
268	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(8);
269
270	/* Intercept all DRx reads and writes. */
271	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
272	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
273
274	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
275	* All breakpoints are automatically cleared when the VM exits.
276	*/
277
278	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
279	if (pVM->hwaccm.s.fNestedPaging)
280	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14); /* no longer need to intercept #PF. */
281
282	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
283	\| SVM_CTRL1_INTERCEPT_VINTR
284	\| SVM_CTRL1_INTERCEPT_NMI
285	\| SVM_CTRL1_INTERCEPT_SMI
286	\| SVM_CTRL1_INTERCEPT_INIT
287	\| SVM_CTRL1_INTERCEPT_RDPMC
288	\| SVM_CTRL1_INTERCEPT_CPUID
289	\| SVM_CTRL1_INTERCEPT_RSM
290	\| SVM_CTRL1_INTERCEPT_HLT
291	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
292	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
293	\| SVM_CTRL1_INTERCEPT_INVLPG
294	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
295	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
296	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
297	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
298	;
299	/* With nested paging we don't care about invlpg anymore. */
300	if (pVM->hwaccm.s.fNestedPaging)
301	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
302
303	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
304	\| SVM_CTRL2_INTERCEPT_VMMCALL
305	\| SVM_CTRL2_INTERCEPT_VMLOAD
306	\| SVM_CTRL2_INTERCEPT_VMSAVE
307	\| SVM_CTRL2_INTERCEPT_STGI
308	\| SVM_CTRL2_INTERCEPT_CLGI
309	\| SVM_CTRL2_INTERCEPT_SKINIT
310	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
311	\| SVM_CTRL2_INTERCEPT_WBINVD
312	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
313	;
314	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
315	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
316	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
317
318	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
319	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
320
321	/* Set IO and MSR bitmap addresses. */
322	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
323	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
324
325	/* No LBR virtualization. */
326	pVMCB->ctrl.u64LBRVirt = 0;
327
328	/** The ASID must start at 1; the host uses 0. */
329	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
330
331	return rc;
332	}
333
334
335	/**
336	* Injects an event (trap or external interrupt)
337	*
338	* @param pVM The VM to operate on.
339	* @param pVMCB SVM control block
340	* @param pCtx CPU Context
341	* @param pIntInfo SVM interrupt info
342	*/
343	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
344	{
345	#ifdef VBOX_STRICT
346	if (pEvent->n.u8Vector == 0xE)
347	Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
348	else
349	if (pEvent->n.u8Vector < 0x20)
350	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
351	else
352	{
353	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
354	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
355	Assert(pCtx->eflags.u32 & X86_EFL_IF);
356	}
357	#endif
358
359	/* Set event injection state. */
360	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
361	}
362
363
364	/**
365	* Checks for pending guest interrupts and injects them
366	*
367	* @returns VBox status code.
368	* @param pVM The VM to operate on.
369	* @param pVMCB SVM control block
370	* @param pCtx CPU Context
371	*/
372	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
373	{
374	int rc;
375
376	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
377	if (pVM->hwaccm.s.Event.fPending)
378	{
379	SVM_EVENT Event;
380
381	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
382	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
383	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
384	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
385
386	pVM->hwaccm.s.Event.fPending = false;
387	return VINF_SUCCESS;
388	}
389
390	/* When external interrupts are pending, we should exit the VM when IF is set. */
391	if ( !TRPMHasTrap(pVM)
392	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
393	{
394	if (!(pCtx->eflags.u32 & X86_EFL_IF))
395	{
396	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
397	{
398	Log(("Enable irq window exit!\n"));
399	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
400	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
401	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
402	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; /* ignore the priority in the TPR; just deliver it */
403	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
404	}
405	}
406	else
407	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
408	{
409	uint8_t u8Interrupt;
410
411	rc = PDMGetInterrupt(pVM, &u8Interrupt);
412	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
413	if (VBOX_SUCCESS(rc))
414	{
415	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
416	AssertRC(rc);
417	}
418	else
419	{
420	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
421	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
422	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
423	/* Just continue */
424	}
425	}
426	else
427	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
428	}
429
430	#ifdef VBOX_STRICT
431	if (TRPMHasTrap(pVM))
432	{
433	uint8_t u8Vector;
434	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
435	AssertRC(rc);
436	}
437	#endif
438
439	if ( pCtx->eflags.u32 & X86_EFL_IF
440	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
441	&& TRPMHasTrap(pVM)
442	)
443	{
444	uint8_t u8Vector;
445	int rc;
446	TRPMEVENT enmType;
447	SVM_EVENT Event;
448	uint32_t u32ErrorCode;
449
450	Event.au64[0] = 0;
451
452	/* If a new event is pending, then dispatch it now. */
453	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
454	AssertRC(rc);
455	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
456	Assert(enmType != TRPM_SOFTWARE_INT);
457
458	/* Clear the pending trap. */
459	rc = TRPMResetTrap(pVM);
460	AssertRC(rc);
461
462	Event.n.u8Vector = u8Vector;
463	Event.n.u1Valid = 1;
464	Event.n.u32ErrorCode = u32ErrorCode;
465
466	if (enmType == TRPM_TRAP)
467	{
468	switch (u8Vector) {
469	case 8:
470	case 10:
471	case 11:
472	case 12:
473	case 13:
474	case 14:
475	case 17:
476	/* Valid error codes. */
477	Event.n.u1ErrorCodeValid = 1;
478	break;
479	default:
480	break;
481	}
482	if (u8Vector == X86_XCPT_NMI)
483	Event.n.u3Type = SVM_EVENT_NMI;
484	else
485	Event.n.u3Type = SVM_EVENT_EXCEPTION;
486	}
487	else
488	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
489
490	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
491	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
492	} /* if (interrupts can be dispatched) */
493
494	return VINF_SUCCESS;
495	}
496
497
498	/**
499	* Loads the guest state
500	*
501	* @returns VBox status code.
502	* @param pVM The VM to operate on.
503	* @param pCtx Guest context
504	*/
505	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
506	{
507	RTGCUINTPTR val;
508	SVM_VMCB *pVMCB;
509
510	if (pVM == NULL)
511	return VERR_INVALID_PARAMETER;
512
513	/* Setup AMD SVM. */
514	Assert(pVM->hwaccm.s.svm.fSupported);
515
516	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
517	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
518
519	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
520	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
521	{
522	SVM_WRITE_SELREG(CS, cs);
523	SVM_WRITE_SELREG(SS, ss);
524	SVM_WRITE_SELREG(DS, ds);
525	SVM_WRITE_SELREG(ES, es);
526	SVM_WRITE_SELREG(FS, fs);
527	SVM_WRITE_SELREG(GS, gs);
528	}
529
530	/* Guest CPU context: LDTR. */
531	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
532	{
533	SVM_WRITE_SELREG(LDTR, ldtr);
534	}
535
536	/* Guest CPU context: TR. */
537	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
538	{
539	SVM_WRITE_SELREG(TR, tr);
540	}
541
542	/* Guest CPU context: GDTR. */
543	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
544	{
545	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
546	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
547	}
548
549	/* Guest CPU context: IDTR. */
550	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
551	{
552	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
553	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
554	}
555
556	/*
557	* Sysenter MSRs
558	*/
559	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
560	{
561	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
562	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
563	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
564	}
565
566	/* Control registers */
567	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
568	{
569	val = pCtx->cr0;
570	if (CPUMIsGuestFPUStateActive(pVM) == false)
571	{
572	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
573	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
574	}
575	else
576	{
577	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
578	/** @todo check if we support the old style mess correctly. */
579	if (!(val & X86_CR0_NE))
580	{
581	Log(("Forcing X86_CR0_NE!!!\n"));
582
583	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
584	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
585	{
586	pVMCB->ctrl.u32InterceptException \|= RT_BIT(16);
587	pVM->hwaccm.s.fFPUOldStyleOverride = true;
588	}
589	}
590	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
591	}
592	/* Always enable caching. */
593	val &= ~(X86_CR0_CD\|X86_CR0_NW);
594
595	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (host) physical level. */
596	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
597	if (!pVM->hwaccm.s.fNestedPaging)
598	{
599	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
600	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
601	}
602	pVMCB->guest.u64CR0 = val;
603	}
604	/* CR2 as well */
605	pVMCB->guest.u64CR2 = pCtx->cr2;
606
607	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
608	{
609	/* Save our shadow CR3 register. */
610	if (pVM->hwaccm.s.fNestedPaging)
611	{
612	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
613	pVMCB->guest.u64CR3 = pCtx->cr3;
614	}
615	else
616	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
617	}
618
619	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
620	{
621	val = pCtx->cr4;
622	if (!pVM->hwaccm.s.fNestedPaging)
623	{
624	switch(pVM->hwaccm.s.enmShadowMode)
625	{
626	case PGMMODE_REAL:
627	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
628	AssertFailed();
629	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
630
631	case PGMMODE_32_BIT: /* 32-bit paging. */
632	break;
633
634	case PGMMODE_PAE: /* PAE paging. */
635	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
636	/** @todo use normal 32 bits paging */
637	val \|= X86_CR4_PAE;
638	break;
639
640	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
641	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
642	AssertFailed();
643	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
644
645	default: /* shut up gcc */
646	AssertFailed();
647	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
648	}
649	}
650	pVMCB->guest.u64CR4 = val;
651	}
652
653	/* Debug registers. */
654	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
655	{
656	/** @todo DR0-6 */
657	val = pCtx->dr7;
658	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
659	val \|= 0x400; /* must be one */
660	#ifdef VBOX_STRICT
661	val = 0x400;
662	#endif
663	pVMCB->guest.u64DR7 = val;
664
665	pVMCB->guest.u64DR6 = pCtx->dr6;
666	}
667
668	/* EIP, ESP and EFLAGS */
669	pVMCB->guest.u64RIP = pCtx->eip;
670	pVMCB->guest.u64RSP = pCtx->esp;
671	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
672
673	/* Set CPL */
674	pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
675
676	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
677	pVMCB->guest.u64RAX = pCtx->eax;
678
679	/* vmrun will fail otherwise. */
680	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
681
682	/** TSC offset. */
683	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
684	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
685	else
686	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
687
688	/** @todo 64 bits stuff (?):
689	* - STAR
690	* - LSTAR
691	* - CSTAR
692	* - SFMASK
693	* - KernelGSBase
694	*/
695
696	#ifdef DEBUG
697	/* Intercept X86_XCPT_DB if stepping is enabled */
698	if (DBGFIsStepping(pVM))
699	pVMCB->ctrl.u32InterceptException \|= RT_BIT(1);
700	else
701	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
702	#endif
703
704	/* Done. */
705	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
706
707	return VINF_SUCCESS;
708	}
709
710
711	/**
712	* Runs guest code in an SVM VM.
713	*
714	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
715	*
716	* @returns VBox status code.
717	* @param pVM The VM to operate on.
718	* @param pCtx Guest context
719	* @param pCpu CPU info struct
720	*/
721	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
722	{
723	int rc = VINF_SUCCESS;
724	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
725	SVM_VMCB *pVMCB;
726	bool fGuestStateSynced = false;
727	unsigned cResume = 0;
728
729	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
730
731	AssertReturn(pCpu->fSVMConfigured, VERR_EM_INTERNAL_ERROR);
732
733	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
734	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
735
736	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
737	*/
738	ResumeExecution:
739	/* Safety precaution; looping for too long here can have a very bad effect on the host */
740	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
741	{
742	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
743	rc = VINF_EM_RAW_INTERRUPT;
744	goto end;
745	}
746
747	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
748	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
749	{
750	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
751	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
752	{
753	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
754	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
755	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
756	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
757	*/
758	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
759	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
760	pVMCB->ctrl.u64IntShadow = 0;
761	}
762	}
763	else
764	{
765	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
766	pVMCB->ctrl.u64IntShadow = 0;
767	}
768
769	/* Check for pending actions that force us to go back to ring 3. */
770	#ifdef DEBUG
771	/* Intercept X86_XCPT_DB if stepping is enabled */
772	if (!DBGFIsStepping(pVM))
773	#endif
774	{
775	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
776	{
777	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
778	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
779	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
780	rc = VINF_EM_RAW_TO_R3;
781	goto end;
782	}
783	}
784
785	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
786	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
787	{
788	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
789	rc = VINF_EM_PENDING_REQUEST;
790	goto end;
791	}
792
793	/* When external interrupts are pending, we should exit the VM when IF is set. */
794	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
795	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
796	if (VBOX_FAILURE(rc))
797	{
798	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
799	goto end;
800	}
801
802	/* Load the guest state */
803	rc = SVMR0LoadGuestState(pVM, pCtx);
804	if (rc != VINF_SUCCESS)
805	{
806	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
807	goto end;
808	}
809	fGuestStateSynced = true;
810
811	/* All done! Let's start VM execution. */
812	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
813
814	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
815	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
816
817	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
818	if (!pVM->hwaccm.s.svm.fResumeVM)
819	{
820	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
821	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
822	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
823	{
824	/* Force a TLB flush on VM entry. */
825	pVM->hwaccm.s.svm.fForceTLBFlush = true;
826	}
827	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
828	}
829
830	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
831	if ( pVM->hwaccm.s.svm.fForceTLBFlush
832	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
833	{
834	if (++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID)
835	{
836	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
837	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
838	pCpu->cTLBFlushes++;
839	}
840	else
841	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
842
843	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
844	}
845	else
846	{
847	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
848	if (!pCpu->uCurrentASID)
849	pCpu->uCurrentASID = 1;
850
851	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
852	}
853
854	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
855	pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
856
857	#ifdef VBOX_WITH_STATISTICS
858	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
859	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
860	else
861	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
862	#endif
863
864	/* In case we execute a goto ResumeExecution later on. */
865	pVM->hwaccm.s.svm.fResumeVM = true;
866	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
867
868	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
869	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
870	\| SVM_CTRL2_INTERCEPT_VMMCALL
871	\| SVM_CTRL2_INTERCEPT_VMLOAD
872	\| SVM_CTRL2_INTERCEPT_VMSAVE
873	\| SVM_CTRL2_INTERCEPT_STGI
874	\| SVM_CTRL2_INTERCEPT_CLGI
875	\| SVM_CTRL2_INTERCEPT_SKINIT
876	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
877	\| SVM_CTRL2_INTERCEPT_WBINVD
878	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
879	));
880	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
881	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
882	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
883	Assert(pVMCB->ctrl.u64LBRVirt == 0);
884
885	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
886	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
887
888	/**
889	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
890	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
891	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
892	*/
893
894	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
895
896	/* Reason for the VM exit */
897	exitCode = pVMCB->ctrl.u64ExitCode;
898
899	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
900	{
901	HWACCMDumpRegs(pCtx);
902	#ifdef DEBUG
903	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
904	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
905	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
906	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
907	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
908	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
909	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
910	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
911	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
912	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
913
914	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
915	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
916	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
917	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
918
919	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
920	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
921	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
922	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
923	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
924	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
925	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
926	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
927	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
928	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
929
930	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
931	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
932	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
933	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
934	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
935	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
936	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
937	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
938	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
939	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
940	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
941	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
942	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
943	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
944	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
945	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
946	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
947
948	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
949	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
950
951	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
952	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
953	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
954	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
955	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
956	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
957	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
958	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
959	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
960	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
961	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
962	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
963	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
964	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
965	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
966	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
967	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
968	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
969	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
970	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
971
972	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
973	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
974
975	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
976	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
977	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
978	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
979
980	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
981	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
982
983	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
984	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
985	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
986	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
987
988	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
989	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
990	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
991	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
992	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
993	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
994	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
995
996	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
997	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
998	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
999	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1000
1001	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1002	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1003	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1004
1005	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1006	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1007	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1008	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1009	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1010	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1011	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1012	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1013	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1014	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1015	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1016	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1017
1018	#endif
1019	rc = VERR_SVM_UNABLE_TO_START_VM;
1020	goto end;
1021	}
1022
1023	/* Let's first sync back eip, esp, and eflags. */
1024	pCtx->eip = pVMCB->guest.u64RIP;
1025	pCtx->esp = pVMCB->guest.u64RSP;
1026	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1027	/* eax is saved/restore across the vmrun instruction */
1028	pCtx->eax = pVMCB->guest.u64RAX;
1029
1030	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1031	SVM_READ_SELREG(SS, ss);
1032	SVM_READ_SELREG(CS, cs);
1033	SVM_READ_SELREG(DS, ds);
1034	SVM_READ_SELREG(ES, es);
1035	SVM_READ_SELREG(FS, fs);
1036	SVM_READ_SELREG(GS, gs);
1037
1038	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1039	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1040	if (pVM->hwaccm.s.fNestedPaging)
1041	{
1042	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1043	CPUMSetGuestCR4(pVM, pVMCB->guest.u64CR4);
1044	}
1045
1046	/** @note NOW IT'S SAFE FOR LOGGING! */
1047
1048	/* Take care of instruction fusing (sti, mov ss) */
1049	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1050	{
1051	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
1052	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1053	}
1054	else
1055	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1056
1057	Log2(("exitCode = %x\n", exitCode));
1058
1059	/* Sync back the debug registers. */
1060	/** @todo Implement debug registers correctly. */
1061	pCtx->dr6 = pVMCB->guest.u64DR6;
1062	pCtx->dr7 = pVMCB->guest.u64DR7;
1063
1064	/* Check if an injected event was interrupted prematurely. */
1065	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1066	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1067	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1068	{
1069	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
1070	pVM->hwaccm.s.Event.fPending = true;
1071	/* Error code present? (redundant) */
1072	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1073	{
1074	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1075	}
1076	else
1077	pVM->hwaccm.s.Event.errCode = 0;
1078	}
1079	#ifdef VBOX_WITH_STATISTICS
1080	if (exitCode == SVM_EXIT_NPF)
1081	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1082	else
1083	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1084	#endif
1085
1086	/* Deal with the reason of the VM-exit. */
1087	switch (exitCode)
1088	{
1089	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1090	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1091	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1092	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1093	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1094	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1095	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1096	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1097	{
1098	/* Pending trap. */
1099	SVM_EVENT Event;
1100	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1101
1102	Log2(("Hardware/software interrupt %d\n", vector));
1103	switch (vector)
1104	{
1105	#ifdef DEBUG
1106	case X86_XCPT_DB:
1107	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1108	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1109	break;
1110	#endif
1111
1112	case X86_XCPT_NM:
1113	{
1114	uint32_t oldCR0;
1115
1116	Log(("#NM fault at %VGv\n", pCtx->eip));
1117
1118	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1119	oldCR0 = ASMGetCR0();
1120	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1121	rc = CPUMHandleLazyFPU(pVM);
1122	if (rc == VINF_SUCCESS)
1123	{
1124	Assert(CPUMIsGuestFPUStateActive(pVM));
1125
1126	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1127	ASMSetCR0(oldCR0);
1128
1129	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1130
1131	/* Continue execution. */
1132	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1133	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1134
1135	goto ResumeExecution;
1136	}
1137
1138	Log(("Forward #NM fault to the guest\n"));
1139	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1140
1141	Event.au64[0] = 0;
1142	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1143	Event.n.u1Valid = 1;
1144	Event.n.u8Vector = X86_XCPT_NM;
1145
1146	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1147	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1148	goto ResumeExecution;
1149	}
1150
1151	case X86_XCPT_PF: /* Page fault */
1152	{
1153	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1154	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1155
1156	Assert(!pVM->hwaccm.s.fNestedPaging);
1157
1158	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1159	/* Exit qualification contains the linear address of the page fault. */
1160	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1161	TRPMSetErrorCode(pVM, errCode);
1162	TRPMSetFaultAddress(pVM, uFaultAddress);
1163
1164	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1165	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1166	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1167	if (rc == VINF_SUCCESS)
1168	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1169	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1170	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1171
1172	TRPMResetTrap(pVM);
1173
1174	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1175	goto ResumeExecution;
1176	}
1177	else
1178	if (rc == VINF_EM_RAW_GUEST_TRAP)
1179	{ /* A genuine pagefault.
1180	* Forward the trap to the guest by injecting the exception and resuming execution.
1181	*/
1182	Log2(("Forward page fault to the guest\n"));
1183	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1184	/* The error code might have been changed. */
1185	errCode = TRPMGetErrorCode(pVM);
1186
1187	TRPMResetTrap(pVM);
1188
1189	/* Now we must update CR2. */
1190	pCtx->cr2 = uFaultAddress;
1191
1192	Event.au64[0] = 0;
1193	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1194	Event.n.u1Valid = 1;
1195	Event.n.u8Vector = X86_XCPT_PF;
1196	Event.n.u1ErrorCodeValid = 1;
1197	Event.n.u32ErrorCode = errCode;
1198
1199	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1200
1201	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1202	goto ResumeExecution;
1203	}
1204	#ifdef VBOX_STRICT
1205	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1206	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1207	#endif
1208	/* Need to go back to the recompiler to emulate the instruction. */
1209	TRPMResetTrap(pVM);
1210	break;
1211	}
1212
1213	case X86_XCPT_MF: /* Floating point exception. */
1214	{
1215	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1216	if (!(pCtx->cr0 & X86_CR0_NE))
1217	{
1218	/* old style FPU error reporting needs some extra work. */
1219	/** @todo don't fall back to the recompiler, but do it manually. */
1220	rc = VINF_EM_RAW_EMULATE_INSTR;
1221	break;
1222	}
1223	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1224
1225	Event.au64[0] = 0;
1226	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1227	Event.n.u1Valid = 1;
1228	Event.n.u8Vector = X86_XCPT_MF;
1229
1230	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1231
1232	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1233	goto ResumeExecution;
1234	}
1235
1236	#ifdef VBOX_STRICT
1237	case X86_XCPT_GP: /* General protection failure exception.*/
1238	case X86_XCPT_UD: /* Unknown opcode exception. */
1239	case X86_XCPT_DE: /* Debug exception. */
1240	case X86_XCPT_SS: /* Stack segment exception. */
1241	case X86_XCPT_NP: /* Segment not present exception. */
1242	{
1243	Event.au64[0] = 0;
1244	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1245	Event.n.u1Valid = 1;
1246	Event.n.u8Vector = vector;
1247
1248	switch(vector)
1249	{
1250	case X86_XCPT_GP:
1251	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1252	Event.n.u1ErrorCodeValid = 1;
1253	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1254	break;
1255	case X86_XCPT_DE:
1256	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1257	break;
1258	case X86_XCPT_UD:
1259	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1260	break;
1261	case X86_XCPT_SS:
1262	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1263	Event.n.u1ErrorCodeValid = 1;
1264	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1265	break;
1266	case X86_XCPT_NP:
1267	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1268	Event.n.u1ErrorCodeValid = 1;
1269	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1270	break;
1271	}
1272	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->eip, pCtx->esi));
1273	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1274
1275	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1276	goto ResumeExecution;
1277	}
1278	#endif
1279	default:
1280	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1281	rc = VERR_EM_INTERNAL_ERROR;
1282	break;
1283
1284	} /* switch (vector) */
1285	break;
1286	}
1287
1288	case SVM_EXIT_NPF:
1289	{
1290	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1291	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1292	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1293
1294	Assert(pVM->hwaccm.s.fNestedPaging);
1295
1296	Log2(("Page fault at %VGp cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1297	/* Exit qualification contains the linear address of the page fault. */
1298	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1299	TRPMSetErrorCode(pVM, errCode);
1300	TRPMSetFaultAddress(pVM, uFaultAddress);
1301
1302	/* Handle the pagefault trap for the nested shadow table. */
1303	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1304	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->eip, rc));
1305	if (rc == VINF_SUCCESS)
1306	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1307	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->eip, uFaultAddress, errCode));
1308	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1309
1310	TRPMResetTrap(pVM);
1311
1312	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1313	goto ResumeExecution;
1314	}
1315
1316	#ifdef VBOX_STRICT
1317	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1318	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1319	#endif
1320	/* Need to go back to the recompiler to emulate the instruction. */
1321	TRPMResetTrap(pVM);
1322	break;
1323	}
1324
1325	case SVM_EXIT_VINTR:
1326	/* A virtual interrupt is about to be delivered, which means IF=1. */
1327	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1328	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1329	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 0;
1330	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1331	goto ResumeExecution;
1332
1333	case SVM_EXIT_FERR_FREEZE:
1334	case SVM_EXIT_INTR:
1335	case SVM_EXIT_NMI:
1336	case SVM_EXIT_SMI:
1337	case SVM_EXIT_INIT:
1338	/* External interrupt; leave to allow it to be dispatched again. */
1339	rc = VINF_EM_RAW_INTERRUPT;
1340	break;
1341
1342	case SVM_EXIT_WBINVD:
1343	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1344	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1345	/* Skip instruction and continue directly. */
1346	pCtx->eip += 2; /** @note hardcoded opcode size! */
1347	/* Continue execution.*/
1348	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1349	goto ResumeExecution;
1350
1351	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1352	{
1353	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1354	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1355	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1356	if (rc == VINF_SUCCESS)
1357	{
1358	/* Update EIP and continue execution. */
1359	pCtx->eip += 2; /** @note hardcoded opcode size! */
1360	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1361	goto ResumeExecution;
1362	}
1363	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1364	rc = VINF_EM_RAW_EMULATE_INSTR;
1365	break;
1366	}
1367
1368	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1369	{
1370	Log2(("SVM: Rdtsc\n"));
1371	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1372	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1373	if (rc == VINF_SUCCESS)
1374	{
1375	/* Update EIP and continue execution. */
1376	pCtx->eip += 2; /** @note hardcoded opcode size! */
1377	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1378	goto ResumeExecution;
1379	}
1380	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1381	rc = VINF_EM_RAW_EMULATE_INSTR;
1382	break;
1383	}
1384
1385	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1386	{
1387	Log2(("SVM: invlpg\n"));
1388	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1389
1390	Assert(!pVM->hwaccm.s.fNestedPaging);
1391
1392	/* Truly a pita. Why can't SVM give the same information as VMX? */
1393	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1394	if (rc == VINF_SUCCESS)
1395	{
1396	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1397	goto ResumeExecution; /* eip already updated */
1398	}
1399	break;
1400	}
1401
1402	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1403	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1404	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1405	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1406	{
1407	uint32_t cbSize;
1408
1409	Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1410	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1411	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1412
1413	switch (exitCode - SVM_EXIT_WRITE_CR0)
1414	{
1415	case 0:
1416	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1417	break;
1418	case 2:
1419	break;
1420	case 3:
1421	Assert(!pVM->hwaccm.s.fNestedPaging);
1422	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1423	break;
1424	case 4:
1425	Assert(!pVM->hwaccm.s.fNestedPaging);
1426	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1427	break;
1428	default:
1429	AssertFailed();
1430	}
1431	/* Check if a sync operation is pending. */
1432	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1433	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1434	{
1435	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1436	AssertRC(rc);
1437
1438	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1439
1440	/** @note Force a TLB flush. SVM requires us to do it manually. */
1441	pVM->hwaccm.s.svm.fForceTLBFlush = true;
1442	}
1443	if (rc == VINF_SUCCESS)
1444	{
1445	/* EIP has been updated already. */
1446
1447	/* Only resume if successful. */
1448	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1449	goto ResumeExecution;
1450	}
1451	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1452	break;
1453	}
1454
1455	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1456	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1457	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1458	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1459	{
1460	uint32_t cbSize;
1461
1462	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1463	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1464	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1465	if (rc == VINF_SUCCESS)
1466	{
1467	/* EIP has been updated already. */
1468
1469	/* Only resume if successful. */
1470	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1471	goto ResumeExecution;
1472	}
1473	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1474	break;
1475	}
1476
1477	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1478	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1479	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1480	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1481	{
1482	uint32_t cbSize;
1483
1484	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1485	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1486	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1487	if (rc == VINF_SUCCESS)
1488	{
1489	/* EIP has been updated already. */
1490
1491	/* Only resume if successful. */
1492	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1493	goto ResumeExecution;
1494	}
1495	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1496	break;
1497	}
1498
1499	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1500	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1501	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1502	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1503	{
1504	uint32_t cbSize;
1505
1506	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1507	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1508	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1509	if (rc == VINF_SUCCESS)
1510	{
1511	/* EIP has been updated already. */
1512
1513	/* Only resume if successful. */
1514	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1515	goto ResumeExecution;
1516	}
1517	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1518	break;
1519	}
1520
1521	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1522	case SVM_EXIT_IOIO: /* I/O instruction. */
1523	{
1524	SVM_IOIO_EXIT IoExitInfo;
1525	uint32_t uIOSize, uAndVal;
1526
1527	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1528
1529	/** @todo could use a lookup table here */
1530	if (IoExitInfo.n.u1OP8)
1531	{
1532	uIOSize = 1;
1533	uAndVal = 0xff;
1534	}
1535	else
1536	if (IoExitInfo.n.u1OP16)
1537	{
1538	uIOSize = 2;
1539	uAndVal = 0xffff;
1540	}
1541	else
1542	if (IoExitInfo.n.u1OP32)
1543	{
1544	uIOSize = 4;
1545	uAndVal = 0xffffffff;
1546	}
1547	else
1548	{
1549	AssertFailed(); /* should be fatal. */
1550	rc = VINF_EM_RAW_EMULATE_INSTR;
1551	break;
1552	}
1553
1554	if (IoExitInfo.n.u1STR)
1555	{
1556	/* ins/outs */
1557	uint32_t prefix = 0;
1558	if (IoExitInfo.n.u1REP)
1559	prefix \|= PREFIX_REP;
1560
1561	if (IoExitInfo.n.u1Type == 0)
1562	{
1563	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1564	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1565	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1566	}
1567	else
1568	{
1569	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1570	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1571	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1572	}
1573	}
1574	else
1575	{
1576	/* normal in/out */
1577	Assert(!IoExitInfo.n.u1REP);
1578
1579	if (IoExitInfo.n.u1Type == 0)
1580	{
1581	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1582	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1583	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1584	}
1585	else
1586	{
1587	uint32_t u32Val = 0;
1588
1589	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1590	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1591	if (IOM_SUCCESS(rc))
1592	{
1593	/* Write back to the EAX register. */
1594	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1595	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1596	}
1597	}
1598	}
1599	/*
1600	* Handled the I/O return codes.
1601	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1602	*/
1603	if (IOM_SUCCESS(rc))
1604	{
1605	/* Update EIP and continue execution. */
1606	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1607	if (RT_LIKELY(rc == VINF_SUCCESS))
1608	{
1609	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1610	goto ResumeExecution;
1611	}
1612	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1613	break;
1614	}
1615
1616	#ifdef VBOX_STRICT
1617	if (rc == VINF_IOM_HC_IOPORT_READ)
1618	Assert(IoExitInfo.n.u1Type != 0);
1619	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1620	Assert(IoExitInfo.n.u1Type == 0);
1621	else
1622	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1623	#endif
1624	Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1625	break;
1626	}
1627
1628	case SVM_EXIT_HLT:
1629	/** Check if external interrupts are pending; if so, don't switch back. */
1630	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1631	{
1632	pCtx->eip++; /* skip hlt */
1633	goto ResumeExecution;
1634	}
1635
1636	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1637	break;
1638
1639	case SVM_EXIT_RSM:
1640	case SVM_EXIT_INVLPGA:
1641	case SVM_EXIT_VMRUN:
1642	case SVM_EXIT_VMMCALL:
1643	case SVM_EXIT_VMLOAD:
1644	case SVM_EXIT_VMSAVE:
1645	case SVM_EXIT_STGI:
1646	case SVM_EXIT_CLGI:
1647	case SVM_EXIT_SKINIT:
1648	case SVM_EXIT_RDTSCP:
1649	{
1650	/* Unsupported instructions. */
1651	SVM_EVENT Event;
1652
1653	Event.au64[0] = 0;
1654	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1655	Event.n.u1Valid = 1;
1656	Event.n.u8Vector = X86_XCPT_UD;
1657
1658	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1659	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1660
1661	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1662	goto ResumeExecution;
1663	}
1664
1665	/* Emulate in ring 3. */
1666	case SVM_EXIT_MONITOR:
1667	case SVM_EXIT_RDPMC:
1668	case SVM_EXIT_PAUSE:
1669	case SVM_EXIT_MWAIT_UNCOND:
1670	case SVM_EXIT_MWAIT_ARMED:
1671	case SVM_EXIT_MSR:
1672	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1673	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1674	break;
1675
1676	case SVM_EXIT_SHUTDOWN:
1677	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1678	break;
1679
1680	case SVM_EXIT_IDTR_READ:
1681	case SVM_EXIT_GDTR_READ:
1682	case SVM_EXIT_LDTR_READ:
1683	case SVM_EXIT_TR_READ:
1684	case SVM_EXIT_IDTR_WRITE:
1685	case SVM_EXIT_GDTR_WRITE:
1686	case SVM_EXIT_LDTR_WRITE:
1687	case SVM_EXIT_TR_WRITE:
1688	case SVM_EXIT_CR0_SEL_WRITE:
1689	default:
1690	/* Unexpected exit codes. */
1691	rc = VERR_EM_INTERNAL_ERROR;
1692	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1693	break;
1694	}
1695
1696	end:
1697	if (fGuestStateSynced)
1698	{
1699	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1700	SVM_READ_SELREG(LDTR, ldtr);
1701	SVM_READ_SELREG(TR, tr);
1702
1703	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1704	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1705
1706	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1707	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1708
1709	/*
1710	* System MSRs
1711	*/
1712	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1713	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1714	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1715	}
1716
1717	/* Signal changes for the recompiler. */
1718	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1719
1720	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1721	if (exitCode == SVM_EXIT_INTR)
1722	{
1723	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1724	/* On the next entry we'll only sync the host context. */
1725	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1726	}
1727	else
1728	{
1729	/* On the next entry we'll sync everything. */
1730	/** @todo we can do better than this */
1731	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1732	}
1733
1734	/* translate into a less severe return code */
1735	if (rc == VERR_EM_INTERPRETER)
1736	rc = VINF_EM_RAW_EMULATE_INSTR;
1737
1738	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1739	return rc;
1740	}
1741
1742	/**
1743	* Enters the AMD-V session
1744	*
1745	* @returns VBox status code.
1746	* @param pVM The VM to operate on.
1747	* @param pCpu CPU info struct
1748	*/
1749	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1750	{
1751	Assert(pVM->hwaccm.s.svm.fSupported);
1752
1753	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1754	pVM->hwaccm.s.svm.fResumeVM = false;
1755
1756	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1757	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1758
1759	return VINF_SUCCESS;
1760	}
1761
1762
1763	/**
1764	* Leaves the AMD-V session
1765	*
1766	* @returns VBox status code.
1767	* @param pVM The VM to operate on.
1768	*/
1769	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1770	{
1771	Assert(pVM->hwaccm.s.svm.fSupported);
1772	return VINF_SUCCESS;
1773	}
1774
1775
1776	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1777	{
1778	OP_PARAMVAL param1;
1779	RTGCPTR addr;
1780
1781	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1782	if(VBOX_FAILURE(rc))
1783	return VERR_EM_INTERPRETER;
1784
1785	switch(param1.type)
1786	{
1787	case PARMTYPE_IMMEDIATE:
1788	case PARMTYPE_ADDRESS:
1789	if(!(param1.flags & PARAM_VAL32))
1790	return VERR_EM_INTERPRETER;
1791	addr = (RTGCPTR)param1.val.val32;
1792	break;
1793
1794	default:
1795	return VERR_EM_INTERPRETER;
1796	}
1797
1798	/** @todo is addr always a flat linear address or ds based
1799	* (in absence of segment override prefixes)????
1800	*/
1801	rc = PGMInvalidatePage(pVM, addr);
1802	if (VBOX_SUCCESS(rc))
1803	{
1804	/* Manually invalidate the page for the VM's TLB. */
1805	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1806	SVMInvlpgA(addr, uASID);
1807	return VINF_SUCCESS;
1808	}
1809	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1810	return rc;
1811	}
1812
1813	/**
1814	* Interprets INVLPG
1815	*
1816	* @returns VBox status code.
1817	* @retval VINF_* Scheduling instructions.
1818	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1819	* @retval VERR_* Fatal errors.
1820	*
1821	* @param pVM The VM handle.
1822	* @param pRegFrame The register frame.
1823	* @param ASID Tagged TLB id for the guest
1824	*
1825	* Updates the EIP if an instruction was executed successfully.
1826	*/
1827	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1828	{
1829	/*
1830	* Only allow 32-bit code.
1831	*/
1832	if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1833	{
1834	RTGCPTR pbCode;
1835	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1836	if (VBOX_SUCCESS(rc))
1837	{
1838	uint32_t cbOp;
1839	DISCPUSTATE Cpu;
1840
1841	Cpu.mode = CPUMODE_32BIT;
1842	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1843	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1844	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1845	{
1846	Assert(cbOp == Cpu.opsize);
1847	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1848	if (VBOX_SUCCESS(rc))
1849	{
1850	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1851	}
1852	return rc;
1853	}
1854	}
1855	}
1856	return VERR_EM_INTERPRETER;
1857	}
1858
1859
1860	/**
1861	* Invalidates a guest page
1862	*
1863	* @returns VBox status code.
1864	* @param pVM The VM to operate on.
1865	* @param GCVirt Page to invalidate
1866	*/
1867	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
1868	{
1869	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
1870
1871	/* Skip it if a TLB flush is already pending. */
1872	if (!fFlushPending)
1873	{
1874	SVM_VMCB *pVMCB;
1875
1876	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
1877	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1878	Assert(pVM->hwaccm.s.svm.fSupported);
1879
1880	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
1881	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
1882
1883	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
1884	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
1885	}
1886	return VINF_SUCCESS;
1887	}
1888

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 9062

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