VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 9074

Last change on this file since 9074 was 9074, checked in by vboxsync, 17 years ago

Log normal page faults in nested paging mode too (DEBUG only).
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1/* $Id: HWSVMR0.cpp 9074 2008-05-23 12:11:36Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include "HWSVMR0.h"
47
48static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50/**
51 * Sets up and activates AMD-V on the current CPU
52 *
53 * @returns VBox status code.
54 * @param pCpu CPU info struct
55 * @param pVM The VM to operate on.
56 * @param pvPageCpu Pointer to the global cpu page
57 * @param pPageCpuPhys Physical address of the global cpu page
58 */
59HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60{
61 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62 AssertReturn(pVM, VERR_INVALID_PARAMETER);
63 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67#ifdef LOG_ENABLED
68 SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69#endif
70
71 /* Turn on AMD-V in the EFER MSR. */
72 uint64_t val = ASMRdMsr(MSR_K6_EFER);
73 if (!(val & MSR_K6_EFER_SVME))
74 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
75
76 /* Write the physical page address where the CPU will store the host state while executing the VM. */
77 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79 pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80 pCpu->cTLBFlushes = 0;
81 return VINF_SUCCESS;
82}
83
84/**
85 * Deactivates AMD-V on the current CPU
86 *
87 * @returns VBox status code.
88 * @param pCpu CPU info struct
89 * @param pvPageCpu Pointer to the global cpu page
90 * @param pPageCpuPhys Physical address of the global cpu page
91 */
92HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93{
94 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97#ifdef LOG_ENABLED
98 SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99#endif
100
101 /* Turn off AMD-V in the EFER MSR. */
102 uint64_t val = ASMRdMsr(MSR_K6_EFER);
103 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105 /* Invalidate host state physical address. */
106 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107 pCpu->uCurrentASID = 0;
108
109 return VINF_SUCCESS;
110}
111
112/**
113 * Does Ring-0 per VM AMD-V init.
114 *
115 * @returns VBox status code.
116 * @param pVM The VM to operate on.
117 */
118HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119{
120 int rc;
121
122 /* Allocate one page for the VM control block (VMCB). */
123 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
124 if (RT_FAILURE(rc))
125 return rc;
126
127 pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
128 pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
129 ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
130
131 /* Allocate one page for the host context */
132 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
133 if (RT_FAILURE(rc))
134 return rc;
135
136 pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
137 pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
138 ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
139
140 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
141 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
142 if (RT_FAILURE(rc))
143 return rc;
144
145 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
146 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
147 /* Set all bits to intercept all IO accesses. */
148 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
149
150 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
151 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
152 if (RT_FAILURE(rc))
153 return rc;
154
155 pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
156 pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
157 /* Set all bits to intercept all MSR accesses. */
158 ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
159
160 /* Erratum 170 which requires a forced TLB flush for each world switch:
161 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
162 *
163 * All BH-G1/2 and DH-G1/2 models include a fix:
164 * Athlon X2: 0x6b 1/2
165 * 0x68 1/2
166 * Athlon 64: 0x7f 1
167 * 0x6f 2
168 * Sempron: 0x7f 1/2
169 * 0x6f 2
170 * 0x6c 2
171 * 0x7c 2
172 * Turion 64: 0x68 2
173 *
174 */
175 uint32_t u32Dummy;
176 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
177 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
178 u32BaseFamily= (u32Version >> 8) & 0xf;
179 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
180 u32Model = ((u32Version >> 4) & 0xf);
181 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
182 u32Stepping = u32Version & 0xf;
183 if ( u32Family == 0xf
184 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
185 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
186 {
187 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
188 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
189 }
190
191 /* Invalidate the last cpu we were running on. */
192 pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
193 return VINF_SUCCESS;
194}
195
196/**
197 * Does Ring-0 per VM AMD-V termination.
198 *
199 * @returns VBox status code.
200 * @param pVM The VM to operate on.
201 */
202HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
203{
204 if (pVM->hwaccm.s.svm.pMemObjVMCB)
205 {
206 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
207 pVM->hwaccm.s.svm.pVMCB = 0;
208 pVM->hwaccm.s.svm.pVMCBPhys = 0;
209 pVM->hwaccm.s.svm.pMemObjVMCB = 0;
210 }
211 if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
212 {
213 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
214 pVM->hwaccm.s.svm.pVMCBHost = 0;
215 pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
216 pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
217 }
218 if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
219 {
220 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
221 pVM->hwaccm.s.svm.pIOBitmap = 0;
222 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
223 pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
224 }
225 if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
226 {
227 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
228 pVM->hwaccm.s.svm.pMSRBitmap = 0;
229 pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
230 pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
231 }
232 return VINF_SUCCESS;
233}
234
235/**
236 * Sets up AMD-V for the specified VM
237 *
238 * @returns VBox status code.
239 * @param pVM The VM to operate on.
240 */
241HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
242{
243 int rc = VINF_SUCCESS;
244 SVM_VMCB *pVMCB;
245
246 AssertReturn(pVM, VERR_INVALID_PARAMETER);
247
248 Assert(pVM->hwaccm.s.svm.fSupported);
249
250 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
251 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
252
253 /* Program the control fields. Most of them never have to be changed again. */
254 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
255 /* Note: CR8 reads will refer to V_TPR, so no need to catch them. */
256 /** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
257 if (!pVM->hwaccm.s.fNestedPaging)
258 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
259 else
260 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
261
262 /*
263 * CR0/3/4 writes must be intercepted for obvious reasons.
264 */
265 if (!pVM->hwaccm.s.fNestedPaging)
266 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
267 else
268 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
269
270 /* Intercept all DRx reads and writes. */
271 pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
272 pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
273
274 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
275 * All breakpoints are automatically cleared when the VM exits.
276 */
277
278 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
279#ifndef DEBUG
280 if (pVM->hwaccm.s.fNestedPaging)
281 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14); /* no longer need to intercept #PF. */
282#endif
283
284 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
285 | SVM_CTRL1_INTERCEPT_VINTR
286 | SVM_CTRL1_INTERCEPT_NMI
287 | SVM_CTRL1_INTERCEPT_SMI
288 | SVM_CTRL1_INTERCEPT_INIT
289 | SVM_CTRL1_INTERCEPT_RDPMC
290 | SVM_CTRL1_INTERCEPT_CPUID
291 | SVM_CTRL1_INTERCEPT_RSM
292 | SVM_CTRL1_INTERCEPT_HLT
293 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
294 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
295 | SVM_CTRL1_INTERCEPT_INVLPG
296 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
297 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
298 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
299 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
300 ;
301 /* With nested paging we don't care about invlpg anymore. */
302 if (pVM->hwaccm.s.fNestedPaging)
303 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
304
305 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
306 | SVM_CTRL2_INTERCEPT_VMMCALL
307 | SVM_CTRL2_INTERCEPT_VMLOAD
308 | SVM_CTRL2_INTERCEPT_VMSAVE
309 | SVM_CTRL2_INTERCEPT_STGI
310 | SVM_CTRL2_INTERCEPT_CLGI
311 | SVM_CTRL2_INTERCEPT_SKINIT
312 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
313 | SVM_CTRL2_INTERCEPT_WBINVD
314 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
315 ;
316 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
317 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
318 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
319
320 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
321 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
322
323 /* Set IO and MSR bitmap addresses. */
324 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
325 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
326
327 /* No LBR virtualization. */
328 pVMCB->ctrl.u64LBRVirt = 0;
329
330 /** The ASID must start at 1; the host uses 0. */
331 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
332
333 return rc;
334}
335
336
337/**
338 * Injects an event (trap or external interrupt)
339 *
340 * @param pVM The VM to operate on.
341 * @param pVMCB SVM control block
342 * @param pCtx CPU Context
343 * @param pIntInfo SVM interrupt info
344 */
345inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
346{
347#ifdef VBOX_STRICT
348 if (pEvent->n.u8Vector == 0xE)
349 Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
350 else
351 if (pEvent->n.u8Vector < 0x20)
352 Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
353 else
354 {
355 Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
356 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
357 Assert(pCtx->eflags.u32 & X86_EFL_IF);
358 }
359#endif
360
361 /* Set event injection state. */
362 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
363}
364
365
366/**
367 * Checks for pending guest interrupts and injects them
368 *
369 * @returns VBox status code.
370 * @param pVM The VM to operate on.
371 * @param pVMCB SVM control block
372 * @param pCtx CPU Context
373 */
374static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
375{
376 int rc;
377
378 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
379 if (pVM->hwaccm.s.Event.fPending)
380 {
381 SVM_EVENT Event;
382
383 Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
384 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
385 Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
386 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
387
388 pVM->hwaccm.s.Event.fPending = false;
389 return VINF_SUCCESS;
390 }
391
392 /* When external interrupts are pending, we should exit the VM when IF is set. */
393 if ( !TRPMHasTrap(pVM)
394 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
395 {
396 if (!(pCtx->eflags.u32 & X86_EFL_IF))
397 {
398 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
399 {
400 Log(("Enable irq window exit!\n"));
401 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
402 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
403 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
404 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1; /* ignore the priority in the TPR; just deliver it */
405 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
406 }
407 }
408 else
409 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
410 {
411 uint8_t u8Interrupt;
412
413 rc = PDMGetInterrupt(pVM, &u8Interrupt);
414 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
415 if (VBOX_SUCCESS(rc))
416 {
417 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
418 AssertRC(rc);
419 }
420 else
421 {
422 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
423 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
424 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
425 /* Just continue */
426 }
427 }
428 else
429 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
430 }
431
432#ifdef VBOX_STRICT
433 if (TRPMHasTrap(pVM))
434 {
435 uint8_t u8Vector;
436 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
437 AssertRC(rc);
438 }
439#endif
440
441 if ( pCtx->eflags.u32 & X86_EFL_IF
442 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
443 && TRPMHasTrap(pVM)
444 )
445 {
446 uint8_t u8Vector;
447 int rc;
448 TRPMEVENT enmType;
449 SVM_EVENT Event;
450 uint32_t u32ErrorCode;
451
452 Event.au64[0] = 0;
453
454 /* If a new event is pending, then dispatch it now. */
455 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
456 AssertRC(rc);
457 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
458 Assert(enmType != TRPM_SOFTWARE_INT);
459
460 /* Clear the pending trap. */
461 rc = TRPMResetTrap(pVM);
462 AssertRC(rc);
463
464 Event.n.u8Vector = u8Vector;
465 Event.n.u1Valid = 1;
466 Event.n.u32ErrorCode = u32ErrorCode;
467
468 if (enmType == TRPM_TRAP)
469 {
470 switch (u8Vector) {
471 case 8:
472 case 10:
473 case 11:
474 case 12:
475 case 13:
476 case 14:
477 case 17:
478 /* Valid error codes. */
479 Event.n.u1ErrorCodeValid = 1;
480 break;
481 default:
482 break;
483 }
484 if (u8Vector == X86_XCPT_NMI)
485 Event.n.u3Type = SVM_EVENT_NMI;
486 else
487 Event.n.u3Type = SVM_EVENT_EXCEPTION;
488 }
489 else
490 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
491
492 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
493 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
494 } /* if (interrupts can be dispatched) */
495
496 return VINF_SUCCESS;
497}
498
499
500/**
501 * Loads the guest state
502 *
503 * @returns VBox status code.
504 * @param pVM The VM to operate on.
505 * @param pCtx Guest context
506 */
507HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
508{
509 RTGCUINTPTR val;
510 SVM_VMCB *pVMCB;
511
512 if (pVM == NULL)
513 return VERR_INVALID_PARAMETER;
514
515 /* Setup AMD SVM. */
516 Assert(pVM->hwaccm.s.svm.fSupported);
517
518 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
519 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
520
521 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
522 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
523 {
524 SVM_WRITE_SELREG(CS, cs);
525 SVM_WRITE_SELREG(SS, ss);
526 SVM_WRITE_SELREG(DS, ds);
527 SVM_WRITE_SELREG(ES, es);
528 SVM_WRITE_SELREG(FS, fs);
529 SVM_WRITE_SELREG(GS, gs);
530 }
531
532 /* Guest CPU context: LDTR. */
533 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
534 {
535 SVM_WRITE_SELREG(LDTR, ldtr);
536 }
537
538 /* Guest CPU context: TR. */
539 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
540 {
541 SVM_WRITE_SELREG(TR, tr);
542 }
543
544 /* Guest CPU context: GDTR. */
545 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
546 {
547 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
548 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
549 }
550
551 /* Guest CPU context: IDTR. */
552 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
553 {
554 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
555 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
556 }
557
558 /*
559 * Sysenter MSRs
560 */
561 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
562 {
563 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
564 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
565 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
566 }
567
568 /* Control registers */
569 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
570 {
571 val = pCtx->cr0;
572 if (CPUMIsGuestFPUStateActive(pVM) == false)
573 {
574 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
575 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
576 }
577 else
578 {
579 Assert(pVM->hwaccm.s.svm.fResumeVM == true);
580 /** @todo check if we support the old style mess correctly. */
581 if (!(val & X86_CR0_NE))
582 {
583 Log(("Forcing X86_CR0_NE!!!\n"));
584
585 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
586 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
587 {
588 pVMCB->ctrl.u32InterceptException |= RT_BIT(16);
589 pVM->hwaccm.s.fFPUOldStyleOverride = true;
590 }
591 }
592 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
593 }
594 /* Always enable caching. */
595 val &= ~(X86_CR0_CD|X86_CR0_NW);
596
597 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (host) physical level. */
598 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
599 if (!pVM->hwaccm.s.fNestedPaging)
600 {
601 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
602 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
603 }
604 pVMCB->guest.u64CR0 = val;
605 }
606 /* CR2 as well */
607 pVMCB->guest.u64CR2 = pCtx->cr2;
608
609 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
610 {
611 /* Save our shadow CR3 register. */
612 if (pVM->hwaccm.s.fNestedPaging)
613 {
614 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
615 pVMCB->guest.u64CR3 = pCtx->cr3;
616 }
617 else
618 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
619 }
620
621 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
622 {
623 val = pCtx->cr4;
624 if (!pVM->hwaccm.s.fNestedPaging)
625 {
626 switch(pVM->hwaccm.s.enmShadowMode)
627 {
628 case PGMMODE_REAL:
629 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
630 AssertFailed();
631 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
632
633 case PGMMODE_32_BIT: /* 32-bit paging. */
634 break;
635
636 case PGMMODE_PAE: /* PAE paging. */
637 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
638 /** @todo use normal 32 bits paging */
639 val |= X86_CR4_PAE;
640 break;
641
642 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
643 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
644 AssertFailed();
645 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
646
647 default: /* shut up gcc */
648 AssertFailed();
649 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
650 }
651 }
652 pVMCB->guest.u64CR4 = val;
653 }
654
655 /* Debug registers. */
656 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
657 {
658 /** @todo DR0-6 */
659 val = pCtx->dr7;
660 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
661 val |= 0x400; /* must be one */
662#ifdef VBOX_STRICT
663 val = 0x400;
664#endif
665 pVMCB->guest.u64DR7 = val;
666
667 pVMCB->guest.u64DR6 = pCtx->dr6;
668 }
669
670 /* EIP, ESP and EFLAGS */
671 pVMCB->guest.u64RIP = pCtx->eip;
672 pVMCB->guest.u64RSP = pCtx->esp;
673 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
674
675 /* Set CPL */
676 pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
677
678 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
679 pVMCB->guest.u64RAX = pCtx->eax;
680
681 /* vmrun will fail otherwise. */
682 pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
683
684 /** TSC offset. */
685 if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
686 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
687 else
688 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
689
690 /** @todo 64 bits stuff (?):
691 * - STAR
692 * - LSTAR
693 * - CSTAR
694 * - SFMASK
695 * - KernelGSBase
696 */
697
698#ifdef DEBUG
699 /* Intercept X86_XCPT_DB if stepping is enabled */
700 if (DBGFIsStepping(pVM))
701 pVMCB->ctrl.u32InterceptException |= RT_BIT(1);
702 else
703 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
704#endif
705
706 /* Done. */
707 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
708
709 return VINF_SUCCESS;
710}
711
712
713/**
714 * Runs guest code in an SVM VM.
715 *
716 * @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
717 *
718 * @returns VBox status code.
719 * @param pVM The VM to operate on.
720 * @param pCtx Guest context
721 * @param pCpu CPU info struct
722 */
723HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
724{
725 int rc = VINF_SUCCESS;
726 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
727 SVM_VMCB *pVMCB;
728 bool fGuestStateSynced = false;
729 unsigned cResume = 0;
730
731 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
732
733 AssertReturn(pCpu->fSVMConfigured, VERR_EM_INTERNAL_ERROR);
734
735 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
736 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
737
738 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
739 */
740ResumeExecution:
741 /* Safety precaution; looping for too long here can have a very bad effect on the host */
742 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
743 {
744 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
745 rc = VINF_EM_RAW_INTERRUPT;
746 goto end;
747 }
748
749 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
750 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
751 {
752 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
753 if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
754 {
755 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
756 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
757 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
758 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
759 */
760 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
761 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
762 pVMCB->ctrl.u64IntShadow = 0;
763 }
764 }
765 else
766 {
767 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
768 pVMCB->ctrl.u64IntShadow = 0;
769 }
770
771 /* Check for pending actions that force us to go back to ring 3. */
772#ifdef DEBUG
773 /* Intercept X86_XCPT_DB if stepping is enabled */
774 if (!DBGFIsStepping(pVM))
775#endif
776 {
777 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
778 {
779 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
780 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
781 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
782 rc = VINF_EM_RAW_TO_R3;
783 goto end;
784 }
785 }
786
787 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
788 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
789 {
790 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
791 rc = VINF_EM_PENDING_REQUEST;
792 goto end;
793 }
794
795 /* When external interrupts are pending, we should exit the VM when IF is set. */
796 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
797 rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
798 if (VBOX_FAILURE(rc))
799 {
800 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
801 goto end;
802 }
803
804 /* Load the guest state */
805 rc = SVMR0LoadGuestState(pVM, pCtx);
806 if (rc != VINF_SUCCESS)
807 {
808 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
809 goto end;
810 }
811 fGuestStateSynced = true;
812
813 /* All done! Let's start VM execution. */
814 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
815
816 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
817 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
818
819 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
820 if (!pVM->hwaccm.s.svm.fResumeVM)
821 {
822 if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
823 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
824 || pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
825 {
826 /* Force a TLB flush on VM entry. */
827 pVM->hwaccm.s.svm.fForceTLBFlush = true;
828 }
829 pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
830 }
831
832 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
833 if ( pVM->hwaccm.s.svm.fForceTLBFlush
834 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
835 {
836 if (++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID)
837 {
838 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
839 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
840 pCpu->cTLBFlushes++;
841 }
842 else
843 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
844
845 pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
846 }
847 else
848 {
849 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
850 if (!pCpu->uCurrentASID)
851 pCpu->uCurrentASID = 1;
852
853 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
854 }
855
856 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
857 pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
858
859#ifdef VBOX_WITH_STATISTICS
860 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
861 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
862 else
863 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
864#endif
865
866 /* In case we execute a goto ResumeExecution later on. */
867 pVM->hwaccm.s.svm.fResumeVM = true;
868 pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
869
870 Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
871 Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
872 | SVM_CTRL2_INTERCEPT_VMMCALL
873 | SVM_CTRL2_INTERCEPT_VMLOAD
874 | SVM_CTRL2_INTERCEPT_VMSAVE
875 | SVM_CTRL2_INTERCEPT_STGI
876 | SVM_CTRL2_INTERCEPT_CLGI
877 | SVM_CTRL2_INTERCEPT_SKINIT
878 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
879 | SVM_CTRL2_INTERCEPT_WBINVD
880 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
881 ));
882 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
883 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
884 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
885 Assert(pVMCB->ctrl.u64LBRVirt == 0);
886
887 SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
888 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
889
890 /**
891 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
892 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
893 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
894 */
895
896 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
897
898 /* Reason for the VM exit */
899 exitCode = pVMCB->ctrl.u64ExitCode;
900
901 if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
902 {
903 HWACCMDumpRegs(pCtx);
904#ifdef DEBUG
905 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
906 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
907 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
908 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
909 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
910 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
911 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
912 Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
913 Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
914 Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
915
916 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
917 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
918 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
919 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
920
921 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
922 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
923 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
924 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
925 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
926 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
927 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
928 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
929 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
930 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
931
932 Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
933 Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
934 Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
935 Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
936 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
937 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
938 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
939 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
940 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
941 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
942 Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
943 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
944 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
945 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
946 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
947 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
948 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
949
950 Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
951 Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
952
953 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
954 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
955 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
956 Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
957 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
958 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
959 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
960 Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
961 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
962 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
963 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
964 Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
965 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
966 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
967 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
968 Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
969 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
970 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
971 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
972 Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
973
974 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
975 Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
976
977 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
978 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
979 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
980 Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
981
982 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
983 Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
984
985 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
986 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
987 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
988 Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
989
990 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
991 Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
992 Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
993 Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
994 Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
995 Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
996 Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
997
998 Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
999 Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1000 Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1001 Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1002
1003 Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1004 Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1005 Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1006
1007 Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1008 Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1009 Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1010 Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1011 Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1012 Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1013 Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1014 Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1015 Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1016 Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1017 Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1018 Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1019
1020#endif
1021 rc = VERR_SVM_UNABLE_TO_START_VM;
1022 goto end;
1023 }
1024
1025 /* Let's first sync back eip, esp, and eflags. */
1026 pCtx->eip = pVMCB->guest.u64RIP;
1027 pCtx->esp = pVMCB->guest.u64RSP;
1028 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1029 /* eax is saved/restore across the vmrun instruction */
1030 pCtx->eax = pVMCB->guest.u64RAX;
1031
1032 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1033 SVM_READ_SELREG(SS, ss);
1034 SVM_READ_SELREG(CS, cs);
1035 SVM_READ_SELREG(DS, ds);
1036 SVM_READ_SELREG(ES, es);
1037 SVM_READ_SELREG(FS, fs);
1038 SVM_READ_SELREG(GS, gs);
1039
1040 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1041 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1042 if (pVM->hwaccm.s.fNestedPaging)
1043 {
1044 CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1045 PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1046 }
1047
1048 /** @note NOW IT'S SAFE FOR LOGGING! */
1049
1050 /* Take care of instruction fusing (sti, mov ss) */
1051 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1052 {
1053 Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
1054 EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1055 }
1056 else
1057 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1058
1059 Log2(("exitCode = %x\n", exitCode));
1060
1061 /* Sync back the debug registers. */
1062 /** @todo Implement debug registers correctly. */
1063 pCtx->dr6 = pVMCB->guest.u64DR6;
1064 pCtx->dr7 = pVMCB->guest.u64DR7;
1065
1066 /* Check if an injected event was interrupted prematurely. */
1067 pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1068 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1069 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1070 {
1071 Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
1072 pVM->hwaccm.s.Event.fPending = true;
1073 /* Error code present? (redundant) */
1074 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1075 {
1076 pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1077 }
1078 else
1079 pVM->hwaccm.s.Event.errCode = 0;
1080 }
1081#ifdef VBOX_WITH_STATISTICS
1082 if (exitCode == SVM_EXIT_NPF)
1083 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1084 else
1085 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1086#endif
1087
1088 /* Deal with the reason of the VM-exit. */
1089 switch (exitCode)
1090 {
1091 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1092 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1093 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1094 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1095 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1096 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1097 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1098 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1099 {
1100 /* Pending trap. */
1101 SVM_EVENT Event;
1102 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1103
1104 Log2(("Hardware/software interrupt %d\n", vector));
1105 switch (vector)
1106 {
1107#ifdef DEBUG
1108 case X86_XCPT_DB:
1109 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1110 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1111 break;
1112#endif
1113
1114 case X86_XCPT_NM:
1115 {
1116 uint32_t oldCR0;
1117
1118 Log(("#NM fault at %VGv\n", pCtx->eip));
1119
1120 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1121 oldCR0 = ASMGetCR0();
1122 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1123 rc = CPUMHandleLazyFPU(pVM);
1124 if (rc == VINF_SUCCESS)
1125 {
1126 Assert(CPUMIsGuestFPUStateActive(pVM));
1127
1128 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
1129 ASMSetCR0(oldCR0);
1130
1131 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1132
1133 /* Continue execution. */
1134 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1135 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1136
1137 goto ResumeExecution;
1138 }
1139
1140 Log(("Forward #NM fault to the guest\n"));
1141 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1142
1143 Event.au64[0] = 0;
1144 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1145 Event.n.u1Valid = 1;
1146 Event.n.u8Vector = X86_XCPT_NM;
1147
1148 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1149 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1150 goto ResumeExecution;
1151 }
1152
1153 case X86_XCPT_PF: /* Page fault */
1154 {
1155 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1156 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1157
1158#ifdef DEBUG
1159 if (pVM->hwaccm.s.fNestedPaging)
1160 { /* A genuine pagefault.
1161 * Forward the trap to the guest by injecting the exception and resuming execution.
1162 */
1163 Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1164 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1165
1166 TRPMResetTrap(pVM);
1167
1168 /* Now we must update CR2. */
1169 pCtx->cr2 = uFaultAddress;
1170
1171 Event.au64[0] = 0;
1172 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1173 Event.n.u1Valid = 1;
1174 Event.n.u8Vector = X86_XCPT_PF;
1175 Event.n.u1ErrorCodeValid = 1;
1176 Event.n.u32ErrorCode = errCode;
1177
1178 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1179
1180 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1181 goto ResumeExecution;
1182 }
1183#endif
1184 Assert(!pVM->hwaccm.s.fNestedPaging);
1185
1186 Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1187 /* Exit qualification contains the linear address of the page fault. */
1188 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1189 TRPMSetErrorCode(pVM, errCode);
1190 TRPMSetFaultAddress(pVM, uFaultAddress);
1191
1192 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1193 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1194 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1195 if (rc == VINF_SUCCESS)
1196 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1197 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1198 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1199
1200 TRPMResetTrap(pVM);
1201
1202 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1203 goto ResumeExecution;
1204 }
1205 else
1206 if (rc == VINF_EM_RAW_GUEST_TRAP)
1207 { /* A genuine pagefault.
1208 * Forward the trap to the guest by injecting the exception and resuming execution.
1209 */
1210 Log2(("Forward page fault to the guest\n"));
1211 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1212 /* The error code might have been changed. */
1213 errCode = TRPMGetErrorCode(pVM);
1214
1215 TRPMResetTrap(pVM);
1216
1217 /* Now we must update CR2. */
1218 pCtx->cr2 = uFaultAddress;
1219
1220 Event.au64[0] = 0;
1221 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1222 Event.n.u1Valid = 1;
1223 Event.n.u8Vector = X86_XCPT_PF;
1224 Event.n.u1ErrorCodeValid = 1;
1225 Event.n.u32ErrorCode = errCode;
1226
1227 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1228
1229 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1230 goto ResumeExecution;
1231 }
1232#ifdef VBOX_STRICT
1233 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1234 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1235#endif
1236 /* Need to go back to the recompiler to emulate the instruction. */
1237 TRPMResetTrap(pVM);
1238 break;
1239 }
1240
1241 case X86_XCPT_MF: /* Floating point exception. */
1242 {
1243 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1244 if (!(pCtx->cr0 & X86_CR0_NE))
1245 {
1246 /* old style FPU error reporting needs some extra work. */
1247 /** @todo don't fall back to the recompiler, but do it manually. */
1248 rc = VINF_EM_RAW_EMULATE_INSTR;
1249 break;
1250 }
1251 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1252
1253 Event.au64[0] = 0;
1254 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1255 Event.n.u1Valid = 1;
1256 Event.n.u8Vector = X86_XCPT_MF;
1257
1258 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1259
1260 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1261 goto ResumeExecution;
1262 }
1263
1264#ifdef VBOX_STRICT
1265 case X86_XCPT_GP: /* General protection failure exception.*/
1266 case X86_XCPT_UD: /* Unknown opcode exception. */
1267 case X86_XCPT_DE: /* Debug exception. */
1268 case X86_XCPT_SS: /* Stack segment exception. */
1269 case X86_XCPT_NP: /* Segment not present exception. */
1270 {
1271 Event.au64[0] = 0;
1272 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1273 Event.n.u1Valid = 1;
1274 Event.n.u8Vector = vector;
1275
1276 switch(vector)
1277 {
1278 case X86_XCPT_GP:
1279 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1280 Event.n.u1ErrorCodeValid = 1;
1281 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1282 break;
1283 case X86_XCPT_DE:
1284 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1285 break;
1286 case X86_XCPT_UD:
1287 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1288 break;
1289 case X86_XCPT_SS:
1290 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1291 Event.n.u1ErrorCodeValid = 1;
1292 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1293 break;
1294 case X86_XCPT_NP:
1295 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1296 Event.n.u1ErrorCodeValid = 1;
1297 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1298 break;
1299 }
1300 Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->eip, pCtx->esi));
1301 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1302
1303 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1304 goto ResumeExecution;
1305 }
1306#endif
1307 default:
1308 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1309 rc = VERR_EM_INTERNAL_ERROR;
1310 break;
1311
1312 } /* switch (vector) */
1313 break;
1314 }
1315
1316 case SVM_EXIT_NPF:
1317 {
1318 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1319 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1320 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1321
1322 Assert(pVM->hwaccm.s.fNestedPaging);
1323
1324 Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->eip, uFaultAddress, errCode));
1325 /* Exit qualification contains the linear address of the page fault. */
1326 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1327 TRPMSetErrorCode(pVM, errCode);
1328 TRPMSetFaultAddress(pVM, uFaultAddress);
1329
1330 /* Handle the pagefault trap for the nested shadow table. */
1331 rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1332 Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->eip, rc));
1333 if (rc == VINF_SUCCESS)
1334 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1335 Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->eip, uFaultAddress, errCode));
1336 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1337
1338 TRPMResetTrap(pVM);
1339
1340 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1341 goto ResumeExecution;
1342 }
1343
1344#ifdef VBOX_STRICT
1345 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1346 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1347#endif
1348 /* Need to go back to the recompiler to emulate the instruction. */
1349 TRPMResetTrap(pVM);
1350 break;
1351 }
1352
1353 case SVM_EXIT_VINTR:
1354 /* A virtual interrupt is about to be delivered, which means IF=1. */
1355 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1356 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1357 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 0;
1358 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1359 goto ResumeExecution;
1360
1361 case SVM_EXIT_FERR_FREEZE:
1362 case SVM_EXIT_INTR:
1363 case SVM_EXIT_NMI:
1364 case SVM_EXIT_SMI:
1365 case SVM_EXIT_INIT:
1366 /* External interrupt; leave to allow it to be dispatched again. */
1367 rc = VINF_EM_RAW_INTERRUPT;
1368 break;
1369
1370 case SVM_EXIT_WBINVD:
1371 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1372 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1373 /* Skip instruction and continue directly. */
1374 pCtx->eip += 2; /** @note hardcoded opcode size! */
1375 /* Continue execution.*/
1376 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1377 goto ResumeExecution;
1378
1379 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1380 {
1381 Log2(("SVM: Cpuid %x\n", pCtx->eax));
1382 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1383 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1384 if (rc == VINF_SUCCESS)
1385 {
1386 /* Update EIP and continue execution. */
1387 pCtx->eip += 2; /** @note hardcoded opcode size! */
1388 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1389 goto ResumeExecution;
1390 }
1391 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1392 rc = VINF_EM_RAW_EMULATE_INSTR;
1393 break;
1394 }
1395
1396 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1397 {
1398 Log2(("SVM: Rdtsc\n"));
1399 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1400 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1401 if (rc == VINF_SUCCESS)
1402 {
1403 /* Update EIP and continue execution. */
1404 pCtx->eip += 2; /** @note hardcoded opcode size! */
1405 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1406 goto ResumeExecution;
1407 }
1408 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1409 rc = VINF_EM_RAW_EMULATE_INSTR;
1410 break;
1411 }
1412
1413 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1414 {
1415 Log2(("SVM: invlpg\n"));
1416 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1417
1418 Assert(!pVM->hwaccm.s.fNestedPaging);
1419
1420 /* Truly a pita. Why can't SVM give the same information as VMX? */
1421 rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1422 if (rc == VINF_SUCCESS)
1423 {
1424 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1425 goto ResumeExecution; /* eip already updated */
1426 }
1427 break;
1428 }
1429
1430 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1431 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1432 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1433 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1434 {
1435 uint32_t cbSize;
1436
1437 Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1438 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1439 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1440
1441 switch (exitCode - SVM_EXIT_WRITE_CR0)
1442 {
1443 case 0:
1444 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1445 break;
1446 case 2:
1447 break;
1448 case 3:
1449 Assert(!pVM->hwaccm.s.fNestedPaging);
1450 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1451 break;
1452 case 4:
1453 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1454 break;
1455 default:
1456 AssertFailed();
1457 }
1458 /* Check if a sync operation is pending. */
1459 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1460 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1461 {
1462 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1463 AssertRC(rc);
1464
1465 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1466
1467 /** @note Force a TLB flush. SVM requires us to do it manually. */
1468 pVM->hwaccm.s.svm.fForceTLBFlush = true;
1469 }
1470 if (rc == VINF_SUCCESS)
1471 {
1472 /* EIP has been updated already. */
1473
1474 /* Only resume if successful. */
1475 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1476 goto ResumeExecution;
1477 }
1478 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1479 break;
1480 }
1481
1482 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1483 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1484 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1485 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1486 {
1487 uint32_t cbSize;
1488
1489 Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1490 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1491 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1492 if (rc == VINF_SUCCESS)
1493 {
1494 /* EIP has been updated already. */
1495
1496 /* Only resume if successful. */
1497 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1498 goto ResumeExecution;
1499 }
1500 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1501 break;
1502 }
1503
1504 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1505 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1506 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1507 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1508 {
1509 uint32_t cbSize;
1510
1511 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1512 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1513 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1514 if (rc == VINF_SUCCESS)
1515 {
1516 /* EIP has been updated already. */
1517
1518 /* Only resume if successful. */
1519 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1520 goto ResumeExecution;
1521 }
1522 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1523 break;
1524 }
1525
1526 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1527 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1528 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1529 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1530 {
1531 uint32_t cbSize;
1532
1533 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1534 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1535 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1536 if (rc == VINF_SUCCESS)
1537 {
1538 /* EIP has been updated already. */
1539
1540 /* Only resume if successful. */
1541 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1542 goto ResumeExecution;
1543 }
1544 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1545 break;
1546 }
1547
1548 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1549 case SVM_EXIT_IOIO: /* I/O instruction. */
1550 {
1551 SVM_IOIO_EXIT IoExitInfo;
1552 uint32_t uIOSize, uAndVal;
1553
1554 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1555
1556 /** @todo could use a lookup table here */
1557 if (IoExitInfo.n.u1OP8)
1558 {
1559 uIOSize = 1;
1560 uAndVal = 0xff;
1561 }
1562 else
1563 if (IoExitInfo.n.u1OP16)
1564 {
1565 uIOSize = 2;
1566 uAndVal = 0xffff;
1567 }
1568 else
1569 if (IoExitInfo.n.u1OP32)
1570 {
1571 uIOSize = 4;
1572 uAndVal = 0xffffffff;
1573 }
1574 else
1575 {
1576 AssertFailed(); /* should be fatal. */
1577 rc = VINF_EM_RAW_EMULATE_INSTR;
1578 break;
1579 }
1580
1581 if (IoExitInfo.n.u1STR)
1582 {
1583 /* ins/outs */
1584 uint32_t prefix = 0;
1585 if (IoExitInfo.n.u1REP)
1586 prefix |= PREFIX_REP;
1587
1588 if (IoExitInfo.n.u1Type == 0)
1589 {
1590 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1591 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1592 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1593 }
1594 else
1595 {
1596 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1597 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1598 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1599 }
1600 }
1601 else
1602 {
1603 /* normal in/out */
1604 Assert(!IoExitInfo.n.u1REP);
1605
1606 if (IoExitInfo.n.u1Type == 0)
1607 {
1608 Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1609 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1610 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1611 }
1612 else
1613 {
1614 uint32_t u32Val = 0;
1615
1616 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1617 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1618 if (IOM_SUCCESS(rc))
1619 {
1620 /* Write back to the EAX register. */
1621 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1622 Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1623 }
1624 }
1625 }
1626 /*
1627 * Handled the I/O return codes.
1628 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1629 */
1630 if (IOM_SUCCESS(rc))
1631 {
1632 /* Update EIP and continue execution. */
1633 pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1634 if (RT_LIKELY(rc == VINF_SUCCESS))
1635 {
1636 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1637 goto ResumeExecution;
1638 }
1639 Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1640 break;
1641 }
1642
1643#ifdef VBOX_STRICT
1644 if (rc == VINF_IOM_HC_IOPORT_READ)
1645 Assert(IoExitInfo.n.u1Type != 0);
1646 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1647 Assert(IoExitInfo.n.u1Type == 0);
1648 else
1649 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1650#endif
1651 Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1652 break;
1653 }
1654
1655 case SVM_EXIT_HLT:
1656 /** Check if external interrupts are pending; if so, don't switch back. */
1657 if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
1658 {
1659 pCtx->eip++; /* skip hlt */
1660 goto ResumeExecution;
1661 }
1662
1663 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1664 break;
1665
1666 case SVM_EXIT_RSM:
1667 case SVM_EXIT_INVLPGA:
1668 case SVM_EXIT_VMRUN:
1669 case SVM_EXIT_VMMCALL:
1670 case SVM_EXIT_VMLOAD:
1671 case SVM_EXIT_VMSAVE:
1672 case SVM_EXIT_STGI:
1673 case SVM_EXIT_CLGI:
1674 case SVM_EXIT_SKINIT:
1675 case SVM_EXIT_RDTSCP:
1676 {
1677 /* Unsupported instructions. */
1678 SVM_EVENT Event;
1679
1680 Event.au64[0] = 0;
1681 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1682 Event.n.u1Valid = 1;
1683 Event.n.u8Vector = X86_XCPT_UD;
1684
1685 Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1686 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1687
1688 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1689 goto ResumeExecution;
1690 }
1691
1692 /* Emulate in ring 3. */
1693 case SVM_EXIT_MONITOR:
1694 case SVM_EXIT_RDPMC:
1695 case SVM_EXIT_PAUSE:
1696 case SVM_EXIT_MWAIT_UNCOND:
1697 case SVM_EXIT_MWAIT_ARMED:
1698 case SVM_EXIT_MSR:
1699 case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1700 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1701 break;
1702
1703 case SVM_EXIT_SHUTDOWN:
1704 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1705 break;
1706
1707 case SVM_EXIT_IDTR_READ:
1708 case SVM_EXIT_GDTR_READ:
1709 case SVM_EXIT_LDTR_READ:
1710 case SVM_EXIT_TR_READ:
1711 case SVM_EXIT_IDTR_WRITE:
1712 case SVM_EXIT_GDTR_WRITE:
1713 case SVM_EXIT_LDTR_WRITE:
1714 case SVM_EXIT_TR_WRITE:
1715 case SVM_EXIT_CR0_SEL_WRITE:
1716 default:
1717 /* Unexpected exit codes. */
1718 rc = VERR_EM_INTERNAL_ERROR;
1719 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1720 break;
1721 }
1722
1723end:
1724 if (fGuestStateSynced)
1725 {
1726 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1727 SVM_READ_SELREG(LDTR, ldtr);
1728 SVM_READ_SELREG(TR, tr);
1729
1730 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1731 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1732
1733 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1734 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1735
1736 /*
1737 * System MSRs
1738 */
1739 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1740 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1741 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1742 }
1743
1744 /* Signal changes for the recompiler. */
1745 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
1746
1747 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1748 if (exitCode == SVM_EXIT_INTR)
1749 {
1750 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1751 /* On the next entry we'll only sync the host context. */
1752 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
1753 }
1754 else
1755 {
1756 /* On the next entry we'll sync everything. */
1757 /** @todo we can do better than this */
1758 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
1759 }
1760
1761 /* translate into a less severe return code */
1762 if (rc == VERR_EM_INTERPRETER)
1763 rc = VINF_EM_RAW_EMULATE_INSTR;
1764
1765 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1766 return rc;
1767}
1768
1769/**
1770 * Enters the AMD-V session
1771 *
1772 * @returns VBox status code.
1773 * @param pVM The VM to operate on.
1774 * @param pCpu CPU info struct
1775 */
1776HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1777{
1778 Assert(pVM->hwaccm.s.svm.fSupported);
1779
1780 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1781 pVM->hwaccm.s.svm.fResumeVM = false;
1782
1783 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1784 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
1785
1786 return VINF_SUCCESS;
1787}
1788
1789
1790/**
1791 * Leaves the AMD-V session
1792 *
1793 * @returns VBox status code.
1794 * @param pVM The VM to operate on.
1795 */
1796HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1797{
1798 Assert(pVM->hwaccm.s.svm.fSupported);
1799 return VINF_SUCCESS;
1800}
1801
1802
1803static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1804{
1805 OP_PARAMVAL param1;
1806 RTGCPTR addr;
1807
1808 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1809 if(VBOX_FAILURE(rc))
1810 return VERR_EM_INTERPRETER;
1811
1812 switch(param1.type)
1813 {
1814 case PARMTYPE_IMMEDIATE:
1815 case PARMTYPE_ADDRESS:
1816 if(!(param1.flags & PARAM_VAL32))
1817 return VERR_EM_INTERPRETER;
1818 addr = (RTGCPTR)param1.val.val32;
1819 break;
1820
1821 default:
1822 return VERR_EM_INTERPRETER;
1823 }
1824
1825 /** @todo is addr always a flat linear address or ds based
1826 * (in absence of segment override prefixes)????
1827 */
1828 rc = PGMInvalidatePage(pVM, addr);
1829 if (VBOX_SUCCESS(rc))
1830 {
1831 /* Manually invalidate the page for the VM's TLB. */
1832 Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1833 SVMInvlpgA(addr, uASID);
1834 return VINF_SUCCESS;
1835 }
1836 Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1837 return rc;
1838}
1839
1840/**
1841 * Interprets INVLPG
1842 *
1843 * @returns VBox status code.
1844 * @retval VINF_* Scheduling instructions.
1845 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1846 * @retval VERR_* Fatal errors.
1847 *
1848 * @param pVM The VM handle.
1849 * @param pRegFrame The register frame.
1850 * @param ASID Tagged TLB id for the guest
1851 *
1852 * Updates the EIP if an instruction was executed successfully.
1853 */
1854static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1855{
1856 /*
1857 * Only allow 32-bit code.
1858 */
1859 if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1860 {
1861 RTGCPTR pbCode;
1862 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1863 if (VBOX_SUCCESS(rc))
1864 {
1865 uint32_t cbOp;
1866 DISCPUSTATE Cpu;
1867
1868 Cpu.mode = CPUMODE_32BIT;
1869 rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1870 Assert(VBOX_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);
1871 if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1872 {
1873 Assert(cbOp == Cpu.opsize);
1874 rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1875 if (VBOX_SUCCESS(rc))
1876 {
1877 pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1878 }
1879 return rc;
1880 }
1881 }
1882 }
1883 return VERR_EM_INTERPRETER;
1884}
1885
1886
1887/**
1888 * Invalidates a guest page
1889 *
1890 * @returns VBox status code.
1891 * @param pVM The VM to operate on.
1892 * @param GCVirt Page to invalidate
1893 */
1894HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
1895{
1896 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | pVM->hwaccm.s.svm.fForceTLBFlush;
1897
1898 /* Skip it if a TLB flush is already pending. */
1899 if (!fFlushPending)
1900 {
1901 SVM_VMCB *pVMCB;
1902
1903 Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
1904 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1905 Assert(pVM->hwaccm.s.svm.fSupported);
1906
1907 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
1908 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
1909
1910 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
1911 SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
1912 }
1913 return VINF_SUCCESS;
1914}
1915
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