VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.h@ 42046

Last change on this file since 42046 was 41906, checked in by vboxsync, 12 years ago

CPUM: Combined the visible and hidden selector register data into one structure. Preparing for lazily resolving+caching of hidden registers in raw-mode.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 7.2 KB
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1/* $Id: HWSVMR0.h 41906 2012-06-24 15:44:03Z vboxsync $ */
2/** @file
3 * HM SVM (AMD-V) - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___VMMR0_HWSVMR0_h
19#define ___VMMR0_HWSVMR0_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hwaccm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/hwacc_svm.h>
29
30RT_C_DECLS_BEGIN
31
32/** @defgroup grp_svm_int Internal
33 * @ingroup grp_svm
34 * @internal
35 * @{
36 */
37
38#ifdef IN_RING0
39
40/**
41 * Enters the AMD-V session
42 *
43 * @returns VBox status code.
44 * @param pVM Pointer to the VM.
45 * @param pVCpu Pointer to the VMCPU.
46 * @param pCpu Pointer to the CPU info struct.
47 */
48VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu);
49
50/**
51 * Leaves the AMD-V session
52 *
53 * @returns VBox status code.
54 * @param pVM Pointer to the VM.
55 * @param pVCpu Pointer to the VMCPU.
56 * @param pCtx Pointer to the guest CPU context.
57 */
58VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
59
60/**
61 * Sets up and activates AMD-V on the current CPU
62 *
63 * @returns VBox status code.
64 * @param pCpu Pointer to the CPU info struct.
65 * @param pVM Pointer to the VM (can be NULL after a resume!).
66 * @param pvPageCpu Pointer to the global CPU page.
67 * @param pPageCpuPhys Physical address of the global CPU page.
68 */
69VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS HCPhysCpuPage);
70
71/**
72 * Deactivates AMD-V on the current CPU
73 *
74 * @returns VBox status code.
75 * @param pCpu Pointer to the CPU info struct.
76 * @param pvPageCpu Pointer to the global CPU page.
77 * @param pPageCpuPhys Physical address of the global CPU page.
78 */
79VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
80
81/**
82 * Does Ring-0 per VM AMD-V init.
83 *
84 * @returns VBox status code.
85 * @param pVM Pointer to the VM.
86 */
87VMMR0DECL(int) SVMR0InitVM(PVM pVM);
88
89/**
90 * Does Ring-0 per VM AMD-V termination.
91 *
92 * @returns VBox status code.
93 * @param pVM Pointer to the VM.
94 */
95VMMR0DECL(int) SVMR0TermVM(PVM pVM);
96
97/**
98 * Sets up AMD-V for the specified VM
99 *
100 * @returns VBox status code.
101 * @param pVM Pointer to the VM.
102 */
103VMMR0DECL(int) SVMR0SetupVM(PVM pVM);
104
105
106/**
107 * Runs guest code in an AMD-V VM.
108 *
109 * @returns VBox status code.
110 * @param pVM Pointer to the VM.
111 * @param pVCpu Pointer to the VMCPU.
112 * @param pCtx Pointer to the guest CPU context.
113 */
114VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
115
116
117/**
118 * Save the host state.
119 *
120 * @returns VBox status code.
121 * @param pVM Pointer to the VM.
122 * @param pVCpu Pointer to the VMCPU.
123 */
124VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu);
125
126/**
127 * Loads the guest state.
128 *
129 * @returns VBox status code.
130 * @param pVM Pointer to the VM.
131 * @param pVCpu Pointer to the VMCPU.
132 * @param pCtx Pointer to the guest CPU context.
133 */
134VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
135
136
137#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
138/**
139 * Prepares for and executes VMRUN (64-bit guests from a 32-bit host).
140 *
141 * @returns VBox status code.
142 * @param pVMCBHostPhys Physical address of host VMCB.
143 * @param pVMCBPhys Physical address of the VMCB.
144 * @param pCtx Pointer to the guest CPU context.
145 * @param pVM Pointer to the VM.
146 * @param pVCpu Pointer to the VMCPU. (not used)
147 */
148DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
149
150/**
151 * Executes the specified handler in 64-bit mode.
152 *
153 * @returns VBox status code.
154 * @param pVM Pointer to the VM.
155 * @param pVCpu Pointer to the VMCPU.
156 * @param pCtx Pointer to the guest CPU context.
157 * @param pfnHandler Pointer to the RC handler function.
158 * @param cbParam Number of parameters.
159 * @param paParam Array of 32-bit parameters.
160 */
161VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam,
162 uint32_t *paParam);
163#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
164
165/**
166 * Prepares for and executes VMRUN (32-bit guests).
167 *
168 * @returns VBox status code.
169 * @param pVMCBHostPhys Physical address of host VMCB.
170 * @param pVMCBPhys Physical address of the VMCB.
171 * @param pCtx Pointer to the guest CPU context.
172 * @param pVM Pointer to the VM. (not used)
173 * @param pVCpu Pointer to the VMCPU. (not used)
174 */
175DECLASM(int) SVMR0VMRun(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
176
177
178/**
179 * Prepares for and executes VMRUN (64-bit guests).
180 *
181 * @returns VBox status code.
182 * @param pVMCBHostPhys Physical address of host VMCB.
183 * @param pVMCBPhys Physical address of the VMCB.
184 * @param pCtx Pointer to the guest CPU context.
185 * @param pVM Pointer to the VM. (not used)
186 * @param pVCpu Pointer to the VMCPU. (not used)
187 */
188DECLASM(int) SVMR0VMRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
189
190/**
191 * Executes INVLPGA.
192 *
193 * @param pPageGC Virtual page to invalidate.
194 * @param u32ASID Tagged TLB id.
195 */
196DECLASM(void) SVMR0InvlpgA(RTGCPTR pPageGC, uint32_t u32ASID);
197
198/** Convert hidden selector attribute word between VMX and SVM formats. */
199#define SVM_HIDSEGATTR_VMX2SVM(a) (a & 0xFF) | ((a & 0xF000) >> 4)
200#define SVM_HIDSEGATTR_SVM2VMX(a) (a & 0xFF) | ((a & 0x0F00) << 4)
201
202#define SVM_WRITE_SELREG(REG, reg) \
203 do \
204 { \
205 Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
206 Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
207 pVMCB->guest.REG.u16Sel = pCtx->reg.Sel; \
208 pVMCB->guest.REG.u32Limit = pCtx->reg.u32Limit; \
209 pVMCB->guest.REG.u64Base = pCtx->reg.u64Base; \
210 pVMCB->guest.REG.u16Attr = SVM_HIDSEGATTR_VMX2SVM(pCtx->reg.Attr.u); \
211 } while (0)
212
213#define SVM_READ_SELREG(REG, reg) \
214 do \
215 { \
216 pCtx->reg.Sel = pVMCB->guest.REG.u16Sel; \
217 pCtx->reg.ValidSel = pVMCB->guest.REG.u16Sel; \
218 pCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
219 pCtx->reg.u32Limit = pVMCB->guest.REG.u32Limit; \
220 pCtx->reg.u64Base = pVMCB->guest.REG.u64Base; \
221 pCtx->reg.Attr.u = SVM_HIDSEGATTR_SVM2VMX(pVMCB->guest.REG.u16Attr); \
222 } while (0)
223
224#endif /* IN_RING0 */
225
226/** @} */
227
228RT_C_DECLS_END
229
230#endif /* !___VMMR0_HWSVMR0_h */
231
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