VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 13263

Last change on this file since 13263 was 13263, checked in by vboxsync, 16 years ago

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1/* $Id: HWVMXR0.cpp 13263 2008-10-14 13:22:36Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43/*******************************************************************************
44* Global Variables *
45*******************************************************************************/
46/* IO operation lookup arrays. */
47static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
48static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
49
50/*******************************************************************************
51* Local Functions *
52*******************************************************************************/
53#ifdef VBOX_STRICT
54static void VMXR0ReportWorldSwitchError(PVM pVM, int rc, PCPUMCTX pCtx);
55#else
56#define VMXR0ReportWorldSwitchError(a, b, c) do { } while (0);
57#endif /* VBOX_STRICT */
58static void vmxR0SetupTLBEPT(PVM pVM);
59static void vmxR0SetupTLBVPID(PVM pVM);
60static void vmxR0SetupTLBDummy(PVM pVM);
61static void vmxR0FlushEPT(PVM pVM, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
62static void vmxR0FlushVPID(PVM pVM, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
63
64
65static void VMXR0CheckError(PVM pVM, int rc)
66{
67 if (rc == VERR_VMX_GENERIC)
68 {
69 RTCCUINTREG instrError;
70
71 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
72 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
73 }
74 pVM->hwaccm.s.lLastError = rc;
75}
76
77/**
78 * Sets up and activates VT-x on the current CPU
79 *
80 * @returns VBox status code.
81 * @param pCpu CPU info struct
82 * @param pVM The VM to operate on.
83 * @param pvPageCpu Pointer to the global cpu page
84 * @param pPageCpuPhys Physical address of the global cpu page
85 */
86VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
87{
88 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
89 AssertReturn(pVM, VERR_INVALID_PARAMETER);
90 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
91
92 /* Setup Intel VMX. */
93 Assert(pVM->hwaccm.s.vmx.fSupported);
94
95#ifdef LOG_ENABLED
96 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
97#endif
98 /* Set revision dword at the beginning of the VMXON structure. */
99 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
100
101 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
102 * (which can have very bad consequences!!!)
103 */
104
105 /* Make sure the VMX instructions don't cause #UD faults. */
106 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
107
108 /* Enter VMX Root Mode */
109 int rc = VMXEnable(pPageCpuPhys);
110 if (VBOX_FAILURE(rc))
111 {
112 VMXR0CheckError(pVM, rc);
113 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
114 return VERR_VMX_VMXON_FAILED;
115 }
116 return VINF_SUCCESS;
117}
118
119/**
120 * Deactivates VT-x on the current CPU
121 *
122 * @returns VBox status code.
123 * @param pCpu CPU info struct
124 * @param pvPageCpu Pointer to the global cpu page
125 * @param pPageCpuPhys Physical address of the global cpu page
126 */
127VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
128{
129 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
130 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
131
132 /* Leave VMX Root Mode. */
133 VMXDisable();
134
135 /* And clear the X86_CR4_VMXE bit */
136 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
137
138#ifdef LOG_ENABLED
139 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
140#endif
141 return VINF_SUCCESS;
142}
143
144/**
145 * Does Ring-0 per VM VT-x init.
146 *
147 * @returns VBox status code.
148 * @param pVM The VM to operate on.
149 */
150VMMR0DECL(int) VMXR0InitVM(PVM pVM)
151{
152 int rc;
153
154#ifdef LOG_ENABLED
155 SUPR0Printf("VMXR0InitVM %x\n", pVM);
156#endif
157 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
158 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
159
160
161 /* Allocate one page for the VM control structure (VMCS). */
162 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
163 AssertRC(rc);
164 if (RT_FAILURE(rc))
165 return rc;
166
167 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
168 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
169 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
170
171 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
172 {
173 /* Allocate one page for the virtual APIC mmio cache. */
174 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
175 AssertRC(rc);
176 if (RT_FAILURE(rc))
177 return rc;
178
179 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
180 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
181 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
182 }
183 else
184 {
185 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
186 pVM->hwaccm.s.vmx.pAPIC = 0;
187 pVM->hwaccm.s.vmx.pAPICPhys = 0;
188 }
189
190 /* Allocate the MSR bitmap if this feature is supported. */
191 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
192 {
193 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
194 AssertRC(rc);
195 if (RT_FAILURE(rc))
196 return rc;
197
198 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
199 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
200 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
201 }
202
203 /* Current guest paging mode. */
204 pVM->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
205
206#ifdef LOG_ENABLED
207 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys);
208#endif
209 return VINF_SUCCESS;
210}
211
212/**
213 * Does Ring-0 per VM VT-x termination.
214 *
215 * @returns VBox status code.
216 * @param pVM The VM to operate on.
217 */
218VMMR0DECL(int) VMXR0TermVM(PVM pVM)
219{
220 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
221 {
222 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
223 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
224 pVM->hwaccm.s.vmx.pVMCS = 0;
225 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
226 }
227 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
228 {
229 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
230 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
231 pVM->hwaccm.s.vmx.pAPIC = 0;
232 pVM->hwaccm.s.vmx.pAPICPhys = 0;
233 }
234 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
235 {
236 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
237 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
238 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
239 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
240 }
241 return VINF_SUCCESS;
242}
243
244/**
245 * Sets up VT-x for the specified VM
246 *
247 * @returns VBox status code.
248 * @param pVM The VM to operate on.
249 */
250VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
251{
252 int rc = VINF_SUCCESS;
253 uint32_t val;
254
255 AssertReturn(pVM, VERR_INVALID_PARAMETER);
256 Assert(pVM->hwaccm.s.vmx.pVMCS);
257
258 /* Set revision dword at the beginning of the VMCS structure. */
259 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
260
261 /* Clear VM Control Structure. */
262 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
263 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
264 if (VBOX_FAILURE(rc))
265 goto vmx_end;
266
267 /* Activate the VM Control Structure. */
268 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
269 if (VBOX_FAILURE(rc))
270 goto vmx_end;
271
272 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
273 * Set required bits to one and zero according to the MSR capabilities.
274 */
275 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
276 /* External and non-maskable interrupts cause VM-exits. */
277 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
278 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
279
280 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
281 AssertRC(rc);
282
283 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
284 * Set required bits to one and zero according to the MSR capabilities.
285 */
286 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
287 /* Program which event cause VM-exits and which features we want to use. */
288 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
289 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
290 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
291 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
292 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
293
294 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
295 if (!pVM->hwaccm.s.fNestedPaging)
296 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
297 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
298 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
299
300 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
301
302#if HC_ARCH_BITS == 64
303 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
304 {
305 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
306 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
307 Assert(pVM->hwaccm.s.vmx.pAPIC);
308 }
309 else
310 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
311 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
312#endif
313
314#ifdef VBOX_WITH_VTX_MSR_BITMAPS
315 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
316 {
317 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
318 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
319 }
320#endif
321
322 /* We will use the secondary control if it's present. */
323 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
324
325 /* Mask away the bits that the CPU doesn't support */
326 /** @todo make sure they don't conflict with the above requirements. */
327 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
328 pVM->hwaccm.s.vmx.proc_ctls = val;
329
330 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
331 AssertRC(rc);
332
333 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
334 {
335 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
336 * Set required bits to one and zero according to the MSR capabilities.
337 */
338 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
339 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
340
341#ifdef HWACCM_VTX_WITH_EPT
342 if (pVM->hwaccm.s.fNestedPaging)
343 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
344#endif /* HWACCM_VTX_WITH_EPT */
345#ifdef HWACCM_VTX_WITH_VPID
346 else
347 if (pVM->hwaccm.s.vmx.fVPID)
348 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
349#endif /* HWACCM_VTX_WITH_VPID */
350
351 /* Mask away the bits that the CPU doesn't support */
352 /** @todo make sure they don't conflict with the above requirements. */
353 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
354
355 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
356 AssertRC(rc);
357 }
358
359 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
360 * Set required bits to one and zero according to the MSR capabilities.
361 */
362 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
363 AssertRC(rc);
364
365 /* VMX_VMCS_CTRL_EXIT_CONTROLS
366 * Set required bits to one and zero according to the MSR capabilities.
367 */
368 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
369
370 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
371 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
372#if HC_ARCH_BITS == 64
373 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
374#else
375 /* else Must be zero when AMD64 is not available. */
376#endif
377 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
378 /* Don't acknowledge external interrupts on VM-exit. */
379 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
380 AssertRC(rc);
381
382 /* Forward all exception except #NM & #PF to the guest.
383 * We always need to check pagefaults since our shadow page table can be out of sync.
384 * And we always lazily sync the FPU & XMM state.
385 */
386
387 /** @todo Possible optimization:
388 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
389 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
390 * registers ourselves of course.
391 *
392 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
393 */
394 pVM->hwaccm.s.vmx.u32TrapMask = HWACCM_VMX_TRAP_MASK;
395#ifndef DEBUG
396 if (pVM->hwaccm.s.fNestedPaging)
397 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
398#endif
399 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
400 AssertRC(rc);
401
402 /* Don't filter page faults; all of them should cause a switch. */
403 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
404 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
405 AssertRC(rc);
406
407 /* Init TSC offset to zero. */
408 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
409#if HC_ARCH_BITS == 32
410 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
411#endif
412 AssertRC(rc);
413
414 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
415#if HC_ARCH_BITS == 32
416 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
417#endif
418 AssertRC(rc);
419
420 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
421#if HC_ARCH_BITS == 32
422 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
423#endif
424 AssertRC(rc);
425
426 /* Set the MSR bitmap address. */
427 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
428 {
429 /* Optional */
430 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
431#if HC_ARCH_BITS == 32
432 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32ULL);
433#endif
434 AssertRC(rc);
435 }
436
437 /* Clear MSR controls. */
438 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
439 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
441#if HC_ARCH_BITS == 32
442 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
443 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
444 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
445#endif
446 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
447 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
448 AssertRC(rc);
449
450 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
451 {
452 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
453 /* Optional */
454 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
455 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
456#if HC_ARCH_BITS == 32
457 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32ULL);
458#endif
459 AssertRC(rc);
460 }
461
462 /* Set link pointer to -1. Not currently used. */
463#if HC_ARCH_BITS == 32
464 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
465 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
466#else
467 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
468#endif
469 AssertRC(rc);
470
471 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
472 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
473 AssertRC(rc);
474
475 /* Choose the right TLB setup function. */
476 if (pVM->hwaccm.s.fNestedPaging)
477 {
478 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
479
480 /* Default values for flushing. */
481 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
482 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
483
484 /* If the capabilities specify we can do more, then make use of it. */
485 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
486 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
487 else
488 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
489 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
490
491 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
492 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
493 }
494#ifdef HWACCM_VTX_WITH_VPID
495 else
496 if (pVM->hwaccm.s.vmx.fVPID)
497 {
498 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
499
500 /* Default values for flushing. */
501 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
502 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
503
504 /* If the capabilities specify we can do more, then make use of it. */
505 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
506 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
507 else
508 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
509 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
510
511 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
512 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
513 }
514#endif /* HWACCM_VTX_WITH_VPID */
515 else
516 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
517
518
519vmx_end:
520 VMXR0CheckError(pVM, rc);
521 return rc;
522}
523
524
525/**
526 * Injects an event (trap or external interrupt)
527 *
528 * @returns VBox status code.
529 * @param pVM The VM to operate on.
530 * @param pCtx CPU Context
531 * @param intInfo VMX interrupt info
532 * @param cbInstr Opcode length of faulting instruction
533 * @param errCode Error code (optional)
534 */
535static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
536{
537 int rc;
538
539#ifdef VBOX_STRICT
540 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
541 if (iGate == 0xE)
542 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
543 else
544 if (iGate < 0x20)
545 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
546 else
547 {
548 LogFlow(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
549 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
550 Assert(pCtx->eflags.u32 & X86_EFL_IF);
551 }
552#endif
553
554#ifdef HWACCM_VMX_EMULATE_REALMODE
555 if (CPUMIsGuestInRealModeEx(pCtx))
556 {
557 /* Injecting events doesn't work right with real mode emulation.
558 * (#GP if we try to inject external hardware interrupts)
559 * Fake an 'int x' instruction. Note that we need to take special precautions when
560 * the inject is interrupted as the normal pending event method seems to be broken in this case.
561 */
562 LogFlow(("Fake 'int %x' inject (real mode)\n", iGate));
563 /* Make sure the return address is set to the current IP. (ugly hack alert) */
564 pCtx->rip--;
565 cbInstr = 1;
566 intInfo = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo) | (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
567
568 pVM->hwaccm.s.vmx.RealMode.Event.intInfo = intInfo;
569 pVM->hwaccm.s.vmx.RealMode.Event.fPending = true;
570 pVM->hwaccm.s.vmx.RealMode.eip = pCtx->eip;
571 }
572#endif /* HWACCM_VMX_EMULATE_REALMODE */
573
574 /* Set event injection state. */
575 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
576
577 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
578 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
579
580 AssertRC(rc);
581 return rc;
582}
583
584
585/**
586 * Checks for pending guest interrupts and injects them
587 *
588 * @returns VBox status code.
589 * @param pVM The VM to operate on.
590 * @param pCtx CPU Context
591 */
592static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
593{
594 int rc;
595
596 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
597 if (pVM->hwaccm.s.Event.fPending)
598 {
599 Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
600 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
601 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
602 AssertRC(rc);
603
604 pVM->hwaccm.s.Event.fPending = false;
605 return VINF_SUCCESS;
606 }
607
608 /* When external interrupts are pending, we should exit the VM when IF is set. */
609 if ( !TRPMHasTrap(pVM)
610 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
611 {
612 if (!(pCtx->eflags.u32 & X86_EFL_IF))
613 {
614 if (!(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
615 {
616 LogFlow(("Enable irq window exit!\n"));
617 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
618 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
619 AssertRC(rc);
620 }
621 /* else nothing to do but wait */
622 }
623 else
624 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
625 {
626 uint8_t u8Interrupt;
627
628 rc = PDMGetInterrupt(pVM, &u8Interrupt);
629 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
630 if (VBOX_SUCCESS(rc))
631 {
632 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
633 AssertRC(rc);
634 }
635 else
636 {
637 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
638 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
639 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
640 /* Just continue */
641 }
642 }
643 else
644 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
645 }
646
647#ifdef VBOX_STRICT
648 if (TRPMHasTrap(pVM))
649 {
650 uint8_t u8Vector;
651 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
652 AssertRC(rc);
653 }
654#endif
655
656 if ( pCtx->eflags.u32 & X86_EFL_IF
657 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
658 && TRPMHasTrap(pVM)
659 )
660 {
661 uint8_t u8Vector;
662 int rc;
663 TRPMEVENT enmType;
664 RTGCUINTPTR intInfo;
665 RTGCUINT errCode;
666
667 /* If a new event is pending, then dispatch it now. */
668 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
669 AssertRC(rc);
670 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
671 Assert(enmType != TRPM_SOFTWARE_INT);
672
673 /* Clear the pending trap. */
674 rc = TRPMResetTrap(pVM);
675 AssertRC(rc);
676
677 intInfo = u8Vector;
678 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
679
680 if (enmType == TRPM_TRAP)
681 {
682 switch (u8Vector) {
683 case 8:
684 case 10:
685 case 11:
686 case 12:
687 case 13:
688 case 14:
689 case 17:
690 /* Valid error codes. */
691 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
692 break;
693 default:
694 break;
695 }
696 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
697 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
698 else
699 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
700 }
701 else
702 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
703
704 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
705 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
706 AssertRC(rc);
707 } /* if (interrupts can be dispatched) */
708
709 return VINF_SUCCESS;
710}
711
712/**
713 * Save the host state
714 *
715 * @returns VBox status code.
716 * @param pVM The VM to operate on.
717 */
718VMMR0DECL(int) VMXR0SaveHostState(PVM pVM)
719{
720 int rc = VINF_SUCCESS;
721
722 /*
723 * Host CPU Context
724 */
725 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
726 {
727 RTIDTR idtr;
728 RTGDTR gdtr;
729 RTSEL SelTR;
730 PX86DESCHC pDesc;
731 uintptr_t trBase;
732
733 /* Control registers */
734 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
735 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
736 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
737 AssertRC(rc);
738 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
739 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
740 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
741
742 /* Selector registers. */
743 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
744 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
745 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
746 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
747#if HC_ARCH_BITS == 32
748 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
749 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
750#endif
751 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
752 SelTR = ASMGetTR();
753 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
754 AssertRC(rc);
755 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
756 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
757 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
758 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
759 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
760 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
761 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
762
763 /* GDTR & IDTR */
764 ASMGetGDTR(&gdtr);
765 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
766 ASMGetIDTR(&idtr);
767 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
768 AssertRC(rc);
769 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
770 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
771
772 /* Save the base address of the TR selector. */
773 if (SelTR > gdtr.cbGdt)
774 {
775 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
776 return VERR_VMX_INVALID_HOST_STATE;
777 }
778
779 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
780#if HC_ARCH_BITS == 64
781 trBase = X86DESC64_BASE(*pDesc);
782#else
783 trBase = X86DESC_BASE(*pDesc);
784#endif
785 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
786 AssertRC(rc);
787 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
788
789 /* FS and GS base. */
790#if HC_ARCH_BITS == 64
791 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
792 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
793 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
794 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
795#endif
796 AssertRC(rc);
797
798 /* Sysenter MSRs. */
799 /** @todo expensive!! */
800 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
801 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
802#if HC_ARCH_BITS == 32
803 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
804 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
805 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
806 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
807#else
808 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
809 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
810 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
811 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
812#endif
813 AssertRC(rc);
814
815 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
816 }
817 return rc;
818}
819
820/**
821 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
822 *
823 * @param pVM The VM to operate on.
824 * @param pCtx Guest context
825 */
826static void vmxR0PrefetchPAEPdptrs(PVM pVM, PCPUMCTX pCtx)
827{
828 if (CPUMIsGuestInPAEModeEx(pCtx))
829 {
830 X86PDPE Pdpe;
831
832 for (unsigned i=0;i<4;i++)
833 {
834 Pdpe = PGMGstGetPaePDPtr(pVM, i);
835 int rc = VMXWriteVMCS(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
836#if HC_ARCH_BITS == 32
837 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_PDPTR0_FULL + i*2 + 1, Pdpe.u >> 32ULL);
838#endif
839 AssertRC(rc);
840 }
841 }
842}
843
844/**
845 * Loads the guest state
846 *
847 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
848 *
849 * @returns VBox status code.
850 * @param pVM The VM to operate on.
851 * @param pCtx Guest context
852 */
853VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
854{
855 int rc = VINF_SUCCESS;
856 RTGCUINTPTR val;
857 X86EFLAGS eflags;
858
859 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
860 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
861 {
862#ifdef HWACCM_VMX_EMULATE_REALMODE
863 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
864 if (pVM->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
865 {
866# define VTX_CORRECT_PROT_SEL(reg) \
867 { \
868 if ( pCtx->reg##Hid.u64Base == (pVM->hwaccm.s.vmx.RealMode.reg##Hid.u64Base & 0xfffff) \
869 && pCtx->reg == ((pVM->hwaccm.s.vmx.RealMode.reg##Hid.u64Base >> 4) & ~X86_SEL_RPL)) \
870 { \
871 pCtx->reg##Hid = pVM->hwaccm.s.vmx.RealMode.reg##Hid; \
872 pCtx->reg = pVM->hwaccm.s.vmx.RealMode.reg; \
873 } \
874 }
875
876 /* Correct weird requirements for switching to protected mode. */
877 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
878 && enmGuestMode >= PGMMODE_PROTECTED)
879 {
880 /* DPL of all hidden selector registers must match the current CPL (0). */
881 pCtx->csHid.Attr.n.u2Dpl = 0;
882 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
883
884 pCtx->dsHid.Attr.n.u2Dpl = 0;
885 pCtx->esHid.Attr.n.u2Dpl = 0;
886 pCtx->fsHid.Attr.n.u2Dpl = 0;
887 pCtx->gsHid.Attr.n.u2Dpl = 0;
888 pCtx->ssHid.Attr.n.u2Dpl = 0;
889
890 /* RPL of all selectors must match the current CPL (0). */
891 pCtx->cs &= ~X86_SEL_RPL;
892 pCtx->ds &= ~X86_SEL_RPL;
893 pCtx->es &= ~X86_SEL_RPL;
894 pCtx->fs &= ~X86_SEL_RPL;
895 pCtx->gs &= ~X86_SEL_RPL;
896 pCtx->ss &= ~X86_SEL_RPL;
897
898 if (pVM->hwaccm.s.vmx.RealMode.fValid)
899 {
900 VTX_CORRECT_PROT_SEL(ds);
901 VTX_CORRECT_PROT_SEL(es);
902 VTX_CORRECT_PROT_SEL(fs);
903 VTX_CORRECT_PROT_SEL(gs);
904 pVM->hwaccm.s.vmx.RealMode.fValid = false;
905 }
906 }
907 else
908 /* Switching from protected mode to real mode. */
909 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode >= PGMMODE_PROTECTED
910 && enmGuestMode == PGMMODE_REAL)
911 {
912 /* Save the original hidden selectors in case we need to restore them later on. */
913 pVM->hwaccm.s.vmx.RealMode.ds = pCtx->ds;
914 pVM->hwaccm.s.vmx.RealMode.dsHid = pCtx->dsHid;
915 pVM->hwaccm.s.vmx.RealMode.es = pCtx->es;
916 pVM->hwaccm.s.vmx.RealMode.esHid = pCtx->esHid;
917 pVM->hwaccm.s.vmx.RealMode.fs = pCtx->fs;
918 pVM->hwaccm.s.vmx.RealMode.fsHid = pCtx->fsHid;
919 pVM->hwaccm.s.vmx.RealMode.gs = pCtx->gs;
920 pVM->hwaccm.s.vmx.RealMode.gsHid = pCtx->gsHid;
921 pVM->hwaccm.s.vmx.RealMode.ss = pCtx->ss;
922 pVM->hwaccm.s.vmx.RealMode.ssHid = pCtx->ssHid;
923 pVM->hwaccm.s.vmx.RealMode.fValid = true;
924
925 /* The selector value & base must be adjusted or else... */
926 pCtx->cs = pCtx->csHid.u64Base >> 4;
927 pCtx->ds = pCtx->dsHid.u64Base >> 4;
928 pCtx->es = pCtx->esHid.u64Base >> 4;
929 pCtx->fs = pCtx->fsHid.u64Base >> 4;
930 pCtx->gs = pCtx->gsHid.u64Base >> 4;
931 pCtx->ss = pCtx->ssHid.u64Base >> 4;
932
933 /* The limit must also be adjusted. */
934 pCtx->csHid.u32Limit &= 0xffff;
935 pCtx->dsHid.u32Limit &= 0xffff;
936 pCtx->esHid.u32Limit &= 0xffff;
937 pCtx->fsHid.u32Limit &= 0xffff;
938 pCtx->gsHid.u32Limit &= 0xffff;
939 pCtx->ssHid.u32Limit &= 0xffff;
940
941 Assert(pCtx->csHid.u64Base <= 0xfffff);
942 Assert(pCtx->dsHid.u64Base <= 0xfffff);
943 Assert(pCtx->esHid.u64Base <= 0xfffff);
944 Assert(pCtx->fsHid.u64Base <= 0xfffff);
945 Assert(pCtx->gsHid.u64Base <= 0xfffff);
946 }
947 pVM->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
948 }
949 else
950 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
951 if ( CPUMIsGuestInRealModeEx(pCtx)
952 && pCtx->csHid.u64Base == 0xffff0000)
953 {
954 pCtx->csHid.u64Base = 0xf0000;
955 pCtx->cs = 0xf000;
956 }
957#endif /* HWACCM_VMX_EMULATE_REALMODE */
958
959 VMX_WRITE_SELREG(ES, es);
960 AssertRC(rc);
961
962 VMX_WRITE_SELREG(CS, cs);
963 AssertRC(rc);
964
965 VMX_WRITE_SELREG(SS, ss);
966 AssertRC(rc);
967
968 VMX_WRITE_SELREG(DS, ds);
969 AssertRC(rc);
970
971 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
972 VMX_WRITE_SELREG(FS, fs);
973 AssertRC(rc);
974
975 VMX_WRITE_SELREG(GS, gs);
976 AssertRC(rc);
977 }
978
979 /* Guest CPU context: LDTR. */
980 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
981 {
982 if (pCtx->ldtr == 0)
983 {
984 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
985 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
986 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
987 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
988 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
989 }
990 else
991 {
992 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
993 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
994 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
995 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
996 }
997 AssertRC(rc);
998 }
999 /* Guest CPU context: TR. */
1000 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1001 {
1002#ifdef HWACCM_VMX_EMULATE_REALMODE
1003 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1004 if (CPUMIsGuestInRealModeEx(pCtx))
1005 {
1006 RTGCPHYS GCPhys;
1007
1008 /* We convert it here every time as pci regions could be reconfigured. */
1009 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1010 AssertRC(rc);
1011
1012 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, 0);
1013 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1014 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1015
1016 X86DESCATTR attr;
1017
1018 attr.u = 0;
1019 attr.n.u1Present = 1;
1020 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1021 val = attr.u;
1022 }
1023 else
1024#endif /* HWACCM_VMX_EMULATE_REALMODE */
1025 {
1026 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
1027 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1028 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
1029
1030 val = pCtx->trHid.Attr.u;
1031
1032 /* The TSS selector must be busy. */
1033 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1034 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1035 else
1036 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1037 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1038
1039 }
1040 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
1041 AssertRC(rc);
1042 }
1043 /* Guest CPU context: GDTR. */
1044 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1045 {
1046 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1047 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1048 AssertRC(rc);
1049 }
1050 /* Guest CPU context: IDTR. */
1051 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1052 {
1053 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1054 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1055 AssertRC(rc);
1056 }
1057
1058 /*
1059 * Sysenter MSRs (unconditional)
1060 */
1061 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1062 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1063 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1064 AssertRC(rc);
1065
1066 /* Control registers */
1067 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1068 {
1069 val = pCtx->cr0;
1070 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1071 Log2(("Guest CR0-shadow %08x\n", val));
1072 if (CPUMIsGuestFPUStateActive(pVM) == false)
1073 {
1074 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1075 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1076 }
1077 else
1078 {
1079 /** @todo check if we support the old style mess correctly. */
1080 if (!(val & X86_CR0_NE))
1081 {
1082 Log(("Forcing X86_CR0_NE!!!\n"));
1083
1084 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1085 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
1086 {
1087 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_MF);
1088 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1089 AssertRC(rc);
1090 pVM->hwaccm.s.fFPUOldStyleOverride = true;
1091 }
1092 }
1093
1094 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1095 }
1096 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1097 val |= X86_CR0_PE | X86_CR0_PG;
1098 if (pVM->hwaccm.s.fNestedPaging)
1099 {
1100 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1101 {
1102 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1103 pVM->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1104 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1105 }
1106 else
1107 {
1108 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1109 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1110 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1111 }
1112 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1113 AssertRC(rc);
1114 }
1115 else
1116 {
1117 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1118 val |= X86_CR0_WP;
1119 }
1120
1121 /* Always enable caching. */
1122 val &= ~(X86_CR0_CD|X86_CR0_NW);
1123
1124 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
1125 Log2(("Guest CR0 %08x\n", val));
1126 /* CR0 flags owned by the host; if the guests attempts to change them, then
1127 * the VM will exit.
1128 */
1129 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1130 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1131 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1132 | X86_CR0_TS
1133 | X86_CR0_ET /* Bit not restored during VM-exit! */
1134 | X86_CR0_CD /* Bit not restored during VM-exit! */
1135 | X86_CR0_NW /* Bit not restored during VM-exit! */
1136 | X86_CR0_NE
1137 | X86_CR0_MP;
1138 pVM->hwaccm.s.vmx.cr0_mask = val;
1139
1140 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1141 Log2(("Guest CR0-mask %08x\n", val));
1142 AssertRC(rc);
1143 }
1144 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1145 {
1146 /* CR4 */
1147 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1148 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1149 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1150 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1151
1152 if (!pVM->hwaccm.s.fNestedPaging)
1153 {
1154 switch(pVM->hwaccm.s.enmShadowMode)
1155 {
1156 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1157 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1158 case PGMMODE_32_BIT: /* 32-bit paging. */
1159 break;
1160
1161 case PGMMODE_PAE: /* PAE paging. */
1162 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1163 /** @todo use normal 32 bits paging */
1164 val |= X86_CR4_PAE;
1165 break;
1166
1167 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1168 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1169#ifdef VBOX_ENABLE_64_BITS_GUESTS
1170 break;
1171#else
1172 AssertFailed();
1173 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1174#endif
1175 default: /* shut up gcc */
1176 AssertFailed();
1177 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1178 }
1179 }
1180 else
1181 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1182 {
1183 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1184 val |= X86_CR4_PSE;
1185 /* Our identity mapping is a 32 bits page directory. */
1186 val &= ~X86_CR4_PAE;
1187 }
1188
1189#ifdef HWACCM_VMX_EMULATE_REALMODE
1190 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1191 if (CPUMIsGuestInRealModeEx(pCtx))
1192 val |= X86_CR4_VME;
1193#endif /* HWACCM_VMX_EMULATE_REALMODE */
1194
1195 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
1196 Log2(("Guest CR4 %08x\n", val));
1197 /* CR4 flags owned by the host; if the guests attempts to change them, then
1198 * the VM will exit.
1199 */
1200 val = 0
1201#ifdef HWACCM_VMX_EMULATE_REALMODE
1202 | X86_CR4_VME
1203#endif
1204 | X86_CR4_PAE
1205 | X86_CR4_PGE
1206 | X86_CR4_PSE
1207 | X86_CR4_VMXE;
1208 pVM->hwaccm.s.vmx.cr4_mask = val;
1209
1210 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1211 Log2(("Guest CR4-mask %08x\n", val));
1212 AssertRC(rc);
1213 }
1214
1215 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1216 {
1217 if (pVM->hwaccm.s.fNestedPaging)
1218 {
1219 AssertMsg(PGMGetEPTCR3(pVM) == PGMGetHyperCR3(pVM), ("%VHp vs %VHp\n", PGMGetEPTCR3(pVM), PGMGetHyperCR3(pVM)));
1220 pVM->hwaccm.s.vmx.GCPhysEPTP = PGMGetEPTCR3(pVM);
1221
1222 Assert(!(pVM->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1223 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1224 pVM->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1225 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1226
1227 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EPTP_FULL, pVM->hwaccm.s.vmx.GCPhysEPTP);
1228#if HC_ARCH_BITS == 32
1229 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EPTP_HIGH, (uint32_t)(pVM->hwaccm.s.vmx.GCPhysEPTP >> 32ULL));
1230#endif
1231 AssertRC(rc);
1232
1233 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1234 {
1235 RTGCPHYS GCPhys;
1236
1237 /* We convert it here every time as pci regions could be reconfigured. */
1238 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1239 AssertRC(rc);
1240
1241 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1242 * take care of the translation to host physical addresses.
1243 */
1244 val = GCPhys;
1245 }
1246 else
1247 {
1248 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1249 val = pCtx->cr3;
1250 /* Prefetch the four PDPT entries in PAE mode. */
1251 vmxR0PrefetchPAEPdptrs(pVM, pCtx);
1252 }
1253 }
1254 else
1255 {
1256 val = PGMGetHyperCR3(pVM);
1257 Assert(val);
1258 }
1259
1260 /* Save our shadow CR3 register. */
1261 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
1262 AssertRC(rc);
1263 }
1264
1265 /* Debug registers. */
1266 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1267 {
1268 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1269 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1270
1271 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1272 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1273 pCtx->dr[7] |= 0x400; /* must be one */
1274
1275 /* Resync DR7 */
1276 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
1277 AssertRC(rc);
1278
1279 /* Sync the debug state now if any breakpoint is armed. */
1280 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1281 && !CPUMIsGuestDebugStateActive(pVM)
1282 && !DBGFIsStepping(pVM))
1283 {
1284 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxArmed);
1285
1286 /* Disable drx move intercepts. */
1287 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1288 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1289 AssertRC(rc);
1290
1291 /* Save the host and load the guest debug state. */
1292 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
1293 AssertRC(rc);
1294 }
1295
1296 /* IA32_DEBUGCTL MSR. */
1297 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1298 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
1299 AssertRC(rc);
1300
1301 /** @todo do we really ever need this? */
1302 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1303 AssertRC(rc);
1304 }
1305
1306 /* EIP, ESP and EFLAGS */
1307 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
1308 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
1309 AssertRC(rc);
1310
1311 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1312 eflags = pCtx->eflags;
1313 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1314 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1315
1316#ifdef HWACCM_VMX_EMULATE_REALMODE
1317 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1318 if (CPUMIsGuestInRealModeEx(pCtx))
1319 {
1320 pVM->hwaccm.s.vmx.RealMode.eflags = eflags;
1321
1322 eflags.Bits.u1VM = 1;
1323 eflags.Bits.u2IOPL = 3;
1324 }
1325#endif /* HWACCM_VMX_EMULATE_REALMODE */
1326 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1327 AssertRC(rc);
1328
1329 /* TSC offset. */
1330 uint64_t u64TSCOffset;
1331
1332 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1333 {
1334 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1335 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1336#if HC_ARCH_BITS == 32
1337 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
1338#endif
1339 AssertRC(rc);
1340
1341 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1342 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1343 AssertRC(rc);
1344 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
1345 }
1346 else
1347 {
1348 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1349 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1350 AssertRC(rc);
1351 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1352 }
1353
1354 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1355 * Set required bits to one and zero according to the MSR capabilities.
1356 */
1357 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1358 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1359 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1360
1361 /* 64 bits guest mode? */
1362 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1363 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1364 /* else Must be zero when AMD64 is not available. */
1365
1366 /* Mask away the bits that the CPU doesn't support */
1367 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1368 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1369 AssertRC(rc);
1370
1371 /* 64 bits guest mode? */
1372 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1373 {
1374#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
1375 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1376#else
1377 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1378#endif
1379 /* Unconditionally update these as wrmsr might have changed them. */
1380 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1381 AssertRC(rc);
1382 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1383 AssertRC(rc);
1384 }
1385 else
1386 {
1387 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1388 }
1389
1390#ifdef DEBUG
1391 /* Intercept X86_XCPT_DB if stepping is enabled */
1392 if (DBGFIsStepping(pVM))
1393 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_DB);
1394 else
1395 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_DB);
1396
1397 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1398#endif
1399
1400#ifdef VBOX_STRICT
1401 Assert(pVM->hwaccm.s.vmx.u32TrapMask & RT_BIT(X86_XCPT_GP));
1402#else
1403# ifdef HWACCM_VMX_EMULATE_REALMODE
1404 /* Intercept #GP faults in real mode to handle privileged instructions. */
1405 if (CPUMIsGuestInRealModeEx(pCtx))
1406 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_GP);
1407 else
1408 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_GP);
1409# endif /* HWACCM_VMX_EMULATE_REALMODE */
1410 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1411 AssertRC(rc);
1412#endif
1413
1414 /* Done. */
1415 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1416
1417 return rc;
1418}
1419
1420/**
1421 * Syncs back the guest state
1422 *
1423 * @returns VBox status code.
1424 * @param pVM The VM to operate on.
1425 * @param pCtx Guest context
1426 */
1427DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, CPUMCTX *pCtx)
1428{
1429 RTCCUINTREG val, valShadow;
1430 RTGCUINTPTR uInterruptState;
1431 int rc;
1432
1433 /* Let's first sync back eip, esp, and eflags. */
1434 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1435 AssertRC(rc);
1436 pCtx->rip = val;
1437 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1438 AssertRC(rc);
1439 pCtx->rsp = val;
1440 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1441 AssertRC(rc);
1442 pCtx->eflags.u32 = val;
1443
1444 /* Take care of instruction fusing (sti, mov ss) */
1445 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1446 uInterruptState = val;
1447 if (uInterruptState != 0)
1448 {
1449 Assert(uInterruptState <= 2); /* only sti & mov ss */
1450 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1451 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1452 }
1453 else
1454 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1455
1456 /* Control registers. */
1457 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1458 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1459 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1460 CPUMSetGuestCR0(pVM, val);
1461
1462 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1463 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1464 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1465 CPUMSetGuestCR4(pVM, val);
1466
1467 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1468 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1469 if ( pVM->hwaccm.s.fNestedPaging
1470 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1471 {
1472 /* Can be updated behind our back in the nested paging case. */
1473 CPUMSetGuestCR2(pVM, ASMGetCR2());
1474
1475 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
1476
1477 if (val != pCtx->cr3)
1478 {
1479 CPUMSetGuestCR3(pVM, val);
1480 PGMUpdateCR3(pVM, val);
1481 }
1482 /* Prefetch the four PDPT entries in PAE mode. */
1483 vmxR0PrefetchPAEPdptrs(pVM, pCtx);
1484 }
1485
1486 /* Sync back DR7 here. */
1487 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1488 pCtx->dr[7] = val;
1489
1490 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1491 VMX_READ_SELREG(ES, es);
1492 VMX_READ_SELREG(SS, ss);
1493 VMX_READ_SELREG(CS, cs);
1494 VMX_READ_SELREG(DS, ds);
1495 VMX_READ_SELREG(FS, fs);
1496 VMX_READ_SELREG(GS, gs);
1497
1498 /*
1499 * System MSRs
1500 */
1501 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1502 pCtx->SysEnter.cs = val;
1503 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1504 pCtx->SysEnter.eip = val;
1505 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1506 pCtx->SysEnter.esp = val;
1507
1508 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1509 VMX_READ_SELREG(LDTR, ldtr);
1510
1511 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1512 pCtx->gdtr.cbGdt = val;
1513 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1514 pCtx->gdtr.pGdt = val;
1515
1516 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1517 pCtx->idtr.cbIdt = val;
1518 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1519 pCtx->idtr.pIdt = val;
1520
1521#ifdef HWACCM_VMX_EMULATE_REALMODE
1522 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1523 if (CPUMIsGuestInRealModeEx(pCtx))
1524 {
1525 /* Hide our emulation flags */
1526 pCtx->eflags.Bits.u1VM = 0;
1527 pCtx->eflags.Bits.u2IOPL = pVM->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1528
1529 /* Force a TR resync every time in case we switch modes. */
1530 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1531 }
1532 else
1533#endif /* HWACCM_VMX_EMULATE_REALMODE */
1534 {
1535 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1536 VMX_READ_SELREG(TR, tr);
1537 }
1538 return VINF_SUCCESS;
1539}
1540
1541/**
1542 * Dummy placeholder
1543 *
1544 * @param pVM The VM to operate on.
1545 */
1546static void vmxR0SetupTLBDummy(PVM pVM)
1547{
1548 return;
1549}
1550
1551/**
1552 * Setup the tagged TLB for EPT
1553 *
1554 * @returns VBox status code.
1555 * @param pVM The VM to operate on.
1556 */
1557static void vmxR0SetupTLBEPT(PVM pVM)
1558{
1559 PHWACCM_CPUINFO pCpu;
1560
1561 Assert(pVM->hwaccm.s.fNestedPaging);
1562 Assert(!pVM->hwaccm.s.vmx.fVPID);
1563
1564 /* Deal with tagged TLBs if VPID or EPT is supported. */
1565 pCpu = HWACCMR0GetCurrentCpu();
1566 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1567 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1568 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1569 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1570 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1571 {
1572 /* Force a TLB flush on VM entry. */
1573 pVM->hwaccm.s.fForceTLBFlush = true;
1574 }
1575 else
1576 Assert(!pCpu->fFlushTLB);
1577
1578 pVM->hwaccm.s.idLastCpu = pCpu->idCpu;
1579 pCpu->fFlushTLB = false;
1580
1581 if (pVM->hwaccm.s.fForceTLBFlush)
1582 vmxR0FlushEPT(pVM, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1583
1584#ifdef VBOX_WITH_STATISTICS
1585 if (pVM->hwaccm.s.fForceTLBFlush)
1586 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
1587 else
1588 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
1589#endif
1590}
1591
1592#ifdef HWACCM_VTX_WITH_VPID
1593/**
1594 * Setup the tagged TLB for VPID
1595 *
1596 * @returns VBox status code.
1597 * @param pVM The VM to operate on.
1598 */
1599static void vmxR0SetupTLBVPID(PVM pVM)
1600{
1601 PHWACCM_CPUINFO pCpu;
1602
1603 Assert(pVM->hwaccm.s.vmx.fVPID);
1604 Assert(!pVM->hwaccm.s.fNestedPaging);
1605
1606 /* Deal with tagged TLBs if VPID or EPT is supported. */
1607 pCpu = HWACCMR0GetCurrentCpu();
1608 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1609 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1610 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1611 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1612 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1613 {
1614 /* Force a TLB flush on VM entry. */
1615 pVM->hwaccm.s.fForceTLBFlush = true;
1616 }
1617 else
1618 Assert(!pCpu->fFlushTLB);
1619
1620 pVM->hwaccm.s.idLastCpu = pCpu->idCpu;
1621
1622 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1623 if (pVM->hwaccm.s.fForceTLBFlush)
1624 {
1625 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1626 || pCpu->fFlushTLB)
1627 {
1628 pCpu->fFlushTLB = false;
1629 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1630 pCpu->cTLBFlushes++;
1631 }
1632 else
1633 {
1634 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
1635 pVM->hwaccm.s.fForceTLBFlush = false;
1636 }
1637
1638 pVM->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1639 pVM->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1640 }
1641 else
1642 {
1643 Assert(!pCpu->fFlushTLB);
1644
1645 if (!pCpu->uCurrentASID || !pVM->hwaccm.s.uCurrentASID)
1646 pVM->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1647 }
1648 AssertMsg(pVM->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1649 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1650 AssertMsg(pVM->hwaccm.s.uCurrentASID >= 1 && pVM->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVM->hwaccm.s.uCurrentASID));
1651
1652 int rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_VPID, pVM->hwaccm.s.uCurrentASID);
1653 AssertRC(rc);
1654
1655 if (pVM->hwaccm.s.fForceTLBFlush)
1656 vmxR0FlushVPID(pVM, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1657
1658#ifdef VBOX_WITH_STATISTICS
1659 if (pVM->hwaccm.s.fForceTLBFlush)
1660 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
1661 else
1662 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
1663#endif
1664}
1665#endif /* HWACCM_VTX_WITH_VPID */
1666
1667/**
1668 * Runs guest code in a VT-x VM.
1669 *
1670 * @returns VBox status code.
1671 * @param pVM The VM to operate on.
1672 * @param pCtx Guest context
1673 */
1674VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1675{
1676 int rc = VINF_SUCCESS;
1677 RTCCUINTREG val;
1678 RTCCUINTREG exitReason, instrError, cbInstr;
1679 RTGCUINTPTR exitQualification;
1680 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1681 RTGCUINTPTR errCode, instrInfo;
1682 bool fSyncTPR = false;
1683 PHWACCM_CPUINFO pCpu = 0;
1684 unsigned cResume = 0;
1685#ifdef VBOX_STRICT
1686 RTCPUID idCpuCheck;
1687#endif
1688
1689 Log2(("\nE"));
1690
1691 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1692
1693#ifdef VBOX_STRICT
1694 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1695 AssertRC(rc);
1696 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1697
1698 /* allowed zero */
1699 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1700 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1701
1702 /* allowed one */
1703 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1704 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1705
1706 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1707 AssertRC(rc);
1708 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1709
1710 /* allowed zero */
1711 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1712 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1713
1714 /* allowed one */
1715 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1716 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1717
1718 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1719 AssertRC(rc);
1720 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1721
1722 /* allowed zero */
1723 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1724 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1725
1726 /* allowed one */
1727 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1728 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1729
1730 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1731 AssertRC(rc);
1732 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1733
1734 /* allowed zero */
1735 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1736 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1737
1738 /* allowed one */
1739 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1740 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1741#endif
1742
1743 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1744 */
1745ResumeExecution:
1746 AssertMsg(pVM->hwaccm.s.idEnteredCpu == RTMpCpuId(),
1747 ("Expected %d, I'm %d; cResume=%d exitReason=%RTreg exitQualification=%RTreg\n",
1748 (int)pVM->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
1749
1750 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1751 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1752 {
1753 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1754 rc = VINF_EM_RAW_INTERRUPT;
1755 goto end;
1756 }
1757
1758 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1759 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1760 {
1761 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1762 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1763 {
1764 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1765 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1766 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1767 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1768 */
1769 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1770 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1771 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1772 AssertRC(rc);
1773 }
1774 }
1775 else
1776 {
1777 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1778 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1779 AssertRC(rc);
1780 }
1781
1782 /* Check for pending actions that force us to go back to ring 3. */
1783 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1784 {
1785 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1786 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1787 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1788 rc = VINF_EM_RAW_TO_R3;
1789 goto end;
1790 }
1791 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1792 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1793 {
1794 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1795 rc = VINF_EM_PENDING_REQUEST;
1796 goto end;
1797 }
1798
1799 /* When external interrupts are pending, we should exit the VM when IF is set. */
1800 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1801 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1802 if (VBOX_FAILURE(rc))
1803 {
1804 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1805 goto end;
1806 }
1807
1808 /** @todo check timers?? */
1809
1810 /* TPR caching using CR8 is only available in 64 bits mode */
1811 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1812 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1813 /**
1814 * @todo reduce overhead
1815 */
1816 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1817 && pVM->hwaccm.s.vmx.pAPIC)
1818 {
1819 /* TPR caching in CR8 */
1820 uint8_t u8TPR;
1821 bool fPending;
1822
1823 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1824 AssertRC(rc);
1825 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1826 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1827
1828 /* Two options here:
1829 * - external interrupt pending, but masked by the TPR value.
1830 * -> a CR8 update that lower the current TPR value should cause an exit
1831 * - no pending interrupts
1832 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1833 */
1834 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1835 AssertRC(rc);
1836
1837 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
1838 fSyncTPR = true;
1839 }
1840
1841#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
1842 if ( pVM->hwaccm.s.fNestedPaging
1843# ifdef HWACCM_VTX_WITH_VPID
1844 || pVM->hwaccm.s.vmx.fVPID
1845# endif /* HWACCM_VTX_WITH_VPID */
1846 )
1847 {
1848 pCpu = HWACCMR0GetCurrentCpu();
1849 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1850 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1851 {
1852 if (pVM->hwaccm.s.idLastCpu != pCpu->idCpu)
1853 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.idLastCpu, pCpu->idCpu));
1854 else
1855 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1856 }
1857 if (pCpu->fFlushTLB)
1858 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1859 }
1860#endif
1861
1862 /*
1863 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1864 * (until the actual world switch)
1865 */
1866#ifdef VBOX_STRICT
1867 idCpuCheck = RTMpCpuId();
1868#endif
1869 /* Save the host state first. */
1870 rc = VMXR0SaveHostState(pVM);
1871 if (rc != VINF_SUCCESS)
1872 {
1873 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1874 goto end;
1875 }
1876 /* Load the guest state */
1877 rc = VMXR0LoadGuestState(pVM, pCtx);
1878 if (rc != VINF_SUCCESS)
1879 {
1880 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1881 goto end;
1882 }
1883
1884 /* Deal with tagged TLB setup and invalidation. */
1885 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM);
1886
1887 /* Non-register state Guest Context */
1888 /** @todo change me according to cpu state */
1889 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1890 AssertRC(rc);
1891
1892 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1893
1894 /* Manual save and restore:
1895 * - General purpose registers except RIP, RSP
1896 *
1897 * Trashed:
1898 * - CR2 (we don't care)
1899 * - LDTR (reset to 0)
1900 * - DRx (presumably not changed at all)
1901 * - DR7 (reset to 0x400)
1902 * - EFLAGS (reset to RT_BIT(1); not relevant)
1903 *
1904 */
1905
1906 /* All done! Let's start VM execution. */
1907 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1908#ifdef VBOX_STRICT
1909 Assert(idCpuCheck == RTMpCpuId());
1910#endif
1911 TMNotifyStartOfExecution(pVM);
1912 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1913 TMNotifyEndOfExecution(pVM);
1914
1915 /* In case we execute a goto ResumeExecution later on. */
1916 pVM->hwaccm.s.vmx.fResumeVM = true;
1917 pVM->hwaccm.s.fForceTLBFlush = false;
1918
1919 /*
1920 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1921 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1922 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1923 */
1924
1925 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1926 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1927
1928 if (rc != VINF_SUCCESS)
1929 {
1930 VMXR0ReportWorldSwitchError(pVM, rc, pCtx);
1931 goto end;
1932 }
1933 /* Success. Query the guest state and figure out what has happened. */
1934
1935 /* Investigate why there was a VM-exit. */
1936 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1937 STAM_COUNTER_INC(&pVM->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1938
1939 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1940 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1941 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1942 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1943 intInfo = val;
1944 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1945 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1946 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1947 instrInfo = val;
1948 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1949 exitQualification = val;
1950 AssertRC(rc);
1951
1952 /* Sync back the guest state */
1953 rc = VMXR0SaveGuestState(pVM, pCtx);
1954 AssertRC(rc);
1955
1956 /* Note! NOW IT'S SAFE FOR LOGGING! */
1957 Log2(("Raw exit reason %08x\n", exitReason));
1958
1959 /* Check if an injected event was interrupted prematurely. */
1960 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1961 AssertRC(rc);
1962#ifdef HWACCM_VMX_EMULATE_REALMODE
1963 /* For some reason injected software interrupts are ignored (not signalled as pending) when e.g. a shadow page fault occurs. */
1964 if ( CPUMIsGuestInRealModeEx(pCtx)
1965 && pVM->hwaccm.s.vmx.RealMode.eip == pCtx->eip
1966 && pVM->hwaccm.s.vmx.RealMode.Event.fPending)
1967 {
1968 Assert(!pVM->hwaccm.s.Event.fPending);
1969
1970 Log(("Pending real-mode inject %VX64 at %VGv\n", pVM->hwaccm.s.vmx.RealMode.Event.intInfo, pCtx->rip));
1971
1972 /* We faked an 'int x' instruction and messed with IP, so correct it here. */
1973 pCtx->rip++;
1974 pVM->hwaccm.s.Event.intInfo = pVM->hwaccm.s.vmx.RealMode.Event.intInfo;
1975 pVM->hwaccm.s.Event.fPending = true;
1976 }
1977 else
1978#endif /* HWACCM_VMX_EMULATE_REALMODE */
1979 {
1980 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1981 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1982 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1983 {
1984 pVM->hwaccm.s.Event.fPending = true;
1985 /* Error code present? */
1986 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1987 {
1988 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1989 AssertRC(rc);
1990 pVM->hwaccm.s.Event.errCode = val;
1991 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1992 }
1993 else
1994 {
1995 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1996 pVM->hwaccm.s.Event.errCode = 0;
1997 }
1998 }
1999 }
2000 pVM->hwaccm.s.vmx.RealMode.Event.fPending = false;
2001
2002#ifdef VBOX_STRICT
2003 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2004 HWACCMDumpRegs(pVM, pCtx);
2005#endif
2006
2007 Log2(("E%d", exitReason));
2008 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
2009 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
2010 Log2(("Interruption error code %d\n", errCode));
2011 Log2(("IntInfo = %08x\n", intInfo));
2012 Log2(("New EIP=%VGv\n", pCtx->rip));
2013
2014 if (fSyncTPR)
2015 {
2016 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
2017 AssertRC(rc);
2018 }
2019
2020 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2021 switch (exitReason)
2022 {
2023 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2024 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2025 {
2026 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2027
2028 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2029 {
2030 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2031 /* External interrupt; leave to allow it to be dispatched again. */
2032 rc = VINF_EM_RAW_INTERRUPT;
2033 break;
2034 }
2035 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2036 {
2037 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2038 /* External interrupt; leave to allow it to be dispatched again. */
2039 rc = VINF_EM_RAW_INTERRUPT;
2040 break;
2041
2042 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2043 AssertFailed(); /* can't come here; fails the first check. */
2044 break;
2045
2046 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2047 Assert(vector == 3 || vector == 4);
2048 /* no break */
2049 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2050 Log2(("Hardware/software interrupt %d\n", vector));
2051 switch (vector)
2052 {
2053 case X86_XCPT_NM:
2054 {
2055 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
2056
2057 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2058 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2059 rc = CPUMR0LoadGuestFPU(pVM, pCtx);
2060 if (rc == VINF_SUCCESS)
2061 {
2062 Assert(CPUMIsGuestFPUStateActive(pVM));
2063
2064 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
2065
2066 /* Continue execution. */
2067 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2068 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2069
2070 goto ResumeExecution;
2071 }
2072
2073 Log(("Forward #NM fault to the guest\n"));
2074 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
2075 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2076 AssertRC(rc);
2077 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2078 goto ResumeExecution;
2079 }
2080
2081 case X86_XCPT_PF: /* Page fault */
2082 {
2083#ifdef DEBUG
2084 if (pVM->hwaccm.s.fNestedPaging)
2085 { /* A genuine pagefault.
2086 * Forward the trap to the guest by injecting the exception and resuming execution.
2087 */
2088 Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2089
2090 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2091
2092 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
2093
2094 /* Now we must update CR2. */
2095 pCtx->cr2 = exitQualification;
2096 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2097 AssertRC(rc);
2098
2099 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2100 goto ResumeExecution;
2101 }
2102#endif
2103 Assert(!pVM->hwaccm.s.fNestedPaging);
2104
2105 Log2(("Page fault at %VGv error code %x\n", exitQualification, errCode));
2106 /* Exit qualification contains the linear address of the page fault. */
2107 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2108 TRPMSetErrorCode(pVM, errCode);
2109 TRPMSetFaultAddress(pVM, exitQualification);
2110
2111 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2112 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2113 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
2114 if (rc == VINF_SUCCESS)
2115 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2116 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
2117 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
2118
2119 TRPMResetTrap(pVM);
2120
2121 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2122 goto ResumeExecution;
2123 }
2124 else
2125 if (rc == VINF_EM_RAW_GUEST_TRAP)
2126 { /* A genuine pagefault.
2127 * Forward the trap to the guest by injecting the exception and resuming execution.
2128 */
2129 Log2(("Forward page fault to the guest\n"));
2130
2131 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
2132 /* The error code might have been changed. */
2133 errCode = TRPMGetErrorCode(pVM);
2134
2135 TRPMResetTrap(pVM);
2136
2137 /* Now we must update CR2. */
2138 pCtx->cr2 = exitQualification;
2139 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2140 AssertRC(rc);
2141
2142 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2143 goto ResumeExecution;
2144 }
2145#ifdef VBOX_STRICT
2146 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2147 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2148#endif
2149 /* Need to go back to the recompiler to emulate the instruction. */
2150 TRPMResetTrap(pVM);
2151 break;
2152 }
2153
2154 case X86_XCPT_MF: /* Floating point exception. */
2155 {
2156 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
2157 if (!(pCtx->cr0 & X86_CR0_NE))
2158 {
2159 /* old style FPU error reporting needs some extra work. */
2160 /** @todo don't fall back to the recompiler, but do it manually. */
2161 rc = VINF_EM_RAW_EMULATE_INSTR;
2162 break;
2163 }
2164 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
2165 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2166 AssertRC(rc);
2167
2168 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2169 goto ResumeExecution;
2170 }
2171
2172 case X86_XCPT_DB: /* Debug exception. */
2173 {
2174 uint64_t uDR6;
2175
2176 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2177 *
2178 * Exit qualification bits:
2179 * 3:0 B0-B3 which breakpoint condition was met
2180 * 12:4 Reserved (0)
2181 * 13 BD - debug register access detected
2182 * 14 BS - single step execution or branch taken
2183 * 63:15 Reserved (0)
2184 */
2185 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDB);
2186
2187 /* Note that we don't support guest and host-initiated debugging at the same time. */
2188 Assert(DBGFIsStepping(pVM));
2189
2190 uDR6 = X86_DR6_INIT_VAL;
2191 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2192 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
2193 if (rc == VINF_EM_RAW_GUEST_TRAP)
2194 {
2195 /** @todo this isn't working, but we'll never get here normally. */
2196
2197 /* Update DR6 here. */
2198 pCtx->dr[6] = uDR6;
2199
2200 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2201 pCtx->dr[7] &= ~X86_DR7_GD;
2202
2203 /* Paranoia. */
2204 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2205 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2206 pCtx->dr[7] |= 0x400; /* must be one */
2207
2208 /* Resync DR7 */
2209 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2210 AssertRC(rc);
2211
2212 Log(("Trap %x (debug) at %VGv exit qualification %VX64\n", vector, pCtx->rip, exitQualification));
2213 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2214 AssertRC(rc);
2215
2216 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2217 goto ResumeExecution;
2218 }
2219 /* Return to ring 3 to deal with the debug exit code. */
2220 break;
2221 }
2222
2223 case X86_XCPT_GP: /* General protection failure exception.*/
2224 {
2225 uint32_t cbSize;
2226
2227 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
2228#ifdef VBOX_STRICT
2229 if (!CPUMIsGuestInRealModeEx(pCtx))
2230 {
2231 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
2232 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2233 AssertRC(rc);
2234 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2235 goto ResumeExecution;
2236 }
2237#endif
2238 Assert(CPUMIsGuestInRealModeEx(pCtx));
2239
2240 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %VGv\n", pCtx->rip));
2241 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2242 if (rc == VINF_SUCCESS)
2243 {
2244 /* EIP has been updated already. */
2245
2246 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2247 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2248
2249 /* Only resume if successful. */
2250 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2251 goto ResumeExecution;
2252 }
2253 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Vrc\n", rc));
2254 break;
2255 }
2256
2257#ifdef VBOX_STRICT
2258 case X86_XCPT_DE: /* Divide error. */
2259 case X86_XCPT_UD: /* Unknown opcode exception. */
2260 case X86_XCPT_SS: /* Stack segment exception. */
2261 case X86_XCPT_NP: /* Segment not present exception. */
2262 {
2263 switch(vector)
2264 {
2265 case X86_XCPT_DE:
2266 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
2267 break;
2268 case X86_XCPT_UD:
2269 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
2270 break;
2271 case X86_XCPT_SS:
2272 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
2273 break;
2274 case X86_XCPT_NP:
2275 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
2276 break;
2277 }
2278
2279 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
2280 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2281 AssertRC(rc);
2282
2283 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2284 goto ResumeExecution;
2285 }
2286#endif
2287 default:
2288 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2289 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2290 break;
2291 } /* switch (vector) */
2292
2293 break;
2294
2295 default:
2296 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2297 AssertFailed();
2298 break;
2299 }
2300
2301 break;
2302 }
2303
2304 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2305 {
2306 RTGCPHYS GCPhys;
2307
2308 Assert(pVM->hwaccm.s.fNestedPaging);
2309
2310#if HC_ARCH_BITS == 64
2311 rc = VMXReadVMCS(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2312 AssertRC(rc);
2313#else
2314 uint32_t val_hi;
2315 rc = VMXReadVMCS(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &val);
2316 AssertRC(rc);
2317 rc = VMXReadVMCS(VMX_VMCS_EXIT_PHYS_ADDR_HIGH, &val_hi);
2318 AssertRC(rc);
2319 GCPhys = RT_MAKE_U64(val, val_hi);
2320#endif
2321
2322 Assert(((exitQualification >> 7) & 3) != 2);
2323
2324 /* Determine the kind of violation. */
2325 errCode = 0;
2326 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2327 errCode |= X86_TRAP_PF_ID;
2328
2329 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2330 errCode |= X86_TRAP_PF_RW;
2331
2332 /* If the page is present, then it's a page level protection fault. */
2333 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2334 errCode |= X86_TRAP_PF_P;
2335
2336 Log(("EPT Page fault %x at %VGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2337
2338 /* GCPhys contains the guest physical address of the page fault. */
2339 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2340 TRPMSetErrorCode(pVM, errCode);
2341 TRPMSetFaultAddress(pVM, GCPhys);
2342
2343 /* Handle the pagefault trap for the nested shadow table. */
2344 rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2345 Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
2346 if (rc == VINF_SUCCESS)
2347 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2348 Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, exitQualification , errCode));
2349 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
2350
2351 TRPMResetTrap(pVM);
2352
2353 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2354 goto ResumeExecution;
2355 }
2356
2357#ifdef VBOX_STRICT
2358 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2359 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2360#endif
2361 /* Need to go back to the recompiler to emulate the instruction. */
2362 TRPMResetTrap(pVM);
2363 break;
2364 }
2365
2366 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2367 /* Clear VM-exit on IF=1 change. */
2368 LogFlow(("VMX_EXIT_IRQ_WINDOW %VGv pending=%d IF=%d\n", pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2369 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2370 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2371 AssertRC(rc);
2372 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
2373 goto ResumeExecution; /* we check for pending guest interrupts there */
2374
2375 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2376 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2377 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
2378 /* Skip instruction and continue directly. */
2379 pCtx->rip += cbInstr;
2380 /* Continue execution.*/
2381 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2382 goto ResumeExecution;
2383
2384 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2385 {
2386 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2387 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
2388 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
2389 if (rc == VINF_SUCCESS)
2390 {
2391 /* Update EIP and continue execution. */
2392 Assert(cbInstr == 2);
2393 pCtx->rip += cbInstr;
2394 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2395 goto ResumeExecution;
2396 }
2397 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
2398 rc = VINF_EM_RAW_EMULATE_INSTR;
2399 break;
2400 }
2401
2402 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2403 {
2404 Log2(("VMX: Rdtsc\n"));
2405 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
2406 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
2407 if (rc == VINF_SUCCESS)
2408 {
2409 /* Update EIP and continue execution. */
2410 Assert(cbInstr == 2);
2411 pCtx->rip += cbInstr;
2412 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2413 goto ResumeExecution;
2414 }
2415 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
2416 rc = VINF_EM_RAW_EMULATE_INSTR;
2417 break;
2418 }
2419
2420 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2421 {
2422 Log2(("VMX: invlpg\n"));
2423 Assert(!pVM->hwaccm.s.fNestedPaging);
2424
2425 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
2426 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
2427 if (rc == VINF_SUCCESS)
2428 {
2429 /* Update EIP and continue execution. */
2430 pCtx->rip += cbInstr;
2431 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2432 goto ResumeExecution;
2433 }
2434 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
2435 break;
2436 }
2437
2438 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2439 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2440 {
2441 uint32_t cbSize;
2442
2443 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2444 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
2445 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2446 if (rc == VINF_SUCCESS)
2447 {
2448 /* EIP has been updated already. */
2449
2450 /* Only resume if successful. */
2451 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2452 goto ResumeExecution;
2453 }
2454 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
2455 break;
2456 }
2457
2458 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2459 {
2460 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
2461 {
2462 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
2463 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
2464 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
2465 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
2466 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
2467 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
2468
2469 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
2470 {
2471 case 0:
2472 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
2473 break;
2474 case 2:
2475 break;
2476 case 3:
2477 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
2478 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2479 break;
2480 case 4:
2481 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2482 break;
2483 case 8:
2484 /* CR8 contains the APIC TPR */
2485 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2486 break;
2487
2488 default:
2489 AssertFailed();
2490 break;
2491 }
2492 /* Check if a sync operation is pending. */
2493 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2494 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2495 {
2496 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2497 AssertRC(rc);
2498 }
2499 break;
2500
2501 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
2502 Log2(("VMX: mov x, crx\n"));
2503 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
2504
2505 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
2506
2507 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
2508 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2509
2510 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
2511 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
2512 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
2513 break;
2514
2515 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2516 Log2(("VMX: clts\n"));
2517 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
2518 rc = EMInterpretCLTS(pVM);
2519 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2520 break;
2521
2522 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2523 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2524 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
2525 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2526 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2527 break;
2528 }
2529
2530 /* Update EIP if no error occurred. */
2531 if (VBOX_SUCCESS(rc))
2532 pCtx->rip += cbInstr;
2533
2534 if (rc == VINF_SUCCESS)
2535 {
2536 /* Only resume if successful. */
2537 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2538 goto ResumeExecution;
2539 }
2540 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2541 break;
2542 }
2543
2544 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2545 {
2546 if (!DBGFIsStepping(pVM))
2547 {
2548 /* Disable drx move intercepts. */
2549 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2550 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2551 AssertRC(rc);
2552
2553 /* Save the host and load the guest debug state. */
2554 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
2555 AssertRC(rc);
2556
2557#ifdef VBOX_WITH_STATISTICS
2558 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
2559 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2560 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2561 else
2562 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2563#endif
2564
2565 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2566 goto ResumeExecution;
2567 }
2568
2569 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2570 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2571 {
2572 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2573 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2574 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2575 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2576 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2577 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2578 Log2(("DR7=%08x\n", pCtx->dr[7]));
2579 }
2580 else
2581 {
2582 Log2(("VMX: mov x, drx\n"));
2583 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2584 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2585 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2586 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2587 }
2588 /* Update EIP if no error occurred. */
2589 if (VBOX_SUCCESS(rc))
2590 pCtx->rip += cbInstr;
2591
2592 if (rc == VINF_SUCCESS)
2593 {
2594 /* Only resume if successful. */
2595 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2596 goto ResumeExecution;
2597 }
2598 Assert(rc == VERR_EM_INTERPRETER);
2599 break;
2600 }
2601
2602 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2603 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2604 {
2605 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2606 uint32_t uPort;
2607 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2608
2609 /** @todo necessary to make the distinction? */
2610 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2611 {
2612 uPort = pCtx->edx & 0xffff;
2613 }
2614 else
2615 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2616
2617 /* paranoia */
2618 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2619 {
2620 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2621 break;
2622 }
2623
2624 uint32_t cbSize = g_aIOSize[uIOWidth];
2625
2626 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2627 {
2628 /* ins/outs */
2629 uint32_t prefix = 0;
2630 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
2631 prefix |= PREFIX_REP;
2632
2633 if (fIOWrite)
2634 {
2635 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2636 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
2637 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2638 }
2639 else
2640 {
2641 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2642 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
2643 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2644 }
2645 }
2646 else
2647 {
2648 /* normal in/out */
2649 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
2650
2651 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2652
2653 if (fIOWrite)
2654 {
2655 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2656 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2657 }
2658 else
2659 {
2660 uint32_t u32Val = 0;
2661
2662 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2663 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2664 if (IOM_SUCCESS(rc))
2665 {
2666 /* Write back to the EAX register. */
2667 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2668 }
2669 }
2670 }
2671 /*
2672 * Handled the I/O return codes.
2673 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2674 */
2675 if (IOM_SUCCESS(rc))
2676 {
2677 /* Update EIP and continue execution. */
2678 pCtx->rip += cbInstr;
2679 if (RT_LIKELY(rc == VINF_SUCCESS))
2680 {
2681 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2682 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2683 {
2684 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxIOCheck);
2685 for (unsigned i=0;i<4;i++)
2686 {
2687 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2688
2689 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
2690 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2691 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2692 {
2693 uint64_t uDR6;
2694
2695 Assert(CPUMIsGuestDebugStateActive(pVM));
2696
2697 uDR6 = ASMGetDR6();
2698
2699 /* Clear all breakpoint status flags and set the one we just hit. */
2700 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2701 uDR6 |= (uint64_t)RT_BIT(i);
2702
2703 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2704 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2705 * the contents have been read.
2706 */
2707 ASMSetDR6(uDR6);
2708
2709 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2710 pCtx->dr[7] &= ~X86_DR7_GD;
2711
2712 /* Paranoia. */
2713 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2714 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2715 pCtx->dr[7] |= 0x400; /* must be one */
2716
2717 /* Resync DR7 */
2718 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2719 AssertRC(rc);
2720
2721 /* Construct inject info. */
2722 intInfo = X86_XCPT_DB;
2723 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2724 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2725
2726 Log(("Inject IO debug trap at %VGv\n", pCtx->rip));
2727 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
2728 AssertRC(rc);
2729
2730 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2731 goto ResumeExecution;
2732 }
2733 }
2734 }
2735
2736 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2737 goto ResumeExecution;
2738 }
2739 break;
2740 }
2741
2742#ifdef VBOX_STRICT
2743 if (rc == VINF_IOM_HC_IOPORT_READ)
2744 Assert(!fIOWrite);
2745 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2746 Assert(fIOWrite);
2747 else
2748 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2749#endif
2750 break;
2751 }
2752
2753 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2754 LogFlow(("VMX_EXIT_TPR\n"));
2755 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2756 goto ResumeExecution;
2757
2758 default:
2759 /* The rest is handled after syncing the entire CPU state. */
2760 break;
2761 }
2762
2763 /* Note: the guest state isn't entirely synced back at this stage. */
2764
2765 /* Investigate why there was a VM-exit. (part 2) */
2766 switch (exitReason)
2767 {
2768 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2769 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2770 case VMX_EXIT_EPT_VIOLATION:
2771 /* Already handled above. */
2772 break;
2773
2774 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2775 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2776 break;
2777
2778 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2779 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2780 rc = VINF_EM_RAW_INTERRUPT;
2781 AssertFailed(); /* Can't happen. Yet. */
2782 break;
2783
2784 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2785 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2786 rc = VINF_EM_RAW_INTERRUPT;
2787 AssertFailed(); /* Can't happen afaik. */
2788 break;
2789
2790 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2791 rc = VERR_EM_INTERPRETER;
2792 break;
2793
2794 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2795 /** Check if external interrupts are pending; if so, don't switch back. */
2796 pCtx->rip++; /* skip hlt */
2797 if ( pCtx->eflags.Bits.u1IF
2798 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2799 goto ResumeExecution;
2800
2801 rc = VINF_EM_HALT;
2802 break;
2803
2804 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2805 AssertFailed(); /* can't happen. */
2806 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2807 break;
2808
2809 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2810 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2811 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2812 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2813 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2814 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2815 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2816 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2817 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2818 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2819 /** @todo inject #UD immediately */
2820 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2821 break;
2822
2823 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2824 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2825 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2826 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2827 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2828 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2829 /* already handled above */
2830 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2831 || rc == VINF_EM_RAW_INTERRUPT
2832 || rc == VERR_EM_INTERPRETER
2833 || rc == VINF_EM_RAW_EMULATE_INSTR
2834 || rc == VINF_PGM_SYNC_CR3
2835 || rc == VINF_IOM_HC_IOPORT_READ
2836 || rc == VINF_IOM_HC_IOPORT_WRITE
2837 || rc == VINF_EM_RAW_GUEST_TRAP
2838 || rc == VINF_TRPM_XCPT_DISPATCHED
2839 || rc == VINF_EM_RESCHEDULE_REM,
2840 ("rc = %d\n", rc));
2841 break;
2842
2843 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2844 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2845 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2846 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2847 rc = VERR_EM_INTERPRETER;
2848 break;
2849
2850 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2851 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2852 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2853 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2854 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2855 break;
2856
2857 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2858 Assert(rc == VINF_EM_RAW_INTERRUPT);
2859 break;
2860
2861 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2862 {
2863#ifdef VBOX_STRICT
2864 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2865
2866 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2867 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2868
2869 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2870 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2871
2872 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2873 Log(("VMX_VMCS_GUEST_CR3 %VGp\n", val));
2874
2875 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2876 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2877
2878 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
2879 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
2880
2881 VMX_LOG_SELREG(CS, "CS");
2882 VMX_LOG_SELREG(DS, "DS");
2883 VMX_LOG_SELREG(ES, "ES");
2884 VMX_LOG_SELREG(FS, "FS");
2885 VMX_LOG_SELREG(GS, "GS");
2886 VMX_LOG_SELREG(SS, "SS");
2887 VMX_LOG_SELREG(TR, "TR");
2888 VMX_LOG_SELREG(LDTR, "LDTR");
2889
2890 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2891 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2892 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2893 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2894#endif /* VBOX_STRICT */
2895 rc = VERR_VMX_INVALID_GUEST_STATE;
2896 break;
2897 }
2898
2899 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2900 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2901 default:
2902 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
2903 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2904 break;
2905
2906 }
2907end:
2908
2909 /* Signal changes for the recompiler. */
2910 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2911
2912 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2913 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2914 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2915 {
2916 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2917 /* On the next entry we'll only sync the host context. */
2918 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2919 }
2920 else
2921 {
2922 /* On the next entry we'll sync everything. */
2923 /** @todo we can do better than this */
2924 /* Not in the VINF_PGM_CHANGE_MODE though! */
2925 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2926 }
2927
2928 /* translate into a less severe return code */
2929 if (rc == VERR_EM_INTERPRETER)
2930 rc = VINF_EM_RAW_EMULATE_INSTR;
2931 else
2932 /* Try to extract more information about what might have gone wrong here. */
2933 if (rc == VERR_VMX_INVALID_VMCS_PTR)
2934 {
2935 VMXGetActivateVMCS(&pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys);
2936 pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS;
2937 }
2938
2939 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2940
2941 Log2(("X"));
2942 return rc;
2943}
2944
2945
2946/**
2947 * Enters the VT-x session
2948 *
2949 * @returns VBox status code.
2950 * @param pVM The VM to operate on.
2951 * @param pCpu CPU info struct
2952 */
2953VMMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2954{
2955 Assert(pVM->hwaccm.s.vmx.fSupported);
2956
2957 unsigned cr4 = ASMGetCR4();
2958 if (!(cr4 & X86_CR4_VMXE))
2959 {
2960 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2961 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2962 }
2963
2964 /* Activate the VM Control Structure. */
2965 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2966 if (VBOX_FAILURE(rc))
2967 return rc;
2968
2969 pVM->hwaccm.s.vmx.fResumeVM = false;
2970 return VINF_SUCCESS;
2971}
2972
2973
2974/**
2975 * Leaves the VT-x session
2976 *
2977 * @returns VBox status code.
2978 * @param pVM The VM to operate on.
2979 * @param pCtx CPU context
2980 */
2981VMMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx)
2982{
2983 Assert(pVM->hwaccm.s.vmx.fSupported);
2984
2985 /* Save the guest debug state if necessary. */
2986 if (CPUMIsGuestDebugStateActive(pVM))
2987 {
2988 CPUMR0SaveGuestDebugState(pVM, pCtx, true /* save DR6 */);
2989
2990 /* Enable drx move intercepts again. */
2991 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2992 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2993 AssertRC(rc);
2994
2995 /* Resync the debug registers the next time. */
2996 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2997 }
2998 else
2999 Assert(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3000
3001 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3002 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
3003 AssertRC(rc);
3004
3005 return VINF_SUCCESS;
3006}
3007
3008/**
3009 * Flush the TLB (EPT)
3010 *
3011 * @returns VBox status code.
3012 * @param pVM The VM to operate on.
3013 * @param enmFlush Type of flush
3014 * @param GCPhys Physical address of the page to flush
3015 */
3016static void vmxR0FlushEPT(PVM pVM, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3017{
3018 uint64_t descriptor[2];
3019
3020 LogFlow(("vmxR0FlushEPT %d %VGv\n", enmFlush, GCPhys));
3021 Assert(pVM->hwaccm.s.fNestedPaging);
3022 descriptor[0] = pVM->hwaccm.s.vmx.GCPhysEPTP;
3023 descriptor[1] = GCPhys;
3024 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3025 AssertRC(rc);
3026}
3027
3028#ifdef HWACCM_VTX_WITH_VPID
3029/**
3030 * Flush the TLB (EPT)
3031 *
3032 * @returns VBox status code.
3033 * @param pVM The VM to operate on.
3034 * @param enmFlush Type of flush
3035 * @param GCPtr Virtual address of the page to flush
3036 */
3037static void vmxR0FlushVPID(PVM pVM, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3038{
3039 uint64_t descriptor[2];
3040
3041 Assert(pVM->hwaccm.s.vmx.fVPID);
3042 descriptor[0] = pVM->hwaccm.s.uCurrentASID;
3043 descriptor[1] = GCPtr;
3044 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3045 AssertRC(rc);
3046}
3047#endif /* HWACCM_VTX_WITH_VPID */
3048
3049/**
3050 * Invalidates a guest page
3051 *
3052 * @returns VBox status code.
3053 * @param pVM The VM to operate on.
3054 * @param GCVirt Page to invalidate
3055 */
3056VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
3057{
3058 bool fFlushPending = pVM->hwaccm.s.fForceTLBFlush;
3059
3060 /* Only relevant if we want to use VPID.
3061 * In the nested paging case we still see such calls, but
3062 * can safely ignore them. (e.g. after cr3 updates)
3063 */
3064#ifdef HWACCM_VTX_WITH_VPID
3065 /* Skip it if a TLB flush is already pending. */
3066 if ( !fFlushPending
3067 && pVM->hwaccm.s.vmx.fVPID)
3068 vmxR0FlushVPID(pVM, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3069#endif /* HWACCM_VTX_WITH_VPID */
3070
3071 return VINF_SUCCESS;
3072}
3073
3074/**
3075 * Invalidates a guest page by physical address
3076 *
3077 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3078 *
3079 * @returns VBox status code.
3080 * @param pVM The VM to operate on.
3081 * @param GCPhys Page to invalidate
3082 */
3083VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
3084{
3085 bool fFlushPending = pVM->hwaccm.s.fForceTLBFlush;
3086
3087 Assert(pVM->hwaccm.s.fNestedPaging);
3088
3089 /* Skip it if a TLB flush is already pending. */
3090 if (!fFlushPending)
3091 vmxR0FlushEPT(pVM, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3092
3093 return VINF_SUCCESS;
3094}
3095
3096#ifdef VBOX_STRICT
3097/**
3098 * Report world switch error and dump some useful debug info
3099 *
3100 * @param pVM The VM to operate on.
3101 * @param rc Return code
3102 * @param pCtx Current CPU context (not updated)
3103 */
3104static void VMXR0ReportWorldSwitchError(PVM pVM, int rc, PCPUMCTX pCtx)
3105{
3106 switch (rc)
3107 {
3108 case VERR_VMX_INVALID_VMXON_PTR:
3109 AssertFailed();
3110 break;
3111
3112 case VERR_VMX_UNABLE_TO_START_VM:
3113 case VERR_VMX_UNABLE_TO_RESUME_VM:
3114 {
3115 int rc;
3116 RTCCUINTREG exitReason, instrError, val;
3117
3118 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
3119 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
3120 AssertRC(rc);
3121 if (rc == VINF_SUCCESS)
3122 {
3123 RTGDTR gdtr;
3124 PX86DESCHC pDesc;
3125
3126 ASMGetGDTR(&gdtr);
3127
3128 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3129 Log(("Current stack %08x\n", &rc));
3130
3131
3132 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
3133 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
3134 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3135 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3136 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3137 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3138 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3139 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3140 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3141 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3142
3143 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3144 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3145
3146 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3147 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
3148
3149 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3150 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3151
3152 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
3153 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3154
3155 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3156 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3157
3158 if (val < gdtr.cbGdt)
3159 {
3160 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3161 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3162 }
3163
3164 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
3165 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3166 if (val < gdtr.cbGdt)
3167 {
3168 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3169 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3170 }
3171
3172 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
3173 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3174 if (val < gdtr.cbGdt)
3175 {
3176 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3177 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3178 }
3179
3180 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
3181 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
3182 if (val < gdtr.cbGdt)
3183 {
3184 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3185 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3186 }
3187
3188 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
3189 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
3190 if (val < gdtr.cbGdt)
3191 {
3192 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3193 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3194 }
3195
3196 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
3197 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
3198 if (val < gdtr.cbGdt)
3199 {
3200 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3201 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3202 }
3203
3204 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
3205 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
3206 if (val < gdtr.cbGdt)
3207 {
3208 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3209 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3210 }
3211
3212 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3213 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
3214
3215 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3216 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
3217 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3218 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
3219
3220 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
3221 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3222
3223 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3224 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
3225
3226 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3227 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
3228
3229 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3230 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
3231 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3232 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
3233
3234#if HC_ARCH_BITS == 64
3235 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
3236 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
3237 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3238 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3239 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3240#endif
3241 }
3242 break;
3243 }
3244
3245 default:
3246 /* impossible */
3247 AssertFailed();
3248 break;
3249 }
3250}
3251#endif /* VBOX_STRICT */
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