VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 17494

Last change on this file since 17494 was 17489, checked in by vboxsync, 16 years ago

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1/* $Id: HWVMXR0.cpp 17489 2009-03-06 16:35:33Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/param.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/string.h>
42#include "HWVMXR0.h"
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47#if defined(RT_ARCH_AMD64)
48# define VMX_IS_64BIT_HOST_MODE() (true)
49#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
50# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
51#else
52# define VMX_IS_64BIT_HOST_MODE() (false)
53#endif
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58/* IO operation lookup arrays. */
59static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
60static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
61
62#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
63/** See HWACCMR0A.asm. */
64extern "C" uint32_t g_fVMXIs64bitHost;
65#endif
66
67/*******************************************************************************
68* Local Functions *
69*******************************************************************************/
70static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
71static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
72static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
73static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
74static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
75static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
76static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
77#ifdef VBOX_STRICT
78static bool vmxR0IsValidReadField(uint32_t idxField);
79static bool vmxR0IsValidWriteField(uint32_t idxField);
80#endif
81
82static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
83{
84 if (rc == VERR_VMX_GENERIC)
85 {
86 RTCCUINTREG instrError;
87
88 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
89 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
90 }
91 pVM->hwaccm.s.lLastError = rc;
92}
93
94/**
95 * Sets up and activates VT-x on the current CPU
96 *
97 * @returns VBox status code.
98 * @param pCpu CPU info struct
99 * @param pVM The VM to operate on. (can be NULL after a resume!!)
100 * @param pvPageCpu Pointer to the global cpu page
101 * @param pPageCpuPhys Physical address of the global cpu page
102 */
103VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
104{
105 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
106 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
107
108#ifdef LOG_ENABLED
109 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
110#endif
111 if (pVM)
112 {
113 /* Set revision dword at the beginning of the VMXON structure. */
114 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
115 }
116
117 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
118 * (which can have very bad consequences!!!)
119 */
120
121 /* Make sure the VMX instructions don't cause #UD faults. */
122 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
123
124 /* Enter VMX Root Mode */
125 int rc = VMXEnable(pPageCpuPhys);
126 if (RT_FAILURE(rc))
127 {
128 if (pVM)
129 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
130 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
131 return VERR_VMX_VMXON_FAILED;
132 }
133 return VINF_SUCCESS;
134}
135
136/**
137 * Deactivates VT-x on the current CPU
138 *
139 * @returns VBox status code.
140 * @param pCpu CPU info struct
141 * @param pvPageCpu Pointer to the global cpu page
142 * @param pPageCpuPhys Physical address of the global cpu page
143 */
144VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
145{
146 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
147 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
148
149 /* Leave VMX Root Mode. */
150 VMXDisable();
151
152 /* And clear the X86_CR4_VMXE bit */
153 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
154
155#ifdef LOG_ENABLED
156 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
157#endif
158 return VINF_SUCCESS;
159}
160
161/**
162 * Does Ring-0 per VM VT-x init.
163 *
164 * @returns VBox status code.
165 * @param pVM The VM to operate on.
166 */
167VMMR0DECL(int) VMXR0InitVM(PVM pVM)
168{
169 int rc;
170
171#ifdef LOG_ENABLED
172 SUPR0Printf("VMXR0InitVM %x\n", pVM);
173#endif
174
175 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
176
177 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
178 {
179 /* Allocate one page for the virtual APIC mmio cache. */
180 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
181 AssertRC(rc);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
186 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
187 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
188 }
189 else
190 {
191 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
192 pVM->hwaccm.s.vmx.pAPIC = 0;
193 pVM->hwaccm.s.vmx.pAPICPhys = 0;
194 }
195
196 /* Allocate the MSR bitmap if this feature is supported. */
197 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
198 {
199 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
200 AssertRC(rc);
201 if (RT_FAILURE(rc))
202 return rc;
203
204 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
205 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
206 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
207 }
208
209#ifdef VBOX_WITH_CRASHDUMP_MAGIC
210 {
211 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
212 AssertRC(rc);
213 if (RT_FAILURE(rc))
214 return rc;
215
216 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
217 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
218
219 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
220 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
221 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
222 }
223#endif
224
225 /* Allocate VMCBs for all guest CPUs. */
226 for (unsigned i=0;i<pVM->cCPUs;i++)
227 {
228 PVMCPU pVCpu = &pVM->aCpus[i];
229
230 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
231
232 /* Allocate one page for the VM control structure (VMCS). */
233 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
234 AssertRC(rc);
235 if (RT_FAILURE(rc))
236 return rc;
237
238 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
239 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
240 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
241
242 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
243 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
244
245 /* Current guest paging mode. */
246 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
247
248#ifdef LOG_ENABLED
249 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
250#endif
251 }
252
253 return VINF_SUCCESS;
254}
255
256/**
257 * Does Ring-0 per VM VT-x termination.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262VMMR0DECL(int) VMXR0TermVM(PVM pVM)
263{
264 for (unsigned i=0;i<pVM->cCPUs;i++)
265 {
266 if (pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
267 {
268 RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, false);
269 pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
270 pVM->aCpus[i].hwaccm.s.vmx.pVMCS = 0;
271 pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys = 0;
272 }
273 }
274 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
275 {
276 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
277 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
278 pVM->hwaccm.s.vmx.pAPIC = 0;
279 pVM->hwaccm.s.vmx.pAPICPhys = 0;
280 }
281 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
282 {
283 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
284 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
285 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
286 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
287 }
288#ifdef VBOX_WITH_CRASHDUMP_MAGIC
289 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
290 {
291 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
292 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
293 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
294 pVM->hwaccm.s.vmx.pScratch = 0;
295 pVM->hwaccm.s.vmx.pScratchPhys = 0;
296 }
297#endif
298 return VINF_SUCCESS;
299}
300
301/**
302 * Sets up VT-x for the specified VM
303 *
304 * @returns VBox status code.
305 * @param pVM The VM to operate on.
306 */
307VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
308{
309 int rc = VINF_SUCCESS;
310 uint32_t val;
311
312 AssertReturn(pVM, VERR_INVALID_PARAMETER);
313
314 for (unsigned i=0;i<pVM->cCPUs;i++)
315 {
316 PVMCPU pVCpu = &pVM->aCpus[i];
317
318 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
319
320 /* Set revision dword at the beginning of the VMCS structure. */
321 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
322
323 /* Clear VM Control Structure. */
324 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
325 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
326 if (RT_FAILURE(rc))
327 goto vmx_end;
328
329 /* Activate the VM Control Structure. */
330 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
331 if (RT_FAILURE(rc))
332 goto vmx_end;
333
334 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
335 * Set required bits to one and zero according to the MSR capabilities.
336 */
337 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
338 /* External and non-maskable interrupts cause VM-exits. */
339 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
340 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
341
342 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
343 AssertRC(rc);
344
345 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
346 * Set required bits to one and zero according to the MSR capabilities.
347 */
348 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
349 /* Program which event cause VM-exits and which features we want to use. */
350 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
351 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
352 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
353 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
354 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
355 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
356
357 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
358 if (!pVM->hwaccm.s.fNestedPaging)
359 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
360 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
361 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
362
363 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
364 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
365 {
366 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
367 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
368 Assert(pVM->hwaccm.s.vmx.pAPIC);
369 }
370 else
371 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
372 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
373
374#ifdef VBOX_WITH_VTX_MSR_BITMAPS
375 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
376 {
377 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
378 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
379 }
380#endif
381
382 /* We will use the secondary control if it's present. */
383 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
384
385 /* Mask away the bits that the CPU doesn't support */
386 /** @todo make sure they don't conflict with the above requirements. */
387 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
388 pVCpu->hwaccm.s.vmx.proc_ctls = val;
389
390 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
391 AssertRC(rc);
392
393 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
394 {
395 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
396 * Set required bits to one and zero according to the MSR capabilities.
397 */
398 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
399 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
400
401#ifdef HWACCM_VTX_WITH_EPT
402 if (pVM->hwaccm.s.fNestedPaging)
403 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
404#endif /* HWACCM_VTX_WITH_EPT */
405#ifdef HWACCM_VTX_WITH_VPID
406 else
407 if (pVM->hwaccm.s.vmx.fVPID)
408 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
409#endif /* HWACCM_VTX_WITH_VPID */
410
411 /* Mask away the bits that the CPU doesn't support */
412 /** @todo make sure they don't conflict with the above requirements. */
413 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
414
415 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
416 AssertRC(rc);
417 }
418
419 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
420 * Set required bits to one and zero according to the MSR capabilities.
421 */
422 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
423 AssertRC(rc);
424
425 /* Forward all exception except #NM & #PF to the guest.
426 * We always need to check pagefaults since our shadow page table can be out of sync.
427 * And we always lazily sync the FPU & XMM state.
428 */
429
430 /** @todo Possible optimization:
431 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
432 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
433 * registers ourselves of course.
434 *
435 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
436 */
437
438 /* Don't filter page faults; all of them should cause a switch. */
439 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
441 AssertRC(rc);
442
443 /* Init TSC offset to zero. */
444 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
445 AssertRC(rc);
446
447 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
448 AssertRC(rc);
449
450 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
451 AssertRC(rc);
452
453 /* Set the MSR bitmap address. */
454 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
455 {
456 /* Optional */
457 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
458 AssertRC(rc);
459 }
460
461 /* Clear MSR controls. */
462 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
463 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
464 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
465 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
467 AssertRC(rc);
468
469 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
470 {
471 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
472 /* Optional */
473 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
474 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
475 AssertRC(rc);
476 }
477
478 /* Set link pointer to -1. Not currently used. */
479 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
480 AssertRC(rc);
481
482 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
483 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
484 AssertRC(rc);
485
486 /* Configure the VMCS read cache. */
487 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
488
489 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
490 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
491 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
492 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
493 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
494 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
495 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
496 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
497 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
498 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
499 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
500 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
501 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
502 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
503 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
504 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
505
506 VMX_SETUP_SELREG(ES, pCache);
507 VMX_SETUP_SELREG(SS, pCache);
508 VMX_SETUP_SELREG(CS, pCache);
509 VMX_SETUP_SELREG(DS, pCache);
510 VMX_SETUP_SELREG(FS, pCache);
511 VMX_SETUP_SELREG(GS, pCache);
512 VMX_SETUP_SELREG(LDTR, pCache);
513 VMX_SETUP_SELREG(TR, pCache);
514
515 /* Status code VMCS reads. */
516 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
517 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
518 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
525
526 if (pVM->hwaccm.s.fNestedPaging)
527 {
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
530 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
531 }
532 else
533 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
534 } /* for each VMCPU */
535
536 /* Choose the right TLB setup function. */
537 if (pVM->hwaccm.s.fNestedPaging)
538 {
539 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
540
541 /* Default values for flushing. */
542 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
543 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
544
545 /* If the capabilities specify we can do more, then make use of it. */
546 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
547 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
548 else
549 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
550 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
551
552 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
553 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
554 }
555#ifdef HWACCM_VTX_WITH_VPID
556 else
557 if (pVM->hwaccm.s.vmx.fVPID)
558 {
559 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
560
561 /* Default values for flushing. */
562 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
563 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
564
565 /* If the capabilities specify we can do more, then make use of it. */
566 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
567 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
568 else
569 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
570 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
571
572 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
574 }
575#endif /* HWACCM_VTX_WITH_VPID */
576 else
577 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
578
579vmx_end:
580 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
581 return rc;
582}
583
584
585/**
586 * Injects an event (trap or external interrupt)
587 *
588 * @returns VBox status code.
589 * @param pVM The VM to operate on.
590 * @param pVCpu The VMCPU to operate on.
591 * @param pCtx CPU Context
592 * @param intInfo VMX interrupt info
593 * @param cbInstr Opcode length of faulting instruction
594 * @param errCode Error code (optional)
595 */
596static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
597{
598 int rc;
599 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
600
601#ifdef VBOX_STRICT
602 if (iGate == 0xE)
603 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
604 else
605 if (iGate < 0x20)
606 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
607 else
608 {
609 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
610 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
611 Assert(pCtx->eflags.u32 & X86_EFL_IF);
612 }
613#endif
614
615#ifdef HWACCM_VMX_EMULATE_REALMODE
616 if (CPUMIsGuestInRealModeEx(pCtx))
617 {
618 RTGCPHYS GCPhysHandler;
619 uint16_t offset, ip;
620 RTSEL sel;
621
622 /* Injecting events doesn't work right with real mode emulation.
623 * (#GP if we try to inject external hardware interrupts)
624 * Inject the interrupt or trap directly instead.
625 */
626 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
627
628 /* Check if the interrupt handler is present. */
629 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
630 {
631 Log(("IDT cbIdt violation\n"));
632 if (iGate != X86_XCPT_DF)
633 {
634 RTGCUINTPTR intInfo;
635
636 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
637 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
638 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
639 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
640
641 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
642 }
643 Log(("Triple fault -> reset the VM!\n"));
644 return VINF_EM_RESET;
645 }
646 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
647 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
648 || iGate == 4)
649 {
650 ip = pCtx->ip + cbInstr;
651 }
652 else
653 ip = pCtx->ip;
654
655 /* Read the selector:offset pair of the interrupt handler. */
656 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
657 PGMPhysRead(pVM, GCPhysHandler, &offset, sizeof(offset));
658 PGMPhysRead(pVM, GCPhysHandler + 2, &sel, sizeof(sel));
659
660 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
661
662 /* Construct the stack frame. */
663 /** @todo should check stack limit. */
664 pCtx->sp -= 2;
665 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
666 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t));
667 pCtx->sp -= 2;
668 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
669 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t));
670 pCtx->sp -= 2;
671 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
672 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip));
673
674 /* Update the CPU state for executing the handler. */
675 pCtx->rip = offset;
676 pCtx->cs = sel;
677 pCtx->csHid.u64Base = sel << 4;
678 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
679
680 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
681 return VINF_SUCCESS;
682 }
683#endif /* HWACCM_VMX_EMULATE_REALMODE */
684
685 /* Set event injection state. */
686 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
687
688 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
689 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
690
691 AssertRC(rc);
692 return rc;
693}
694
695
696/**
697 * Checks for pending guest interrupts and injects them
698 *
699 * @returns VBox status code.
700 * @param pVM The VM to operate on.
701 * @param pVCpu The VMCPU to operate on.
702 * @param pCtx CPU Context
703 */
704static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
705{
706 int rc;
707
708 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
709 if (pVCpu->hwaccm.s.Event.fPending)
710 {
711 Log(("Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
712 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
713 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
714 AssertRC(rc);
715
716 pVCpu->hwaccm.s.Event.fPending = false;
717 return VINF_SUCCESS;
718 }
719
720 if (pVM->hwaccm.s.fInjectNMI)
721 {
722 RTGCUINTPTR intInfo;
723
724 intInfo = X86_XCPT_NMI;
725 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
726 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
727
728 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
729 AssertRC(rc);
730
731 pVM->hwaccm.s.fInjectNMI = false;
732 return VINF_SUCCESS;
733 }
734
735 /* When external interrupts are pending, we should exit the VM when IF is set. */
736 if ( !TRPMHasTrap(pVM)
737 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
738 {
739 if (!(pCtx->eflags.u32 & X86_EFL_IF))
740 {
741 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
742 {
743 LogFlow(("Enable irq window exit!\n"));
744 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
745 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
746 AssertRC(rc);
747 }
748 /* else nothing to do but wait */
749 }
750 else
751 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
752 {
753 uint8_t u8Interrupt;
754
755 rc = PDMGetInterrupt(pVM, &u8Interrupt);
756 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
757 if (RT_SUCCESS(rc))
758 {
759 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
760 AssertRC(rc);
761 }
762 else
763 {
764 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
765 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
766 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
767 /* Just continue */
768 }
769 }
770 else
771 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
772 }
773
774#ifdef VBOX_STRICT
775 if (TRPMHasTrap(pVM))
776 {
777 uint8_t u8Vector;
778 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
779 AssertRC(rc);
780 }
781#endif
782
783 if ( pCtx->eflags.u32 & X86_EFL_IF
784 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
785 && TRPMHasTrap(pVM)
786 )
787 {
788 uint8_t u8Vector;
789 int rc;
790 TRPMEVENT enmType;
791 RTGCUINTPTR intInfo;
792 RTGCUINT errCode;
793
794 /* If a new event is pending, then dispatch it now. */
795 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
796 AssertRC(rc);
797 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
798 Assert(enmType != TRPM_SOFTWARE_INT);
799
800 /* Clear the pending trap. */
801 rc = TRPMResetTrap(pVM);
802 AssertRC(rc);
803
804 intInfo = u8Vector;
805 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
806
807 if (enmType == TRPM_TRAP)
808 {
809 switch (u8Vector) {
810 case 8:
811 case 10:
812 case 11:
813 case 12:
814 case 13:
815 case 14:
816 case 17:
817 /* Valid error codes. */
818 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
819 break;
820 default:
821 break;
822 }
823 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
824 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
825 else
826 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
827 }
828 else
829 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
830
831 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
832 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
833 AssertRC(rc);
834 } /* if (interrupts can be dispatched) */
835
836 return VINF_SUCCESS;
837}
838
839/**
840 * Save the host state
841 *
842 * @returns VBox status code.
843 * @param pVM The VM to operate on.
844 * @param pVCpu The VMCPU to operate on.
845 */
846VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
847{
848 int rc = VINF_SUCCESS;
849
850 /*
851 * Host CPU Context
852 */
853 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
854 {
855 RTIDTR idtr;
856 RTGDTR gdtr;
857 RTSEL SelTR;
858 PX86DESCHC pDesc;
859 uintptr_t trBase;
860 RTSEL cs;
861 RTSEL ss;
862 uint64_t cr3;
863
864 /* Control registers */
865 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
866#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
867 if (VMX_IS_64BIT_HOST_MODE())
868 {
869 cr3 = hwaccmR0Get64bitCR3();
870 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
871 }
872 else
873#endif
874 {
875 cr3 = ASMGetCR3();
876 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
877 }
878 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
879 AssertRC(rc);
880 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
881 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
882 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
883
884 /* Selector registers. */
885#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
886 if (VMX_IS_64BIT_HOST_MODE())
887 {
888 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
889 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
890 }
891 else
892 {
893 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
894 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
895 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
896 }
897#else
898 cs = ASMGetCS();
899 ss = ASMGetSS();
900#endif
901 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
902 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
903 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
904 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
905 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
906 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
907#if HC_ARCH_BITS == 32
908 if (!VMX_IS_64BIT_HOST_MODE())
909 {
910 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
911 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
912 }
913#endif
914 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
915 SelTR = ASMGetTR();
916 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
917 AssertRC(rc);
918 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
919 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
920 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
921 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
922 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
923 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
924 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
925
926 /* GDTR & IDTR */
927#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
928 if (VMX_IS_64BIT_HOST_MODE())
929 {
930 X86XDTR64 gdtr64, idtr64;
931 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
932 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
933 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
934 AssertRC(rc);
935 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
936 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
937 gdtr.cbGdt = gdtr64.cb;
938 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
939 }
940 else
941#endif
942 {
943 ASMGetGDTR(&gdtr);
944 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
945 ASMGetIDTR(&idtr);
946 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
947 AssertRC(rc);
948 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
949 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
950 }
951
952
953 /* Save the base address of the TR selector. */
954 if (SelTR > gdtr.cbGdt)
955 {
956 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
957 return VERR_VMX_INVALID_HOST_STATE;
958 }
959
960#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
961 if (VMX_IS_64BIT_HOST_MODE())
962 {
963 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
964 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
965 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
966 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
967 AssertRC(rc);
968 }
969 else
970#endif
971 {
972 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
973#if HC_ARCH_BITS == 64
974 trBase = X86DESC64_BASE(*pDesc);
975#else
976 trBase = X86DESC_BASE(*pDesc);
977#endif
978 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
979 AssertRC(rc);
980 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
981 }
982
983 /* FS and GS base. */
984#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
985 if (VMX_IS_64BIT_HOST_MODE())
986 {
987 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
988 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
989 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
990 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
991 }
992#endif
993 AssertRC(rc);
994
995 /* Sysenter MSRs. */
996 /** @todo expensive!! */
997 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
998 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
999#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1000 if (VMX_IS_64BIT_HOST_MODE())
1001 {
1002 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1003 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1004 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1005 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1006 }
1007 else
1008 {
1009 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1010 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1011 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1012 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1013 }
1014#elif HC_ARCH_BITS == 32
1015 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1016 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1017 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1018 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1019#else
1020 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1021 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1022 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1023 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1024#endif
1025 AssertRC(rc);
1026
1027#if 0 /* @todo deal with 32/64 */
1028 /* Restore the host EFER - on CPUs that support it. */
1029 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1030 {
1031 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1032 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1033 AssertRC(rc);
1034 }
1035#endif
1036 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1037 }
1038 return rc;
1039}
1040
1041/**
1042 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1043 *
1044 * @param pVM The VM to operate on.
1045 * @param pVCpu The VMCPU to operate on.
1046 * @param pCtx Guest context
1047 */
1048static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1049{
1050 if (CPUMIsGuestInPAEModeEx(pCtx))
1051 {
1052 X86PDPE Pdpe;
1053
1054 for (unsigned i=0;i<4;i++)
1055 {
1056 Pdpe = PGMGstGetPaePDPtr(pVM, i);
1057 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1058 AssertRC(rc);
1059 }
1060 }
1061}
1062
1063/**
1064 * Update the exception bitmap according to the current CPU state
1065 *
1066 * @param pVM The VM to operate on.
1067 * @param pVCpu The VMCPU to operate on.
1068 * @param pCtx Guest context
1069 */
1070static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1071{
1072 uint32_t u32TrapMask;
1073 Assert(pCtx);
1074
1075 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1076#ifndef DEBUG
1077 if (pVM->hwaccm.s.fNestedPaging)
1078 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1079#endif
1080
1081 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1082 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1083 && !(pCtx->cr0 & X86_CR0_NE)
1084 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1085 {
1086 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1087 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1088 }
1089
1090#ifdef DEBUG /* till after branching, enable it by default then. */
1091 /* Intercept X86_XCPT_DB if stepping is enabled */
1092 if (DBGFIsStepping(pVM))
1093 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1094 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1095 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1096#endif
1097
1098#ifdef VBOX_STRICT
1099 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1100#endif
1101
1102# ifdef HWACCM_VMX_EMULATE_REALMODE
1103 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1104 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1105 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1106# endif /* HWACCM_VMX_EMULATE_REALMODE */
1107
1108 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1109 AssertRC(rc);
1110}
1111
1112/**
1113 * Loads the guest state
1114 *
1115 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1116 *
1117 * @returns VBox status code.
1118 * @param pVM The VM to operate on.
1119 * @param pVCpu The VMCPU to operate on.
1120 * @param pCtx Guest context
1121 */
1122VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1123{
1124 int rc = VINF_SUCCESS;
1125 RTGCUINTPTR val;
1126 X86EFLAGS eflags;
1127
1128 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1129 * Set required bits to one and zero according to the MSR capabilities.
1130 */
1131 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1132 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1133 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1134#if 0 /* @todo deal with 32/64 */
1135 /* Required for the EFER write below, not supported on all CPUs. */
1136 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1137#endif
1138 /* 64 bits guest mode? */
1139 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1140 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1141 /* else Must be zero when AMD64 is not available. */
1142
1143 /* Mask away the bits that the CPU doesn't support */
1144 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1145 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1146 AssertRC(rc);
1147
1148 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1149 * Set required bits to one and zero according to the MSR capabilities.
1150 */
1151 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1152
1153 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1154#if 0 /* @todo deal with 32/64 */
1155 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1156#else
1157 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1158#endif
1159
1160#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1161 if (VMX_IS_64BIT_HOST_MODE())
1162 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1163 /* else: Must be zero when AMD64 is not available. */
1164#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1165 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1166 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1167 else
1168 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1169#endif
1170 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1171 /* Don't acknowledge external interrupts on VM-exit. */
1172 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1173 AssertRC(rc);
1174
1175 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1176 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1177 {
1178#ifdef HWACCM_VMX_EMULATE_REALMODE
1179 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1180 {
1181 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1182 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1183 {
1184 /* Correct weird requirements for switching to protected mode. */
1185 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1186 && enmGuestMode >= PGMMODE_PROTECTED)
1187 {
1188 /* Flush the recompiler code cache as it's not unlikely
1189 * the guest will rewrite code it will later execute in real
1190 * mode (OpenBSD 4.0 is one such example)
1191 */
1192 REMFlushTBs(pVM);
1193
1194 /* DPL of all hidden selector registers must match the current CPL (0). */
1195 pCtx->csHid.Attr.n.u2Dpl = 0;
1196 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1197
1198 pCtx->dsHid.Attr.n.u2Dpl = 0;
1199 pCtx->esHid.Attr.n.u2Dpl = 0;
1200 pCtx->fsHid.Attr.n.u2Dpl = 0;
1201 pCtx->gsHid.Attr.n.u2Dpl = 0;
1202 pCtx->ssHid.Attr.n.u2Dpl = 0;
1203
1204 /* The limit must correspond to the granularity bit. */
1205 if (!pCtx->csHid.Attr.n.u1Granularity)
1206 pCtx->csHid.u32Limit &= 0xffff;
1207 if (!pCtx->dsHid.Attr.n.u1Granularity)
1208 pCtx->dsHid.u32Limit &= 0xffff;
1209 if (!pCtx->esHid.Attr.n.u1Granularity)
1210 pCtx->esHid.u32Limit &= 0xffff;
1211 if (!pCtx->fsHid.Attr.n.u1Granularity)
1212 pCtx->fsHid.u32Limit &= 0xffff;
1213 if (!pCtx->gsHid.Attr.n.u1Granularity)
1214 pCtx->gsHid.u32Limit &= 0xffff;
1215 if (!pCtx->ssHid.Attr.n.u1Granularity)
1216 pCtx->ssHid.u32Limit &= 0xffff;
1217 }
1218 else
1219 /* Switching from protected mode to real mode. */
1220 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1221 && enmGuestMode == PGMMODE_REAL)
1222 {
1223 /* The limit must also be set to 0xffff. */
1224 pCtx->csHid.u32Limit = 0xffff;
1225 pCtx->dsHid.u32Limit = 0xffff;
1226 pCtx->esHid.u32Limit = 0xffff;
1227 pCtx->fsHid.u32Limit = 0xffff;
1228 pCtx->gsHid.u32Limit = 0xffff;
1229 pCtx->ssHid.u32Limit = 0xffff;
1230
1231 Assert(pCtx->csHid.u64Base <= 0xfffff);
1232 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1233 Assert(pCtx->esHid.u64Base <= 0xfffff);
1234 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1235 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1236 }
1237 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1238 }
1239 else
1240 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1241 if ( CPUMIsGuestInRealModeEx(pCtx)
1242 && pCtx->csHid.u64Base == 0xffff0000)
1243 {
1244 pCtx->csHid.u64Base = 0xf0000;
1245 pCtx->cs = 0xf000;
1246 }
1247 }
1248#endif /* HWACCM_VMX_EMULATE_REALMODE */
1249
1250 VMX_WRITE_SELREG(ES, es);
1251 AssertRC(rc);
1252
1253 VMX_WRITE_SELREG(CS, cs);
1254 AssertRC(rc);
1255
1256 VMX_WRITE_SELREG(SS, ss);
1257 AssertRC(rc);
1258
1259 VMX_WRITE_SELREG(DS, ds);
1260 AssertRC(rc);
1261
1262 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1263 VMX_WRITE_SELREG(FS, fs);
1264 AssertRC(rc);
1265
1266 VMX_WRITE_SELREG(GS, gs);
1267 AssertRC(rc);
1268 }
1269
1270 /* Guest CPU context: LDTR. */
1271 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1272 {
1273 if (pCtx->ldtr == 0)
1274 {
1275 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1276 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1277 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1278 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1279 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1280 }
1281 else
1282 {
1283 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1284 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1285 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1286 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1287 }
1288 AssertRC(rc);
1289 }
1290 /* Guest CPU context: TR. */
1291 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1292 {
1293#ifdef HWACCM_VMX_EMULATE_REALMODE
1294 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1295 if (CPUMIsGuestInRealModeEx(pCtx))
1296 {
1297 RTGCPHYS GCPhys;
1298
1299 /* We convert it here every time as pci regions could be reconfigured. */
1300 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1301 AssertRC(rc);
1302
1303 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1304 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1305 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1306
1307 X86DESCATTR attr;
1308
1309 attr.u = 0;
1310 attr.n.u1Present = 1;
1311 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1312 val = attr.u;
1313 }
1314 else
1315#endif /* HWACCM_VMX_EMULATE_REALMODE */
1316 {
1317 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1318 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1319 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1320
1321 val = pCtx->trHid.Attr.u;
1322
1323 /* The TSS selector must be busy. */
1324 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1325 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1326 else
1327 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1328 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1329
1330 }
1331 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1332 AssertRC(rc);
1333 }
1334 /* Guest CPU context: GDTR. */
1335 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1336 {
1337 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1338 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1339 AssertRC(rc);
1340 }
1341 /* Guest CPU context: IDTR. */
1342 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1343 {
1344 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1345 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1346 AssertRC(rc);
1347 }
1348
1349 /*
1350 * Sysenter MSRs (unconditional)
1351 */
1352 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1353 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1354 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1355 AssertRC(rc);
1356
1357 /* Control registers */
1358 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1359 {
1360 val = pCtx->cr0;
1361 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1362 Log2(("Guest CR0-shadow %08x\n", val));
1363 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1364 {
1365 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1366 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1367 }
1368 else
1369 {
1370 /** @todo check if we support the old style mess correctly. */
1371 if (!(val & X86_CR0_NE))
1372 Log(("Forcing X86_CR0_NE!!!\n"));
1373
1374 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1375 }
1376 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1377 val |= X86_CR0_PE | X86_CR0_PG;
1378 if (pVM->hwaccm.s.fNestedPaging)
1379 {
1380 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1381 {
1382 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1383 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1384 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1385 }
1386 else
1387 {
1388 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1389 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1390 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1391 }
1392 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1393 AssertRC(rc);
1394 }
1395 else
1396 {
1397 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1398 val |= X86_CR0_WP;
1399 }
1400
1401 /* Always enable caching. */
1402 val &= ~(X86_CR0_CD|X86_CR0_NW);
1403
1404 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1405 Log2(("Guest CR0 %08x\n", val));
1406 /* CR0 flags owned by the host; if the guests attempts to change them, then
1407 * the VM will exit.
1408 */
1409 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1410 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1411 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1412 | X86_CR0_TS
1413 | X86_CR0_ET /* Bit not restored during VM-exit! */
1414 | X86_CR0_CD /* Bit not restored during VM-exit! */
1415 | X86_CR0_NW /* Bit not restored during VM-exit! */
1416 | X86_CR0_NE
1417 | X86_CR0_MP;
1418 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1419
1420 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1421 Log2(("Guest CR0-mask %08x\n", val));
1422 AssertRC(rc);
1423 }
1424 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1425 {
1426 /* CR4 */
1427 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1428 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1429 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1430 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1431
1432 if (!pVM->hwaccm.s.fNestedPaging)
1433 {
1434 switch(pVCpu->hwaccm.s.enmShadowMode)
1435 {
1436 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1437 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1438 case PGMMODE_32_BIT: /* 32-bit paging. */
1439 val &= ~X86_CR4_PAE;
1440 break;
1441
1442 case PGMMODE_PAE: /* PAE paging. */
1443 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1444 /** @todo use normal 32 bits paging */
1445 val |= X86_CR4_PAE;
1446 break;
1447
1448 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1449 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1450#ifdef VBOX_ENABLE_64_BITS_GUESTS
1451 break;
1452#else
1453 AssertFailed();
1454 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1455#endif
1456 default: /* shut up gcc */
1457 AssertFailed();
1458 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1459 }
1460 }
1461 else
1462 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1463 {
1464 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1465 val |= X86_CR4_PSE;
1466 /* Our identity mapping is a 32 bits page directory. */
1467 val &= ~X86_CR4_PAE;
1468 }
1469
1470#ifdef HWACCM_VMX_EMULATE_REALMODE
1471 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1472 if (CPUMIsGuestInRealModeEx(pCtx))
1473 val |= X86_CR4_VME;
1474#endif /* HWACCM_VMX_EMULATE_REALMODE */
1475
1476 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1477 Log2(("Guest CR4 %08x\n", val));
1478 /* CR4 flags owned by the host; if the guests attempts to change them, then
1479 * the VM will exit.
1480 */
1481 val = 0
1482#ifdef HWACCM_VMX_EMULATE_REALMODE
1483 | (pVM->hwaccm.s.vmx.pRealModeTSS ? X86_CR4_VME : 0)
1484#endif
1485 | X86_CR4_PAE
1486 | X86_CR4_PGE
1487 | X86_CR4_PSE
1488 | X86_CR4_VMXE;
1489 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1490
1491 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1492 Log2(("Guest CR4-mask %08x\n", val));
1493 AssertRC(rc);
1494 }
1495
1496 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1497 {
1498 if (pVM->hwaccm.s.fNestedPaging)
1499 {
1500 Assert(PGMGetHyperCR3(pVM));
1501 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVM);
1502
1503 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1504 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1505 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1506 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1507
1508 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1509 AssertRC(rc);
1510
1511 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1512 {
1513 RTGCPHYS GCPhys;
1514
1515 /* We convert it here every time as pci regions could be reconfigured. */
1516 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1517 AssertRC(rc);
1518
1519 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1520 * take care of the translation to host physical addresses.
1521 */
1522 val = GCPhys;
1523 }
1524 else
1525 {
1526 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1527 val = pCtx->cr3;
1528 /* Prefetch the four PDPT entries in PAE mode. */
1529 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1530 }
1531 }
1532 else
1533 {
1534 val = PGMGetHyperCR3(pVM);
1535 Assert(val || VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
1536 }
1537
1538 /* Save our shadow CR3 register. */
1539 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1540 AssertRC(rc);
1541 }
1542
1543 /* Debug registers. */
1544 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1545 {
1546 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1547 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1548
1549 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1550 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1551 pCtx->dr[7] |= 0x400; /* must be one */
1552
1553 /* Resync DR7 */
1554 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1555 AssertRC(rc);
1556
1557 /* Sync the debug state now if any breakpoint is armed. */
1558 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1559 && !CPUMIsGuestDebugStateActive(pVM)
1560 && !DBGFIsStepping(pVM))
1561 {
1562 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1563
1564 /* Disable drx move intercepts. */
1565 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1566 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1567 AssertRC(rc);
1568
1569 /* Save the host and load the guest debug state. */
1570 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1571 AssertRC(rc);
1572 }
1573
1574 /* IA32_DEBUGCTL MSR. */
1575 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1576 AssertRC(rc);
1577
1578 /** @todo do we really ever need this? */
1579 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1580 AssertRC(rc);
1581 }
1582
1583 /* EIP, ESP and EFLAGS */
1584 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1585 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1586 AssertRC(rc);
1587
1588 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1589 eflags = pCtx->eflags;
1590 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1591 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1592
1593#ifdef HWACCM_VMX_EMULATE_REALMODE
1594 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1595 if (CPUMIsGuestInRealModeEx(pCtx))
1596 {
1597 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1598
1599 eflags.Bits.u1VM = 1;
1600 eflags.Bits.u2IOPL = 3;
1601 }
1602#endif /* HWACCM_VMX_EMULATE_REALMODE */
1603 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1604 AssertRC(rc);
1605
1606 /* TSC offset. */
1607 uint64_t u64TSCOffset;
1608
1609 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1610 {
1611 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1612 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1613 AssertRC(rc);
1614
1615 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1616 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1617 AssertRC(rc);
1618 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1619 }
1620 else
1621 {
1622 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1623 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1624 AssertRC(rc);
1625 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1626 }
1627
1628 /* 64 bits guest mode? */
1629 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1630 {
1631#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1632 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1633#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1634 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1635#else
1636# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1637 if (!pVM->hwaccm.s.fAllow64BitGuests)
1638 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1639# endif
1640 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1641#endif
1642 /* Unconditionally update these as wrmsr might have changed them. */
1643 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1644 AssertRC(rc);
1645 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1646 AssertRC(rc);
1647 }
1648 else
1649 {
1650 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1651 }
1652
1653#if 0 /* @todo deal with 32/64 */
1654 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1655 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1656 {
1657 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1658 AssertRC(rc);
1659 }
1660#endif
1661
1662 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1663
1664 /* Done. */
1665 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1666
1667 return rc;
1668}
1669
1670/**
1671 * Syncs back the guest state
1672 *
1673 * @returns VBox status code.
1674 * @param pVM The VM to operate on.
1675 * @param pVCpu The VMCPU to operate on.
1676 * @param pCtx Guest context
1677 */
1678DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1679{
1680 RTGCUINTREG val, valShadow;
1681 RTGCUINTPTR uInterruptState;
1682 int rc;
1683
1684 /* Let's first sync back eip, esp, and eflags. */
1685 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1686 AssertRC(rc);
1687 pCtx->rip = val;
1688 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1689 AssertRC(rc);
1690 pCtx->rsp = val;
1691 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1692 AssertRC(rc);
1693 pCtx->eflags.u32 = val;
1694
1695 /* Take care of instruction fusing (sti, mov ss) */
1696 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1697 uInterruptState = val;
1698 if (uInterruptState != 0)
1699 {
1700 Assert(uInterruptState <= 2); /* only sti & mov ss */
1701 Log(("uInterruptState %x eip=%RGv\n", uInterruptState, pCtx->rip));
1702 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1703 }
1704 else
1705 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1706
1707 /* Control registers. */
1708 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1709 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1710 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1711 CPUMSetGuestCR0(pVM, val);
1712
1713 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1714 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1715 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1716 CPUMSetGuestCR4(pVM, val);
1717
1718 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1719 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1720 if ( pVM->hwaccm.s.fNestedPaging
1721 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1722 {
1723 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1724
1725 /* Can be updated behind our back in the nested paging case. */
1726 CPUMSetGuestCR2(pVM, pCache->cr2);
1727
1728 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1729
1730 if (val != pCtx->cr3)
1731 {
1732 CPUMSetGuestCR3(pVM, val);
1733 PGMUpdateCR3(pVM, val);
1734 }
1735 /* Prefetch the four PDPT entries in PAE mode. */
1736 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1737 }
1738
1739 /* Sync back DR7 here. */
1740 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1741 pCtx->dr[7] = val;
1742
1743 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1744 VMX_READ_SELREG(ES, es);
1745 VMX_READ_SELREG(SS, ss);
1746 VMX_READ_SELREG(CS, cs);
1747 VMX_READ_SELREG(DS, ds);
1748 VMX_READ_SELREG(FS, fs);
1749 VMX_READ_SELREG(GS, gs);
1750
1751 /*
1752 * System MSRs
1753 */
1754 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1755 pCtx->SysEnter.cs = val;
1756 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1757 pCtx->SysEnter.eip = val;
1758 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1759 pCtx->SysEnter.esp = val;
1760
1761 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1762 VMX_READ_SELREG(LDTR, ldtr);
1763
1764 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1765 pCtx->gdtr.cbGdt = val;
1766 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1767 pCtx->gdtr.pGdt = val;
1768
1769 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1770 pCtx->idtr.cbIdt = val;
1771 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1772 pCtx->idtr.pIdt = val;
1773
1774#ifdef HWACCM_VMX_EMULATE_REALMODE
1775 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1776 if (CPUMIsGuestInRealModeEx(pCtx))
1777 {
1778 /* Hide our emulation flags */
1779 pCtx->eflags.Bits.u1VM = 0;
1780 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1781
1782 /* Force a TR resync every time in case we switch modes. */
1783 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1784 }
1785 else
1786#endif /* HWACCM_VMX_EMULATE_REALMODE */
1787 {
1788 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1789 VMX_READ_SELREG(TR, tr);
1790 }
1791 return VINF_SUCCESS;
1792}
1793
1794/**
1795 * Dummy placeholder
1796 *
1797 * @param pVM The VM to operate on.
1798 * @param pVCpu The VMCPU to operate on.
1799 */
1800static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1801{
1802 NOREF(pVM);
1803 NOREF(pVCpu);
1804 return;
1805}
1806
1807/**
1808 * Setup the tagged TLB for EPT
1809 *
1810 * @returns VBox status code.
1811 * @param pVM The VM to operate on.
1812 * @param pVCpu The VMCPU to operate on.
1813 */
1814static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1815{
1816 PHWACCM_CPUINFO pCpu;
1817
1818 Assert(pVM->hwaccm.s.fNestedPaging);
1819 Assert(!pVM->hwaccm.s.vmx.fVPID);
1820
1821 /* Deal with tagged TLBs if VPID or EPT is supported. */
1822 pCpu = HWACCMR0GetCurrentCpu();
1823 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1824 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1825 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1826 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1827 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1828 {
1829 /* Force a TLB flush on VM entry. */
1830 pVCpu->hwaccm.s.fForceTLBFlush = true;
1831 }
1832 else
1833 Assert(!pCpu->fFlushTLB);
1834
1835 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1836 pCpu->fFlushTLB = false;
1837
1838 if (pVCpu->hwaccm.s.fForceTLBFlush)
1839 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1840
1841#ifdef VBOX_WITH_STATISTICS
1842 if (pVCpu->hwaccm.s.fForceTLBFlush)
1843 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1844 else
1845 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1846#endif
1847}
1848
1849#ifdef HWACCM_VTX_WITH_VPID
1850/**
1851 * Setup the tagged TLB for VPID
1852 *
1853 * @returns VBox status code.
1854 * @param pVM The VM to operate on.
1855 * @param pVCpu The VMCPU to operate on.
1856 */
1857static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1858{
1859 PHWACCM_CPUINFO pCpu;
1860
1861 Assert(pVM->hwaccm.s.vmx.fVPID);
1862 Assert(!pVM->hwaccm.s.fNestedPaging);
1863
1864 /* Deal with tagged TLBs if VPID or EPT is supported. */
1865 pCpu = HWACCMR0GetCurrentCpu();
1866 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1867 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1868 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1869 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1870 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1871 {
1872 /* Force a TLB flush on VM entry. */
1873 pVCpu->hwaccm.s.fForceTLBFlush = true;
1874 }
1875 else
1876 Assert(!pCpu->fFlushTLB);
1877
1878 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1879
1880 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1881 if (pVCpu->hwaccm.s.fForceTLBFlush)
1882 {
1883 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1884 || pCpu->fFlushTLB)
1885 {
1886 pCpu->fFlushTLB = false;
1887 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1888 pCpu->cTLBFlushes++;
1889 }
1890 else
1891 {
1892 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1893 pVCpu->hwaccm.s.fForceTLBFlush = false;
1894 }
1895
1896 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1897 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1898 }
1899 else
1900 {
1901 Assert(!pCpu->fFlushTLB);
1902
1903 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1904 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1905 }
1906 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1907 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1908 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1909
1910 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1911 AssertRC(rc);
1912
1913 if (pVCpu->hwaccm.s.fForceTLBFlush)
1914 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1915
1916#ifdef VBOX_WITH_STATISTICS
1917 if (pVCpu->hwaccm.s.fForceTLBFlush)
1918 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1919 else
1920 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1921#endif
1922}
1923#endif /* HWACCM_VTX_WITH_VPID */
1924
1925/**
1926 * Runs guest code in a VT-x VM.
1927 *
1928 * @returns VBox status code.
1929 * @param pVM The VM to operate on.
1930 * @param pVCpu The VMCPU to operate on.
1931 * @param pCtx Guest context
1932 */
1933VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1934{
1935 int rc = VINF_SUCCESS;
1936 RTGCUINTREG val;
1937 RTGCUINTREG exitReason, instrError, cbInstr;
1938 RTGCUINTPTR exitQualification;
1939 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1940 RTGCUINTPTR errCode, instrInfo;
1941 bool fSyncTPR = false;
1942 PHWACCM_CPUINFO pCpu = 0;
1943 unsigned cResume = 0;
1944#ifdef VBOX_STRICT
1945 RTCPUID idCpuCheck;
1946#endif
1947#ifdef VBOX_WITH_STATISTICS
1948 bool fStatEntryStarted = true;
1949 bool fStatExit2Started = false;
1950#endif
1951
1952 Log2(("\nE"));
1953
1954 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
1955
1956#ifdef VBOX_STRICT
1957 {
1958 RTCCUINTREG val;
1959
1960 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1961 AssertRC(rc);
1962 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1963
1964 /* allowed zero */
1965 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1966 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1967
1968 /* allowed one */
1969 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1970 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1971
1972 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1973 AssertRC(rc);
1974 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1975
1976 /* Must be set according to the MSR, but can be cleared in case of EPT. */
1977 if (pVM->hwaccm.s.fNestedPaging)
1978 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
1979 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1980 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1981
1982 /* allowed zero */
1983 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1984 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1985
1986 /* allowed one */
1987 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1988 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1989
1990 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1991 AssertRC(rc);
1992 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1993
1994 /* allowed zero */
1995 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1996 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1997
1998 /* allowed one */
1999 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2000 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2001
2002 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2003 AssertRC(rc);
2004 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2005
2006 /* allowed zero */
2007 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2008 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2009
2010 /* allowed one */
2011 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2012 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2013 }
2014#endif
2015
2016#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2017 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2018#endif
2019
2020 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2021 */
2022ResumeExecution:
2023 STAM_STATS({
2024 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2025 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2026 });
2027 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2028 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2029 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2030 Assert(!HWACCMR0SuspendPending());
2031
2032 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2033 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
2034 {
2035 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2036 rc = VINF_EM_RAW_INTERRUPT;
2037 goto end;
2038 }
2039
2040 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2041 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
2042 {
2043 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
2044 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
2045 {
2046 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2047 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2048 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2049 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2050 */
2051 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
2052 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2053 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2054 AssertRC(rc);
2055 }
2056 }
2057 else
2058 {
2059 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2060 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2061 AssertRC(rc);
2062 }
2063
2064 /* Check for pending actions that force us to go back to ring 3. */
2065 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
2066 {
2067 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
2068 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2069 rc = VINF_EM_RAW_TO_R3;
2070 goto end;
2071 }
2072 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2073 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
2074 {
2075 rc = VINF_EM_PENDING_REQUEST;
2076 goto end;
2077 }
2078
2079 /* When external interrupts are pending, we should exit the VM when IF is set. */
2080 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2081 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2082 if (RT_FAILURE(rc))
2083 goto end;
2084
2085 /** @todo check timers?? */
2086
2087 /* TPR caching using CR8 is only available in 64 bits mode */
2088 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2089 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2090 /**
2091 * @todo reduce overhead
2092 */
2093 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
2094 && pVM->hwaccm.s.vmx.pAPIC)
2095 {
2096 /* TPR caching in CR8 */
2097 uint8_t u8TPR;
2098 bool fPending;
2099
2100 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
2101 AssertRC(rc);
2102 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2103 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
2104
2105 /* Two options here:
2106 * - external interrupt pending, but masked by the TPR value.
2107 * -> a CR8 update that lower the current TPR value should cause an exit
2108 * - no pending interrupts
2109 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2110 */
2111 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
2112 AssertRC(rc);
2113
2114 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
2115 fSyncTPR = true;
2116 }
2117
2118#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2119 if ( pVM->hwaccm.s.fNestedPaging
2120# ifdef HWACCM_VTX_WITH_VPID
2121 || pVM->hwaccm.s.vmx.fVPID
2122# endif /* HWACCM_VTX_WITH_VPID */
2123 )
2124 {
2125 pCpu = HWACCMR0GetCurrentCpu();
2126 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2127 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2128 {
2129 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2130 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2131 else
2132 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2133 }
2134 if (pCpu->fFlushTLB)
2135 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2136 else
2137 if (pVCpu->hwaccm.s.fForceTLBFlush)
2138 LogFlow(("Manual TLB flush\n"));
2139 }
2140#endif
2141#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2142 PGMDynMapFlushAutoSet(pVCpu);
2143#endif
2144
2145 /*
2146 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2147 * (until the actual world switch)
2148 */
2149#ifdef VBOX_STRICT
2150 idCpuCheck = RTMpCpuId();
2151#endif
2152#ifdef LOG_LOGGING
2153 VMMR0LogFlushDisable(pVCpu);
2154#endif
2155 /* Save the host state first. */
2156 rc = VMXR0SaveHostState(pVM, pVCpu);
2157 if (rc != VINF_SUCCESS)
2158 goto end;
2159 /* Load the guest state */
2160 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2161 if (rc != VINF_SUCCESS)
2162 goto end;
2163
2164 /* Deal with tagged TLB setup and invalidation. */
2165 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2166
2167 /* Non-register state Guest Context */
2168 /** @todo change me according to cpu state */
2169 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2170 AssertRC(rc);
2171
2172 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2173
2174 /* Manual save and restore:
2175 * - General purpose registers except RIP, RSP
2176 *
2177 * Trashed:
2178 * - CR2 (we don't care)
2179 * - LDTR (reset to 0)
2180 * - DRx (presumably not changed at all)
2181 * - DR7 (reset to 0x400)
2182 * - EFLAGS (reset to RT_BIT(1); not relevant)
2183 *
2184 */
2185
2186
2187 /* All done! Let's start VM execution. */
2188 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2189#ifdef VBOX_STRICT
2190 Assert(idCpuCheck == RTMpCpuId());
2191#endif
2192
2193#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2194 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2195 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2196#endif
2197
2198 TMNotifyStartOfExecution(pVM);
2199 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2200 TMNotifyEndOfExecution(pVM);
2201
2202 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2203
2204 /* In case we execute a goto ResumeExecution later on. */
2205 pVCpu->hwaccm.s.fResumeVM = true;
2206 pVCpu->hwaccm.s.fForceTLBFlush = false;
2207
2208 /*
2209 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2210 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2211 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2212 */
2213 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2214 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2215
2216 if (rc != VINF_SUCCESS)
2217 {
2218 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2219 goto end;
2220 }
2221
2222 /* Success. Query the guest state and figure out what has happened. */
2223
2224 /* Investigate why there was a VM-exit. */
2225 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2226 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2227
2228 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2229 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2230 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2231 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2232 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2233 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2234 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2235 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2236 AssertRC(rc);
2237
2238 /* Sync back the guest state */
2239 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2240 AssertRC(rc);
2241
2242 /* Note! NOW IT'S SAFE FOR LOGGING! */
2243#ifdef LOG_LOGGING
2244 VMMR0LogFlushEnable(pVCpu);
2245#endif
2246 Log2(("Raw exit reason %08x\n", exitReason));
2247
2248 /* Check if an injected event was interrupted prematurely. */
2249 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2250 AssertRC(rc);
2251 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2252 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2253 /* Ignore 'int xx' as they'll be restarted anyway. */
2254 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2255 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2256 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2257 {
2258 pVCpu->hwaccm.s.Event.fPending = true;
2259 /* Error code present? */
2260 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2261 {
2262 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2263 AssertRC(rc);
2264 pVCpu->hwaccm.s.Event.errCode = val;
2265 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2266 }
2267 else
2268 {
2269 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2270 pVCpu->hwaccm.s.Event.errCode = 0;
2271 }
2272 }
2273#ifdef VBOX_STRICT
2274 else
2275 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2276 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2277 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2278 {
2279 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2280 }
2281
2282 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2283 HWACCMDumpRegs(pVM, pCtx);
2284#endif
2285
2286 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2287 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2288 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2289 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2290 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2291
2292 if (fSyncTPR)
2293 {
2294 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
2295 AssertRC(rc);
2296 }
2297
2298 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2299 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2300
2301 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2302 switch (exitReason)
2303 {
2304 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2305 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2306 {
2307 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2308
2309 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2310 {
2311 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2312 /* External interrupt; leave to allow it to be dispatched again. */
2313 rc = VINF_EM_RAW_INTERRUPT;
2314 break;
2315 }
2316 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2317 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2318 {
2319 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2320 /* External interrupt; leave to allow it to be dispatched again. */
2321 rc = VINF_EM_RAW_INTERRUPT;
2322 break;
2323
2324 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2325 AssertFailed(); /* can't come here; fails the first check. */
2326 break;
2327
2328 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2329 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2330 Assert(vector == 1 || vector == 3 || vector == 4);
2331 /* no break */
2332 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2333 Log2(("Hardware/software interrupt %d\n", vector));
2334 switch (vector)
2335 {
2336 case X86_XCPT_NM:
2337 {
2338 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2339
2340 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2341 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2342 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2343 if (rc == VINF_SUCCESS)
2344 {
2345 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2346
2347 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2348
2349 /* Continue execution. */
2350 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2351
2352 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2353 goto ResumeExecution;
2354 }
2355
2356 Log(("Forward #NM fault to the guest\n"));
2357 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2358 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2359 AssertRC(rc);
2360 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2361 goto ResumeExecution;
2362 }
2363
2364 case X86_XCPT_PF: /* Page fault */
2365 {
2366#ifdef DEBUG
2367 if (pVM->hwaccm.s.fNestedPaging)
2368 { /* A genuine pagefault.
2369 * Forward the trap to the guest by injecting the exception and resuming execution.
2370 */
2371 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2372
2373 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2374
2375 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2376
2377 /* Now we must update CR2. */
2378 pCtx->cr2 = exitQualification;
2379 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2380 AssertRC(rc);
2381
2382 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2383 goto ResumeExecution;
2384 }
2385#endif
2386 Assert(!pVM->hwaccm.s.fNestedPaging);
2387
2388 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2389 /* Exit qualification contains the linear address of the page fault. */
2390 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2391 TRPMSetErrorCode(pVM, errCode);
2392 TRPMSetFaultAddress(pVM, exitQualification);
2393
2394 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2395 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2396 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2397 if (rc == VINF_SUCCESS)
2398 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2399 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2400 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2401
2402 TRPMResetTrap(pVM);
2403
2404 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2405 goto ResumeExecution;
2406 }
2407 else
2408 if (rc == VINF_EM_RAW_GUEST_TRAP)
2409 { /* A genuine pagefault.
2410 * Forward the trap to the guest by injecting the exception and resuming execution.
2411 */
2412 Log2(("Forward page fault to the guest\n"));
2413
2414 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2415 /* The error code might have been changed. */
2416 errCode = TRPMGetErrorCode(pVM);
2417
2418 TRPMResetTrap(pVM);
2419
2420 /* Now we must update CR2. */
2421 pCtx->cr2 = exitQualification;
2422 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2423 AssertRC(rc);
2424
2425 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2426 goto ResumeExecution;
2427 }
2428#ifdef VBOX_STRICT
2429 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2430 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2431#endif
2432 /* Need to go back to the recompiler to emulate the instruction. */
2433 TRPMResetTrap(pVM);
2434 break;
2435 }
2436
2437 case X86_XCPT_MF: /* Floating point exception. */
2438 {
2439 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2440 if (!(pCtx->cr0 & X86_CR0_NE))
2441 {
2442 /* old style FPU error reporting needs some extra work. */
2443 /** @todo don't fall back to the recompiler, but do it manually. */
2444 rc = VINF_EM_RAW_EMULATE_INSTR;
2445 break;
2446 }
2447 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2448 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2449 AssertRC(rc);
2450
2451 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2452 goto ResumeExecution;
2453 }
2454
2455 case X86_XCPT_DB: /* Debug exception. */
2456 {
2457 uint64_t uDR6;
2458
2459 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2460 *
2461 * Exit qualification bits:
2462 * 3:0 B0-B3 which breakpoint condition was met
2463 * 12:4 Reserved (0)
2464 * 13 BD - debug register access detected
2465 * 14 BS - single step execution or branch taken
2466 * 63:15 Reserved (0)
2467 */
2468 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2469
2470 /* Note that we don't support guest and host-initiated debugging at the same time. */
2471 Assert(DBGFIsStepping(pVM) || CPUMIsGuestInRealModeEx(pCtx));
2472
2473 uDR6 = X86_DR6_INIT_VAL;
2474 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2475 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
2476 if (rc == VINF_EM_RAW_GUEST_TRAP)
2477 {
2478 /** @todo this isn't working, but we'll never get here normally. */
2479
2480 /* Update DR6 here. */
2481 pCtx->dr[6] = uDR6;
2482
2483 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2484 pCtx->dr[7] &= ~X86_DR7_GD;
2485
2486 /* Paranoia. */
2487 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2488 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2489 pCtx->dr[7] |= 0x400; /* must be one */
2490
2491 /* Resync DR7 */
2492 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2493 AssertRC(rc);
2494
2495 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2496 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2497 AssertRC(rc);
2498
2499 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2500 goto ResumeExecution;
2501 }
2502 /* Return to ring 3 to deal with the debug exit code. */
2503 break;
2504 }
2505
2506#ifdef DEBUG /* till after branching, enable by default after that. */
2507 case X86_XCPT_BP: /* Breakpoint. */
2508 {
2509 rc = DBGFR0Trap03Handler(pVM, CPUMCTX2CORE(pCtx));
2510 if (rc == VINF_EM_RAW_GUEST_TRAP)
2511 {
2512 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2513 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2514 AssertRC(rc);
2515 goto ResumeExecution;
2516 }
2517 if (rc == VINF_SUCCESS)
2518 goto ResumeExecution;
2519 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2520 break;
2521 }
2522#endif
2523
2524 case X86_XCPT_GP: /* General protection failure exception.*/
2525 {
2526 uint32_t cbSize;
2527
2528 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2529#ifdef VBOX_STRICT
2530 if (!CPUMIsGuestInRealModeEx(pCtx))
2531 {
2532 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2533 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2534 AssertRC(rc);
2535 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2536 goto ResumeExecution;
2537 }
2538#endif
2539 Assert(CPUMIsGuestInRealModeEx(pCtx));
2540
2541 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2542 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2543 if (rc == VINF_SUCCESS)
2544 {
2545 /* EIP has been updated already. */
2546
2547 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2548 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2549
2550 /* Only resume if successful. */
2551 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2552 goto ResumeExecution;
2553 }
2554 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2555 break;
2556 }
2557
2558#ifdef VBOX_STRICT
2559 case X86_XCPT_DE: /* Divide error. */
2560 case X86_XCPT_UD: /* Unknown opcode exception. */
2561 case X86_XCPT_SS: /* Stack segment exception. */
2562 case X86_XCPT_NP: /* Segment not present exception. */
2563 {
2564 switch(vector)
2565 {
2566 case X86_XCPT_DE:
2567 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2568 break;
2569 case X86_XCPT_UD:
2570 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2571 break;
2572 case X86_XCPT_SS:
2573 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2574 break;
2575 case X86_XCPT_NP:
2576 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2577 break;
2578 }
2579
2580 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2581 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2582 AssertRC(rc);
2583
2584 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2585 goto ResumeExecution;
2586 }
2587#endif
2588 default:
2589#ifdef HWACCM_VMX_EMULATE_REALMODE
2590 if (CPUMIsGuestInRealModeEx(pCtx))
2591 {
2592 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2593 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2594 AssertRC(rc);
2595
2596 /* Go back to ring 3 in case of a triple fault. */
2597 if ( vector == X86_XCPT_DF
2598 && rc == VINF_EM_RESET)
2599 break;
2600
2601 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2602 goto ResumeExecution;
2603 }
2604#endif
2605 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2606 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2607 break;
2608 } /* switch (vector) */
2609
2610 break;
2611
2612 default:
2613 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2614 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2615 break;
2616 }
2617
2618 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2619 break;
2620 }
2621
2622 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2623 {
2624 RTGCPHYS GCPhys;
2625
2626 Assert(pVM->hwaccm.s.fNestedPaging);
2627
2628 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2629 AssertRC(rc);
2630 Assert(((exitQualification >> 7) & 3) != 2);
2631
2632 /* Determine the kind of violation. */
2633 errCode = 0;
2634 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2635 errCode |= X86_TRAP_PF_ID;
2636
2637 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2638 errCode |= X86_TRAP_PF_RW;
2639
2640 /* If the page is present, then it's a page level protection fault. */
2641 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2642 errCode |= X86_TRAP_PF_P;
2643
2644 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2645
2646 /* GCPhys contains the guest physical address of the page fault. */
2647 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2648 TRPMSetErrorCode(pVM, errCode);
2649 TRPMSetFaultAddress(pVM, GCPhys);
2650
2651 /* Handle the pagefault trap for the nested shadow table. */
2652 rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2653 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2654 if (rc == VINF_SUCCESS)
2655 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2656 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
2657 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
2658
2659 TRPMResetTrap(pVM);
2660
2661 goto ResumeExecution;
2662 }
2663
2664#ifdef VBOX_STRICT
2665 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2666 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2667#endif
2668 /* Need to go back to the recompiler to emulate the instruction. */
2669 TRPMResetTrap(pVM);
2670 break;
2671 }
2672
2673 case VMX_EXIT_EPT_MISCONFIG:
2674 {
2675 RTGCPHYS GCPhys;
2676
2677 Assert(pVM->hwaccm.s.fNestedPaging);
2678
2679 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2680 AssertRC(rc);
2681
2682 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
2683 break;
2684 }
2685
2686 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2687 /* Clear VM-exit on IF=1 change. */
2688 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2689 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2690 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2691 AssertRC(rc);
2692 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
2693 goto ResumeExecution; /* we check for pending guest interrupts there */
2694
2695 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2696 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2697 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
2698 /* Skip instruction and continue directly. */
2699 pCtx->rip += cbInstr;
2700 /* Continue execution.*/
2701 goto ResumeExecution;
2702
2703 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2704 {
2705 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2706 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
2707 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
2708 if (rc == VINF_SUCCESS)
2709 {
2710 /* Update EIP and continue execution. */
2711 Assert(cbInstr == 2);
2712 pCtx->rip += cbInstr;
2713 goto ResumeExecution;
2714 }
2715 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
2716 rc = VINF_EM_RAW_EMULATE_INSTR;
2717 break;
2718 }
2719
2720 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2721 {
2722 Log2(("VMX: Rdtsc\n"));
2723 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2724 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
2725 if (rc == VINF_SUCCESS)
2726 {
2727 /* Update EIP and continue execution. */
2728 Assert(cbInstr == 2);
2729 pCtx->rip += cbInstr;
2730 goto ResumeExecution;
2731 }
2732 AssertMsgFailed(("EMU: rdtsc failed with %Rrc\n", rc));
2733 rc = VINF_EM_RAW_EMULATE_INSTR;
2734 break;
2735 }
2736
2737 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2738 {
2739 Log2(("VMX: invlpg\n"));
2740 Assert(!pVM->hwaccm.s.fNestedPaging);
2741
2742 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2743 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
2744 if (rc == VINF_SUCCESS)
2745 {
2746 /* Update EIP and continue execution. */
2747 pCtx->rip += cbInstr;
2748 goto ResumeExecution;
2749 }
2750 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
2751 break;
2752 }
2753
2754 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2755 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2756 {
2757 uint32_t cbSize;
2758
2759 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2760 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
2761 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2762 if (rc == VINF_SUCCESS)
2763 {
2764 /* EIP has been updated already. */
2765
2766 /* Only resume if successful. */
2767 goto ResumeExecution;
2768 }
2769 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
2770 break;
2771 }
2772
2773 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2774 {
2775 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2776
2777 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
2778 {
2779 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
2780 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
2781 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
2782 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
2783 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
2784 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
2785
2786 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
2787 {
2788 case 0:
2789 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
2790 break;
2791 case 2:
2792 break;
2793 case 3:
2794 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
2795 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2796 break;
2797 case 4:
2798 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2799 break;
2800 case 8:
2801 /* CR8 contains the APIC TPR */
2802 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2803 break;
2804
2805 default:
2806 AssertFailed();
2807 break;
2808 }
2809 /* Check if a sync operation is pending. */
2810 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2811 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2812 {
2813 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2814 AssertRC(rc);
2815 }
2816 break;
2817
2818 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
2819 Log2(("VMX: mov x, crx\n"));
2820 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
2821
2822 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
2823
2824 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
2825 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2826
2827 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
2828 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
2829 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
2830 break;
2831
2832 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2833 Log2(("VMX: clts\n"));
2834 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
2835 rc = EMInterpretCLTS(pVM);
2836 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2837 break;
2838
2839 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2840 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2841 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
2842 rc = EMInterpretLMSW(pVM, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2843 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2844 break;
2845 }
2846
2847 /* Update EIP if no error occurred. */
2848 if (RT_SUCCESS(rc))
2849 pCtx->rip += cbInstr;
2850
2851 if (rc == VINF_SUCCESS)
2852 {
2853 /* Only resume if successful. */
2854 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2855 goto ResumeExecution;
2856 }
2857 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2858 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2859 break;
2860 }
2861
2862 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2863 {
2864 if (!DBGFIsStepping(pVM))
2865 {
2866 /* Disable drx move intercepts. */
2867 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2868 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2869 AssertRC(rc);
2870
2871 /* Save the host and load the guest debug state. */
2872 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
2873 AssertRC(rc);
2874
2875#ifdef VBOX_WITH_STATISTICS
2876 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2877 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2878 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2879 else
2880 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2881#endif
2882
2883 goto ResumeExecution;
2884 }
2885
2886 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2887 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2888 {
2889 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2890 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2891 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2892 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2893 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2894 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2895 Log2(("DR7=%08x\n", pCtx->dr[7]));
2896 }
2897 else
2898 {
2899 Log2(("VMX: mov x, drx\n"));
2900 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2901 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2902 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2903 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2904 }
2905 /* Update EIP if no error occurred. */
2906 if (RT_SUCCESS(rc))
2907 pCtx->rip += cbInstr;
2908
2909 if (rc == VINF_SUCCESS)
2910 {
2911 /* Only resume if successful. */
2912 goto ResumeExecution;
2913 }
2914 Assert(rc == VERR_EM_INTERPRETER);
2915 break;
2916 }
2917
2918 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2919 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2920 {
2921 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
2922 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2923 uint32_t uPort;
2924 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2925
2926 /** @todo necessary to make the distinction? */
2927 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2928 {
2929 uPort = pCtx->edx & 0xffff;
2930 }
2931 else
2932 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2933
2934 /* paranoia */
2935 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2936 {
2937 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2938 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
2939 break;
2940 }
2941
2942 uint32_t cbSize = g_aIOSize[uIOWidth];
2943
2944 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2945 {
2946 /* ins/outs */
2947 DISCPUSTATE Cpu;
2948
2949 /* Disassemble manually to deal with segment prefixes. */
2950 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
2951 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
2952 rc = EMInterpretDisasOne(pVM, CPUMCTX2CORE(pCtx), &Cpu, NULL);
2953 if (rc == VINF_SUCCESS)
2954 {
2955 if (fIOWrite)
2956 {
2957 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
2958 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2959 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
2960 }
2961 else
2962 {
2963 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
2964 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2965 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
2966 }
2967 }
2968 else
2969 rc = VINF_EM_RAW_EMULATE_INSTR;
2970 }
2971 else
2972 {
2973 /* normal in/out */
2974 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
2975
2976 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2977
2978 if (fIOWrite)
2979 {
2980 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2981 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2982 }
2983 else
2984 {
2985 uint32_t u32Val = 0;
2986
2987 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2988 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2989 if (IOM_SUCCESS(rc))
2990 {
2991 /* Write back to the EAX register. */
2992 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2993 }
2994 }
2995 }
2996 /*
2997 * Handled the I/O return codes.
2998 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2999 */
3000 if (IOM_SUCCESS(rc))
3001 {
3002 /* Update EIP and continue execution. */
3003 pCtx->rip += cbInstr;
3004 if (RT_LIKELY(rc == VINF_SUCCESS))
3005 {
3006 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3007 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3008 {
3009 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3010 for (unsigned i=0;i<4;i++)
3011 {
3012 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3013
3014 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3015 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3016 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3017 {
3018 uint64_t uDR6;
3019
3020 Assert(CPUMIsGuestDebugStateActive(pVM));
3021
3022 uDR6 = ASMGetDR6();
3023
3024 /* Clear all breakpoint status flags and set the one we just hit. */
3025 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3026 uDR6 |= (uint64_t)RT_BIT(i);
3027
3028 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3029 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3030 * the contents have been read.
3031 */
3032 ASMSetDR6(uDR6);
3033
3034 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3035 pCtx->dr[7] &= ~X86_DR7_GD;
3036
3037 /* Paranoia. */
3038 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3039 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3040 pCtx->dr[7] |= 0x400; /* must be one */
3041
3042 /* Resync DR7 */
3043 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3044 AssertRC(rc);
3045
3046 /* Construct inject info. */
3047 intInfo = X86_XCPT_DB;
3048 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3049 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3050
3051 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3052 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3053 AssertRC(rc);
3054
3055 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3056 goto ResumeExecution;
3057 }
3058 }
3059 }
3060
3061 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3062 goto ResumeExecution;
3063 }
3064 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3065 break;
3066 }
3067
3068#ifdef VBOX_STRICT
3069 if (rc == VINF_IOM_HC_IOPORT_READ)
3070 Assert(!fIOWrite);
3071 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3072 Assert(fIOWrite);
3073 else
3074 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3075#endif
3076 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3077 break;
3078 }
3079
3080 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3081 LogFlow(("VMX_EXIT_TPR\n"));
3082 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3083 goto ResumeExecution;
3084
3085 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3086 goto ResumeExecution;
3087
3088 default:
3089 /* The rest is handled after syncing the entire CPU state. */
3090 break;
3091 }
3092
3093 /* Note: the guest state isn't entirely synced back at this stage. */
3094
3095 /* Investigate why there was a VM-exit. (part 2) */
3096 switch (exitReason)
3097 {
3098 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3099 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3100 case VMX_EXIT_EPT_VIOLATION:
3101 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3102 /* Already handled above. */
3103 break;
3104
3105 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3106 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3107 break;
3108
3109 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3110 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3111 rc = VINF_EM_RAW_INTERRUPT;
3112 AssertFailed(); /* Can't happen. Yet. */
3113 break;
3114
3115 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3116 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3117 rc = VINF_EM_RAW_INTERRUPT;
3118 AssertFailed(); /* Can't happen afaik. */
3119 break;
3120
3121 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3122 rc = VERR_EM_INTERPRETER;
3123 break;
3124
3125 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3126 /** Check if external interrupts are pending; if so, don't switch back. */
3127 pCtx->rip++; /* skip hlt */
3128 if ( pCtx->eflags.Bits.u1IF
3129 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
3130 goto ResumeExecution;
3131
3132 rc = VINF_EM_HALT;
3133 break;
3134
3135 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3136 AssertFailed(); /* can't happen. */
3137 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3138 break;
3139
3140 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3141 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3142 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3143 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3144 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3145 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3146 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3147 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3148 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3149 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3150 /** @todo inject #UD immediately */
3151 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3152 break;
3153
3154 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3155 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3156 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3157 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3158 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3159 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3160 /* already handled above */
3161 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3162 || rc == VINF_EM_RAW_INTERRUPT
3163 || rc == VERR_EM_INTERPRETER
3164 || rc == VINF_EM_RAW_EMULATE_INSTR
3165 || rc == VINF_PGM_SYNC_CR3
3166 || rc == VINF_IOM_HC_IOPORT_READ
3167 || rc == VINF_IOM_HC_IOPORT_WRITE
3168 || rc == VINF_EM_RAW_GUEST_TRAP
3169 || rc == VINF_TRPM_XCPT_DISPATCHED
3170 || rc == VINF_EM_RESCHEDULE_REM,
3171 ("rc = %d\n", rc));
3172 break;
3173
3174 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3175 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3176 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3177 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3178 rc = VERR_EM_INTERPRETER;
3179 break;
3180
3181 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3182 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3183 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3184 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3185 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3186 break;
3187
3188 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3189 Assert(rc == VINF_EM_RAW_INTERRUPT);
3190 break;
3191
3192 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3193 {
3194#ifdef VBOX_STRICT
3195 RTCCUINTREG val = 0;
3196
3197 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3198
3199 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3200 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3201
3202 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3203 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3204
3205 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3206 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3207
3208 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3209 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3210
3211 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3212 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3213
3214 VMX_LOG_SELREG(CS, "CS");
3215 VMX_LOG_SELREG(DS, "DS");
3216 VMX_LOG_SELREG(ES, "ES");
3217 VMX_LOG_SELREG(FS, "FS");
3218 VMX_LOG_SELREG(GS, "GS");
3219 VMX_LOG_SELREG(SS, "SS");
3220 VMX_LOG_SELREG(TR, "TR");
3221 VMX_LOG_SELREG(LDTR, "LDTR");
3222
3223 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3224 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3225 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3226 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3227#endif /* VBOX_STRICT */
3228 rc = VERR_VMX_INVALID_GUEST_STATE;
3229 break;
3230 }
3231
3232 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3233 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3234 default:
3235 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3236 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3237 break;
3238
3239 }
3240end:
3241
3242 /* Signal changes for the recompiler. */
3243 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3244
3245 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3246 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3247 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3248 {
3249 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3250 /* On the next entry we'll only sync the host context. */
3251 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3252 }
3253 else
3254 {
3255 /* On the next entry we'll sync everything. */
3256 /** @todo we can do better than this */
3257 /* Not in the VINF_PGM_CHANGE_MODE though! */
3258 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3259 }
3260
3261 /* translate into a less severe return code */
3262 if (rc == VERR_EM_INTERPRETER)
3263 rc = VINF_EM_RAW_EMULATE_INSTR;
3264 else
3265 /* Try to extract more information about what might have gone wrong here. */
3266 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3267 {
3268 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3269 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3270 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3271 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3272 }
3273
3274 STAM_STATS({
3275 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3276 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3277 });
3278 Log2(("X"));
3279 return rc;
3280}
3281
3282
3283/**
3284 * Enters the VT-x session
3285 *
3286 * @returns VBox status code.
3287 * @param pVM The VM to operate on.
3288 * @param pVCpu The VMCPU to operate on.
3289 * @param pCpu CPU info struct
3290 */
3291VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3292{
3293 Assert(pVM->hwaccm.s.vmx.fSupported);
3294
3295 unsigned cr4 = ASMGetCR4();
3296 if (!(cr4 & X86_CR4_VMXE))
3297 {
3298 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3299 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3300 }
3301
3302 /* Activate the VM Control Structure. */
3303 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3304 if (RT_FAILURE(rc))
3305 return rc;
3306
3307 pVCpu->hwaccm.s.fResumeVM = false;
3308 return VINF_SUCCESS;
3309}
3310
3311
3312/**
3313 * Leaves the VT-x session
3314 *
3315 * @returns VBox status code.
3316 * @param pVM The VM to operate on.
3317 * @param pVCpu The VMCPU to operate on.
3318 * @param pCtx CPU context
3319 */
3320VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3321{
3322 Assert(pVM->hwaccm.s.vmx.fSupported);
3323
3324 /* Save the guest debug state if necessary. */
3325 if (CPUMIsGuestDebugStateActive(pVM))
3326 {
3327 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3328
3329 /* Enable drx move intercepts again. */
3330 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3331 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3332 AssertRC(rc);
3333
3334 /* Resync the debug registers the next time. */
3335 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3336 }
3337 else
3338 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3339
3340 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3341 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3342 AssertRC(rc);
3343
3344 return VINF_SUCCESS;
3345}
3346
3347/**
3348 * Flush the TLB (EPT)
3349 *
3350 * @returns VBox status code.
3351 * @param pVM The VM to operate on.
3352 * @param pVCpu The VM CPU to operate on.
3353 * @param enmFlush Type of flush
3354 * @param GCPhys Physical address of the page to flush
3355 */
3356static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3357{
3358 uint64_t descriptor[2];
3359
3360 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3361 Assert(pVM->hwaccm.s.fNestedPaging);
3362 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3363 descriptor[1] = GCPhys;
3364 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3365 AssertRC(rc);
3366}
3367
3368#ifdef HWACCM_VTX_WITH_VPID
3369/**
3370 * Flush the TLB (EPT)
3371 *
3372 * @returns VBox status code.
3373 * @param pVM The VM to operate on.
3374 * @param pVCpu The VM CPU to operate on.
3375 * @param enmFlush Type of flush
3376 * @param GCPtr Virtual address of the page to flush
3377 */
3378static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3379{
3380#if HC_ARCH_BITS == 32
3381 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3382 if ( CPUMIsGuestInLongMode(pVM)
3383 && !VMX_IS_64BIT_HOST_MODE())
3384 {
3385 pVCpu->hwaccm.s.fForceTLBFlush = true;
3386 }
3387 else
3388#endif
3389 {
3390 uint64_t descriptor[2];
3391
3392 Assert(pVM->hwaccm.s.vmx.fVPID);
3393 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3394 descriptor[1] = GCPtr;
3395 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3396 AssertRC(rc);
3397 }
3398}
3399#endif /* HWACCM_VTX_WITH_VPID */
3400
3401/**
3402 * Invalidates a guest page
3403 *
3404 * @returns VBox status code.
3405 * @param pVM The VM to operate on.
3406 * @param pVCpu The VM CPU to operate on.
3407 * @param GCVirt Page to invalidate
3408 */
3409VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3410{
3411 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3412
3413 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3414
3415 /* Only relevant if we want to use VPID.
3416 * In the nested paging case we still see such calls, but
3417 * can safely ignore them. (e.g. after cr3 updates)
3418 */
3419#ifdef HWACCM_VTX_WITH_VPID
3420 /* Skip it if a TLB flush is already pending. */
3421 if ( !fFlushPending
3422 && pVM->hwaccm.s.vmx.fVPID)
3423 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3424#endif /* HWACCM_VTX_WITH_VPID */
3425
3426 return VINF_SUCCESS;
3427}
3428
3429/**
3430 * Invalidates a guest page by physical address
3431 *
3432 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3433 *
3434 * @returns VBox status code.
3435 * @param pVM The VM to operate on.
3436 * @param pVCpu The VM CPU to operate on.
3437 * @param GCPhys Page to invalidate
3438 */
3439VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3440{
3441 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3442
3443 Assert(pVM->hwaccm.s.fNestedPaging);
3444
3445 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3446
3447 /* Skip it if a TLB flush is already pending. */
3448 if (!fFlushPending)
3449 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3450
3451 return VINF_SUCCESS;
3452}
3453
3454/**
3455 * Report world switch error and dump some useful debug info
3456 *
3457 * @param pVM The VM to operate on.
3458 * @param pVCpu The VMCPU to operate on.
3459 * @param rc Return code
3460 * @param pCtx Current CPU context (not updated)
3461 */
3462static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3463{
3464 switch (rc)
3465 {
3466 case VERR_VMX_INVALID_VMXON_PTR:
3467 AssertFailed();
3468 break;
3469
3470 case VERR_VMX_UNABLE_TO_START_VM:
3471 case VERR_VMX_UNABLE_TO_RESUME_VM:
3472 {
3473 int rc;
3474 RTCCUINTREG exitReason, instrError;
3475
3476 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3477 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3478 AssertRC(rc);
3479 if (rc == VINF_SUCCESS)
3480 {
3481 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3482 Log(("Current stack %08x\n", &rc));
3483
3484 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3485 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3486
3487#ifdef VBOX_STRICT
3488 RTGDTR gdtr;
3489 PX86DESCHC pDesc;
3490 RTCCUINTREG val;
3491
3492 ASMGetGDTR(&gdtr);
3493
3494 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3495 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3496 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3497 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3498 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3499 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3500 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3501 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3502 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3503 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3504
3505 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3506 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3507
3508 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3509 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3510
3511 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3512 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3513
3514 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3515 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3516
3517 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3518 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3519
3520 if (val < gdtr.cbGdt)
3521 {
3522 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3523 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3524 }
3525
3526 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3527 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3528 if (val < gdtr.cbGdt)
3529 {
3530 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3531 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3532 }
3533
3534 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
3535 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3536 if (val < gdtr.cbGdt)
3537 {
3538 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3539 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3540 }
3541
3542 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
3543 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
3544 if (val < gdtr.cbGdt)
3545 {
3546 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3547 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3548 }
3549
3550 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
3551 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
3552 if (val < gdtr.cbGdt)
3553 {
3554 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3555 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3556 }
3557
3558 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
3559 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
3560 if (val < gdtr.cbGdt)
3561 {
3562 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3563 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3564 }
3565
3566 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
3567 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
3568 if (val < gdtr.cbGdt)
3569 {
3570 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3571 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3572 }
3573
3574 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3575 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
3576
3577 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3578 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
3579 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3580 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
3581
3582 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
3583 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3584
3585 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3586 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
3587
3588 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3589 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
3590
3591 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3592 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
3593 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3594 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
3595
3596# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3597 if (VMX_IS_64BIT_HOST_MODE())
3598 {
3599 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
3600 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
3601 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3602 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3603 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3604 }
3605# endif
3606#endif /* VBOX_STRICT */
3607 }
3608 break;
3609 }
3610
3611 default:
3612 /* impossible */
3613 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
3614 break;
3615 }
3616}
3617
3618#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3619/**
3620 * Prepares for and executes VMLAUNCH (64 bits guest mode)
3621 *
3622 * @returns VBox status code
3623 * @param fResume vmlauch/vmresume
3624 * @param pCtx Guest context
3625 * @param pCache VMCS cache
3626 * @param pVM The VM to operate on.
3627 * @param pVCpu The VMCPU to operate on.
3628 */
3629DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
3630{
3631 uint32_t aParam[6];
3632 PHWACCM_CPUINFO pCpu;
3633 RTHCPHYS pPageCpuPhys;
3634 int rc;
3635
3636 pCpu = HWACCMR0GetCurrentCpu();
3637 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3638
3639#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3640 pCache->uPos = 1;
3641 pCache->interPD = PGMGetInterPaeCR3(pVM);
3642 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
3643#endif
3644
3645#ifdef DEBUG
3646 pCache->TestIn.pPageCpuPhys = 0;
3647 pCache->TestIn.pVMCSPhys = 0;
3648 pCache->TestIn.pCache = 0;
3649 pCache->TestOut.pVMCSPhys = 0;
3650 pCache->TestOut.pCache = 0;
3651 pCache->TestOut.pCtx = 0;
3652 pCache->TestOut.eflags = 0;
3653#endif
3654
3655 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
3656 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
3657 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
3658 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
3659 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
3660 aParam[5] = 0;
3661
3662#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3663 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
3664 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
3665#endif
3666 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
3667
3668#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3669 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
3670 Assert(pCtx->dr[4] == 10);
3671 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
3672#endif
3673
3674#ifdef DEBUG
3675 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
3676 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
3677 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
3678 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
3679 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
3680 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
3681 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
3682#endif
3683 return rc;
3684}
3685
3686/**
3687 * Executes the specified handler in 64 mode
3688 *
3689 * @returns VBox status code.
3690 * @param pVM The VM to operate on.
3691 * @param pVCpu The VMCPU to operate on.
3692 * @param pCtx Guest context
3693 * @param pfnHandler RC handler
3694 * @param cbParam Number of parameters
3695 * @param paParam Array of 32 bits parameters
3696 */
3697VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
3698{
3699 int rc, rc2;
3700 PHWACCM_CPUINFO pCpu;
3701 RTHCPHYS pPageCpuPhys;
3702
3703 /* @todo This code is not guest SMP safe (hyper context) */
3704 AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
3705 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
3706 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
3707 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
3708
3709#ifdef VBOX_STRICT
3710 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
3711 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
3712
3713 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
3714 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
3715#endif
3716
3717 pCpu = HWACCMR0GetCurrentCpu();
3718 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3719
3720 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3721 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3722
3723 /* Leave VMX Root Mode. */
3724 VMXDisable();
3725
3726 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3727
3728 CPUMSetHyperESP(pVM, VMMGetStackRC(pVM));
3729 CPUMSetHyperEIP(pVM, pfnHandler);
3730 for (int i=(int)cbParam-1;i>=0;i--)
3731 CPUMPushHyper(pVM, paParam[i]);
3732
3733 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3734 /* Call switcher. */
3735 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
3736 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3737
3738 /* Make sure the VMX instructions don't cause #UD faults. */
3739 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
3740
3741 /* Enter VMX Root Mode */
3742 rc2 = VMXEnable(pPageCpuPhys);
3743 if (RT_FAILURE(rc2))
3744 {
3745 if (pVM)
3746 VMXR0CheckError(pVM, pVCpu, rc2);
3747 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3748 return VERR_VMX_VMXON_FAILED;
3749 }
3750
3751 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3752 AssertRCReturn(rc2, rc2);
3753#ifdef RT_OS_WINDOWS
3754 Assert(ASMGetFlags() & X86_EFL_IF);
3755#else
3756 Assert(!(ASMGetFlags() & X86_EFL_IF));
3757#endif
3758 return rc;
3759}
3760
3761#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
3762
3763
3764#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3765/**
3766 * Executes VMWRITE
3767 *
3768 * @returns VBox status code
3769 * @param pVCpu The VMCPU to operate on.
3770 * @param idxField VMCS index
3771 * @param u64Val 16, 32 or 64 bits value
3772 */
3773VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
3774{
3775 int rc;
3776
3777 switch (idxField)
3778 {
3779 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
3780 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
3781 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
3782 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
3783 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
3784 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
3785 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
3786 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
3787 case VMX_VMCS_GUEST_LINK_PTR_FULL:
3788 case VMX_VMCS_GUEST_PDPTR0_FULL:
3789 case VMX_VMCS_GUEST_PDPTR1_FULL:
3790 case VMX_VMCS_GUEST_PDPTR2_FULL:
3791 case VMX_VMCS_GUEST_PDPTR3_FULL:
3792 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
3793 case VMX_VMCS_GUEST_EFER_FULL:
3794 case VMX_VMCS_CTRL_EPTP_FULL:
3795 /* These fields consist of two parts, which are both writable in 32 bits mode. */
3796 rc = VMXWriteVMCS32(idxField, u64Val);
3797 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
3798 AssertRC(rc);
3799 return rc;
3800
3801 case VMX_VMCS64_GUEST_LDTR_BASE:
3802 case VMX_VMCS64_GUEST_TR_BASE:
3803 case VMX_VMCS64_GUEST_GDTR_BASE:
3804 case VMX_VMCS64_GUEST_IDTR_BASE:
3805 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3806 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3807 case VMX_VMCS64_GUEST_CR0:
3808 case VMX_VMCS64_GUEST_CR4:
3809 case VMX_VMCS64_GUEST_CR3:
3810 case VMX_VMCS64_GUEST_DR7:
3811 case VMX_VMCS64_GUEST_RIP:
3812 case VMX_VMCS64_GUEST_RSP:
3813 case VMX_VMCS64_GUEST_CS_BASE:
3814 case VMX_VMCS64_GUEST_DS_BASE:
3815 case VMX_VMCS64_GUEST_ES_BASE:
3816 case VMX_VMCS64_GUEST_FS_BASE:
3817 case VMX_VMCS64_GUEST_GS_BASE:
3818 case VMX_VMCS64_GUEST_SS_BASE:
3819 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
3820 if (u64Val >> 32ULL)
3821 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
3822 else
3823 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
3824
3825 return rc;
3826
3827 default:
3828 AssertMsgFailed(("Unexpected field %x\n", idxField));
3829 return VERR_INVALID_PARAMETER;
3830 }
3831}
3832
3833/**
3834 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
3835 *
3836 * @param pVCpu The VMCPU to operate on.
3837 * @param idxField VMCS field
3838 * @param u64Val Value
3839 */
3840VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
3841{
3842 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
3843
3844 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
3845
3846 /* Make sure there are no duplicates. */
3847 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
3848 {
3849 if (pCache->Write.aField[i] == idxField)
3850 {
3851 pCache->Write.aFieldVal[i] = u64Val;
3852 return VINF_SUCCESS;
3853 }
3854 }
3855
3856 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
3857 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
3858 pCache->Write.cValidEntries++;
3859 return VINF_SUCCESS;
3860}
3861
3862#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3863
3864#ifdef VBOX_STRICT
3865static bool vmxR0IsValidReadField(uint32_t idxField)
3866{
3867 switch(idxField)
3868 {
3869 case VMX_VMCS64_GUEST_RIP:
3870 case VMX_VMCS64_GUEST_RSP:
3871 case VMX_VMCS_GUEST_RFLAGS:
3872 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
3873 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
3874 case VMX_VMCS64_GUEST_CR0:
3875 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
3876 case VMX_VMCS64_GUEST_CR4:
3877 case VMX_VMCS64_GUEST_DR7:
3878 case VMX_VMCS32_GUEST_SYSENTER_CS:
3879 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3880 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3881 case VMX_VMCS32_GUEST_GDTR_LIMIT:
3882 case VMX_VMCS64_GUEST_GDTR_BASE:
3883 case VMX_VMCS32_GUEST_IDTR_LIMIT:
3884 case VMX_VMCS64_GUEST_IDTR_BASE:
3885 case VMX_VMCS16_GUEST_FIELD_CS:
3886 case VMX_VMCS32_GUEST_CS_LIMIT:
3887 case VMX_VMCS64_GUEST_CS_BASE:
3888 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
3889 case VMX_VMCS16_GUEST_FIELD_DS:
3890 case VMX_VMCS32_GUEST_DS_LIMIT:
3891 case VMX_VMCS64_GUEST_DS_BASE:
3892 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
3893 case VMX_VMCS16_GUEST_FIELD_ES:
3894 case VMX_VMCS32_GUEST_ES_LIMIT:
3895 case VMX_VMCS64_GUEST_ES_BASE:
3896 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
3897 case VMX_VMCS16_GUEST_FIELD_FS:
3898 case VMX_VMCS32_GUEST_FS_LIMIT:
3899 case VMX_VMCS64_GUEST_FS_BASE:
3900 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
3901 case VMX_VMCS16_GUEST_FIELD_GS:
3902 case VMX_VMCS32_GUEST_GS_LIMIT:
3903 case VMX_VMCS64_GUEST_GS_BASE:
3904 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
3905 case VMX_VMCS16_GUEST_FIELD_SS:
3906 case VMX_VMCS32_GUEST_SS_LIMIT:
3907 case VMX_VMCS64_GUEST_SS_BASE:
3908 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
3909 case VMX_VMCS16_GUEST_FIELD_LDTR:
3910 case VMX_VMCS32_GUEST_LDTR_LIMIT:
3911 case VMX_VMCS64_GUEST_LDTR_BASE:
3912 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
3913 case VMX_VMCS16_GUEST_FIELD_TR:
3914 case VMX_VMCS32_GUEST_TR_LIMIT:
3915 case VMX_VMCS64_GUEST_TR_BASE:
3916 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
3917 case VMX_VMCS32_RO_EXIT_REASON:
3918 case VMX_VMCS32_RO_VM_INSTR_ERROR:
3919 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
3920 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
3921 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
3922 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
3923 case VMX_VMCS_RO_EXIT_QUALIFICATION:
3924 case VMX_VMCS32_RO_IDT_INFO:
3925 case VMX_VMCS32_RO_IDT_ERRCODE:
3926 case VMX_VMCS64_GUEST_CR3:
3927 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
3928 return true;
3929 }
3930 return false;
3931}
3932
3933static bool vmxR0IsValidWriteField(uint32_t idxField)
3934{
3935 switch(idxField)
3936 {
3937 case VMX_VMCS64_GUEST_LDTR_BASE:
3938 case VMX_VMCS64_GUEST_TR_BASE:
3939 case VMX_VMCS64_GUEST_GDTR_BASE:
3940 case VMX_VMCS64_GUEST_IDTR_BASE:
3941 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3942 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3943 case VMX_VMCS64_GUEST_CR0:
3944 case VMX_VMCS64_GUEST_CR4:
3945 case VMX_VMCS64_GUEST_CR3:
3946 case VMX_VMCS64_GUEST_DR7:
3947 case VMX_VMCS64_GUEST_RIP:
3948 case VMX_VMCS64_GUEST_RSP:
3949 case VMX_VMCS64_GUEST_CS_BASE:
3950 case VMX_VMCS64_GUEST_DS_BASE:
3951 case VMX_VMCS64_GUEST_ES_BASE:
3952 case VMX_VMCS64_GUEST_FS_BASE:
3953 case VMX_VMCS64_GUEST_GS_BASE:
3954 case VMX_VMCS64_GUEST_SS_BASE:
3955 return true;
3956 }
3957 return false;
3958}
3959
3960#endif
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