HWVMXR0.cpp@ 2132

Last change on this file since 2132 was 2124, checked in by vboxsync, 18 years ago
TRPM changes to assert and report trap/interrupt types accurately.
Property svn:keywords set to `Id`
File size: 69.2 KB

Line
1	/* $Id: HWVMXR0.cpp 2124 2007-04-17 12:25:17Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include "HWVMXR0.h"
41
42
43	/* IO operation lookup arrays. */
44	static uint32_t aIOSize[4] = {1, 2, 0, 4};
45	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
46
47
48	/**
49	* Sets up and activates VMX
50	*
51	* @returns VBox status code.
52	* @param pVM The VM to operate on.
53	*/
54	HWACCMR0DECL(int) VMXR0Setup(PVM pVM)
55	{
56	int rc = VINF_SUCCESS;
57	uint32_t val;
58
59	if (pVM == NULL)
60	return VERR_INVALID_PARAMETER;
61
62	/* Setup Intel VMX. */
63	Assert(pVM->hwaccm.s.vmx.fSupported);
64
65	/* Set revision dword at the beginning of both structures. */
66	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
67	(uint32_t )pVM->hwaccm.s.vmx.pVMXON = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
68
69	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
70	* (which can have very bad consequences!!!)
71	*/
72
73	/* Make sure the VMX instructions don't cause #UD faults. */
74	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
75
76	/* Enter VMX Root Mode */
77	rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
78	if (VBOX_FAILURE(rc))
79	{
80	return rc;
81	}
82
83	/* Clear VM Control Structure. */
84	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
85	if (VBOX_FAILURE(rc))
86	goto vmx_end;
87
88	/* Activate the VM Control Structure. */
89	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
90	if (VBOX_FAILURE(rc))
91	goto vmx_end;
92
93	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
94	* Set required bits to one and zero according to the MSR capabilities.
95	*/
96	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
97	/* External and non-maskable interrupts cause VM-exits. */
98	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
99	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
100
101	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
102	AssertRC(rc);
103
104	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
105	* Set required bits to one and zero according to the MSR capabilities.
106	*/
107	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
108	/* Program which event cause VM-exits and which features we want to use. */
109	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
110	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
111	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
112	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
113	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
114	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
115
116	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
117
118	/*
119	if AMD64 guest mode
120	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
121	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
122	*/
123	/* Mask away the bits that the CPU doesn't support */
124	/** @todo make sure they don't conflict with the above requirements. */
125	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
126	pVM->hwaccm.s.vmx.proc_ctls = val;
127
128	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
129	AssertRC(rc);
130
131	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
132	* Set required bits to one and zero according to the MSR capabilities.
133	*/
134	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
135	AssertRC(rc);
136
137	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
138	* Set required bits to one and zero according to the MSR capabilities.
139	*/
140	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
141	if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
142	{
143	/** @todo 32 bits guest mode only for now. */
144	/* val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
145	}
146	/* Mask away the bits that the CPU doesn't support */
147	/** @todo make sure they don't conflict with the above requirements. */
148	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
149	/* else Must be zero when AMD64 is not available. */
150	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
151	AssertRC(rc);
152
153	/* VMX_VMCS_CTRL_EXIT_CONTROLS
154	* Set required bits to one and zero according to the MSR capabilities.
155	*/
156	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
157	#if HC_ARCH_BITS == 64
158	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
159	#else
160	/* else Must be zero when AMD64 is not available. */
161	#endif
162	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
163	/* Don't acknowledge external interrupts on VM-exit. */
164	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
165	AssertRC(rc);
166
167	/* Forward all exception except #NM & #PF to the guest.
168	* We always need to check pagefaults since our shadow page table can be out of sync.
169	* And we always lazily sync the FPU & XMM state.
170	*/
171
172	/*
173	* @todo Possible optimization:
174	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
175	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
176	* registers ourselves of course.
177	*
178	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
179	*/
180	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
181	AssertRC(rc);
182
183	/* Don't filter page faults; all of them should cause a switch. */
184	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
185	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
186	AssertRC(rc);
187
188	/* Init TSC offset to zero. */
189	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
190	#if HC_ARCH_BITS == 32
191	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
192	#endif
193	AssertRC(rc);
194
195	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
196	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
197	AssertRC(rc);
198
199	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
200	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
201	AssertRC(rc);
202
203	/* Clear MSR controls. */
204	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
205	{
206	/* Optional */
207	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
208	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
209	AssertRC(rc);
210	}
211	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
212	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
213	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
214	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
215	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
216	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH, 0);
217	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
218	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
219	AssertRC(rc);
220
221	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
222	{
223	/* Optional */
224	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
225	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
226	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
227	AssertRC(rc);
228	}
229
230	/* Set link pointer to -1. Not currently used. */
231	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
232	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
233	AssertRC(rc);
234
235	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
236	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
237	AssertRC(rc);
238
239	vmx_end:
240	/* Leave VMX Root Mode. */
241	VMXDisable();
242	return rc;
243	}
244
245
246	/**
247	* Injects an event (trap or external interrupt)
248	*
249	* @returns VBox status code.
250	* @param pVM The VM to operate on.
251	* @param pCtx CPU Context
252	* @param intInfo VMX interrupt info
253	* @param cbInstr Opcode length of faulting instruction
254	* @param errCode Error code (optional)
255	*/
256	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
257	{
258	int rc;
259
260	#ifdef VBOX_STRICT
261	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
262	if (iGate == 0xE)
263	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
264	else
265	if (iGate < 0x20)
266	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
267	else
268	{
269	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
270	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
271	Assert(pCtx->eflags.u32 & X86_EFL_IF);
272	}
273	#endif
274
275	/* Set event injection state. */
276	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
277	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
278	);
279
280	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
281	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
282
283	AssertRC(rc);
284	return rc;
285	}
286
287
288	/**
289	* Checks for pending guest interrupts and injects them
290	*
291	* @returns VBox status code.
292	* @param pVM The VM to operate on.
293	* @param pCtx CPU Context
294	*/
295	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
296	{
297	int rc;
298
299	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
300	if (pVM->hwaccm.s.Event.fPending)
301	{
302	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
303	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
304	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
305	AssertRC(rc);
306
307	pVM->hwaccm.s.Event.fPending = false;
308	return VINF_SUCCESS;
309	}
310
311	/* When external interrupts are pending, we should exit the VM when IF is set. */
312	if ( !TRPMHasTrap(pVM)
313	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
314	{
315	if (!(pCtx->eflags.u32 & X86_EFL_IF))
316	{
317	Log2(("Enable irq window exit!\n"));
318	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT);
319	AssertRC(rc);
320	}
321	else
322	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
323	{
324	uint8_t u8Interrupt;
325
326	rc = PDMGetInterrupt(pVM, &u8Interrupt);
327	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
328	if (VBOX_SUCCESS(rc))
329	{
330	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
331	AssertRC(rc);
332	}
333	else
334	{
335	/* can't happen... */
336	AssertFailed();
337	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
338	return VINF_EM_RAW_INTERRUPT_PENDING;
339	}
340	}
341	else
342	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
343	}
344
345	#ifdef VBOX_STRICT
346	if (TRPMHasTrap(pVM))
347	{
348	uint8_t u8Vector;
349	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
350	AssertRC(rc);
351	}
352	#endif
353
354	if ( pCtx->eflags.u32 & X86_EFL_IF
355	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
356	&& TRPMHasTrap(pVM)
357	)
358	{
359	uint8_t u8Vector;
360	int rc;
361	TRPMEVENT enmType;
362	RTGCUINTPTR intInfo, errCode;
363
364	/* If a new event is pending, then dispatch it now. */
365	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
366	AssertRC(rc);
367	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
368	Assert(enmType != TRPM_SOFTWARE_INT);
369
370	/* Clear the pending trap. */
371	rc = TRPMResetTrap(pVM);
372	AssertRC(rc);
373
374	intInfo = u8Vector;
375	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
376
377	if (enmType == TRPM_TRAP)
378	{
379	switch (u8Vector) {
380	case 8:
381	case 10:
382	case 11:
383	case 12:
384	case 13:
385	case 14:
386	case 17:
387	/* Valid error codes. */
388	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
389	break;
390	default:
391	break;
392	}
393	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
394	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
395	else
396	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
397	}
398	else
399	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
400
401	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
402	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
403	AssertRC(rc);
404	} /* if (interrupts can be dispatched) */
405
406	return VINF_SUCCESS;
407	}
408
409	/**
410	* Save the host state
411	*
412	* @returns VBox status code.
413	* @param pVM The VM to operate on.
414	*/
415	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
416	{
417	int rc = VINF_SUCCESS;
418
419	/*
420	* Host CPU Context
421	*/
422	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
423	{
424	RTIDTR idtr;
425	RTGDTR gdtr;
426	RTSEL SelTR;
427	PVBOXDESC pDesc;
428	uintptr_t trBase;
429
430	/* Control registers */
431	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
432	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
433	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
434	AssertRC(rc);
435	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
436	Log2(("VMX_VMCS_HOST_CR3 %08x\n", ASMGetCR3()));
437	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
438
439	/* Selector registers. */
440	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
441	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
442	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
443	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
444	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
445	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
446	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
447	SelTR = ASMGetTR();
448	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
449	AssertRC(rc);
450	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
451	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
452	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
453	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
454	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
455	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
456	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
457
458	/* GDTR & IDTR */
459	ASMGetGDTR(&gdtr);
460	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
461	ASMGetIDTR(&idtr);
462	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
463	AssertRC(rc);
464	Log2(("VMX_VMCS_HOST_GDTR_BASE %VGv\n", gdtr.pGdt));
465	Log2(("VMX_VMCS_HOST_IDTR_BASE %VGv\n", idtr.pIdt));
466
467	/* Save the base address of the TR selector. */
468	if (SelTR > gdtr.cbGdt)
469	{
470	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
471	return VERR_VMX_INVALID_HOST_STATE;
472	}
473
474	pDesc = &((PVBOXDESC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT];
475	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16) \| (pDesc->Gen.u8BaseHigh2 << 24);
476	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
477	AssertRC(rc);
478	Log2(("VMX_VMCS_HOST_TR_BASE %VGv\n", trBase));
479
480	/* FS and GS base. */
481	#if HC_ARCH_BITS == 32
482	rc = VMXWriteVMCS(VMX_VMCS_HOST_FS_BASE, 0);
483	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_GS_BASE, 0);
484	#else
485	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
486	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
487	#endif
488	AssertRC(rc);
489
490	/* Sysenter MSRs. */
491	/** @todo expensive!! */
492	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
493	#if HC_ARCH_BITS == 32
494	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
495	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
496	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
497	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VGv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
498	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VGv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
499	#else
500	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
501	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
502	#endif
503	AssertRC(rc);
504
505	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
506	}
507	return rc;
508	}
509
510
511	/**
512	* Loads the guest state
513	*
514	* @returns VBox status code.
515	* @param pVM The VM to operate on.
516	* @param pCtx Guest context
517	*/
518	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
519	{
520	int rc = VINF_SUCCESS;
521	RTGCUINTPTR val;
522
523	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
524	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
525	{
526	VMX_WRITE_SELREG(ES, es);
527	AssertRC(rc);
528
529	VMX_WRITE_SELREG(CS, cs);
530	AssertRC(rc);
531
532	VMX_WRITE_SELREG(SS, ss);
533	AssertRC(rc);
534
535	VMX_WRITE_SELREG(DS, ds);
536	AssertRC(rc);
537
538	VMX_WRITE_SELREG(FS, fs);
539	AssertRC(rc);
540
541	VMX_WRITE_SELREG(GS, gs);
542	AssertRC(rc);
543	}
544
545	/* Guest CPU context: LDTR. */
546	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
547	{
548	if (pCtx->ldtr == 0)
549	{
550	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
551	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
552	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
553	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
554	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
555	}
556	else
557	{
558	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
559	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
560	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
561	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
562	}
563	AssertRC(rc);
564	}
565	/* Guest CPU context: TR. */
566	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
567	{
568	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
569	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
570	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
571	val = pCtx->trHid.Attr.u;
572
573	/* The TSS selector must be busy. */
574	if ((val & 0xF) == X86_SEL_TYPE_SYS_386_TSS_AVAIL)
575	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
576	else
577	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
578	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
579
580	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
581	AssertRC(rc);
582	}
583	/* Guest CPU context: GDTR. */
584	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
585	{
586	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
587	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
588	AssertRC(rc);
589	}
590	/* Guest CPU context: IDTR. */
591	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
592	{
593	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
594	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
595	AssertRC(rc);
596	}
597
598	/*
599	* Sysenter MSRs
600	*/
601	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
602	{
603	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
604	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
605	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
606	AssertRC(rc);
607	}
608
609	/* Control registers */
610	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
611	{
612	val = pCtx->cr0;
613	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
614	Log2(("Guest CR0-shadow %08x\n", val));
615	if (CPUMIsGuestFPUStateActive(pVM) == false)
616	{
617	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
618	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
619	}
620	else
621	{
622	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
623	/** @todo check if we support the old style mess correctly. */
624	if (!(val & X86_CR0_NE))
625	{
626	Log(("Forcing X86_CR0_NE!!!\n"));
627
628	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
629	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
630	{
631	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| BIT(16));
632	AssertRC(rc);
633	pVM->hwaccm.s.fFPUOldStyleOverride = true;
634	}
635	}
636
637	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
638	}
639	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
640	Log2(("Guest CR0 %08x\n", val));
641	/* CR0 flags owned by the host; if the guests attempts to change them, then
642	* the VM will exit.
643	*/
644	val = X86_CR0_PE
645	\| X86_CR0_WP /** @todo do we care? (we do if we start patching the guest) */
646	\| X86_CR0_PG
647	\| X86_CR0_TS
648	\| X86_CR0_ET
649	\| X86_CR0_NE
650	\| X86_CR0_MP;
651	pVM->hwaccm.s.vmx.cr0_mask = val;
652
653	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
654	Log2(("Guest CR0-mask %08x\n", val));
655	AssertRC(rc);
656	}
657	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
658	{
659	/* CR4 */
660	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
661	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
662	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
663	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
664	switch(pVM->hwaccm.s.enmShadowMode)
665	{
666	case PGMMODE_REAL:
667	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
668	AssertFailed();
669	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
670
671	case PGMMODE_32_BIT: /* 32-bit paging. */
672	break;
673
674	case PGMMODE_PAE: /* PAE paging. */
675	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
676	/** @todo use normal 32 bits paging */
677	val \|= X86_CR4_PAE;
678	break;
679
680	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
681	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
682	AssertFailed();
683	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
684
685	default: /* shut up gcc */
686	AssertFailed();
687	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
688	}
689	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
690	Log2(("Guest CR4 %08x\n", val));
691	/* CR4 flags owned by the host; if the guests attempts to change them, then
692	* the VM will exit.
693	*/
694	val = X86_CR4_PAE
695	\| X86_CR4_PGE
696	\| X86_CR4_PSE
697	\| X86_CR4_VMXE;
698	pVM->hwaccm.s.vmx.cr4_mask = val;
699
700	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
701	Log2(("Guest CR4-mask %08x\n", val));
702	AssertRC(rc);
703	}
704
705	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
706	{
707	/* Save our shadow CR3 register. */
708	val = PGMGetHyperCR3(pVM);
709	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
710	AssertRC(rc);
711	}
712
713	/* Debug registers. */
714	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
715	{
716	/** @todo DR0-6 */
717	val = pCtx->dr7;
718	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
719	val \|= 0x400; /* must be one */
720	#ifdef VBOX_STRICT
721	val = 0x400;
722	#endif
723	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
724	AssertRC(rc);
725
726	/* IA32_DEBUGCTL MSR. */
727	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
728	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
729	AssertRC(rc);
730
731	/** @todo */
732	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
733	AssertRC(rc);
734	}
735
736	/* EIP, ESP and EFLAGS */
737	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
738	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
739	AssertRC(rc);
740
741	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
742	val = pCtx->eflags.u32;
743	val &= VMX_EFLAGS_RESERVED_0;
744	val \|= VMX_EFLAGS_RESERVED_1;
745	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, val);
746	AssertRC(rc);
747
748	/** TSC offset. */
749	uint64_t u64TSCOffset = TMCpuTickGetOffset(pVM);
750
751	#if HC_ARCH_BITS == 64
752	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
753	#else
754	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
755	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
756	#endif
757	AssertRC(rc);
758
759	/* Done. */
760	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
761
762	return rc;
763	}
764
765	/**
766	* Runs guest code in a VMX VM.
767	*
768	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
769	*
770	* @returns VBox status code.
771	* @param pVM The VM to operate on.
772	* @param pCtx Guest context
773	*/
774	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
775	{
776	int rc = VINF_SUCCESS;
777	RTCCUINTREG val, valShadow;
778	RTCCUINTREG exitReason, instrError, cbInstr;
779	RTGCUINTPTR exitQualification;
780	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
781	RTGCUINTPTR errCode, instrInfo, uInterruptState;
782
783	Log2(("\nE"));
784
785	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
786
787	#ifdef VBOX_STRICT
788	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
789	AssertRC(rc);
790	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
791
792	/* allowed zero */
793	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
794	{
795	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
796	}
797	/* allowed one */
798	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
799	{
800	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
801	}
802
803	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
804	AssertRC(rc);
805	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
806
807	/* allowed zero */
808	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
809	{
810	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
811	}
812	/* allowed one */
813	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
814	{
815	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
816	}
817
818	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
819	AssertRC(rc);
820	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
821
822	/* allowed zero */
823	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
824	{
825	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
826	}
827	/* allowed one */
828	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
829	{
830	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
831	}
832
833	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
834	AssertRC(rc);
835	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
836
837	/* allowed zero */
838	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
839	{
840	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
841	}
842	/* allowed one */
843	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
844	{
845	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
846	}
847	#endif
848
849	#if 0
850	/*
851	* Check if debug registers are armed.
852	*/
853	uint32_t u32DR7 = ASMGetDR7();
854	if (u32DR7 & X86_DR7_ENABLED_MASK)
855	{
856	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
857	}
858	else
859	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
860	#endif
861
862	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
863	*/
864	ResumeExecution:
865
866	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
867	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
868	{
869	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
870	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
871	{
872	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
873	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
874	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
875	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
876	*/
877	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
878	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
879	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
880	AssertRC(rc);
881	}
882	}
883	else
884	{
885	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
886	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
887	AssertRC(rc);
888	}
889
890	/* Check for pending actions that force us to go back to ring 3. */
891	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
892	{
893	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
894	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
895	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
896	rc = VINF_EM_RAW_TO_R3;
897	goto end;
898	}
899	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
900	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
901	{
902	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
903	rc = VINF_EM_PENDING_REQUEST;
904	goto end;
905	}
906
907	/* When external interrupts are pending, we should exit the VM when IF is set. */
908	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
909	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
910	if (VBOX_FAILURE(rc))
911	{
912	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
913	goto end;
914	}
915
916	/** @todo check timers?? */
917
918	/* Save the host state first. */
919	rc = VMXR0SaveHostState(pVM);
920	if (rc != VINF_SUCCESS)
921	{
922	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
923	goto end;
924	}
925	/* Load the guest state */
926	rc = VMXR0LoadGuestState(pVM, pCtx);
927	if (rc != VINF_SUCCESS)
928	{
929	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
930	goto end;
931	}
932
933	/* Non-register state Guest Context */
934	/** @todo change me according to cpu state */
935	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
936	AssertRC(rc);
937
938	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
939
940	/* Manual save and restore:
941	* - General purpose registers except RIP, RSP
942	*
943	* Trashed:
944	* - CR2 (we don't care)
945	* - LDTR (reset to 0)
946	* - DRx (presumably not changed at all)
947	* - DR7 (reset to 0x400)
948	* - EFLAGS (reset to BIT(1); not relevant)
949	*
950	*/
951
952	/* All done! Let's start VM execution. */
953	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
954	if (pVM->hwaccm.s.vmx.fResumeVM == false)
955	{
956	rc = VMXStartVM(pCtx);
957	}
958	else
959	{
960	rc = VMXResumeVM(pCtx);
961	}
962
963	/* In case we execute a goto ResumeExecution later on. */
964	pVM->hwaccm.s.vmx.fResumeVM = true;
965
966	/**
967	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
968	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
969	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
970	*/
971
972	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
973	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
974
975	switch (rc)
976	{
977	case VINF_SUCCESS:
978	break;
979
980	case VERR_VMX_INVALID_VMXON_PTR:
981	AssertFailed();
982	goto end;
983
984	case VERR_VMX_UNABLE_TO_START_VM:
985	case VERR_VMX_UNABLE_TO_RESUME_VM:
986	{
987	#ifdef VBOX_STRICT
988	int rc1;
989
990	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
991	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
992	AssertRC(rc1);
993	if (rc1 == VINF_SUCCESS)
994	{
995	RTGDTR gdtr;
996	PVBOXDESC pDesc;
997
998	ASMGetGDTR(&gdtr);
999	VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
1000
1001	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1002	Log(("Current stack %08x\n", &rc1));
1003
1004	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1005	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1006
1007	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1008	Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
1009
1010	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1011	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1012
1013	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1014	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1015	if (val < gdtr.cbGdt)
1016	{
1017	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1018	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1019	}
1020
1021	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1022	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1023	if (val < gdtr.cbGdt)
1024	{
1025	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1026	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1027	}
1028
1029	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1030	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1031	if (val < gdtr.cbGdt)
1032	{
1033	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1034	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1035	}
1036
1037	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1038	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1039	if (val < gdtr.cbGdt)
1040	{
1041	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1042	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1043	}
1044
1045	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1046	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1047	if (val < gdtr.cbGdt)
1048	{
1049	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1050	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1051	}
1052
1053	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1054	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1055	if (val < gdtr.cbGdt)
1056	{
1057	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1058	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1059	}
1060
1061	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1062	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1063	if (val < gdtr.cbGdt)
1064	{
1065	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1066	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1067	}
1068
1069	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1070	Log(("VMX_VMCS_HOST_TR_BASE %VGv\n", val));
1071
1072	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1073	Log(("VMX_VMCS_HOST_GDTR_BASE %VGv\n", val));
1074	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1075	Log(("VMX_VMCS_HOST_IDTR_BASE %VGv\n", val));
1076
1077	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1078	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1079
1080	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1081	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VGv\n", val));
1082
1083	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1084	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VGv\n", val));
1085
1086	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1087	Log(("VMX_VMCS_HOST_RSP %VGv\n", val));
1088	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1089	Log(("VMX_VMCS_HOST_RIP %VGv\n", val));
1090	}
1091	#endif /* VBOX_STRICT */
1092	goto end;
1093	}
1094
1095	default:
1096	/* impossible */
1097	AssertFailed();
1098	goto end;
1099	}
1100	/* Success. Query the guest state and figure out what has happened. */
1101
1102	/* Investigate why there was a VM-exit. */
1103	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1104	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReason[exitReason & MASK_EXITREASON_STAT]);
1105
1106	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1107	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1108	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1109	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1110	intInfo = val;
1111	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1112	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1113	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1114	instrInfo = val;
1115	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1116	exitQualification = val;
1117	AssertRC(rc);
1118
1119	/* Take care of instruction fusing (sti, mov ss) */
1120	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1121	uInterruptState = val;
1122	if (uInterruptState != 0)
1123	{
1124	Assert(uInterruptState <= 2); /* only sti & mov ss */
1125	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1126	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1127	}
1128	else
1129	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1130
1131	/* Let's first sync back eip, esp, and eflags. */
1132	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1133	AssertRC(rc);
1134	pCtx->eip = val;
1135	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1136	AssertRC(rc);
1137	pCtx->esp = val;
1138	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1139	AssertRC(rc);
1140	pCtx->eflags.u32 = val;
1141
1142	/* Control registers. */
1143	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1144	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1145	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1146	CPUMSetGuestCR0(pVM, val);
1147
1148	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1149	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1150	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1151	CPUMSetGuestCR4(pVM, val);
1152
1153	CPUMSetGuestCR2(pVM, ASMGetCR2());
1154
1155	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1156	CPUMSetGuestDR7(pVM, val);
1157
1158	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1159	VMX_READ_SELREG(ES, es);
1160	VMX_READ_SELREG(SS, ss);
1161	VMX_READ_SELREG(CS, cs);
1162	VMX_READ_SELREG(DS, ds);
1163	VMX_READ_SELREG(FS, fs);
1164	VMX_READ_SELREG(GS, gs);
1165
1166	/** @note NOW IT'S SAFE FOR LOGGING! */
1167	Log2(("Raw exit reason %08x\n", exitReason));
1168
1169	/* Check if an injected event was interrupted prematurely. */
1170	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1171	AssertRC(rc);
1172	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1173	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1174	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1175	{
1176	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1177	pVM->hwaccm.s.Event.fPending = true;
1178	/* Error code present? */
1179	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1180	{
1181	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1182	AssertRC(rc);
1183	pVM->hwaccm.s.Event.errCode = val;
1184	}
1185	else
1186	pVM->hwaccm.s.Event.errCode = 0;
1187	}
1188
1189	#ifdef VBOX_STRICT
1190	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1191	HWACCMDumpRegs(pCtx);
1192	#endif
1193
1194	Log2(("E%d", exitReason));
1195	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1196	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1197	Log2(("Interruption error code %d\n", errCode));
1198	Log2(("IntInfo = %08x\n", intInfo));
1199	Log2(("New EIP=%VGv\n", pCtx->eip));
1200
1201	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1202	switch (exitReason)
1203	{
1204	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1205	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1206	{
1207	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1208
1209	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1210	{
1211	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1212	/* External interrupt; leave to allow it to be dispatched again. */
1213	rc = VINF_EM_RAW_INTERRUPT;
1214	break;
1215	}
1216	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1217	{
1218	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1219	/* External interrupt; leave to allow it to be dispatched again. */
1220	rc = VINF_EM_RAW_INTERRUPT;
1221	break;
1222
1223	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1224	AssertFailed(); /* can't come here; fails the first check. */
1225	break;
1226
1227	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1228	Assert(vector == 3 \|\| vector == 4);
1229	/* no break */
1230	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1231	Log2(("Hardware/software interrupt %d\n", vector));
1232	switch (vector)
1233	{
1234	case X86_XCPT_NM:
1235	{
1236	uint32_t oldCR0;
1237
1238	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1239
1240	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1241	oldCR0 = ASMGetCR0();
1242	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1243	rc = CPUMHandleLazyFPU(pVM);
1244	if (rc == VINF_SUCCESS)
1245	{
1246	Assert(CPUMIsGuestFPUStateActive(pVM));
1247
1248	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1249	ASMSetCR0(oldCR0);
1250
1251	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1252
1253	/* Continue execution. */
1254	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1255	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1256
1257	goto ResumeExecution;
1258	}
1259
1260	Log(("Forward #NM fault to the guest\n"));
1261	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1262	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1263	AssertRC(rc);
1264	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1265	goto ResumeExecution;
1266	}
1267
1268	case X86_XCPT_PF: /* Page fault */
1269	{
1270	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1271	/* Exit qualification contains the linear address of the page fault. */
1272	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1273	TRPMSetErrorCode(pVM, errCode);
1274	TRPMSetFaultAddress(pVM, exitQualification);
1275
1276	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1277	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1278	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1279	if (rc == VINF_SUCCESS)
1280	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1281	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1282	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1283
1284	TRPMResetTrap(pVM);
1285
1286	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1287	goto ResumeExecution;
1288	}
1289	else
1290	if (rc == VINF_EM_RAW_GUEST_TRAP)
1291	{ /* A genuine pagefault.
1292	* Forward the trap to the guest by injecting the exception and resuming execution.
1293	*/
1294	Log2(("Forward page fault to the guest\n"));
1295	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1296	/* The error code might have been changed. */
1297	errCode = TRPMGetErrorCode(pVM);
1298
1299	TRPMResetTrap(pVM);
1300
1301	/* Now we must update CR2. */
1302	pCtx->cr2 = exitQualification;
1303	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1304	AssertRC(rc);
1305
1306	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1307	goto ResumeExecution;
1308	}
1309	#ifdef VBOX_STRICT
1310	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1311	Log(("PGMTrap0eHandler failed with %d\n", rc));
1312	#endif
1313	/* Need to go back to the recompiler to emulate the instruction. */
1314	TRPMResetTrap(pVM);
1315	break;
1316	}
1317
1318	case X86_XCPT_MF: /* Floating point exception. */
1319	{
1320	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1321	if (!(pCtx->cr0 & X86_CR0_NE))
1322	{
1323	/* old style FPU error reporting needs some extra work. */
1324	/** @todo don't fall back to the recompiler, but do it manually. */
1325	rc = VINF_EM_RAW_EMULATE_INSTR;
1326	break;
1327	}
1328	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1329	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1330	AssertRC(rc);
1331
1332	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1333	goto ResumeExecution;
1334	}
1335
1336	#ifdef VBOX_STRICT
1337	case X86_XCPT_GP: /* General protection failure exception.*/
1338	case X86_XCPT_UD: /* Unknown opcode exception. */
1339	case X86_XCPT_DE: /* Debug exception. */
1340	case X86_XCPT_SS: /* Stack segment exception. */
1341	case X86_XCPT_NP: /* Segment not present exception. */
1342	{
1343	switch(vector)
1344	{
1345	case X86_XCPT_DE:
1346	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1347	break;
1348	case X86_XCPT_UD:
1349	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1350	break;
1351	case X86_XCPT_SS:
1352	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1353	break;
1354	case X86_XCPT_NP:
1355	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1356	break;
1357	case X86_XCPT_GP:
1358	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1359	break;
1360	}
1361
1362	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1363	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1364	AssertRC(rc);
1365
1366	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1367	goto ResumeExecution;
1368	}
1369	#endif
1370	default:
1371	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1372	rc = VERR_EM_INTERNAL_ERROR;
1373	break;
1374	} /* switch (vector) */
1375
1376	break;
1377
1378	default:
1379	rc = VERR_EM_INTERNAL_ERROR;
1380	AssertFailed();
1381	break;
1382	}
1383
1384	break;
1385	}
1386
1387	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1388	/* Clear VM-exit on IF=1 change. */
1389	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1390	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1391	AssertRC(rc);
1392	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1393	goto ResumeExecution; /* we check for pending guest interrupts there */
1394
1395	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1396	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1397	/* Skip instruction and continue directly. */
1398	pCtx->eip += cbInstr;
1399	/* Continue execution.*/
1400	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1401	goto ResumeExecution;
1402
1403	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1404	{
1405	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1406	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1407	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1408	if (rc == VINF_SUCCESS)
1409	{
1410	/* Update EIP and continue execution. */
1411	pCtx->eip += cbInstr;
1412	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1413	goto ResumeExecution;
1414	}
1415	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1416	rc = VINF_EM_RAW_EMULATE_INSTR;
1417	break;
1418	}
1419
1420	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1421	{
1422	Log2(("VMX: invlpg\n"));
1423	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1424	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1425	if (rc == VINF_SUCCESS)
1426	{
1427	/* Update EIP and continue execution. */
1428	pCtx->eip += cbInstr;
1429	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1430	goto ResumeExecution;
1431	}
1432	AssertMsgFailed(("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1433	rc = VINF_EM_RAW_EMULATE_INSTR;
1434	break;
1435	}
1436
1437	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1438	{
1439	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1440	{
1441	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1442	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1443	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1444	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1445	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1446	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1447
1448	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1449	{
1450	case 0:
1451	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1452	break;
1453	case 2:
1454	break;
1455	case 3:
1456	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1457	break;
1458	case 4:
1459	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1460	break;
1461	default:
1462	AssertFailed();
1463	}
1464	/* Check if a sync operation is pending. */
1465	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1466	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1467	{
1468	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1469	AssertRC(rc);
1470	}
1471	break;
1472
1473	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1474	Log2(("VMX: mov x, crx\n"));
1475	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1476	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1477	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1478	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1479	break;
1480
1481	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1482	Log2(("VMX: clts\n"));
1483	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1484	rc = EMInterpretCLTS(pVM);
1485	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1486	break;
1487
1488	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1489	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1490	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1491	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1492	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1493	break;
1494	}
1495
1496	/* Update EIP if no error occurred. */
1497	if (VBOX_SUCCESS(rc))
1498	pCtx->eip += cbInstr;
1499
1500	if (rc == VINF_SUCCESS)
1501	{
1502	/* Only resume if successful. */
1503	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1504	goto ResumeExecution;
1505	}
1506	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1507	if (rc == VERR_EM_INTERPRETER)
1508	rc = VINF_EM_RAW_EMULATE_INSTR;
1509	break;
1510	}
1511
1512	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1513	{
1514	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1515	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1516	{
1517	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1518	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1519	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1520	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1521	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1522	Log2(("DR7=%08x\n", pCtx->dr7));
1523	}
1524	else
1525	{
1526	Log2(("VMX: mov x, drx\n"));
1527	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1528	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1529	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1530	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1531	}
1532	/* Update EIP if no error occurred. */
1533	if (VBOX_SUCCESS(rc))
1534	pCtx->eip += cbInstr;
1535
1536	if (rc == VINF_SUCCESS)
1537	{
1538	/* Only resume if successful. */
1539	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1540	goto ResumeExecution;
1541	}
1542	Assert(rc == VERR_EM_INTERPRETER);
1543	rc = VINF_EM_RAW_EMULATE_INSTR;
1544	break;
1545	}
1546
1547	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1548	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1549	{
1550	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1551	uint32_t uPort;
1552
1553	/** @todo necessary to make the distinction? */
1554	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1555	{
1556	uPort = pCtx->edx & 0xffff;
1557	}
1558	else
1559	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1560
1561	/* First simple in and out instructions. */
1562	/** @todo str & rep */
1563	if ( !VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification)
1564	&& !VMX_EXIT_QUALIFICATION_IO_REP(exitQualification)
1565	/* paranoid checks ahead */
1566	&& uIOWidth != 2
1567	&& uIOWidth < 4
1568	)
1569	{
1570	uint32_t cbSize = aIOSize[uIOWidth];
1571	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1572
1573	if (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT)
1574	{
1575	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1576	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1577	}
1578	else
1579	{
1580	uint32_t u32Val = 0;
1581
1582	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1583	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1584	if (rc == VINF_SUCCESS)
1585	{
1586	/* Write back to the EAX register. */
1587	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1588	}
1589	}
1590	if (rc == VINF_SUCCESS)
1591	{
1592	/* Update EIP and continue execution. */
1593	pCtx->eip += cbInstr;
1594	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1595	goto ResumeExecution;
1596	}
1597	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1598	rc = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT)
1599	? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1600	}
1601	else
1602	rc = VINF_IOM_HC_IOPORT_READWRITE;
1603
1604	break;
1605	}
1606
1607	default:
1608	/* The rest is handled after syncing the entire CPU state. */
1609	break;
1610	}
1611
1612	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1613	VMX_READ_SELREG(LDTR, ldtr);
1614	VMX_READ_SELREG(TR, tr);
1615
1616	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1617	pCtx->gdtr.cbGdt = val;
1618	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1619	pCtx->gdtr.pGdt = val;
1620
1621	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1622	pCtx->idtr.cbIdt = val;
1623	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1624	pCtx->idtr.pIdt = val;
1625
1626	/*
1627	* System MSRs
1628	*/
1629	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1630	pCtx->SysEnter.cs = val;
1631	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1632	pCtx->SysEnter.eip = val;
1633	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1634	pCtx->SysEnter.esp = val;
1635
1636	/* Signal changes for the recompiler. */
1637	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1638
1639	/* Investigate why there was a VM-exit. (part 2) */
1640	switch (exitReason)
1641	{
1642	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1643	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1644	/* Already handled above. */
1645	break;
1646
1647	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1648	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1649	break;
1650
1651	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1652	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1653	rc = VINF_EM_RAW_INTERRUPT;
1654	AssertFailed(); /* Can't happen. Yet. */
1655	break;
1656
1657	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1658	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1659	rc = VINF_EM_RAW_INTERRUPT;
1660	AssertFailed(); /* Can't happen afaik. */
1661	break;
1662
1663	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1664	rc = VINF_EM_RAW_RING_SWITCH_INT;
1665	break;
1666
1667	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1668	/** Check if external interrupts are pending; if so, don't switch back. */
1669	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1670	{
1671	pCtx->eip++; /* skip hlt */
1672	goto ResumeExecution;
1673	}
1674
1675	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1676	break;
1677
1678	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1679	rc = VERR_EM_INTERNAL_ERROR;
1680	AssertFailed(); /* we don't let it fault. */
1681	break;
1682
1683	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1684	AssertFailed(); /* can't happen. */
1685	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1686	break;
1687
1688	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1689	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1690	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1691	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1692	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1693	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1694	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1695	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1696	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1697	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1698	/** @todo inject #UD immediately */
1699	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1700	break;
1701
1702	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1703	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1704	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1705	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1706	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1707	/* already handled above */
1708	AssertMsg(rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_EM_RAW_INTERRUPT \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_PGM_SYNC_CR3 \|\| rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE \|\| rc == VINF_IOM_HC_IOPORT_READWRITE, ("rc = %d\n", rc));
1709	break;
1710
1711	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1712	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1713	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1714	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1715	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1716	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1717	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1718	break;
1719
1720	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1721	Assert(rc == VINF_EM_RAW_INTERRUPT);
1722	break;
1723
1724	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1725	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1726	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1727	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1728	default:
1729	rc = VERR_EM_INTERNAL_ERROR;
1730	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1731	break;
1732
1733	}
1734	end:
1735
1736	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
1737	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
1738	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1739	{
1740	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1741	/* On the next entry we'll only sync the host context. */
1742	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1743	}
1744	else
1745	{
1746	/* On the next entry we'll sync everything. */
1747	/** @todo we can do better than this */
1748	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1749	}
1750
1751	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1752	Log2(("X"));
1753	return rc;
1754	}
1755
1756
1757	/**
1758	* Enable VMX
1759	*
1760	* @returns VBox status code.
1761	* @param pVM The VM to operate on.
1762	*/
1763	HWACCMR0DECL(int) VMXR0Enable(PVM pVM)
1764	{
1765	Assert(pVM->hwaccm.s.vmx.fSupported);
1766
1767	/* Make sure the VMX instructions don't cause #UD faults. */
1768	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
1769
1770	/* Enter VMX Root Mode */
1771	int rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
1772	if (VBOX_FAILURE(rc))
1773	return rc;
1774
1775	/* Activate the VM Control Structure. */
1776	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1777	if (VBOX_FAILURE(rc))
1778	{
1779	/* Leave VMX Root Mode. */
1780	VMXDisable();
1781	return rc;
1782	}
1783	pVM->hwaccm.s.vmx.fResumeVM = false;
1784	return VINF_SUCCESS;
1785	}
1786
1787
1788	/**
1789	* Disable VMX
1790	*
1791	* @returns VBox status code.
1792	* @param pVM The VM to operate on.
1793	*/
1794	HWACCMR0DECL(int) VMXR0Disable(PVM pVM)
1795	{
1796	Assert(pVM->hwaccm.s.vmx.fSupported);
1797
1798	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
1799	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1800	AssertRC(rc);
1801
1802	/* Leave VMX Root Mode. */
1803	VMXDisable();
1804
1805	return VINF_SUCCESS;
1806	}
1807

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 2132

Download in other formats: