VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 9462

Last change on this file since 9462 was 9457, checked in by vboxsync, 17 years ago

Reapplied fixed 31707.
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1/* $Id: HWVMXR0.cpp 9457 2008-06-06 09:46:39Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43
44/* IO operation lookup arrays. */
45static uint32_t aIOSize[4] = {1, 2, 0, 4};
46static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49static void VMXR0CheckError(PVM pVM, int rc)
50{
51 if (rc == VERR_VMX_GENERIC)
52 {
53 RTCCUINTREG instrError;
54
55 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57 }
58 pVM->hwaccm.s.lLastError = rc;
59}
60
61/**
62 * Sets up and activates VT-x on the current CPU
63 *
64 * @returns VBox status code.
65 * @param pCpu CPU info struct
66 * @param pVM The VM to operate on.
67 * @param pvPageCpu Pointer to the global cpu page
68 * @param pPageCpuPhys Physical address of the global cpu page
69 */
70HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71{
72 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73 AssertReturn(pVM, VERR_INVALID_PARAMETER);
74 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76 /* Setup Intel VMX. */
77 Assert(pVM->hwaccm.s.vmx.fSupported);
78
79#ifdef LOG_ENABLED
80 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81#endif
82 /* Set revision dword at the beginning of the VMXON structure. */
83 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85 /* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86 * (which can have very bad consequences!!!)
87 */
88
89 /* Make sure the VMX instructions don't cause #UD faults. */
90 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
91
92 /* Enter VMX Root Mode */
93 int rc = VMXEnable(pPageCpuPhys);
94 if (VBOX_FAILURE(rc))
95 {
96 VMXR0CheckError(pVM, rc);
97 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98 return VERR_VMX_VMXON_FAILED;
99 }
100 return VINF_SUCCESS;
101}
102
103/**
104 * Deactivates VT-x on the current CPU
105 *
106 * @returns VBox status code.
107 * @param pCpu CPU info struct
108 * @param pvPageCpu Pointer to the global cpu page
109 * @param pPageCpuPhys Physical address of the global cpu page
110 */
111HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112{
113 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116 /* Leave VMX Root Mode. */
117 VMXDisable();
118
119 /* And clear the X86_CR4_VMXE bit */
120 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122#ifdef LOG_ENABLED
123 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124#endif
125 return VINF_SUCCESS;
126}
127
128/**
129 * Does Ring-0 per VM VT-x init.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135{
136 int rc;
137
138#ifdef LOG_ENABLED
139 SUPR0Printf("VMXR0InitVM %x\n", pVM);
140#endif
141
142 /* Allocate one page for the VM control structure (VMCS). */
143 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
144 AssertRC(rc);
145 if (RT_FAILURE(rc))
146 return rc;
147
148 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
149 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
150 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
151
152 /* Allocate one page for the TSS we need for real mode emulation. */
153 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
154 AssertRC(rc);
155 if (RT_FAILURE(rc))
156 return rc;
157
158 pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
159 pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
160
161 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
162 * for I/O operations. */
163 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
164 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
165 /* Bit set to 0 means redirection enabled. */
166 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
167
168#ifdef LOG_ENABLED
169 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
170#endif
171 return VINF_SUCCESS;
172}
173
174/**
175 * Does Ring-0 per VM VT-x termination.
176 *
177 * @returns VBox status code.
178 * @param pVM The VM to operate on.
179 */
180HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
181{
182 if (pVM->hwaccm.s.vmx.pMemObjVMCS)
183 {
184 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
185 pVM->hwaccm.s.vmx.pMemObjVMCS = 0;
186 pVM->hwaccm.s.vmx.pVMCS = 0;
187 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
188 }
189 if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS)
190 {
191 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
192 pVM->hwaccm.s.vmx.pMemObjRealModeTSS = 0;
193 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
194 pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
195 }
196 return VINF_SUCCESS;
197}
198
199/**
200 * Sets up VT-x for the specified VM
201 *
202 * @returns VBox status code.
203 * @param pVM The VM to operate on.
204 */
205HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
206{
207 int rc = VINF_SUCCESS;
208 uint32_t val;
209
210 AssertReturn(pVM, VERR_INVALID_PARAMETER);
211 Assert(pVM->hwaccm.s.vmx.pVMCS);
212
213 /* Set revision dword at the beginning of the VMCS structure. */
214 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
215
216 /* Clear VM Control Structure. */
217 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
218 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
219 if (VBOX_FAILURE(rc))
220 goto vmx_end;
221
222 /* Activate the VM Control Structure. */
223 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
224 if (VBOX_FAILURE(rc))
225 goto vmx_end;
226
227 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
228 * Set required bits to one and zero according to the MSR capabilities.
229 */
230 val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
231 /* External and non-maskable interrupts cause VM-exits. */
232 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
233 val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
234
235 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
236 AssertRC(rc);
237
238 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
239 * Set required bits to one and zero according to the MSR capabilities.
240 */
241 val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
242 /* Program which event cause VM-exits and which features we want to use. */
243 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
244 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
245 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
246 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
247 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
248 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
249
250 /** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
251
252 /*
253 if AMD64 guest mode
254 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
255 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
256 */
257#if HC_ARCH_BITS == 64
258 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
259 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
260#endif
261 /* Mask away the bits that the CPU doesn't support */
262 /** @todo make sure they don't conflict with the above requirements. */
263 val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
264 pVM->hwaccm.s.vmx.proc_ctls = val;
265
266 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
267 AssertRC(rc);
268
269 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
270 * Set required bits to one and zero according to the MSR capabilities.
271 */
272 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
273 AssertRC(rc);
274
275 /* VMX_VMCS_CTRL_EXIT_CONTROLS
276 * Set required bits to one and zero according to the MSR capabilities.
277 */
278 val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
279#if HC_ARCH_BITS == 64
280 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
281#else
282 /* else Must be zero when AMD64 is not available. */
283#endif
284 val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
285 /* Don't acknowledge external interrupts on VM-exit. */
286 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
287 AssertRC(rc);
288
289 /* Forward all exception except #NM & #PF to the guest.
290 * We always need to check pagefaults since our shadow page table can be out of sync.
291 * And we always lazily sync the FPU & XMM state.
292 */
293
294 /*
295 * @todo Possible optimization:
296 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
297 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
298 * registers ourselves of course.
299 *
300 * @note only possible if the current state is actually ours (X86_CR0_TS flag)
301 */
302 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
303 AssertRC(rc);
304
305 /* Don't filter page faults; all of them should cause a switch. */
306 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
307 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
308 AssertRC(rc);
309
310 /* Init TSC offset to zero. */
311 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
312#if HC_ARCH_BITS == 32
313 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
314#endif
315 AssertRC(rc);
316
317 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
318#if HC_ARCH_BITS == 32
319 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
320#endif
321 AssertRC(rc);
322
323 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
324#if HC_ARCH_BITS == 32
325 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
326#endif
327 AssertRC(rc);
328
329 /* Clear MSR controls. */
330 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
331 {
332 /* Optional */
333 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
334#if HC_ARCH_BITS == 32
335 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
336#endif
337 AssertRC(rc);
338 }
339 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
340 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
341 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
342#if HC_ARCH_BITS == 32
343 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
344 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
345 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
346#endif
347 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
348 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
349 AssertRC(rc);
350
351 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
352 {
353 /* Optional */
354 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
355 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
356#if HC_ARCH_BITS == 32
357 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
358#endif
359 AssertRC(rc);
360 }
361
362 /* Set link pointer to -1. Not currently used. */
363#if HC_ARCH_BITS == 32
364 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
365 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
366#else
367 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
368#endif
369 AssertRC(rc);
370
371 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
372 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
373 AssertRC(rc);
374
375vmx_end:
376 VMXR0CheckError(pVM, rc);
377 return rc;
378}
379
380
381/**
382 * Injects an event (trap or external interrupt)
383 *
384 * @returns VBox status code.
385 * @param pVM The VM to operate on.
386 * @param pCtx CPU Context
387 * @param intInfo VMX interrupt info
388 * @param cbInstr Opcode length of faulting instruction
389 * @param errCode Error code (optional)
390 */
391static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
392{
393 int rc;
394
395#ifdef VBOX_STRICT
396 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
397 if (iGate == 0xE)
398 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
399 else
400 if (iGate < 0x20)
401 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
402 else
403 {
404 Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
405 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
406 Assert(pCtx->eflags.u32 & X86_EFL_IF);
407 }
408#endif
409
410 /* Set event injection state. */
411 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
412 intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
413 );
414
415 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
416 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
417
418 AssertRC(rc);
419 return rc;
420}
421
422
423/**
424 * Checks for pending guest interrupts and injects them
425 *
426 * @returns VBox status code.
427 * @param pVM The VM to operate on.
428 * @param pCtx CPU Context
429 */
430static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
431{
432 int rc;
433
434 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
435 if (pVM->hwaccm.s.Event.fPending)
436 {
437 Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
438 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
439 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
440 AssertRC(rc);
441
442 pVM->hwaccm.s.Event.fPending = false;
443 return VINF_SUCCESS;
444 }
445
446 /* When external interrupts are pending, we should exit the VM when IF is set. */
447 if ( !TRPMHasTrap(pVM)
448 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
449 {
450 if (!(pCtx->eflags.u32 & X86_EFL_IF))
451 {
452 Log2(("Enable irq window exit!\n"));
453 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
454 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
455 AssertRC(rc);
456 }
457 else
458 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
459 {
460 uint8_t u8Interrupt;
461
462 rc = PDMGetInterrupt(pVM, &u8Interrupt);
463 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
464 if (VBOX_SUCCESS(rc))
465 {
466 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
467 AssertRC(rc);
468 }
469 else
470 {
471 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
472 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
473 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
474 /* Just continue */
475 }
476 }
477 else
478 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
479 }
480
481#ifdef VBOX_STRICT
482 if (TRPMHasTrap(pVM))
483 {
484 uint8_t u8Vector;
485 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
486 AssertRC(rc);
487 }
488#endif
489
490 if ( pCtx->eflags.u32 & X86_EFL_IF
491 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
492 && TRPMHasTrap(pVM)
493 )
494 {
495 uint8_t u8Vector;
496 int rc;
497 TRPMEVENT enmType;
498 RTGCUINTPTR intInfo;
499 RTGCUINT errCode;
500
501 /* If a new event is pending, then dispatch it now. */
502 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
503 AssertRC(rc);
504 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
505 Assert(enmType != TRPM_SOFTWARE_INT);
506
507 /* Clear the pending trap. */
508 rc = TRPMResetTrap(pVM);
509 AssertRC(rc);
510
511 intInfo = u8Vector;
512 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
513
514 if (enmType == TRPM_TRAP)
515 {
516 switch (u8Vector) {
517 case 8:
518 case 10:
519 case 11:
520 case 12:
521 case 13:
522 case 14:
523 case 17:
524 /* Valid error codes. */
525 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
526 break;
527 default:
528 break;
529 }
530 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
531 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
532 else
533 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
534 }
535 else
536 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
537
538 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
539 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
540 AssertRC(rc);
541 } /* if (interrupts can be dispatched) */
542
543 return VINF_SUCCESS;
544}
545
546/**
547 * Save the host state
548 *
549 * @returns VBox status code.
550 * @param pVM The VM to operate on.
551 */
552HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
553{
554 int rc = VINF_SUCCESS;
555
556 /*
557 * Host CPU Context
558 */
559 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
560 {
561 RTIDTR idtr;
562 RTGDTR gdtr;
563 RTSEL SelTR;
564 PX86DESCHC pDesc;
565 uintptr_t trBase;
566
567 /* Control registers */
568 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
569 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
570 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
571 AssertRC(rc);
572 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
573 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
574 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
575
576 /* Selector registers. */
577 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
578 /** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
579 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
580 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
581#if HC_ARCH_BITS == 32
582 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
583 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
584#endif
585 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
586 SelTR = ASMGetTR();
587 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
588 AssertRC(rc);
589 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
590 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
591 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
592 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
593 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
594 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
595 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
596
597 /* GDTR & IDTR */
598 ASMGetGDTR(&gdtr);
599 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
600 ASMGetIDTR(&idtr);
601 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
602 AssertRC(rc);
603 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
604 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
605
606 /* Save the base address of the TR selector. */
607 if (SelTR > gdtr.cbGdt)
608 {
609 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
610 return VERR_VMX_INVALID_HOST_STATE;
611 }
612
613 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
614#if HC_ARCH_BITS == 64
615 trBase = X86DESC64_BASE(*pDesc);
616#else
617 trBase = X86DESC_BASE(*pDesc);
618#endif
619 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
620 AssertRC(rc);
621 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
622
623 /* FS and GS base. */
624#if HC_ARCH_BITS == 64
625 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
626 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
627 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
628 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
629#endif
630 AssertRC(rc);
631
632 /* Sysenter MSRs. */
633 /** @todo expensive!! */
634 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
635 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
636#if HC_ARCH_BITS == 32
637 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
638 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
639 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
640 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
641#else
642 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
643 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
644 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
645 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
646#endif
647 AssertRC(rc);
648
649 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
650 }
651 return rc;
652}
653
654
655/**
656 * Loads the guest state
657 *
658 * @returns VBox status code.
659 * @param pVM The VM to operate on.
660 * @param pCtx Guest context
661 */
662HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
663{
664 int rc = VINF_SUCCESS;
665 RTGCUINTPTR val;
666 X86EFLAGS eflags;
667
668 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
669 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
670 {
671 VMX_WRITE_SELREG(ES, es);
672 AssertRC(rc);
673
674 VMX_WRITE_SELREG(CS, cs);
675 AssertRC(rc);
676
677 VMX_WRITE_SELREG(SS, ss);
678 AssertRC(rc);
679
680 VMX_WRITE_SELREG(DS, ds);
681 AssertRC(rc);
682
683 VMX_WRITE_SELREG(FS, fs);
684 AssertRC(rc);
685
686 VMX_WRITE_SELREG(GS, gs);
687 AssertRC(rc);
688 }
689
690 /* Guest CPU context: LDTR. */
691 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
692 {
693 if (pCtx->ldtr == 0)
694 {
695 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
696 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
697 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
698 /** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
699 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
700 }
701 else
702 {
703 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
704 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
705 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
706 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
707 }
708 AssertRC(rc);
709 }
710 /* Guest CPU context: TR. */
711 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
712 {
713 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
714
715 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
716 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
717 {
718 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
719 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
720 }
721 else
722 {
723 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
724 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
725 }
726 val = pCtx->trHid.Attr.u;
727
728 /* The TSS selector must be busy. */
729 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
730 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
731 else
732 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
733 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
734
735 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
736 AssertRC(rc);
737 }
738 /* Guest CPU context: GDTR. */
739 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
740 {
741 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
742 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
743 AssertRC(rc);
744 }
745 /* Guest CPU context: IDTR. */
746 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
747 {
748 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
749 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
750 AssertRC(rc);
751 }
752
753 /*
754 * Sysenter MSRs
755 */
756 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
757 {
758 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
759 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
760 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
761 AssertRC(rc);
762 }
763
764 /* Control registers */
765 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
766 {
767 val = pCtx->cr0;
768 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
769 Log2(("Guest CR0-shadow %08x\n", val));
770 if (CPUMIsGuestFPUStateActive(pVM) == false)
771 {
772 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
773 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
774 }
775 else
776 {
777 Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
778 /** @todo check if we support the old style mess correctly. */
779 if (!(val & X86_CR0_NE))
780 {
781 Log(("Forcing X86_CR0_NE!!!\n"));
782
783 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
784 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
785 {
786 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK | RT_BIT(X86_XCPT_MF));
787 AssertRC(rc);
788 pVM->hwaccm.s.fFPUOldStyleOverride = true;
789 }
790 }
791
792 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
793 }
794 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
795 val |= X86_CR0_PE | X86_CR0_PG;
796 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
797 val |= X86_CR0_WP;
798
799 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
800 Log2(("Guest CR0 %08x\n", val));
801 /* CR0 flags owned by the host; if the guests attempts to change them, then
802 * the VM will exit.
803 */
804 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
805 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
806 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
807 | X86_CR0_TS
808 | X86_CR0_ET
809 | X86_CR0_NE
810 | X86_CR0_MP;
811 pVM->hwaccm.s.vmx.cr0_mask = val;
812
813 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
814 Log2(("Guest CR0-mask %08x\n", val));
815 AssertRC(rc);
816 }
817 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
818 {
819 /* CR4 */
820 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
821 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
822 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
823 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
824 switch(pVM->hwaccm.s.enmShadowMode)
825 {
826 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
827 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
828 case PGMMODE_32_BIT: /* 32-bit paging. */
829 break;
830
831 case PGMMODE_PAE: /* PAE paging. */
832 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
833 /** @todo use normal 32 bits paging */
834 val |= X86_CR4_PAE;
835 break;
836
837 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
838 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
839#ifdef VBOX_ENABLE_64_BITS_GUESTS
840 break;
841#else
842 AssertFailed();
843 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
844#endif
845 default: /* shut up gcc */
846 AssertFailed();
847 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
848 }
849 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
850 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
851 val |= X86_CR4_VME;
852
853 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
854 Log2(("Guest CR4 %08x\n", val));
855 /* CR4 flags owned by the host; if the guests attempts to change them, then
856 * the VM will exit.
857 */
858 val = X86_CR4_PAE
859 | X86_CR4_PGE
860 | X86_CR4_PSE
861 | X86_CR4_VMXE;
862 pVM->hwaccm.s.vmx.cr4_mask = val;
863
864 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
865 Log2(("Guest CR4-mask %08x\n", val));
866 AssertRC(rc);
867 }
868
869 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
870 {
871 /* Save our shadow CR3 register. */
872 val = PGMGetHyperCR3(pVM);
873 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
874 AssertRC(rc);
875 }
876
877 /* Debug registers. */
878 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
879 {
880 /** @todo DR0-6 */
881 val = pCtx->dr7;
882 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
883 val |= 0x400; /* must be one */
884#ifdef VBOX_STRICT
885 val = 0x400;
886#endif
887 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
888 AssertRC(rc);
889
890 /* IA32_DEBUGCTL MSR. */
891 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
892 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
893 AssertRC(rc);
894
895 /** @todo */
896 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
897 AssertRC(rc);
898 }
899
900 /* EIP, ESP and EFLAGS */
901 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
902 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
903 AssertRC(rc);
904
905 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
906 eflags = pCtx->eflags;
907 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
908 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
909
910 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
911 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
912 {
913 eflags.Bits.u1VM = 1;
914 eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
915 eflags.Bits.u2IOPL = 3;
916 }
917
918 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
919 AssertRC(rc);
920
921 /** TSC offset. */
922 uint64_t u64TSCOffset;
923
924 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
925 {
926 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
927#if HC_ARCH_BITS == 64
928 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
929#else
930 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
931 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
932#endif
933 AssertRC(rc);
934
935 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
936 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
937 AssertRC(rc);
938 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
939 }
940 else
941 {
942 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
943 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
944 AssertRC(rc);
945 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
946 }
947
948 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
949 * Set required bits to one and zero according to the MSR capabilities.
950 */
951 val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
952
953 /* Mask away the bits that the CPU doesn't support */
954 /** @todo make sure they don't conflict with the above requirements. */
955 val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
956 /* else Must be zero when AMD64 is not available. */
957 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
958 AssertRC(rc);
959
960 /* 64 bits guest mode? */
961 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
962 {
963 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
964#ifndef VBOX_WITH_64_BITS_GUESTS
965 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
966#else
967 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
968#endif
969 }
970 else
971 {
972 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
973 }
974
975 /* Done. */
976 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
977
978 return rc;
979}
980
981/**
982 * Runs guest code in a VT-x VM.
983 *
984 * @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
985 *
986 * @returns VBox status code.
987 * @param pVM The VM to operate on.
988 * @param pCtx Guest context
989 * @param pCpu CPU info struct
990 */
991HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
992{
993 int rc = VINF_SUCCESS;
994 RTCCUINTREG val, valShadow;
995 RTCCUINTREG exitReason, instrError, cbInstr;
996 RTGCUINTPTR exitQualification;
997 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
998 RTGCUINTPTR errCode, instrInfo, uInterruptState;
999 bool fGuestStateSynced = false;
1000 unsigned cResume = 0;
1001
1002 Log2(("\nE"));
1003
1004 AssertReturn(pCpu->fConfigured, VERR_EM_INTERNAL_ERROR);
1005
1006 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1007
1008#ifdef VBOX_STRICT
1009 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1010 AssertRC(rc);
1011 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1012
1013 /* allowed zero */
1014 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
1015 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1016
1017 /* allowed one */
1018 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
1019 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1020
1021 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1022 AssertRC(rc);
1023 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1024
1025 /* allowed zero */
1026 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
1027 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1028
1029 /* allowed one */
1030 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
1031 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1032
1033 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1034 AssertRC(rc);
1035 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1036
1037 /* allowed zero */
1038 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
1039 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1040
1041 /* allowed one */
1042 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
1043 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1044
1045 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1046 AssertRC(rc);
1047 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1048
1049 /* allowed zero */
1050 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
1051 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1052
1053 /* allowed one */
1054 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
1055 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1056#endif
1057
1058#if 0
1059 /*
1060 * Check if debug registers are armed.
1061 */
1062 uint32_t u32DR7 = ASMGetDR7();
1063 if (u32DR7 & X86_DR7_ENABLED_MASK)
1064 {
1065 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
1066 }
1067 else
1068 pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1069#endif
1070
1071 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1072 */
1073ResumeExecution:
1074 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1075 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1076 {
1077 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1078 rc = VINF_EM_RAW_INTERRUPT;
1079 goto end;
1080 }
1081
1082 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1083 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1084 {
1085 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
1086 if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
1087 {
1088 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1089 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1090 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1091 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1092 */
1093 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1094 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1095 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1096 AssertRC(rc);
1097 }
1098 }
1099 else
1100 {
1101 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1102 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1103 AssertRC(rc);
1104 }
1105
1106 /* Check for pending actions that force us to go back to ring 3. */
1107 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1108 {
1109 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1110 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1111 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1112 rc = VINF_EM_RAW_TO_R3;
1113 goto end;
1114 }
1115 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1116 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1117 {
1118 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1119 rc = VINF_EM_PENDING_REQUEST;
1120 goto end;
1121 }
1122
1123 /* When external interrupts are pending, we should exit the VM when IF is set. */
1124 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
1125 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1126 if (VBOX_FAILURE(rc))
1127 {
1128 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1129 goto end;
1130 }
1131
1132 /** @todo check timers?? */
1133
1134 /* Save the host state first. */
1135 rc = VMXR0SaveHostState(pVM);
1136 if (rc != VINF_SUCCESS)
1137 {
1138 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1139 goto end;
1140 }
1141 /* Load the guest state */
1142 rc = VMXR0LoadGuestState(pVM, pCtx);
1143 if (rc != VINF_SUCCESS)
1144 {
1145 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1146 goto end;
1147 }
1148 fGuestStateSynced = true;
1149
1150 /* Non-register state Guest Context */
1151 /** @todo change me according to cpu state */
1152 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1153 AssertRC(rc);
1154
1155 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1156
1157 /* Manual save and restore:
1158 * - General purpose registers except RIP, RSP
1159 *
1160 * Trashed:
1161 * - CR2 (we don't care)
1162 * - LDTR (reset to 0)
1163 * - DRx (presumably not changed at all)
1164 * - DR7 (reset to 0x400)
1165 * - EFLAGS (reset to RT_BIT(1); not relevant)
1166 *
1167 */
1168
1169 /* All done! Let's start VM execution. */
1170 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1171 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1172
1173 /* In case we execute a goto ResumeExecution later on. */
1174 pVM->hwaccm.s.vmx.fResumeVM = true;
1175
1176 /**
1177 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1178 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1179 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1180 */
1181
1182 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1183 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1184
1185 switch (rc)
1186 {
1187 case VINF_SUCCESS:
1188 break;
1189
1190 case VERR_VMX_INVALID_VMXON_PTR:
1191 AssertFailed();
1192 goto end;
1193
1194 case VERR_VMX_UNABLE_TO_START_VM:
1195 case VERR_VMX_UNABLE_TO_RESUME_VM:
1196 {
1197#ifdef VBOX_STRICT
1198 int rc1;
1199
1200 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1201 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1202 AssertRC(rc1);
1203 if (rc1 == VINF_SUCCESS)
1204 {
1205 RTGDTR gdtr;
1206 PX86DESCHC pDesc;
1207
1208 ASMGetGDTR(&gdtr);
1209
1210 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1211 Log(("Current stack %08x\n", &rc1));
1212
1213
1214 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1215 Log(("Old eip %VGv new %VGv\n", pCtx->eip, (RTGCPTR)val));
1216 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1217 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1218 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1219 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1220 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1221 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1222 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1223 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1224
1225 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1226 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1227
1228 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1229 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1230
1231 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1232 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1233
1234 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1235 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1236 if (val < gdtr.cbGdt)
1237 {
1238 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1239 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1240 }
1241
1242 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1243 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1244 if (val < gdtr.cbGdt)
1245 {
1246 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1247 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1248 }
1249
1250 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1251 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1252 if (val < gdtr.cbGdt)
1253 {
1254 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1255 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1256 }
1257
1258 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1259 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1260 if (val < gdtr.cbGdt)
1261 {
1262 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1263 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1264 }
1265
1266 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1267 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1268 if (val < gdtr.cbGdt)
1269 {
1270 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1271 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1272 }
1273
1274 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1275 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1276 if (val < gdtr.cbGdt)
1277 {
1278 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1279 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1280 }
1281
1282 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1283 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1284 if (val < gdtr.cbGdt)
1285 {
1286 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1287 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1288 }
1289
1290 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1291 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1292
1293 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1294 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1295 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1296 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1297
1298 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1299 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1300
1301 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1302 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1303
1304 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1305 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1306
1307 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1308 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1309 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1310 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1311
1312#if HC_ARCH_BITS == 64
1313 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1314 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1315 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1316 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1317 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1318#endif
1319 }
1320#endif /* VBOX_STRICT */
1321 goto end;
1322 }
1323
1324 default:
1325 /* impossible */
1326 AssertFailed();
1327 goto end;
1328 }
1329 /* Success. Query the guest state and figure out what has happened. */
1330
1331 /* Investigate why there was a VM-exit. */
1332 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1333 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1334
1335 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1336 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1337 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1338 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1339 intInfo = val;
1340 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1341 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1342 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1343 instrInfo = val;
1344 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1345 exitQualification = val;
1346 AssertRC(rc);
1347
1348 /* Let's first sync back eip, esp, and eflags. */
1349 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1350 AssertRC(rc);
1351 pCtx->rip = val;
1352 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1353 AssertRC(rc);
1354 pCtx->rsp = val;
1355 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1356 AssertRC(rc);
1357 pCtx->eflags.u32 = val;
1358
1359 /* Take care of instruction fusing (sti, mov ss) */
1360 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1361 uInterruptState = val;
1362 if (uInterruptState != 0)
1363 {
1364 Assert(uInterruptState <= 2); /* only sti & mov ss */
1365 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1366 EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1367 }
1368 else
1369 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1370
1371 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1372 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1373 {
1374 /* Hide our emulation flags */
1375 pCtx->eflags.Bits.u1VM = 0;
1376 pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1377 pCtx->eflags.Bits.u1VIF = 0;
1378 pCtx->eflags.Bits.u2IOPL = 0;
1379 }
1380
1381 /* Control registers. */
1382 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1383 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1384 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1385 CPUMSetGuestCR0(pVM, val);
1386
1387 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1388 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1389 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1390 CPUMSetGuestCR4(pVM, val);
1391
1392 CPUMSetGuestCR2(pVM, ASMGetCR2());
1393
1394 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1395 CPUMSetGuestDR7(pVM, val);
1396
1397 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1398 VMX_READ_SELREG(ES, es);
1399 VMX_READ_SELREG(SS, ss);
1400 VMX_READ_SELREG(CS, cs);
1401 VMX_READ_SELREG(DS, ds);
1402 VMX_READ_SELREG(FS, fs);
1403 VMX_READ_SELREG(GS, gs);
1404
1405 /** @note NOW IT'S SAFE FOR LOGGING! */
1406 Log2(("Raw exit reason %08x\n", exitReason));
1407
1408 /* Check if an injected event was interrupted prematurely. */
1409 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1410 AssertRC(rc);
1411 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1412 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1413 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1414 {
1415 Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1416 pVM->hwaccm.s.Event.fPending = true;
1417 /* Error code present? */
1418 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1419 {
1420 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1421 AssertRC(rc);
1422 pVM->hwaccm.s.Event.errCode = val;
1423 }
1424 else
1425 pVM->hwaccm.s.Event.errCode = 0;
1426 }
1427
1428#ifdef VBOX_STRICT
1429 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1430 HWACCMDumpRegs(pCtx);
1431#endif
1432
1433 Log2(("E%d", exitReason));
1434 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1435 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1436 Log2(("Interruption error code %d\n", errCode));
1437 Log2(("IntInfo = %08x\n", intInfo));
1438 Log2(("New EIP=%VGv\n", pCtx->eip));
1439
1440 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1441 switch (exitReason)
1442 {
1443 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1444 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1445 {
1446 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1447
1448 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1449 {
1450 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1451 /* External interrupt; leave to allow it to be dispatched again. */
1452 rc = VINF_EM_RAW_INTERRUPT;
1453 break;
1454 }
1455 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1456 {
1457 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1458 /* External interrupt; leave to allow it to be dispatched again. */
1459 rc = VINF_EM_RAW_INTERRUPT;
1460 break;
1461
1462 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1463 AssertFailed(); /* can't come here; fails the first check. */
1464 break;
1465
1466 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1467 Assert(vector == 3 || vector == 4);
1468 /* no break */
1469 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1470 Log2(("Hardware/software interrupt %d\n", vector));
1471 switch (vector)
1472 {
1473 case X86_XCPT_NM:
1474 {
1475 uint32_t oldCR0;
1476
1477 Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1478
1479 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1480 oldCR0 = ASMGetCR0();
1481 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1482 rc = CPUMHandleLazyFPU(pVM);
1483 if (rc == VINF_SUCCESS)
1484 {
1485 Assert(CPUMIsGuestFPUStateActive(pVM));
1486
1487 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
1488 ASMSetCR0(oldCR0);
1489
1490 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1491
1492 /* Continue execution. */
1493 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1494 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1495
1496 goto ResumeExecution;
1497 }
1498
1499 Log(("Forward #NM fault to the guest\n"));
1500 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1501 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1502 AssertRC(rc);
1503 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1504 goto ResumeExecution;
1505 }
1506
1507 case X86_XCPT_PF: /* Page fault */
1508 {
1509 Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1510 /* Exit qualification contains the linear address of the page fault. */
1511 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1512 TRPMSetErrorCode(pVM, errCode);
1513 TRPMSetFaultAddress(pVM, exitQualification);
1514
1515 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1516 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1517 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1518 if (rc == VINF_SUCCESS)
1519 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1520 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1521 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1522
1523 TRPMResetTrap(pVM);
1524
1525 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1526 goto ResumeExecution;
1527 }
1528 else
1529 if (rc == VINF_EM_RAW_GUEST_TRAP)
1530 { /* A genuine pagefault.
1531 * Forward the trap to the guest by injecting the exception and resuming execution.
1532 */
1533 Log2(("Forward page fault to the guest\n"));
1534 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1535 /* The error code might have been changed. */
1536 errCode = TRPMGetErrorCode(pVM);
1537
1538 TRPMResetTrap(pVM);
1539
1540 /* Now we must update CR2. */
1541 pCtx->cr2 = exitQualification;
1542 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1543 AssertRC(rc);
1544
1545 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1546 goto ResumeExecution;
1547 }
1548#ifdef VBOX_STRICT
1549 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1550 Log2(("PGMTrap0eHandler failed with %d\n", rc));
1551#endif
1552 /* Need to go back to the recompiler to emulate the instruction. */
1553 TRPMResetTrap(pVM);
1554 break;
1555 }
1556
1557 case X86_XCPT_MF: /* Floating point exception. */
1558 {
1559 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1560 if (!(pCtx->cr0 & X86_CR0_NE))
1561 {
1562 /* old style FPU error reporting needs some extra work. */
1563 /** @todo don't fall back to the recompiler, but do it manually. */
1564 rc = VINF_EM_RAW_EMULATE_INSTR;
1565 break;
1566 }
1567 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1568 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1569 AssertRC(rc);
1570
1571 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1572 goto ResumeExecution;
1573 }
1574
1575#ifdef VBOX_STRICT
1576 case X86_XCPT_GP: /* General protection failure exception.*/
1577 case X86_XCPT_UD: /* Unknown opcode exception. */
1578 case X86_XCPT_DE: /* Debug exception. */
1579 case X86_XCPT_SS: /* Stack segment exception. */
1580 case X86_XCPT_NP: /* Segment not present exception. */
1581 {
1582 switch(vector)
1583 {
1584 case X86_XCPT_DE:
1585 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1586 break;
1587 case X86_XCPT_UD:
1588 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1589 break;
1590 case X86_XCPT_SS:
1591 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1592 break;
1593 case X86_XCPT_NP:
1594 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1595 break;
1596 case X86_XCPT_GP:
1597 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1598 break;
1599 }
1600
1601 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1602 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1603 AssertRC(rc);
1604
1605 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1606 goto ResumeExecution;
1607 }
1608#endif
1609 default:
1610 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1611 rc = VERR_EM_INTERNAL_ERROR;
1612 break;
1613 } /* switch (vector) */
1614
1615 break;
1616
1617 default:
1618 rc = VERR_EM_INTERNAL_ERROR;
1619 AssertFailed();
1620 break;
1621 }
1622
1623 break;
1624 }
1625
1626 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1627 /* Clear VM-exit on IF=1 change. */
1628 Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1629 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1630 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1631 AssertRC(rc);
1632 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1633 goto ResumeExecution; /* we check for pending guest interrupts there */
1634
1635 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1636 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1637 /* Skip instruction and continue directly. */
1638 pCtx->eip += cbInstr;
1639 /* Continue execution.*/
1640 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1641 goto ResumeExecution;
1642
1643 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1644 {
1645 Log2(("VMX: Cpuid %x\n", pCtx->eax));
1646 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1647 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1648 if (rc == VINF_SUCCESS)
1649 {
1650 /* Update EIP and continue execution. */
1651 Assert(cbInstr == 2);
1652 pCtx->eip += cbInstr;
1653 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1654 goto ResumeExecution;
1655 }
1656 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1657 rc = VINF_EM_RAW_EMULATE_INSTR;
1658 break;
1659 }
1660
1661 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1662 {
1663 Log2(("VMX: Rdtsc\n"));
1664 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1665 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1666 if (rc == VINF_SUCCESS)
1667 {
1668 /* Update EIP and continue execution. */
1669 Assert(cbInstr == 2);
1670 pCtx->eip += cbInstr;
1671 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1672 goto ResumeExecution;
1673 }
1674 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1675 rc = VINF_EM_RAW_EMULATE_INSTR;
1676 break;
1677 }
1678
1679 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1680 {
1681 Log2(("VMX: invlpg\n"));
1682 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1683 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1684 if (rc == VINF_SUCCESS)
1685 {
1686 /* Update EIP and continue execution. */
1687 pCtx->eip += cbInstr;
1688 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1689 goto ResumeExecution;
1690 }
1691 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1692 break;
1693 }
1694
1695 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1696 {
1697 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1698 {
1699 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1700 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1701 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1702 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1703 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1704 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1705
1706 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1707 {
1708 case 0:
1709 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1710 break;
1711 case 2:
1712 break;
1713 case 3:
1714 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1715 break;
1716 case 4:
1717 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1718 break;
1719 default:
1720 AssertFailed();
1721 }
1722 /* Check if a sync operation is pending. */
1723 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1724 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1725 {
1726 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1727 AssertRC(rc);
1728 }
1729 break;
1730
1731 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1732 Log2(("VMX: mov x, crx\n"));
1733 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1734 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1735 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1736 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1737 break;
1738
1739 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1740 Log2(("VMX: clts\n"));
1741 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1742 rc = EMInterpretCLTS(pVM);
1743 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1744 break;
1745
1746 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1747 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1748 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1749 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1750 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1751 break;
1752 }
1753
1754 /* Update EIP if no error occurred. */
1755 if (VBOX_SUCCESS(rc))
1756 pCtx->eip += cbInstr;
1757
1758 if (rc == VINF_SUCCESS)
1759 {
1760 /* Only resume if successful. */
1761 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1762 goto ResumeExecution;
1763 }
1764 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1765 break;
1766 }
1767
1768 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1769 {
1770 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1771 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1772 {
1773 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1774 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1775 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1776 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1777 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1778 Log2(("DR7=%08x\n", pCtx->dr7));
1779 }
1780 else
1781 {
1782 Log2(("VMX: mov x, drx\n"));
1783 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1784 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1785 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1786 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1787 }
1788 /* Update EIP if no error occurred. */
1789 if (VBOX_SUCCESS(rc))
1790 pCtx->eip += cbInstr;
1791
1792 if (rc == VINF_SUCCESS)
1793 {
1794 /* Only resume if successful. */
1795 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1796 goto ResumeExecution;
1797 }
1798 Assert(rc == VERR_EM_INTERPRETER);
1799 break;
1800 }
1801
1802 /** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1803 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1804 {
1805 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1806 uint32_t uPort;
1807 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1808
1809 /** @todo necessary to make the distinction? */
1810 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1811 {
1812 uPort = pCtx->edx & 0xffff;
1813 }
1814 else
1815 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1816
1817 /* paranoia */
1818 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
1819 {
1820 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1821 break;
1822 }
1823
1824 uint32_t cbSize = aIOSize[uIOWidth];
1825
1826 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1827 {
1828 /* ins/outs */
1829 uint32_t prefix = 0;
1830 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1831 prefix |= PREFIX_REP;
1832
1833 if (fIOWrite)
1834 {
1835 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1836 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1837 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1838 }
1839 else
1840 {
1841 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1842 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1843 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1844 }
1845 }
1846 else
1847 {
1848 /* normal in/out */
1849 uint32_t uAndVal = aIOOpAnd[uIOWidth];
1850
1851 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1852
1853 if (fIOWrite)
1854 {
1855 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1856 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1857 }
1858 else
1859 {
1860 uint32_t u32Val = 0;
1861
1862 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1863 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1864 if (IOM_SUCCESS(rc))
1865 {
1866 /* Write back to the EAX register. */
1867 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1868 }
1869 }
1870 }
1871 /*
1872 * Handled the I/O return codes.
1873 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1874 */
1875 if (IOM_SUCCESS(rc))
1876 {
1877 /* Update EIP and continue execution. */
1878 pCtx->eip += cbInstr;
1879 if (RT_LIKELY(rc == VINF_SUCCESS))
1880 {
1881 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1882 goto ResumeExecution;
1883 }
1884 break;
1885 }
1886
1887#ifdef VBOX_STRICT
1888 if (rc == VINF_IOM_HC_IOPORT_READ)
1889 Assert(!fIOWrite);
1890 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1891 Assert(fIOWrite);
1892 else
1893 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1894#endif
1895 break;
1896 }
1897
1898 default:
1899 /* The rest is handled after syncing the entire CPU state. */
1900 break;
1901 }
1902
1903 /* Note: the guest state isn't entirely synced back at this stage. */
1904
1905 /* Investigate why there was a VM-exit. (part 2) */
1906 switch (exitReason)
1907 {
1908 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1909 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1910 /* Already handled above. */
1911 break;
1912
1913 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1914 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1915 break;
1916
1917 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1918 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1919 rc = VINF_EM_RAW_INTERRUPT;
1920 AssertFailed(); /* Can't happen. Yet. */
1921 break;
1922
1923 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1924 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1925 rc = VINF_EM_RAW_INTERRUPT;
1926 AssertFailed(); /* Can't happen afaik. */
1927 break;
1928
1929 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1930 rc = VERR_EM_INTERPRETER;
1931 break;
1932
1933 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1934 /** Check if external interrupts are pending; if so, don't switch back. */
1935 if ( pCtx->eflags.Bits.u1IF
1936 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
1937 {
1938 pCtx->eip++; /* skip hlt */
1939 goto ResumeExecution;
1940 }
1941
1942 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1943 break;
1944
1945 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1946 AssertFailed(); /* can't happen. */
1947 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1948 break;
1949
1950 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1951 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1952 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1953 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1954 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1955 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1956 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1957 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1958 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1959 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1960 /** @todo inject #UD immediately */
1961 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1962 break;
1963
1964 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1965 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1966 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1967 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1968 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1969 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1970 /* already handled above */
1971 AssertMsg( rc == VINF_PGM_CHANGE_MODE
1972 || rc == VINF_EM_RAW_INTERRUPT
1973 || rc == VERR_EM_INTERPRETER
1974 || rc == VINF_EM_RAW_EMULATE_INSTR
1975 || rc == VINF_PGM_SYNC_CR3
1976 || rc == VINF_IOM_HC_IOPORT_READ
1977 || rc == VINF_IOM_HC_IOPORT_WRITE
1978 || rc == VINF_EM_RAW_GUEST_TRAP
1979 || rc == VINF_TRPM_XCPT_DISPATCHED
1980 || rc == VINF_EM_RESCHEDULE_REM,
1981 ("rc = %d\n", rc));
1982 break;
1983
1984 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1985 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1986 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1987 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1988 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1989 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1990 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1991 break;
1992
1993 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1994 Assert(rc == VINF_EM_RAW_INTERRUPT);
1995 break;
1996
1997 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1998 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1999 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2000 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2001 default:
2002 rc = VERR_EM_INTERNAL_ERROR;
2003 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2004 break;
2005
2006 }
2007end:
2008 if (fGuestStateSynced)
2009 {
2010 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2011 VMX_READ_SELREG(LDTR, ldtr);
2012 VMX_READ_SELREG(TR, tr);
2013
2014 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2015 pCtx->gdtr.cbGdt = val;
2016 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2017 pCtx->gdtr.pGdt = val;
2018
2019 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2020 pCtx->idtr.cbIdt = val;
2021 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2022 pCtx->idtr.pIdt = val;
2023
2024 /*
2025 * System MSRs
2026 */
2027 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
2028 pCtx->SysEnter.cs = val;
2029 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
2030 pCtx->SysEnter.eip = val;
2031 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
2032 pCtx->SysEnter.esp = val;
2033 }
2034
2035 /* Signal changes for the recompiler. */
2036 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2037
2038 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2039 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2040 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2041 {
2042 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2043 /* On the next entry we'll only sync the host context. */
2044 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2045 }
2046 else
2047 {
2048 /* On the next entry we'll sync everything. */
2049 /** @todo we can do better than this */
2050 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2051 }
2052
2053 /* translate into a less severe return code */
2054 if (rc == VERR_EM_INTERPRETER)
2055 rc = VINF_EM_RAW_EMULATE_INSTR;
2056
2057 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2058 Log2(("X"));
2059 return rc;
2060}
2061
2062
2063/**
2064 * Enters the VT-x session
2065 *
2066 * @returns VBox status code.
2067 * @param pVM The VM to operate on.
2068 * @param pCpu CPU info struct
2069 */
2070HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2071{
2072 Assert(pVM->hwaccm.s.vmx.fSupported);
2073
2074 unsigned cr4 = ASMGetCR4();
2075 if (!(cr4 & X86_CR4_VMXE))
2076 {
2077 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2078 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2079 }
2080
2081 /* Activate the VM Control Structure. */
2082 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2083 if (VBOX_FAILURE(rc))
2084 return rc;
2085
2086 pVM->hwaccm.s.vmx.fResumeVM = false;
2087 return VINF_SUCCESS;
2088}
2089
2090
2091/**
2092 * Leaves the VT-x session
2093 *
2094 * @returns VBox status code.
2095 * @param pVM The VM to operate on.
2096 */
2097HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2098{
2099 Assert(pVM->hwaccm.s.vmx.fSupported);
2100
2101 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2102 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2103 AssertRC(rc);
2104
2105 return VINF_SUCCESS;
2106}
2107
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