HWVMXR0.cpp@ 10108

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1	/* $Id: HWVMXR0.cpp 10108 2008-07-02 14:06:24Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/string.h>
41	#include "HWVMXR0.h"
42
43
44	/* IO operation lookup arrays. */
45	static uint32_t aIOSize[4] = {1, 2, 0, 4};
46	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49	static void VMXR0CheckError(PVM pVM, int rc)
50	{
51	if (rc == VERR_VMX_GENERIC)
52	{
53	RTCCUINTREG instrError;
54
55	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57	}
58	pVM->hwaccm.s.lLastError = rc;
59	}
60
61	/**
62	* Sets up and activates VT-x on the current CPU
63	*
64	* @returns VBox status code.
65	* @param pCpu CPU info struct
66	* @param pVM The VM to operate on.
67	* @param pvPageCpu Pointer to the global cpu page
68	* @param pPageCpuPhys Physical address of the global cpu page
69	*/
70	HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71	{
72	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73	AssertReturn(pVM, VERR_INVALID_PARAMETER);
74	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76	/* Setup Intel VMX. */
77	Assert(pVM->hwaccm.s.vmx.fSupported);
78
79	#ifdef LOG_ENABLED
80	SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81	#endif
82	/* Set revision dword at the beginning of the VMXON structure. */
83	(uint32_t )pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86	* (which can have very bad consequences!!!)
87	*/
88
89	/* Make sure the VMX instructions don't cause #UD faults. */
90	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
91
92	/* Enter VMX Root Mode */
93	int rc = VMXEnable(pPageCpuPhys);
94	if (VBOX_FAILURE(rc))
95	{
96	VMXR0CheckError(pVM, rc);
97	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98	return VERR_VMX_VMXON_FAILED;
99	}
100	return VINF_SUCCESS;
101	}
102
103	/**
104	* Deactivates VT-x on the current CPU
105	*
106	* @returns VBox status code.
107	* @param pCpu CPU info struct
108	* @param pvPageCpu Pointer to the global cpu page
109	* @param pPageCpuPhys Physical address of the global cpu page
110	*/
111	HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112	{
113	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116	/* Leave VMX Root Mode. */
117	VMXDisable();
118
119	/* And clear the X86_CR4_VMXE bit */
120	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122	#ifdef LOG_ENABLED
123	SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124	#endif
125	return VINF_SUCCESS;
126	}
127
128	/**
129	* Does Ring-0 per VM VT-x init.
130	*
131	* @returns VBox status code.
132	* @param pVM The VM to operate on.
133	*/
134	HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135	{
136	int rc;
137
138	#ifdef LOG_ENABLED
139	SUPR0Printf("VMXR0InitVM %x\n", pVM);
140	#endif
141
142	/* Allocate one page for the VM control structure (VMCS). */
143	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
144	AssertRC(rc);
145	if (RT_FAILURE(rc))
146	return rc;
147
148	pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
149	pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
150	ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
151
152	/* Allocate one page for the TSS we need for real mode emulation. */
153	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
154	AssertRC(rc);
155	if (RT_FAILURE(rc))
156	return rc;
157
158	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
159	pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
160
161	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
162	* for I/O operations. */
163	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
164	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
165	/* Bit set to 0 means redirection enabled. */
166	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
167
168	#ifdef LOG_ENABLED
169	SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
170	#endif
171	return VINF_SUCCESS;
172	}
173
174	/**
175	* Does Ring-0 per VM VT-x termination.
176	*
177	* @returns VBox status code.
178	* @param pVM The VM to operate on.
179	*/
180	HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
181	{
182	if (pVM->hwaccm.s.vmx.pMemObjVMCS)
183	{
184	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
185	pVM->hwaccm.s.vmx.pMemObjVMCS = 0;
186	pVM->hwaccm.s.vmx.pVMCS = 0;
187	pVM->hwaccm.s.vmx.pVMCSPhys = 0;
188	}
189	if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS)
190	{
191	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
192	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = 0;
193	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
194	pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
195	}
196	return VINF_SUCCESS;
197	}
198
199	/**
200	* Sets up VT-x for the specified VM
201	*
202	* @returns VBox status code.
203	* @param pVM The VM to operate on.
204	*/
205	HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
206	{
207	int rc = VINF_SUCCESS;
208	uint32_t val;
209
210	AssertReturn(pVM, VERR_INVALID_PARAMETER);
211	Assert(pVM->hwaccm.s.vmx.pVMCS);
212
213	/* Set revision dword at the beginning of the VMCS structure. */
214	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
215
216	/* Clear VM Control Structure. */
217	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
218	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
219	if (VBOX_FAILURE(rc))
220	goto vmx_end;
221
222	/* Activate the VM Control Structure. */
223	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
224	if (VBOX_FAILURE(rc))
225	goto vmx_end;
226
227	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
228	* Set required bits to one and zero according to the MSR capabilities.
229	*/
230	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
231	/* External and non-maskable interrupts cause VM-exits. */
232	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
233	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
234
235	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
236	AssertRC(rc);
237
238	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
239	* Set required bits to one and zero according to the MSR capabilities.
240	*/
241	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
242	/* Program which event cause VM-exits and which features we want to use. */
243	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
244	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
245	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
246	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
247	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
248	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
249
250	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
251
252	/*
253	if AMD64 guest mode
254	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
255	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
256	*/
257	#if HC_ARCH_BITS == 64
258	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
259	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
260	#endif
261	/* Mask away the bits that the CPU doesn't support */
262	/** @todo make sure they don't conflict with the above requirements. */
263	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
264	pVM->hwaccm.s.vmx.proc_ctls = val;
265
266	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
267	AssertRC(rc);
268
269	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
270	* Set required bits to one and zero according to the MSR capabilities.
271	*/
272	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
273	AssertRC(rc);
274
275	/* VMX_VMCS_CTRL_EXIT_CONTROLS
276	* Set required bits to one and zero according to the MSR capabilities.
277	*/
278	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
279	#if HC_ARCH_BITS == 64
280	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
281	#else
282	/* else Must be zero when AMD64 is not available. */
283	#endif
284	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
285	/* Don't acknowledge external interrupts on VM-exit. */
286	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
287	AssertRC(rc);
288
289	/* Forward all exception except #NM & #PF to the guest.
290	* We always need to check pagefaults since our shadow page table can be out of sync.
291	* And we always lazily sync the FPU & XMM state.
292	*/
293
294	/*
295	* @todo Possible optimization:
296	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
297	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
298	* registers ourselves of course.
299	*
300	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
301	*/
302	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
303	AssertRC(rc);
304
305	/* Don't filter page faults; all of them should cause a switch. */
306	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
307	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
308	AssertRC(rc);
309
310	/* Init TSC offset to zero. */
311	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
312	#if HC_ARCH_BITS == 32
313	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
314	#endif
315	AssertRC(rc);
316
317	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
318	#if HC_ARCH_BITS == 32
319	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
320	#endif
321	AssertRC(rc);
322
323	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
324	#if HC_ARCH_BITS == 32
325	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
326	#endif
327	AssertRC(rc);
328
329	/* Clear MSR controls. */
330	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
331	{
332	/* Optional */
333	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
334	#if HC_ARCH_BITS == 32
335	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
336	#endif
337	AssertRC(rc);
338	}
339	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
340	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
341	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
342	#if HC_ARCH_BITS == 32
343	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
344	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
345	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
346	#endif
347	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
348	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
349	AssertRC(rc);
350
351	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
352	{
353	/* Optional */
354	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
355	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
356	#if HC_ARCH_BITS == 32
357	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
358	#endif
359	AssertRC(rc);
360	}
361
362	/* Set link pointer to -1. Not currently used. */
363	#if HC_ARCH_BITS == 32
364	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
365	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
366	#else
367	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
368	#endif
369	AssertRC(rc);
370
371	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
372	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
373	AssertRC(rc);
374
375	vmx_end:
376	VMXR0CheckError(pVM, rc);
377	return rc;
378	}
379
380
381	/**
382	* Injects an event (trap or external interrupt)
383	*
384	* @returns VBox status code.
385	* @param pVM The VM to operate on.
386	* @param pCtx CPU Context
387	* @param intInfo VMX interrupt info
388	* @param cbInstr Opcode length of faulting instruction
389	* @param errCode Error code (optional)
390	*/
391	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
392	{
393	int rc;
394
395	#ifdef VBOX_STRICT
396	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
397	if (iGate == 0xE)
398	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
399	else
400	if (iGate < 0x20)
401	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
402	else
403	{
404	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
405	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
406	Assert(pCtx->eflags.u32 & X86_EFL_IF);
407	}
408	#endif
409
410	/* Set event injection state. */
411	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
412	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
413	);
414
415	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
416	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
417
418	AssertRC(rc);
419	return rc;
420	}
421
422
423	/**
424	* Checks for pending guest interrupts and injects them
425	*
426	* @returns VBox status code.
427	* @param pVM The VM to operate on.
428	* @param pCtx CPU Context
429	*/
430	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
431	{
432	int rc;
433
434	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
435	if (pVM->hwaccm.s.Event.fPending)
436	{
437	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
438	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
439	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
440	AssertRC(rc);
441
442	pVM->hwaccm.s.Event.fPending = false;
443	return VINF_SUCCESS;
444	}
445
446	/* When external interrupts are pending, we should exit the VM when IF is set. */
447	if ( !TRPMHasTrap(pVM)
448	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
449	{
450	if (!(pCtx->eflags.u32 & X86_EFL_IF))
451	{
452	Log2(("Enable irq window exit!\n"));
453	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
454	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
455	AssertRC(rc);
456	}
457	else
458	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
459	{
460	uint8_t u8Interrupt;
461
462	rc = PDMGetInterrupt(pVM, &u8Interrupt);
463	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
464	if (VBOX_SUCCESS(rc))
465	{
466	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
467	AssertRC(rc);
468	}
469	else
470	{
471	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
472	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
473	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
474	/* Just continue */
475	}
476	}
477	else
478	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
479	}
480
481	#ifdef VBOX_STRICT
482	if (TRPMHasTrap(pVM))
483	{
484	uint8_t u8Vector;
485	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
486	AssertRC(rc);
487	}
488	#endif
489
490	if ( pCtx->eflags.u32 & X86_EFL_IF
491	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
492	&& TRPMHasTrap(pVM)
493	)
494	{
495	uint8_t u8Vector;
496	int rc;
497	TRPMEVENT enmType;
498	RTGCUINTPTR intInfo;
499	RTGCUINT errCode;
500
501	/* If a new event is pending, then dispatch it now. */
502	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
503	AssertRC(rc);
504	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
505	Assert(enmType != TRPM_SOFTWARE_INT);
506
507	/* Clear the pending trap. */
508	rc = TRPMResetTrap(pVM);
509	AssertRC(rc);
510
511	intInfo = u8Vector;
512	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
513
514	if (enmType == TRPM_TRAP)
515	{
516	switch (u8Vector) {
517	case 8:
518	case 10:
519	case 11:
520	case 12:
521	case 13:
522	case 14:
523	case 17:
524	/* Valid error codes. */
525	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
526	break;
527	default:
528	break;
529	}
530	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
531	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
532	else
533	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
534	}
535	else
536	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
537
538	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
539	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
540	AssertRC(rc);
541	} /* if (interrupts can be dispatched) */
542
543	return VINF_SUCCESS;
544	}
545
546	/**
547	* Save the host state
548	*
549	* @returns VBox status code.
550	* @param pVM The VM to operate on.
551	*/
552	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
553	{
554	int rc = VINF_SUCCESS;
555
556	/*
557	* Host CPU Context
558	*/
559	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
560	{
561	RTIDTR idtr;
562	RTGDTR gdtr;
563	RTSEL SelTR;
564	PX86DESCHC pDesc;
565	uintptr_t trBase;
566
567	/* Control registers */
568	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
569	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
570	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
571	AssertRC(rc);
572	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
573	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
574	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
575
576	/* Selector registers. */
577	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
578	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
579	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
580	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
581	#if HC_ARCH_BITS == 32
582	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
583	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
584	#endif
585	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
586	SelTR = ASMGetTR();
587	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
588	AssertRC(rc);
589	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
590	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
591	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
592	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
593	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
594	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
595	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
596
597	/* GDTR & IDTR */
598	ASMGetGDTR(&gdtr);
599	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
600	ASMGetIDTR(&idtr);
601	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
602	AssertRC(rc);
603	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
604	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
605
606	/* Save the base address of the TR selector. */
607	if (SelTR > gdtr.cbGdt)
608	{
609	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
610	return VERR_VMX_INVALID_HOST_STATE;
611	}
612
613	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
614	#if HC_ARCH_BITS == 64
615	trBase = X86DESC64_BASE(*pDesc);
616	#else
617	trBase = X86DESC_BASE(*pDesc);
618	#endif
619	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
620	AssertRC(rc);
621	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
622
623	/* FS and GS base. */
624	#if HC_ARCH_BITS == 64
625	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
626	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
627	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
628	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
629	#endif
630	AssertRC(rc);
631
632	/* Sysenter MSRs. */
633	/** @todo expensive!! */
634	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
635	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
636	#if HC_ARCH_BITS == 32
637	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
638	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
639	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
640	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
641	#else
642	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
643	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
644	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
645	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
646	#endif
647	AssertRC(rc);
648
649	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
650	}
651	return rc;
652	}
653
654
655	/**
656	* Loads the guest state
657	*
658	* @returns VBox status code.
659	* @param pVM The VM to operate on.
660	* @param pCtx Guest context
661	*/
662	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
663	{
664	int rc = VINF_SUCCESS;
665	RTGCUINTPTR val;
666	X86EFLAGS eflags;
667
668	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
669	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
670	{
671	VMX_WRITE_SELREG(ES, es);
672	AssertRC(rc);
673
674	VMX_WRITE_SELREG(CS, cs);
675	AssertRC(rc);
676
677	VMX_WRITE_SELREG(SS, ss);
678	AssertRC(rc);
679
680	VMX_WRITE_SELREG(DS, ds);
681	AssertRC(rc);
682
683	/* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
684	VMX_WRITE_SELREG(FS, fs);
685	AssertRC(rc);
686
687	VMX_WRITE_SELREG(GS, gs);
688	AssertRC(rc);
689	}
690
691	/* Guest CPU context: LDTR. */
692	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
693	{
694	if (pCtx->ldtr == 0)
695	{
696	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
697	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
698	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
699	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
700	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
701	}
702	else
703	{
704	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
705	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
706	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
707	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
708	}
709	AssertRC(rc);
710	}
711	/* Guest CPU context: TR. */
712	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
713	{
714	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
715
716	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
717	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
718	{
719	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
720	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
721	}
722	else
723	{
724	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
725	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
726	}
727	val = pCtx->trHid.Attr.u;
728
729	/* The TSS selector must be busy. */
730	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
731	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
732	else
733	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
734	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
735
736	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
737	AssertRC(rc);
738	}
739	/* Guest CPU context: GDTR. */
740	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
741	{
742	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
743	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
744	AssertRC(rc);
745	}
746	/* Guest CPU context: IDTR. */
747	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
748	{
749	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
750	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
751	AssertRC(rc);
752	}
753
754	/*
755	* Sysenter MSRs (unconditional)
756	*/
757	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
758	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
759	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
760	AssertRC(rc);
761
762	/* Control registers */
763	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
764	{
765	val = pCtx->cr0;
766	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
767	Log2(("Guest CR0-shadow %08x\n", val));
768	if (CPUMIsGuestFPUStateActive(pVM) == false)
769	{
770	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
771	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
772	}
773	else
774	{
775	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
776	/** @todo check if we support the old style mess correctly. */
777	if (!(val & X86_CR0_NE))
778	{
779	Log(("Forcing X86_CR0_NE!!!\n"));
780
781	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
782	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
783	{
784	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| RT_BIT(X86_XCPT_MF));
785	AssertRC(rc);
786	pVM->hwaccm.s.fFPUOldStyleOverride = true;
787	}
788	}
789
790	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
791	}
792	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
793	val \|= X86_CR0_PE \| X86_CR0_PG;
794	/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
795	val \|= X86_CR0_WP;
796
797	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
798	Log2(("Guest CR0 %08x\n", val));
799	/* CR0 flags owned by the host; if the guests attempts to change them, then
800	* the VM will exit.
801	*/
802	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
803	\| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
804	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
805	\| X86_CR0_TS
806	\| X86_CR0_ET
807	\| X86_CR0_NE
808	\| X86_CR0_MP;
809	pVM->hwaccm.s.vmx.cr0_mask = val;
810
811	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
812	Log2(("Guest CR0-mask %08x\n", val));
813	AssertRC(rc);
814	}
815	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
816	{
817	/* CR4 */
818	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
819	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
820	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
821	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
822	switch(pVM->hwaccm.s.enmShadowMode)
823	{
824	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
825	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
826	case PGMMODE_32_BIT: /* 32-bit paging. */
827	break;
828
829	case PGMMODE_PAE: /* PAE paging. */
830	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
831	/** @todo use normal 32 bits paging */
832	val \|= X86_CR4_PAE;
833	break;
834
835	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
836	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
837	#ifdef VBOX_ENABLE_64_BITS_GUESTS
838	break;
839	#else
840	AssertFailed();
841	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
842	#endif
843	default: /* shut up gcc */
844	AssertFailed();
845	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
846	}
847	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
848	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
849	val \|= X86_CR4_VME;
850
851	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
852	Log2(("Guest CR4 %08x\n", val));
853	/* CR4 flags owned by the host; if the guests attempts to change them, then
854	* the VM will exit.
855	*/
856	val = X86_CR4_PAE
857	\| X86_CR4_PGE
858	\| X86_CR4_PSE
859	\| X86_CR4_VMXE;
860	pVM->hwaccm.s.vmx.cr4_mask = val;
861
862	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
863	Log2(("Guest CR4-mask %08x\n", val));
864	AssertRC(rc);
865	}
866
867	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
868	{
869	/* Save our shadow CR3 register. */
870	val = PGMGetHyperCR3(pVM);
871	Assert(val);
872	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
873	AssertRC(rc);
874	}
875
876	/* Debug registers. */
877	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
878	{
879	/** @todo DR0-6 */
880	val = pCtx->dr7;
881	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
882	val \|= 0x400; /* must be one */
883	#ifdef VBOX_STRICT
884	val = 0x400;
885	#endif
886	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
887	AssertRC(rc);
888
889	/* IA32_DEBUGCTL MSR. */
890	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
891	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
892	AssertRC(rc);
893
894	/** @todo */
895	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
896	AssertRC(rc);
897	}
898
899	/* EIP, ESP and EFLAGS */
900	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
901	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
902	AssertRC(rc);
903
904	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
905	eflags = pCtx->eflags;
906	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
907	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
908
909	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
910	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
911	{
912	eflags.Bits.u1VM = 1;
913	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
914	eflags.Bits.u2IOPL = 3;
915	}
916
917	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
918	AssertRC(rc);
919
920	/** TSC offset. */
921	uint64_t u64TSCOffset;
922
923	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
924	{
925	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
926	#if HC_ARCH_BITS == 64
927	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
928	#else
929	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
930	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
931	#endif
932	AssertRC(rc);
933
934	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
935	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
936	AssertRC(rc);
937	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
938	}
939	else
940	{
941	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
942	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
943	AssertRC(rc);
944	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
945	}
946
947	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
948	* Set required bits to one and zero according to the MSR capabilities.
949	*/
950	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
951	/* 64 bits guest mode? */
952	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
953	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
954	/* else Must be zero when AMD64 is not available. */
955
956	/* Mask away the bits that the CPU doesn't support */
957	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
958	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
959	AssertRC(rc);
960
961	/* 64 bits guest mode? */
962	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
963	{
964	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
965	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
966	#else
967	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
968	#endif
969	/* Unconditionally update these as wrmsr might have changed them. */
970	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
971	AssertRC(rc);
972	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
973	AssertRC(rc);
974	}
975	else
976	{
977	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
978	}
979
980	/* Done. */
981	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
982
983	return rc;
984	}
985
986	/**
987	* Runs guest code in a VT-x VM.
988	*
989	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
990	*
991	* @returns VBox status code.
992	* @param pVM The VM to operate on.
993	* @param pCtx Guest context
994	* @param pCpu CPU info struct
995	*/
996	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
997	{
998	int rc = VINF_SUCCESS;
999	RTCCUINTREG val, valShadow;
1000	RTCCUINTREG exitReason, instrError, cbInstr;
1001	RTGCUINTPTR exitQualification;
1002	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1003	RTGCUINTPTR errCode, instrInfo, uInterruptState;
1004	bool fGuestStateSynced = false;
1005	unsigned cResume = 0;
1006
1007	Log2(("\nE"));
1008
1009	AssertReturn(pCpu->fConfigured, VERR_EM_INTERNAL_ERROR);
1010
1011	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1012
1013	#ifdef VBOX_STRICT
1014	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1015	AssertRC(rc);
1016	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1017
1018	/* allowed zero */
1019	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
1020	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1021
1022	/* allowed one */
1023	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
1024	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1025
1026	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1027	AssertRC(rc);
1028	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1029
1030	/* allowed zero */
1031	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
1032	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1033
1034	/* allowed one */
1035	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
1036	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1037
1038	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1039	AssertRC(rc);
1040	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1041
1042	/* allowed zero */
1043	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
1044	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1045
1046	/* allowed one */
1047	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
1048	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1049
1050	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1051	AssertRC(rc);
1052	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1053
1054	/* allowed zero */
1055	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
1056	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1057
1058	/* allowed one */
1059	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
1060	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1061	#endif
1062
1063	#if 0
1064	/*
1065	* Check if debug registers are armed.
1066	*/
1067	uint32_t u32DR7 = ASMGetDR7();
1068	if (u32DR7 & X86_DR7_ENABLED_MASK)
1069	{
1070	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
1071	}
1072	else
1073	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1074	#endif
1075
1076	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1077	*/
1078	ResumeExecution:
1079	/* Safety precaution; looping for too long here can have a very bad effect on the host */
1080	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1081	{
1082	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1083	rc = VINF_EM_RAW_INTERRUPT;
1084	goto end;
1085	}
1086
1087	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1088	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1089	{
1090	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1091	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1092	{
1093	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1094	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1095	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1096	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1097	*/
1098	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1099	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1100	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1101	AssertRC(rc);
1102	}
1103	}
1104	else
1105	{
1106	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1107	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1108	AssertRC(rc);
1109	}
1110
1111	/* Check for pending actions that force us to go back to ring 3. */
1112	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
1113	{
1114	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1115	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1116	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1117	rc = VINF_EM_RAW_TO_R3;
1118	goto end;
1119	}
1120	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1121	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1122	{
1123	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1124	rc = VINF_EM_PENDING_REQUEST;
1125	goto end;
1126	}
1127
1128	/* When external interrupts are pending, we should exit the VM when IF is set. */
1129	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
1130	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1131	if (VBOX_FAILURE(rc))
1132	{
1133	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1134	goto end;
1135	}
1136
1137	/** @todo check timers?? */
1138
1139	/* Save the host state first. */
1140	rc = VMXR0SaveHostState(pVM);
1141	if (rc != VINF_SUCCESS)
1142	{
1143	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1144	goto end;
1145	}
1146	/* Load the guest state */
1147	rc = VMXR0LoadGuestState(pVM, pCtx);
1148	if (rc != VINF_SUCCESS)
1149	{
1150	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1151	goto end;
1152	}
1153	fGuestStateSynced = true;
1154
1155	/* Non-register state Guest Context */
1156	/** @todo change me according to cpu state */
1157	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1158	AssertRC(rc);
1159
1160	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1161
1162	/* Manual save and restore:
1163	* - General purpose registers except RIP, RSP
1164	*
1165	* Trashed:
1166	* - CR2 (we don't care)
1167	* - LDTR (reset to 0)
1168	* - DRx (presumably not changed at all)
1169	* - DR7 (reset to 0x400)
1170	* - EFLAGS (reset to RT_BIT(1); not relevant)
1171	*
1172	*/
1173
1174	/* All done! Let's start VM execution. */
1175	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1176	rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1177
1178	/* In case we execute a goto ResumeExecution later on. */
1179	pVM->hwaccm.s.vmx.fResumeVM = true;
1180
1181	/**
1182	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1183	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1184	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1185	*/
1186
1187	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1188	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1189
1190	switch (rc)
1191	{
1192	case VINF_SUCCESS:
1193	break;
1194
1195	case VERR_VMX_INVALID_VMXON_PTR:
1196	AssertFailed();
1197	goto end;
1198
1199	case VERR_VMX_UNABLE_TO_START_VM:
1200	case VERR_VMX_UNABLE_TO_RESUME_VM:
1201	{
1202	#ifdef VBOX_STRICT
1203	int rc1;
1204
1205	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1206	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1207	AssertRC(rc1);
1208	if (rc1 == VINF_SUCCESS)
1209	{
1210	RTGDTR gdtr;
1211	PX86DESCHC pDesc;
1212
1213	ASMGetGDTR(&gdtr);
1214
1215	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1216	Log(("Current stack %08x\n", &rc1));
1217
1218
1219	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1220	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1221	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1222	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1223	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1224	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1225	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1226	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1227	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1228	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1229
1230	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1231	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1232
1233	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1234	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1235
1236	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1237	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1238
1239	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1240	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1241	if (val < gdtr.cbGdt)
1242	{
1243	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1244	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1245	}
1246
1247	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1248	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1249	if (val < gdtr.cbGdt)
1250	{
1251	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1252	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1253	}
1254
1255	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1256	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1257	if (val < gdtr.cbGdt)
1258	{
1259	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1260	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1261	}
1262
1263	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1264	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1265	if (val < gdtr.cbGdt)
1266	{
1267	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1268	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1269	}
1270
1271	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1272	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1273	if (val < gdtr.cbGdt)
1274	{
1275	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1276	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1277	}
1278
1279	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1280	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1281	if (val < gdtr.cbGdt)
1282	{
1283	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1284	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1285	}
1286
1287	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1288	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1289	if (val < gdtr.cbGdt)
1290	{
1291	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1292	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1293	}
1294
1295	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1296	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1297
1298	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1299	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1300	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1301	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1302
1303	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1304	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1305
1306	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1307	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1308
1309	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1310	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1311
1312	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1313	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1314	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1315	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1316
1317	#if HC_ARCH_BITS == 64
1318	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1319	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1320	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1321	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1322	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1323	#endif
1324	}
1325	#endif /* VBOX_STRICT */
1326	goto end;
1327	}
1328
1329	default:
1330	/* impossible */
1331	AssertFailed();
1332	goto end;
1333	}
1334	/* Success. Query the guest state and figure out what has happened. */
1335
1336	/* Investigate why there was a VM-exit. */
1337	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1338	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1339
1340	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1341	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1342	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1343	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1344	intInfo = val;
1345	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1346	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1347	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1348	instrInfo = val;
1349	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1350	exitQualification = val;
1351	AssertRC(rc);
1352
1353	/* Let's first sync back eip, esp, and eflags. */
1354	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1355	AssertRC(rc);
1356	pCtx->rip = val;
1357	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1358	AssertRC(rc);
1359	pCtx->rsp = val;
1360	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1361	AssertRC(rc);
1362	pCtx->eflags.u32 = val;
1363
1364	/* Take care of instruction fusing (sti, mov ss) */
1365	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1366	uInterruptState = val;
1367	if (uInterruptState != 0)
1368	{
1369	Assert(uInterruptState <= 2); /* only sti & mov ss */
1370	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1371	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1372	}
1373	else
1374	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1375
1376	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1377	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1378	{
1379	/* Hide our emulation flags */
1380	pCtx->eflags.Bits.u1VM = 0;
1381	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1382	pCtx->eflags.Bits.u1VIF = 0;
1383	pCtx->eflags.Bits.u2IOPL = 0;
1384	}
1385
1386	/* Control registers. */
1387	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1388	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1389	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1390	CPUMSetGuestCR0(pVM, val);
1391
1392	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1393	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1394	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1395	CPUMSetGuestCR4(pVM, val);
1396
1397	CPUMSetGuestCR2(pVM, ASMGetCR2());
1398
1399	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1400	CPUMSetGuestDR7(pVM, val);
1401
1402	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1403	VMX_READ_SELREG(ES, es);
1404	VMX_READ_SELREG(SS, ss);
1405	VMX_READ_SELREG(CS, cs);
1406	VMX_READ_SELREG(DS, ds);
1407	VMX_READ_SELREG(FS, fs);
1408	VMX_READ_SELREG(GS, gs);
1409
1410	/** @note NOW IT'S SAFE FOR LOGGING! */
1411	Log2(("Raw exit reason %08x\n", exitReason));
1412
1413	/* Check if an injected event was interrupted prematurely. */
1414	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1415	AssertRC(rc);
1416	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1417	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1418	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1419	{
1420	pVM->hwaccm.s.Event.fPending = true;
1421	/* Error code present? */
1422	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1423	{
1424	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1425	AssertRC(rc);
1426	pVM->hwaccm.s.Event.errCode = val;
1427	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1428	}
1429	else
1430	{
1431	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1432	pVM->hwaccm.s.Event.errCode = 0;
1433	}
1434	}
1435
1436	#ifdef VBOX_STRICT
1437	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1438	HWACCMDumpRegs(pCtx);
1439	#endif
1440
1441	Log2(("E%d", exitReason));
1442	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1443	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1444	Log2(("Interruption error code %d\n", errCode));
1445	Log2(("IntInfo = %08x\n", intInfo));
1446	Log2(("New EIP=%VGv\n", pCtx->rip));
1447
1448	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1449	switch (exitReason)
1450	{
1451	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1452	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1453	{
1454	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1455
1456	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1457	{
1458	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1459	/* External interrupt; leave to allow it to be dispatched again. */
1460	rc = VINF_EM_RAW_INTERRUPT;
1461	break;
1462	}
1463	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1464	{
1465	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1466	/* External interrupt; leave to allow it to be dispatched again. */
1467	rc = VINF_EM_RAW_INTERRUPT;
1468	break;
1469
1470	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1471	AssertFailed(); /* can't come here; fails the first check. */
1472	break;
1473
1474	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1475	Assert(vector == 3 \|\| vector == 4);
1476	/* no break */
1477	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1478	Log2(("Hardware/software interrupt %d\n", vector));
1479	switch (vector)
1480	{
1481	case X86_XCPT_NM:
1482	{
1483	uint32_t oldCR0;
1484
1485	Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1486
1487	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1488	oldCR0 = ASMGetCR0();
1489	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1490	rc = CPUMHandleLazyFPU(pVM);
1491	if (rc == VINF_SUCCESS)
1492	{
1493	Assert(CPUMIsGuestFPUStateActive(pVM));
1494
1495	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1496	ASMSetCR0(oldCR0);
1497
1498	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1499
1500	/* Continue execution. */
1501	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1502	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1503
1504	goto ResumeExecution;
1505	}
1506
1507	Log(("Forward #NM fault to the guest\n"));
1508	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1509	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1510	AssertRC(rc);
1511	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1512	goto ResumeExecution;
1513	}
1514
1515	case X86_XCPT_PF: /* Page fault */
1516	{
1517	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1518	/* Exit qualification contains the linear address of the page fault. */
1519	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1520	TRPMSetErrorCode(pVM, errCode);
1521	TRPMSetFaultAddress(pVM, exitQualification);
1522
1523	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1524	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1525	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1526	if (rc == VINF_SUCCESS)
1527	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1528	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1529	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1530
1531	TRPMResetTrap(pVM);
1532
1533	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1534	goto ResumeExecution;
1535	}
1536	else
1537	if (rc == VINF_EM_RAW_GUEST_TRAP)
1538	{ /* A genuine pagefault.
1539	* Forward the trap to the guest by injecting the exception and resuming execution.
1540	*/
1541	Log2(("Forward page fault to the guest\n"));
1542	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1543	/* The error code might have been changed. */
1544	errCode = TRPMGetErrorCode(pVM);
1545
1546	TRPMResetTrap(pVM);
1547
1548	/* Now we must update CR2. */
1549	pCtx->cr2 = exitQualification;
1550	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1551	AssertRC(rc);
1552
1553	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1554	goto ResumeExecution;
1555	}
1556	#ifdef VBOX_STRICT
1557	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1558	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1559	#endif
1560	/* Need to go back to the recompiler to emulate the instruction. */
1561	TRPMResetTrap(pVM);
1562	break;
1563	}
1564
1565	case X86_XCPT_MF: /* Floating point exception. */
1566	{
1567	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1568	if (!(pCtx->cr0 & X86_CR0_NE))
1569	{
1570	/* old style FPU error reporting needs some extra work. */
1571	/** @todo don't fall back to the recompiler, but do it manually. */
1572	rc = VINF_EM_RAW_EMULATE_INSTR;
1573	break;
1574	}
1575	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1576	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1577	AssertRC(rc);
1578
1579	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1580	goto ResumeExecution;
1581	}
1582
1583	#ifdef VBOX_STRICT
1584	case X86_XCPT_GP: /* General protection failure exception.*/
1585	case X86_XCPT_UD: /* Unknown opcode exception. */
1586	case X86_XCPT_DE: /* Debug exception. */
1587	case X86_XCPT_SS: /* Stack segment exception. */
1588	case X86_XCPT_NP: /* Segment not present exception. */
1589	{
1590	switch(vector)
1591	{
1592	case X86_XCPT_DE:
1593	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1594	break;
1595	case X86_XCPT_UD:
1596	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1597	break;
1598	case X86_XCPT_SS:
1599	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1600	break;
1601	case X86_XCPT_NP:
1602	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1603	break;
1604	case X86_XCPT_GP:
1605	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1606	break;
1607	}
1608
1609	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1610	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1611	AssertRC(rc);
1612
1613	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1614	goto ResumeExecution;
1615	}
1616	#endif
1617	default:
1618	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1619	rc = VERR_EM_INTERNAL_ERROR;
1620	break;
1621	} /* switch (vector) */
1622
1623	break;
1624
1625	default:
1626	rc = VERR_EM_INTERNAL_ERROR;
1627	AssertFailed();
1628	break;
1629	}
1630
1631	break;
1632	}
1633
1634	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1635	/* Clear VM-exit on IF=1 change. */
1636	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1637	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1638	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1639	AssertRC(rc);
1640	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1641	goto ResumeExecution; /* we check for pending guest interrupts there */
1642
1643	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1644	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1645	/* Skip instruction and continue directly. */
1646	pCtx->rip += cbInstr;
1647	/* Continue execution.*/
1648	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1649	goto ResumeExecution;
1650
1651	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1652	{
1653	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1654	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1655	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1656	if (rc == VINF_SUCCESS)
1657	{
1658	/* Update EIP and continue execution. */
1659	Assert(cbInstr == 2);
1660	pCtx->rip += cbInstr;
1661	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1662	goto ResumeExecution;
1663	}
1664	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1665	rc = VINF_EM_RAW_EMULATE_INSTR;
1666	break;
1667	}
1668
1669	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1670	{
1671	Log2(("VMX: Rdtsc\n"));
1672	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1673	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1674	if (rc == VINF_SUCCESS)
1675	{
1676	/* Update EIP and continue execution. */
1677	Assert(cbInstr == 2);
1678	pCtx->rip += cbInstr;
1679	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1680	goto ResumeExecution;
1681	}
1682	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1683	rc = VINF_EM_RAW_EMULATE_INSTR;
1684	break;
1685	}
1686
1687	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1688	{
1689	Log2(("VMX: invlpg\n"));
1690	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1691	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1692	if (rc == VINF_SUCCESS)
1693	{
1694	/* Update EIP and continue execution. */
1695	pCtx->rip += cbInstr;
1696	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1697	goto ResumeExecution;
1698	}
1699	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1700	break;
1701	}
1702
1703	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1704	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1705	{
1706	uint32_t cbSize;
1707
1708	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1709	Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1710	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1711	if (rc == VINF_SUCCESS)
1712	{
1713	/* EIP has been updated already. */
1714
1715	/* Only resume if successful. */
1716	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1717	goto ResumeExecution;
1718	}
1719	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1720	break;
1721	}
1722
1723	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1724	{
1725	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1726	{
1727	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1728	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1729	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1730	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1731	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1732	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1733
1734	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1735	{
1736	case 0:
1737	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1738	break;
1739	case 2:
1740	break;
1741	case 3:
1742	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1743	break;
1744	case 4:
1745	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1746	break;
1747	case 8:
1748	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR8;
1749	break;
1750	default:
1751	AssertFailed();
1752	}
1753	/* Check if a sync operation is pending. */
1754	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1755	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1756	{
1757	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1758	AssertRC(rc);
1759	}
1760	break;
1761
1762	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1763	Log2(("VMX: mov x, crx\n"));
1764	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1765	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1766	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1767	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1768	break;
1769
1770	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1771	Log2(("VMX: clts\n"));
1772	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1773	rc = EMInterpretCLTS(pVM);
1774	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1775	break;
1776
1777	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1778	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1779	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1780	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1781	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1782	break;
1783	}
1784
1785	/* Update EIP if no error occurred. */
1786	if (VBOX_SUCCESS(rc))
1787	pCtx->rip += cbInstr;
1788
1789	if (rc == VINF_SUCCESS)
1790	{
1791	/* Only resume if successful. */
1792	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1793	goto ResumeExecution;
1794	}
1795	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1796	break;
1797	}
1798
1799	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1800	{
1801	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1802	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1803	{
1804	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1805	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1806	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1807	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1808	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1809	Log2(("DR7=%08x\n", pCtx->dr7));
1810	}
1811	else
1812	{
1813	Log2(("VMX: mov x, drx\n"));
1814	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1815	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1816	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1817	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1818	}
1819	/* Update EIP if no error occurred. */
1820	if (VBOX_SUCCESS(rc))
1821	pCtx->rip += cbInstr;
1822
1823	if (rc == VINF_SUCCESS)
1824	{
1825	/* Only resume if successful. */
1826	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1827	goto ResumeExecution;
1828	}
1829	Assert(rc == VERR_EM_INTERPRETER);
1830	break;
1831	}
1832
1833	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1834	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1835	{
1836	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1837	uint32_t uPort;
1838	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1839
1840	/** @todo necessary to make the distinction? */
1841	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1842	{
1843	uPort = pCtx->edx & 0xffff;
1844	}
1845	else
1846	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1847
1848	/* paranoia */
1849	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1850	{
1851	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1852	break;
1853	}
1854
1855	uint32_t cbSize = aIOSize[uIOWidth];
1856
1857	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1858	{
1859	/* ins/outs */
1860	uint32_t prefix = 0;
1861	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1862	prefix \|= PREFIX_REP;
1863
1864	if (fIOWrite)
1865	{
1866	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1867	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1868	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1869	}
1870	else
1871	{
1872	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1873	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1874	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1875	}
1876	}
1877	else
1878	{
1879	/* normal in/out */
1880	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1881
1882	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1883
1884	if (fIOWrite)
1885	{
1886	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1887	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1888	}
1889	else
1890	{
1891	uint32_t u32Val = 0;
1892
1893	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1894	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1895	if (IOM_SUCCESS(rc))
1896	{
1897	/* Write back to the EAX register. */
1898	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1899	}
1900	}
1901	}
1902	/*
1903	* Handled the I/O return codes.
1904	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1905	*/
1906	if (IOM_SUCCESS(rc))
1907	{
1908	/* Update EIP and continue execution. */
1909	pCtx->rip += cbInstr;
1910	if (RT_LIKELY(rc == VINF_SUCCESS))
1911	{
1912	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1913	goto ResumeExecution;
1914	}
1915	break;
1916	}
1917
1918	#ifdef VBOX_STRICT
1919	if (rc == VINF_IOM_HC_IOPORT_READ)
1920	Assert(!fIOWrite);
1921	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1922	Assert(fIOWrite);
1923	else
1924	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1925	#endif
1926	break;
1927	}
1928
1929	default:
1930	/* The rest is handled after syncing the entire CPU state. */
1931	break;
1932	}
1933
1934	/* Note: the guest state isn't entirely synced back at this stage. */
1935
1936	/* Investigate why there was a VM-exit. (part 2) */
1937	switch (exitReason)
1938	{
1939	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1940	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1941	/* Already handled above. */
1942	break;
1943
1944	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1945	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1946	break;
1947
1948	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1949	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1950	rc = VINF_EM_RAW_INTERRUPT;
1951	AssertFailed(); /* Can't happen. Yet. */
1952	break;
1953
1954	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1955	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1956	rc = VINF_EM_RAW_INTERRUPT;
1957	AssertFailed(); /* Can't happen afaik. */
1958	break;
1959
1960	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1961	rc = VERR_EM_INTERPRETER;
1962	break;
1963
1964	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1965	/** Check if external interrupts are pending; if so, don't switch back. */
1966	if ( pCtx->eflags.Bits.u1IF
1967	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1968	{
1969	pCtx->rip++; /* skip hlt */
1970	goto ResumeExecution;
1971	}
1972
1973	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1974	break;
1975
1976	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1977	AssertFailed(); /* can't happen. */
1978	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1979	break;
1980
1981	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1982	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1983	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1984	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1985	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1986	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1987	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1988	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1989	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1990	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1991	/** @todo inject #UD immediately */
1992	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1993	break;
1994
1995	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1996	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1997	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1998	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1999	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2000	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2001	/* already handled above */
2002	AssertMsg( rc == VINF_PGM_CHANGE_MODE
2003	\|\| rc == VINF_EM_RAW_INTERRUPT
2004	\|\| rc == VERR_EM_INTERPRETER
2005	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
2006	\|\| rc == VINF_PGM_SYNC_CR3
2007	\|\| rc == VINF_IOM_HC_IOPORT_READ
2008	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2009	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2010	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
2011	\|\| rc == VINF_EM_RESCHEDULE_REM,
2012	("rc = %d\n", rc));
2013	break;
2014
2015	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2016	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2017	/* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2018	rc = VERR_EM_INTERPRETER;
2019	break;
2020
2021	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2022	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2023	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2024	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2025	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2026	break;
2027
2028	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2029	Assert(rc == VINF_EM_RAW_INTERRUPT);
2030	break;
2031
2032	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2033	{
2034	#ifdef VBOX_STRICT
2035	Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2036
2037	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2038	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2039
2040	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2041	Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2042
2043	VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2044	Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2045
2046	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2047	Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2048
2049	VMX_LOG_SELREG(CS, "CS");
2050	VMX_LOG_SELREG(DS, "DS");
2051	VMX_LOG_SELREG(ES, "ES");
2052	VMX_LOG_SELREG(FS, "FS");
2053	VMX_LOG_SELREG(GS, "GS");
2054	VMX_LOG_SELREG(SS, "SS");
2055	VMX_LOG_SELREG(TR, "TR");
2056	VMX_LOG_SELREG(LDTR, "LDTR");
2057
2058	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2059	Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2060	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2061	Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2062	#endif /* VBOX_STRICT */
2063	rc = VERR_EM_INTERNAL_ERROR;
2064	break;
2065	}
2066
2067	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2068	AssertMsgFailed(("Todo!!\n"));
2069	break;
2070
2071	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2072	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2073	default:
2074	rc = VERR_EM_INTERNAL_ERROR;
2075	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2076	break;
2077
2078	}
2079	end:
2080	if (fGuestStateSynced)
2081	{
2082	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2083	VMX_READ_SELREG(LDTR, ldtr);
2084	VMX_READ_SELREG(TR, tr);
2085
2086	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2087	pCtx->gdtr.cbGdt = val;
2088	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2089	pCtx->gdtr.pGdt = val;
2090
2091	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2092	pCtx->idtr.cbIdt = val;
2093	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2094	pCtx->idtr.pIdt = val;
2095
2096	/*
2097	* System MSRs
2098	*/
2099	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
2100	pCtx->SysEnter.cs = val;
2101	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
2102	pCtx->SysEnter.eip = val;
2103	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
2104	pCtx->SysEnter.esp = val;
2105	}
2106
2107	/* Signal changes for the recompiler. */
2108	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2109
2110	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2111	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2112	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2113	{
2114	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2115	/* On the next entry we'll only sync the host context. */
2116	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2117	}
2118	else
2119	{
2120	/* On the next entry we'll sync everything. */
2121	/** @todo we can do better than this */
2122	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2123	}
2124
2125	/* translate into a less severe return code */
2126	if (rc == VERR_EM_INTERPRETER)
2127	rc = VINF_EM_RAW_EMULATE_INSTR;
2128
2129	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2130	Log2(("X"));
2131	return rc;
2132	}
2133
2134
2135	/**
2136	* Enters the VT-x session
2137	*
2138	* @returns VBox status code.
2139	* @param pVM The VM to operate on.
2140	* @param pCpu CPU info struct
2141	*/
2142	HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2143	{
2144	Assert(pVM->hwaccm.s.vmx.fSupported);
2145
2146	unsigned cr4 = ASMGetCR4();
2147	if (!(cr4 & X86_CR4_VMXE))
2148	{
2149	AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2150	return VERR_VMX_X86_CR4_VMXE_CLEARED;
2151	}
2152
2153	/* Activate the VM Control Structure. */
2154	int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2155	if (VBOX_FAILURE(rc))
2156	return rc;
2157
2158	pVM->hwaccm.s.vmx.fResumeVM = false;
2159	return VINF_SUCCESS;
2160	}
2161
2162
2163	/**
2164	* Leaves the VT-x session
2165	*
2166	* @returns VBox status code.
2167	* @param pVM The VM to operate on.
2168	*/
2169	HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2170	{
2171	Assert(pVM->hwaccm.s.vmx.fSupported);
2172
2173	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2174	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2175	AssertRC(rc);
2176
2177	return VINF_SUCCESS;
2178	}
2179

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 10108

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