VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 10360

Last change on this file since 10360 was 10360, checked in by vboxsync, 16 years ago

Removed the same assertion as before in the AMD-V code.
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File size: 84.2 KB
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1/* $Id: HWVMXR0.cpp 10360 2008-07-08 12:42:08Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43
44/* IO operation lookup arrays. */
45static uint32_t aIOSize[4] = {1, 2, 0, 4};
46static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49static void VMXR0CheckError(PVM pVM, int rc)
50{
51 if (rc == VERR_VMX_GENERIC)
52 {
53 RTCCUINTREG instrError;
54
55 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57 }
58 pVM->hwaccm.s.lLastError = rc;
59}
60
61/**
62 * Sets up and activates VT-x on the current CPU
63 *
64 * @returns VBox status code.
65 * @param pCpu CPU info struct
66 * @param pVM The VM to operate on.
67 * @param pvPageCpu Pointer to the global cpu page
68 * @param pPageCpuPhys Physical address of the global cpu page
69 */
70HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71{
72 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73 AssertReturn(pVM, VERR_INVALID_PARAMETER);
74 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76 /* Setup Intel VMX. */
77 Assert(pVM->hwaccm.s.vmx.fSupported);
78
79#ifdef LOG_ENABLED
80 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81#endif
82 /* Set revision dword at the beginning of the VMXON structure. */
83 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85 /* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86 * (which can have very bad consequences!!!)
87 */
88
89 /* Make sure the VMX instructions don't cause #UD faults. */
90 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
91
92 /* Enter VMX Root Mode */
93 int rc = VMXEnable(pPageCpuPhys);
94 if (VBOX_FAILURE(rc))
95 {
96 VMXR0CheckError(pVM, rc);
97 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98 return VERR_VMX_VMXON_FAILED;
99 }
100 return VINF_SUCCESS;
101}
102
103/**
104 * Deactivates VT-x on the current CPU
105 *
106 * @returns VBox status code.
107 * @param pCpu CPU info struct
108 * @param pvPageCpu Pointer to the global cpu page
109 * @param pPageCpuPhys Physical address of the global cpu page
110 */
111HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112{
113 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116 /* Leave VMX Root Mode. */
117 VMXDisable();
118
119 /* And clear the X86_CR4_VMXE bit */
120 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122#ifdef LOG_ENABLED
123 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124#endif
125 return VINF_SUCCESS;
126}
127
128/**
129 * Does Ring-0 per VM VT-x init.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135{
136 int rc;
137
138#ifdef LOG_ENABLED
139 SUPR0Printf("VMXR0InitVM %x\n", pVM);
140#endif
141
142 /* Allocate one page for the VM control structure (VMCS). */
143 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
144 AssertRC(rc);
145 if (RT_FAILURE(rc))
146 return rc;
147
148 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
149 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
150 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
151
152 /* Allocate one page for the TSS we need for real mode emulation. */
153 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
154 AssertRC(rc);
155 if (RT_FAILURE(rc))
156 return rc;
157
158 pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
159 pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
160
161 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
162 * for I/O operations. */
163 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
164 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
165 /* Bit set to 0 means redirection enabled. */
166 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
167
168 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
169 {
170 /* Allocate one page for the virtual APIC mmio cache. */
171 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
172 AssertRC(rc);
173 if (RT_FAILURE(rc))
174 return rc;
175
176 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
177 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
178 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
179 }
180 else
181 {
182 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
183 pVM->hwaccm.s.vmx.pAPIC = 0;
184 pVM->hwaccm.s.vmx.pAPICPhys = 0;
185 }
186
187#ifdef LOG_ENABLED
188 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
189#endif
190 return VINF_SUCCESS;
191}
192
193/**
194 * Does Ring-0 per VM VT-x termination.
195 *
196 * @returns VBox status code.
197 * @param pVM The VM to operate on.
198 */
199HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
200{
201 if (pVM->hwaccm.s.vmx.pMemObjVMCS)
202 {
203 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
204 pVM->hwaccm.s.vmx.pMemObjVMCS = 0;
205 pVM->hwaccm.s.vmx.pVMCS = 0;
206 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
207 }
208 if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS)
209 {
210 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
211 pVM->hwaccm.s.vmx.pMemObjRealModeTSS = 0;
212 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
213 pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
214 }
215 if (pVM->hwaccm.s.vmx.pMemObjAPIC)
216 {
217 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
218 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
219 pVM->hwaccm.s.vmx.pAPIC = 0;
220 pVM->hwaccm.s.vmx.pAPICPhys = 0;
221 }
222 return VINF_SUCCESS;
223}
224
225/**
226 * Sets up VT-x for the specified VM
227 *
228 * @returns VBox status code.
229 * @param pVM The VM to operate on.
230 */
231HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
232{
233 int rc = VINF_SUCCESS;
234 uint32_t val;
235
236 AssertReturn(pVM, VERR_INVALID_PARAMETER);
237 Assert(pVM->hwaccm.s.vmx.pVMCS);
238
239 /* Set revision dword at the beginning of the VMCS structure. */
240 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
241
242 /* Clear VM Control Structure. */
243 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
244 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
245 if (VBOX_FAILURE(rc))
246 goto vmx_end;
247
248 /* Activate the VM Control Structure. */
249 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
250 if (VBOX_FAILURE(rc))
251 goto vmx_end;
252
253 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
254 * Set required bits to one and zero according to the MSR capabilities.
255 */
256 val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
257 /* External and non-maskable interrupts cause VM-exits. */
258 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
259 val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
260
261 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
262 AssertRC(rc);
263
264 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
265 * Set required bits to one and zero according to the MSR capabilities.
266 */
267 val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
268 /* Program which event cause VM-exits and which features we want to use. */
269 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
270 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
271 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
272 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
273 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
274 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
275
276 /** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
277
278#if HC_ARCH_BITS == 64
279 /* Always exit on CR8 writes. */
280 /* @todo investigate TRP treshold option */
281 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
282
283 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
284 {
285 /* CR8 reads from the APIC shadow page */
286 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
287 }
288 else
289 /* Exit on CR8 reads as well in case the TPR shadow feature isn't present. */
290 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
291#endif
292 /* Mask away the bits that the CPU doesn't support */
293 /** @todo make sure they don't conflict with the above requirements. */
294 val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
295 pVM->hwaccm.s.vmx.proc_ctls = val;
296
297 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
298 AssertRC(rc);
299
300 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
301 * Set required bits to one and zero according to the MSR capabilities.
302 */
303 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
304 AssertRC(rc);
305
306 /* VMX_VMCS_CTRL_EXIT_CONTROLS
307 * Set required bits to one and zero according to the MSR capabilities.
308 */
309 val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
310#if HC_ARCH_BITS == 64
311 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
312#else
313 /* else Must be zero when AMD64 is not available. */
314#endif
315 val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
316 /* Don't acknowledge external interrupts on VM-exit. */
317 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
318 AssertRC(rc);
319
320 /* Forward all exception except #NM & #PF to the guest.
321 * We always need to check pagefaults since our shadow page table can be out of sync.
322 * And we always lazily sync the FPU & XMM state.
323 */
324
325 /*
326 * @todo Possible optimization:
327 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
328 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
329 * registers ourselves of course.
330 *
331 * @note only possible if the current state is actually ours (X86_CR0_TS flag)
332 */
333 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
334 AssertRC(rc);
335
336 /* Don't filter page faults; all of them should cause a switch. */
337 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
338 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
339 AssertRC(rc);
340
341 /* Init TSC offset to zero. */
342 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
343#if HC_ARCH_BITS == 32
344 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
345#endif
346 AssertRC(rc);
347
348 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
349#if HC_ARCH_BITS == 32
350 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
351#endif
352 AssertRC(rc);
353
354 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
355#if HC_ARCH_BITS == 32
356 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
357#endif
358 AssertRC(rc);
359
360 /* Clear MSR controls. */
361 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
362 {
363 /* Optional */
364 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
365#if HC_ARCH_BITS == 32
366 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
367#endif
368 AssertRC(rc);
369 }
370 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
371 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
372 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
373#if HC_ARCH_BITS == 32
374 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
375 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
376 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
377#endif
378 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
379 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
380 AssertRC(rc);
381
382 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
383 {
384 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
385 /* Optional */
386 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
387 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
388#if HC_ARCH_BITS == 32
389 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
390#endif
391 AssertRC(rc);
392 }
393
394 /* Set link pointer to -1. Not currently used. */
395#if HC_ARCH_BITS == 32
396 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
397 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
398#else
399 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
400#endif
401 AssertRC(rc);
402
403 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
404 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
405 AssertRC(rc);
406
407vmx_end:
408 VMXR0CheckError(pVM, rc);
409 return rc;
410}
411
412
413/**
414 * Injects an event (trap or external interrupt)
415 *
416 * @returns VBox status code.
417 * @param pVM The VM to operate on.
418 * @param pCtx CPU Context
419 * @param intInfo VMX interrupt info
420 * @param cbInstr Opcode length of faulting instruction
421 * @param errCode Error code (optional)
422 */
423static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
424{
425 int rc;
426
427#ifdef VBOX_STRICT
428 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
429 if (iGate == 0xE)
430 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
431 else
432 if (iGate < 0x20)
433 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
434 else
435 {
436 Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
437 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
438 Assert(pCtx->eflags.u32 & X86_EFL_IF);
439 }
440#endif
441
442 /* Set event injection state. */
443 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
444 intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
445 );
446
447 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
448 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
449
450 AssertRC(rc);
451 return rc;
452}
453
454
455/**
456 * Checks for pending guest interrupts and injects them
457 *
458 * @returns VBox status code.
459 * @param pVM The VM to operate on.
460 * @param pCtx CPU Context
461 */
462static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
463{
464 int rc;
465
466 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
467 if (pVM->hwaccm.s.Event.fPending)
468 {
469 Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
470 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
471 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
472 AssertRC(rc);
473
474 pVM->hwaccm.s.Event.fPending = false;
475 return VINF_SUCCESS;
476 }
477
478 /* When external interrupts are pending, we should exit the VM when IF is set. */
479 if ( !TRPMHasTrap(pVM)
480 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
481 {
482 if (!(pCtx->eflags.u32 & X86_EFL_IF))
483 {
484 Log2(("Enable irq window exit!\n"));
485 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
486 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
487 AssertRC(rc);
488 }
489 else
490 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
491 {
492 uint8_t u8Interrupt;
493
494 rc = PDMGetInterrupt(pVM, &u8Interrupt);
495 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
496 if (VBOX_SUCCESS(rc))
497 {
498 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
499 AssertRC(rc);
500 }
501 else
502 {
503 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
504 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
505 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
506 /* Just continue */
507 }
508 }
509 else
510 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
511 }
512
513#ifdef VBOX_STRICT
514 if (TRPMHasTrap(pVM))
515 {
516 uint8_t u8Vector;
517 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
518 AssertRC(rc);
519 }
520#endif
521
522 if ( pCtx->eflags.u32 & X86_EFL_IF
523 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
524 && TRPMHasTrap(pVM)
525 )
526 {
527 uint8_t u8Vector;
528 int rc;
529 TRPMEVENT enmType;
530 RTGCUINTPTR intInfo;
531 RTGCUINT errCode;
532
533 /* If a new event is pending, then dispatch it now. */
534 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
535 AssertRC(rc);
536 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
537 Assert(enmType != TRPM_SOFTWARE_INT);
538
539 /* Clear the pending trap. */
540 rc = TRPMResetTrap(pVM);
541 AssertRC(rc);
542
543 intInfo = u8Vector;
544 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
545
546 if (enmType == TRPM_TRAP)
547 {
548 switch (u8Vector) {
549 case 8:
550 case 10:
551 case 11:
552 case 12:
553 case 13:
554 case 14:
555 case 17:
556 /* Valid error codes. */
557 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
558 break;
559 default:
560 break;
561 }
562 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
563 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
564 else
565 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
566 }
567 else
568 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
569
570 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
571 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
572 AssertRC(rc);
573 } /* if (interrupts can be dispatched) */
574
575 return VINF_SUCCESS;
576}
577
578/**
579 * Save the host state
580 *
581 * @returns VBox status code.
582 * @param pVM The VM to operate on.
583 */
584HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
585{
586 int rc = VINF_SUCCESS;
587
588 /*
589 * Host CPU Context
590 */
591 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
592 {
593 RTIDTR idtr;
594 RTGDTR gdtr;
595 RTSEL SelTR;
596 PX86DESCHC pDesc;
597 uintptr_t trBase;
598
599 /* Control registers */
600 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
601 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
602 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
603 AssertRC(rc);
604 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
605 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
606 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
607
608 /* Selector registers. */
609 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
610 /** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
611 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
612 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
613#if HC_ARCH_BITS == 32
614 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
615 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
616#endif
617 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
618 SelTR = ASMGetTR();
619 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
620 AssertRC(rc);
621 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
622 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
623 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
624 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
625 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
626 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
627 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
628
629 /* GDTR & IDTR */
630 ASMGetGDTR(&gdtr);
631 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
632 ASMGetIDTR(&idtr);
633 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
634 AssertRC(rc);
635 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
636 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
637
638 /* Save the base address of the TR selector. */
639 if (SelTR > gdtr.cbGdt)
640 {
641 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
642 return VERR_VMX_INVALID_HOST_STATE;
643 }
644
645 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
646#if HC_ARCH_BITS == 64
647 trBase = X86DESC64_BASE(*pDesc);
648#else
649 trBase = X86DESC_BASE(*pDesc);
650#endif
651 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
652 AssertRC(rc);
653 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
654
655 /* FS and GS base. */
656#if HC_ARCH_BITS == 64
657 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
658 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
659 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
660 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
661#endif
662 AssertRC(rc);
663
664 /* Sysenter MSRs. */
665 /** @todo expensive!! */
666 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
667 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
668#if HC_ARCH_BITS == 32
669 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
670 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
671 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
672 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
673#else
674 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
675 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
676 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
677 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
678#endif
679 AssertRC(rc);
680
681 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
682 }
683 return rc;
684}
685
686
687/**
688 * Loads the guest state
689 *
690 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
691 *
692 * @returns VBox status code.
693 * @param pVM The VM to operate on.
694 * @param pCtx Guest context
695 */
696HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
697{
698 int rc = VINF_SUCCESS;
699 RTGCUINTPTR val;
700 X86EFLAGS eflags;
701
702 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
703 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
704 {
705 VMX_WRITE_SELREG(ES, es);
706 AssertRC(rc);
707
708 VMX_WRITE_SELREG(CS, cs);
709 AssertRC(rc);
710
711 VMX_WRITE_SELREG(SS, ss);
712 AssertRC(rc);
713
714 VMX_WRITE_SELREG(DS, ds);
715 AssertRC(rc);
716
717 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
718 VMX_WRITE_SELREG(FS, fs);
719 AssertRC(rc);
720
721 VMX_WRITE_SELREG(GS, gs);
722 AssertRC(rc);
723 }
724
725 /* Guest CPU context: LDTR. */
726 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
727 {
728 if (pCtx->ldtr == 0)
729 {
730 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
731 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
732 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
733 /** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
734 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
735 }
736 else
737 {
738 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
739 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
740 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
741 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
742 }
743 AssertRC(rc);
744 }
745 /* Guest CPU context: TR. */
746 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
747 {
748 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
749
750 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
751 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
752 {
753 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
754 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
755 }
756 else
757 {
758 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
759 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
760 }
761 val = pCtx->trHid.Attr.u;
762
763 /* The TSS selector must be busy. */
764 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
765 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
766 else
767 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
768 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
769
770 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
771 AssertRC(rc);
772 }
773 /* Guest CPU context: GDTR. */
774 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
775 {
776 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
777 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
778 AssertRC(rc);
779 }
780 /* Guest CPU context: IDTR. */
781 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
782 {
783 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
784 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
785 AssertRC(rc);
786 }
787
788 /*
789 * Sysenter MSRs (unconditional)
790 */
791 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
792 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
793 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
794 AssertRC(rc);
795
796 /* Control registers */
797 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
798 {
799 val = pCtx->cr0;
800 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
801 Log2(("Guest CR0-shadow %08x\n", val));
802 if (CPUMIsGuestFPUStateActive(pVM) == false)
803 {
804 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
805 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
806 }
807 else
808 {
809 /** @todo check if we support the old style mess correctly. */
810 if (!(val & X86_CR0_NE))
811 {
812 Log(("Forcing X86_CR0_NE!!!\n"));
813
814 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
815 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
816 {
817 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK | RT_BIT(X86_XCPT_MF));
818 AssertRC(rc);
819 pVM->hwaccm.s.fFPUOldStyleOverride = true;
820 }
821 }
822
823 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
824 }
825 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
826 val |= X86_CR0_PE | X86_CR0_PG;
827 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
828 val |= X86_CR0_WP;
829
830 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
831 Log2(("Guest CR0 %08x\n", val));
832 /* CR0 flags owned by the host; if the guests attempts to change them, then
833 * the VM will exit.
834 */
835 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
836 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
837 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
838 | X86_CR0_TS
839 | X86_CR0_ET
840 | X86_CR0_NE
841 | X86_CR0_MP;
842 pVM->hwaccm.s.vmx.cr0_mask = val;
843
844 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
845 Log2(("Guest CR0-mask %08x\n", val));
846 AssertRC(rc);
847 }
848 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
849 {
850 /* CR4 */
851 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
852 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
853 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
854 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
855 switch(pVM->hwaccm.s.enmShadowMode)
856 {
857 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
858 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
859 case PGMMODE_32_BIT: /* 32-bit paging. */
860 break;
861
862 case PGMMODE_PAE: /* PAE paging. */
863 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
864 /** @todo use normal 32 bits paging */
865 val |= X86_CR4_PAE;
866 break;
867
868 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
869 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
870#ifdef VBOX_ENABLE_64_BITS_GUESTS
871 break;
872#else
873 AssertFailed();
874 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
875#endif
876 default: /* shut up gcc */
877 AssertFailed();
878 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
879 }
880 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
881 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
882 val |= X86_CR4_VME;
883
884 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
885 Log2(("Guest CR4 %08x\n", val));
886 /* CR4 flags owned by the host; if the guests attempts to change them, then
887 * the VM will exit.
888 */
889 val = X86_CR4_PAE
890 | X86_CR4_PGE
891 | X86_CR4_PSE
892 | X86_CR4_VMXE;
893 pVM->hwaccm.s.vmx.cr4_mask = val;
894
895 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
896 Log2(("Guest CR4-mask %08x\n", val));
897 AssertRC(rc);
898 }
899
900 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
901 {
902 /* Save our shadow CR3 register. */
903 val = PGMGetHyperCR3(pVM);
904 Assert(val);
905 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
906 AssertRC(rc);
907 }
908
909 /* Debug registers. */
910 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
911 {
912 /** @todo DR0-6 */
913 val = pCtx->dr7;
914 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
915 val |= 0x400; /* must be one */
916#ifdef VBOX_STRICT
917 val = 0x400;
918#endif
919 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
920 AssertRC(rc);
921
922 /* IA32_DEBUGCTL MSR. */
923 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
924 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
925 AssertRC(rc);
926
927 /** @todo */
928 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
929 AssertRC(rc);
930 }
931
932 /* EIP, ESP and EFLAGS */
933 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
934 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
935 AssertRC(rc);
936
937 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
938 eflags = pCtx->eflags;
939 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
940 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
941
942 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
943 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
944 {
945 eflags.Bits.u1VM = 1;
946 eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
947 eflags.Bits.u2IOPL = 3;
948 }
949
950 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
951 AssertRC(rc);
952
953 /** TSC offset. */
954 uint64_t u64TSCOffset;
955
956 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
957 {
958 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
959#if HC_ARCH_BITS == 64
960 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
961#else
962 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
963 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
964#endif
965 AssertRC(rc);
966
967 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
968 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
969 AssertRC(rc);
970 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
971 }
972 else
973 {
974 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
975 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
976 AssertRC(rc);
977 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
978 }
979
980 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
981 * Set required bits to one and zero according to the MSR capabilities.
982 */
983 val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
984 /* 64 bits guest mode? */
985 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
986 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
987 /* else Must be zero when AMD64 is not available. */
988
989 /* Mask away the bits that the CPU doesn't support */
990 val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
991 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
992 AssertRC(rc);
993
994 /* 64 bits guest mode? */
995 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
996 {
997#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
998 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
999#else
1000 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1001#endif
1002 /* Unconditionally update these as wrmsr might have changed them. */
1003 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1004 AssertRC(rc);
1005 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1006 AssertRC(rc);
1007 }
1008 else
1009 {
1010 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1011 }
1012
1013 /* Done. */
1014 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1015
1016 return rc;
1017}
1018
1019/**
1020 * Runs guest code in a VT-x VM.
1021 *
1022 * @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
1023 *
1024 * @returns VBox status code.
1025 * @param pVM The VM to operate on.
1026 * @param pCtx Guest context
1027 * @param pCpu CPU info struct
1028 */
1029HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
1030{
1031 int rc = VINF_SUCCESS;
1032 RTCCUINTREG val, valShadow;
1033 RTCCUINTREG exitReason, instrError, cbInstr;
1034 RTGCUINTPTR exitQualification;
1035 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1036 RTGCUINTPTR errCode, instrInfo, uInterruptState;
1037 bool fGuestStateSynced = false;
1038 unsigned cResume = 0;
1039
1040 Log2(("\nE"));
1041
1042 AssertReturn(pCpu->fConfigured, VERR_EM_INTERNAL_ERROR);
1043
1044 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1045
1046#ifdef VBOX_STRICT
1047 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1048 AssertRC(rc);
1049 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1050
1051 /* allowed zero */
1052 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
1053 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1054
1055 /* allowed one */
1056 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
1057 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1058
1059 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1060 AssertRC(rc);
1061 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1062
1063 /* allowed zero */
1064 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
1065 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1066
1067 /* allowed one */
1068 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
1069 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1070
1071 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1072 AssertRC(rc);
1073 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1074
1075 /* allowed zero */
1076 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
1077 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1078
1079 /* allowed one */
1080 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
1081 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1082
1083 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1084 AssertRC(rc);
1085 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1086
1087 /* allowed zero */
1088 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
1089 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1090
1091 /* allowed one */
1092 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
1093 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1094#endif
1095
1096#if 0
1097 /*
1098 * Check if debug registers are armed.
1099 */
1100 uint32_t u32DR7 = ASMGetDR7();
1101 if (u32DR7 & X86_DR7_ENABLED_MASK)
1102 {
1103 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
1104 }
1105 else
1106 pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1107#endif
1108
1109 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1110 */
1111ResumeExecution:
1112 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1113 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1114 {
1115 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1116 rc = VINF_EM_RAW_INTERRUPT;
1117 goto end;
1118 }
1119
1120 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1121 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1122 {
1123 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1124 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1125 {
1126 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1127 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1128 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1129 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1130 */
1131 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1132 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1133 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1134 AssertRC(rc);
1135 }
1136 }
1137 else
1138 {
1139 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1140 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1141 AssertRC(rc);
1142 }
1143
1144 /* Check for pending actions that force us to go back to ring 3. */
1145 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1146 {
1147 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1148 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1149 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1150 rc = VINF_EM_RAW_TO_R3;
1151 goto end;
1152 }
1153 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1154 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1155 {
1156 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1157 rc = VINF_EM_PENDING_REQUEST;
1158 goto end;
1159 }
1160
1161 /* When external interrupts are pending, we should exit the VM when IF is set. */
1162 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
1163 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1164 if (VBOX_FAILURE(rc))
1165 {
1166 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1167 goto end;
1168 }
1169
1170 /** @todo check timers?? */
1171
1172 /* Save the host state first. */
1173 rc = VMXR0SaveHostState(pVM);
1174 if (rc != VINF_SUCCESS)
1175 {
1176 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1177 goto end;
1178 }
1179 /* Load the guest state */
1180 rc = VMXR0LoadGuestState(pVM, pCtx);
1181 if (rc != VINF_SUCCESS)
1182 {
1183 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1184 goto end;
1185 }
1186 fGuestStateSynced = true;
1187
1188 /* TPR caching using CR8 is only available in 64 bits mode */
1189 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1190 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock). */
1191 if ( pCtx->msrEFER & MSR_K6_EFER_LMA
1192 && pVM->hwaccm.s.vmx.pAPIC)
1193 {
1194 /* TPR caching in CR8 */
1195 uint8_t u8TPR;
1196 int rc = PDMApicGetTPR(pVM, &u8TPR);
1197 AssertRC(rc);
1198 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1199 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR;
1200 }
1201
1202 /* Non-register state Guest Context */
1203 /** @todo change me according to cpu state */
1204 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1205 AssertRC(rc);
1206
1207 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1208
1209 /* Manual save and restore:
1210 * - General purpose registers except RIP, RSP
1211 *
1212 * Trashed:
1213 * - CR2 (we don't care)
1214 * - LDTR (reset to 0)
1215 * - DRx (presumably not changed at all)
1216 * - DR7 (reset to 0x400)
1217 * - EFLAGS (reset to RT_BIT(1); not relevant)
1218 *
1219 */
1220
1221 /* All done! Let's start VM execution. */
1222 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1223 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1224
1225 /* In case we execute a goto ResumeExecution later on. */
1226 pVM->hwaccm.s.vmx.fResumeVM = true;
1227
1228 /**
1229 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1230 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1231 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1232 */
1233
1234 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1235 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1236
1237 switch (rc)
1238 {
1239 case VINF_SUCCESS:
1240 break;
1241
1242 case VERR_VMX_INVALID_VMXON_PTR:
1243 AssertFailed();
1244 goto end;
1245
1246 case VERR_VMX_UNABLE_TO_START_VM:
1247 case VERR_VMX_UNABLE_TO_RESUME_VM:
1248 {
1249#ifdef VBOX_STRICT
1250 int rc1;
1251
1252 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1253 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1254 AssertRC(rc1);
1255 if (rc1 == VINF_SUCCESS)
1256 {
1257 RTGDTR gdtr;
1258 PX86DESCHC pDesc;
1259
1260 ASMGetGDTR(&gdtr);
1261
1262 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1263 Log(("Current stack %08x\n", &rc1));
1264
1265
1266 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1267 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1268 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1269 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1270 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1271 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1272 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1273 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1274 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1275 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1276
1277 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1278 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1279
1280 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1281 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1282
1283 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1284 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1285
1286 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1287 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1288 if (val < gdtr.cbGdt)
1289 {
1290 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1291 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1292 }
1293
1294 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1295 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1296 if (val < gdtr.cbGdt)
1297 {
1298 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1299 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1300 }
1301
1302 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1303 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1304 if (val < gdtr.cbGdt)
1305 {
1306 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1307 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1308 }
1309
1310 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1311 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1312 if (val < gdtr.cbGdt)
1313 {
1314 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1315 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1316 }
1317
1318 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1319 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1320 if (val < gdtr.cbGdt)
1321 {
1322 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1323 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1324 }
1325
1326 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1327 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1328 if (val < gdtr.cbGdt)
1329 {
1330 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1331 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1332 }
1333
1334 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1335 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1336 if (val < gdtr.cbGdt)
1337 {
1338 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1339 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1340 }
1341
1342 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1343 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1344
1345 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1346 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1347 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1348 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1349
1350 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1351 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1352
1353 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1354 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1355
1356 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1357 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1358
1359 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1360 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1361 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1362 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1363
1364#if HC_ARCH_BITS == 64
1365 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1366 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1367 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1368 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1369 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1370#endif
1371 }
1372#endif /* VBOX_STRICT */
1373 goto end;
1374 }
1375
1376 default:
1377 /* impossible */
1378 AssertFailed();
1379 goto end;
1380 }
1381 /* Success. Query the guest state and figure out what has happened. */
1382
1383 /* Investigate why there was a VM-exit. */
1384 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1385 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1386
1387 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1388 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1389 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1390 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1391 intInfo = val;
1392 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1393 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1394 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1395 instrInfo = val;
1396 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1397 exitQualification = val;
1398 AssertRC(rc);
1399
1400 /* Let's first sync back eip, esp, and eflags. */
1401 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1402 AssertRC(rc);
1403 pCtx->rip = val;
1404 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1405 AssertRC(rc);
1406 pCtx->rsp = val;
1407 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1408 AssertRC(rc);
1409 pCtx->eflags.u32 = val;
1410
1411 /* Take care of instruction fusing (sti, mov ss) */
1412 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1413 uInterruptState = val;
1414 if (uInterruptState != 0)
1415 {
1416 Assert(uInterruptState <= 2); /* only sti & mov ss */
1417 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1418 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1419 }
1420 else
1421 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1422
1423 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1424 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1425 {
1426 /* Hide our emulation flags */
1427 pCtx->eflags.Bits.u1VM = 0;
1428 pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1429 pCtx->eflags.Bits.u1VIF = 0;
1430 pCtx->eflags.Bits.u2IOPL = 0;
1431 }
1432
1433 /* Control registers. */
1434 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1435 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1436 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1437 CPUMSetGuestCR0(pVM, val);
1438
1439 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1440 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1441 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1442 CPUMSetGuestCR4(pVM, val);
1443
1444 CPUMSetGuestCR2(pVM, ASMGetCR2());
1445
1446 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1447 CPUMSetGuestDR7(pVM, val);
1448
1449 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1450 VMX_READ_SELREG(ES, es);
1451 VMX_READ_SELREG(SS, ss);
1452 VMX_READ_SELREG(CS, cs);
1453 VMX_READ_SELREG(DS, ds);
1454 VMX_READ_SELREG(FS, fs);
1455 VMX_READ_SELREG(GS, gs);
1456
1457 /** @note NOW IT'S SAFE FOR LOGGING! */
1458 Log2(("Raw exit reason %08x\n", exitReason));
1459
1460 /* Check if an injected event was interrupted prematurely. */
1461 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1462 AssertRC(rc);
1463 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1464 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1465 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1466 {
1467 pVM->hwaccm.s.Event.fPending = true;
1468 /* Error code present? */
1469 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1470 {
1471 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1472 AssertRC(rc);
1473 pVM->hwaccm.s.Event.errCode = val;
1474 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1475 }
1476 else
1477 {
1478 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1479 pVM->hwaccm.s.Event.errCode = 0;
1480 }
1481 }
1482
1483#ifdef VBOX_STRICT
1484 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1485 HWACCMDumpRegs(pCtx);
1486#endif
1487
1488 Log2(("E%d", exitReason));
1489 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1490 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1491 Log2(("Interruption error code %d\n", errCode));
1492 Log2(("IntInfo = %08x\n", intInfo));
1493 Log2(("New EIP=%VGv\n", pCtx->rip));
1494
1495 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1496 switch (exitReason)
1497 {
1498 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1499 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1500 {
1501 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1502
1503 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1504 {
1505 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1506 /* External interrupt; leave to allow it to be dispatched again. */
1507 rc = VINF_EM_RAW_INTERRUPT;
1508 break;
1509 }
1510 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1511 {
1512 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1513 /* External interrupt; leave to allow it to be dispatched again. */
1514 rc = VINF_EM_RAW_INTERRUPT;
1515 break;
1516
1517 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1518 AssertFailed(); /* can't come here; fails the first check. */
1519 break;
1520
1521 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1522 Assert(vector == 3 || vector == 4);
1523 /* no break */
1524 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1525 Log2(("Hardware/software interrupt %d\n", vector));
1526 switch (vector)
1527 {
1528 case X86_XCPT_NM:
1529 {
1530 uint32_t oldCR0;
1531
1532 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1533
1534 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1535 oldCR0 = ASMGetCR0();
1536 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1537 rc = CPUMHandleLazyFPU(pVM);
1538 if (rc == VINF_SUCCESS)
1539 {
1540 Assert(CPUMIsGuestFPUStateActive(pVM));
1541
1542 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
1543 ASMSetCR0(oldCR0);
1544
1545 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1546
1547 /* Continue execution. */
1548 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1549 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1550
1551 goto ResumeExecution;
1552 }
1553
1554 Log(("Forward #NM fault to the guest\n"));
1555 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1556 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1557 AssertRC(rc);
1558 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1559 goto ResumeExecution;
1560 }
1561
1562 case X86_XCPT_PF: /* Page fault */
1563 {
1564 Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1565 /* Exit qualification contains the linear address of the page fault. */
1566 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1567 TRPMSetErrorCode(pVM, errCode);
1568 TRPMSetFaultAddress(pVM, exitQualification);
1569
1570 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1571 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1572 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1573 if (rc == VINF_SUCCESS)
1574 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1575 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1576 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1577
1578 TRPMResetTrap(pVM);
1579
1580 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1581 goto ResumeExecution;
1582 }
1583 else
1584 if (rc == VINF_EM_RAW_GUEST_TRAP)
1585 { /* A genuine pagefault.
1586 * Forward the trap to the guest by injecting the exception and resuming execution.
1587 */
1588 Log2(("Forward page fault to the guest\n"));
1589 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1590 /* The error code might have been changed. */
1591 errCode = TRPMGetErrorCode(pVM);
1592
1593 TRPMResetTrap(pVM);
1594
1595 /* Now we must update CR2. */
1596 pCtx->cr2 = exitQualification;
1597 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1598 AssertRC(rc);
1599
1600 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1601 goto ResumeExecution;
1602 }
1603#ifdef VBOX_STRICT
1604 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1605 Log2(("PGMTrap0eHandler failed with %d\n", rc));
1606#endif
1607 /* Need to go back to the recompiler to emulate the instruction. */
1608 TRPMResetTrap(pVM);
1609 break;
1610 }
1611
1612 case X86_XCPT_MF: /* Floating point exception. */
1613 {
1614 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1615 if (!(pCtx->cr0 & X86_CR0_NE))
1616 {
1617 /* old style FPU error reporting needs some extra work. */
1618 /** @todo don't fall back to the recompiler, but do it manually. */
1619 rc = VINF_EM_RAW_EMULATE_INSTR;
1620 break;
1621 }
1622 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1623 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1624 AssertRC(rc);
1625
1626 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1627 goto ResumeExecution;
1628 }
1629
1630#ifdef VBOX_STRICT
1631 case X86_XCPT_GP: /* General protection failure exception.*/
1632 case X86_XCPT_UD: /* Unknown opcode exception. */
1633 case X86_XCPT_DE: /* Debug exception. */
1634 case X86_XCPT_SS: /* Stack segment exception. */
1635 case X86_XCPT_NP: /* Segment not present exception. */
1636 {
1637 switch(vector)
1638 {
1639 case X86_XCPT_DE:
1640 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1641 break;
1642 case X86_XCPT_UD:
1643 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1644 break;
1645 case X86_XCPT_SS:
1646 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1647 break;
1648 case X86_XCPT_NP:
1649 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1650 break;
1651 case X86_XCPT_GP:
1652 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1653 break;
1654 }
1655
1656 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1657 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1658 AssertRC(rc);
1659
1660 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1661 goto ResumeExecution;
1662 }
1663#endif
1664 default:
1665 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1666 rc = VERR_EM_INTERNAL_ERROR;
1667 break;
1668 } /* switch (vector) */
1669
1670 break;
1671
1672 default:
1673 rc = VERR_EM_INTERNAL_ERROR;
1674 AssertFailed();
1675 break;
1676 }
1677
1678 break;
1679 }
1680
1681 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1682 /* Clear VM-exit on IF=1 change. */
1683 Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1684 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1685 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1686 AssertRC(rc);
1687 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1688 goto ResumeExecution; /* we check for pending guest interrupts there */
1689
1690 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1691 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1692 /* Skip instruction and continue directly. */
1693 pCtx->rip += cbInstr;
1694 /* Continue execution.*/
1695 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1696 goto ResumeExecution;
1697
1698 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1699 {
1700 Log2(("VMX: Cpuid %x\n", pCtx->eax));
1701 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1702 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1703 if (rc == VINF_SUCCESS)
1704 {
1705 /* Update EIP and continue execution. */
1706 Assert(cbInstr == 2);
1707 pCtx->rip += cbInstr;
1708 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1709 goto ResumeExecution;
1710 }
1711 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1712 rc = VINF_EM_RAW_EMULATE_INSTR;
1713 break;
1714 }
1715
1716 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1717 {
1718 Log2(("VMX: Rdtsc\n"));
1719 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1720 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1721 if (rc == VINF_SUCCESS)
1722 {
1723 /* Update EIP and continue execution. */
1724 Assert(cbInstr == 2);
1725 pCtx->rip += cbInstr;
1726 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1727 goto ResumeExecution;
1728 }
1729 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1730 rc = VINF_EM_RAW_EMULATE_INSTR;
1731 break;
1732 }
1733
1734 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1735 {
1736 Log2(("VMX: invlpg\n"));
1737 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1738 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1739 if (rc == VINF_SUCCESS)
1740 {
1741 /* Update EIP and continue execution. */
1742 pCtx->rip += cbInstr;
1743 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1744 goto ResumeExecution;
1745 }
1746 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1747 break;
1748 }
1749
1750 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1751 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1752 {
1753 uint32_t cbSize;
1754
1755 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1756 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1757 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1758 if (rc == VINF_SUCCESS)
1759 {
1760 /* EIP has been updated already. */
1761
1762 /* Only resume if successful. */
1763 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1764 goto ResumeExecution;
1765 }
1766 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1767 break;
1768 }
1769
1770 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1771 {
1772 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1773 {
1774 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1775 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1776 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1777 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1778 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1779 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1780
1781 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1782 {
1783 case 0:
1784 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1785 break;
1786 case 2:
1787 break;
1788 case 3:
1789 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1790 break;
1791 case 4:
1792 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1793 break;
1794 case 8:
1795 /* CR8 contains the APIC TPR */
1796 break;
1797
1798 default:
1799 AssertFailed();
1800 break;
1801 }
1802 /* Check if a sync operation is pending. */
1803 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1804 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1805 {
1806 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1807 AssertRC(rc);
1808 }
1809 break;
1810
1811 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1812 Log2(("VMX: mov x, crx\n"));
1813 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1814
1815 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1816 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1817
1818 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1819 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1820 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1821 break;
1822
1823 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1824 Log2(("VMX: clts\n"));
1825 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1826 rc = EMInterpretCLTS(pVM);
1827 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1828 break;
1829
1830 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1831 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1832 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1833 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1834 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1835 break;
1836 }
1837
1838 /* Update EIP if no error occurred. */
1839 if (VBOX_SUCCESS(rc))
1840 pCtx->rip += cbInstr;
1841
1842 if (rc == VINF_SUCCESS)
1843 {
1844 /* Only resume if successful. */
1845 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1846 goto ResumeExecution;
1847 }
1848 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1849 break;
1850 }
1851
1852 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1853 {
1854 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1855 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1856 {
1857 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1858 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1859 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1860 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1861 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1862 Log2(("DR7=%08x\n", pCtx->dr7));
1863 }
1864 else
1865 {
1866 Log2(("VMX: mov x, drx\n"));
1867 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1868 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1869 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1870 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1871 }
1872 /* Update EIP if no error occurred. */
1873 if (VBOX_SUCCESS(rc))
1874 pCtx->rip += cbInstr;
1875
1876 if (rc == VINF_SUCCESS)
1877 {
1878 /* Only resume if successful. */
1879 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1880 goto ResumeExecution;
1881 }
1882 Assert(rc == VERR_EM_INTERPRETER);
1883 break;
1884 }
1885
1886 /** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1887 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1888 {
1889 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1890 uint32_t uPort;
1891 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1892
1893 /** @todo necessary to make the distinction? */
1894 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1895 {
1896 uPort = pCtx->edx & 0xffff;
1897 }
1898 else
1899 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1900
1901 /* paranoia */
1902 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
1903 {
1904 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1905 break;
1906 }
1907
1908 uint32_t cbSize = aIOSize[uIOWidth];
1909
1910 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1911 {
1912 /* ins/outs */
1913 uint32_t prefix = 0;
1914 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1915 prefix |= PREFIX_REP;
1916
1917 if (fIOWrite)
1918 {
1919 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1920 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1921 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1922 }
1923 else
1924 {
1925 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1926 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1927 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1928 }
1929 }
1930 else
1931 {
1932 /* normal in/out */
1933 uint32_t uAndVal = aIOOpAnd[uIOWidth];
1934
1935 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1936
1937 if (fIOWrite)
1938 {
1939 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1940 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1941 }
1942 else
1943 {
1944 uint32_t u32Val = 0;
1945
1946 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1947 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1948 if (IOM_SUCCESS(rc))
1949 {
1950 /* Write back to the EAX register. */
1951 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1952 }
1953 }
1954 }
1955 /*
1956 * Handled the I/O return codes.
1957 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1958 */
1959 if (IOM_SUCCESS(rc))
1960 {
1961 /* Update EIP and continue execution. */
1962 pCtx->rip += cbInstr;
1963 if (RT_LIKELY(rc == VINF_SUCCESS))
1964 {
1965 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1966 goto ResumeExecution;
1967 }
1968 break;
1969 }
1970
1971#ifdef VBOX_STRICT
1972 if (rc == VINF_IOM_HC_IOPORT_READ)
1973 Assert(!fIOWrite);
1974 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1975 Assert(fIOWrite);
1976 else
1977 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1978#endif
1979 break;
1980 }
1981
1982 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1983 /* RIP is already set to the next instruction */
1984 AssertFailed(); /* currently not used */
1985 break;
1986
1987 default:
1988 /* The rest is handled after syncing the entire CPU state. */
1989 break;
1990 }
1991
1992 /* Note: the guest state isn't entirely synced back at this stage. */
1993
1994 /* Investigate why there was a VM-exit. (part 2) */
1995 switch (exitReason)
1996 {
1997 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1998 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1999 /* Already handled above. */
2000 break;
2001
2002 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2003 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2004 break;
2005
2006 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2007 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2008 rc = VINF_EM_RAW_INTERRUPT;
2009 AssertFailed(); /* Can't happen. Yet. */
2010 break;
2011
2012 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2013 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2014 rc = VINF_EM_RAW_INTERRUPT;
2015 AssertFailed(); /* Can't happen afaik. */
2016 break;
2017
2018 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2019 rc = VERR_EM_INTERPRETER;
2020 break;
2021
2022 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2023 /** Check if external interrupts are pending; if so, don't switch back. */
2024 if ( pCtx->eflags.Bits.u1IF
2025 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2026 {
2027 pCtx->rip++; /* skip hlt */
2028 goto ResumeExecution;
2029 }
2030
2031 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
2032 break;
2033
2034 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2035 AssertFailed(); /* can't happen. */
2036 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2037 break;
2038
2039 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2040 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2041 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2042 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2043 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2044 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2045 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2046 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2047 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2048 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2049 /** @todo inject #UD immediately */
2050 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2051 break;
2052
2053 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2054 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2055 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2056 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2057 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2058 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2059 /* already handled above */
2060 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2061 || rc == VINF_EM_RAW_INTERRUPT
2062 || rc == VERR_EM_INTERPRETER
2063 || rc == VINF_EM_RAW_EMULATE_INSTR
2064 || rc == VINF_PGM_SYNC_CR3
2065 || rc == VINF_IOM_HC_IOPORT_READ
2066 || rc == VINF_IOM_HC_IOPORT_WRITE
2067 || rc == VINF_EM_RAW_GUEST_TRAP
2068 || rc == VINF_TRPM_XCPT_DISPATCHED
2069 || rc == VINF_EM_RESCHEDULE_REM,
2070 ("rc = %d\n", rc));
2071 break;
2072
2073 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2074 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2075 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2076 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2077 rc = VERR_EM_INTERPRETER;
2078 break;
2079
2080 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2081 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2082 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2083 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2084 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2085 break;
2086
2087 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2088 Assert(rc == VINF_EM_RAW_INTERRUPT);
2089 break;
2090
2091 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2092 {
2093#ifdef VBOX_STRICT
2094 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2095
2096 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2097 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2098
2099 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2100 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2101
2102 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2103 Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2104
2105 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2106 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2107
2108 VMX_LOG_SELREG(CS, "CS");
2109 VMX_LOG_SELREG(DS, "DS");
2110 VMX_LOG_SELREG(ES, "ES");
2111 VMX_LOG_SELREG(FS, "FS");
2112 VMX_LOG_SELREG(GS, "GS");
2113 VMX_LOG_SELREG(SS, "SS");
2114 VMX_LOG_SELREG(TR, "TR");
2115 VMX_LOG_SELREG(LDTR, "LDTR");
2116
2117 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2118 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2119 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2120 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2121#endif /* VBOX_STRICT */
2122 rc = VERR_EM_INTERNAL_ERROR;
2123 break;
2124 }
2125
2126 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2127 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2128 default:
2129 rc = VERR_EM_INTERNAL_ERROR;
2130 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2131 break;
2132
2133 }
2134end:
2135 if (fGuestStateSynced)
2136 {
2137 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2138 VMX_READ_SELREG(LDTR, ldtr);
2139 VMX_READ_SELREG(TR, tr);
2140
2141 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2142 pCtx->gdtr.cbGdt = val;
2143 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2144 pCtx->gdtr.pGdt = val;
2145
2146 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2147 pCtx->idtr.cbIdt = val;
2148 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2149 pCtx->idtr.pIdt = val;
2150
2151 /*
2152 * System MSRs
2153 */
2154 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
2155 pCtx->SysEnter.cs = val;
2156 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
2157 pCtx->SysEnter.eip = val;
2158 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
2159 pCtx->SysEnter.esp = val;
2160 }
2161
2162 /* Signal changes for the recompiler. */
2163 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2164
2165 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2166 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2167 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2168 {
2169 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2170 /* On the next entry we'll only sync the host context. */
2171 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2172 }
2173 else
2174 {
2175 /* On the next entry we'll sync everything. */
2176 /** @todo we can do better than this */
2177 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2178 }
2179
2180 /* translate into a less severe return code */
2181 if (rc == VERR_EM_INTERPRETER)
2182 rc = VINF_EM_RAW_EMULATE_INSTR;
2183
2184 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2185 Log2(("X"));
2186 return rc;
2187}
2188
2189
2190/**
2191 * Enters the VT-x session
2192 *
2193 * @returns VBox status code.
2194 * @param pVM The VM to operate on.
2195 * @param pCpu CPU info struct
2196 */
2197HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2198{
2199 Assert(pVM->hwaccm.s.vmx.fSupported);
2200
2201 unsigned cr4 = ASMGetCR4();
2202 if (!(cr4 & X86_CR4_VMXE))
2203 {
2204 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2205 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2206 }
2207
2208 /* Activate the VM Control Structure. */
2209 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2210 if (VBOX_FAILURE(rc))
2211 return rc;
2212
2213 pVM->hwaccm.s.vmx.fResumeVM = false;
2214 return VINF_SUCCESS;
2215}
2216
2217
2218/**
2219 * Leaves the VT-x session
2220 *
2221 * @returns VBox status code.
2222 * @param pVM The VM to operate on.
2223 */
2224HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2225{
2226 Assert(pVM->hwaccm.s.vmx.fSupported);
2227
2228 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2229 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2230 AssertRC(rc);
2231
2232 return VINF_SUCCESS;
2233}
2234
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