HWVMXR0.cpp@ 10507

Last change on this file since 10507 was 10502, checked in by vboxsync, 16 years ago
Take precautions for being rescheduled to a different cpu due to long jumps to ring 3. (affects AMD-V only)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 84.9 KB

Line
1	/* $Id: HWVMXR0.cpp 10502 2008-07-11 09:31:15Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/string.h>
41	#include "HWVMXR0.h"
42
43
44	/* IO operation lookup arrays. */
45	static uint32_t aIOSize[4] = {1, 2, 0, 4};
46	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49	static void VMXR0CheckError(PVM pVM, int rc)
50	{
51	if (rc == VERR_VMX_GENERIC)
52	{
53	RTCCUINTREG instrError;
54
55	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57	}
58	pVM->hwaccm.s.lLastError = rc;
59	}
60
61	/**
62	* Sets up and activates VT-x on the current CPU
63	*
64	* @returns VBox status code.
65	* @param pCpu CPU info struct
66	* @param pVM The VM to operate on.
67	* @param pvPageCpu Pointer to the global cpu page
68	* @param pPageCpuPhys Physical address of the global cpu page
69	*/
70	HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71	{
72	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73	AssertReturn(pVM, VERR_INVALID_PARAMETER);
74	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76	/* Setup Intel VMX. */
77	Assert(pVM->hwaccm.s.vmx.fSupported);
78
79	#ifdef LOG_ENABLED
80	SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81	#endif
82	/* Set revision dword at the beginning of the VMXON structure. */
83	(uint32_t )pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86	* (which can have very bad consequences!!!)
87	*/
88
89	/* Make sure the VMX instructions don't cause #UD faults. */
90	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
91
92	/* Enter VMX Root Mode */
93	int rc = VMXEnable(pPageCpuPhys);
94	if (VBOX_FAILURE(rc))
95	{
96	VMXR0CheckError(pVM, rc);
97	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98	return VERR_VMX_VMXON_FAILED;
99	}
100	return VINF_SUCCESS;
101	}
102
103	/**
104	* Deactivates VT-x on the current CPU
105	*
106	* @returns VBox status code.
107	* @param pCpu CPU info struct
108	* @param pvPageCpu Pointer to the global cpu page
109	* @param pPageCpuPhys Physical address of the global cpu page
110	*/
111	HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112	{
113	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116	/* Leave VMX Root Mode. */
117	VMXDisable();
118
119	/* And clear the X86_CR4_VMXE bit */
120	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122	#ifdef LOG_ENABLED
123	SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124	#endif
125	return VINF_SUCCESS;
126	}
127
128	/**
129	* Does Ring-0 per VM VT-x init.
130	*
131	* @returns VBox status code.
132	* @param pVM The VM to operate on.
133	*/
134	HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135	{
136	int rc;
137
138	#ifdef LOG_ENABLED
139	SUPR0Printf("VMXR0InitVM %x\n", pVM);
140	#endif
141
142	/* Allocate one page for the VM control structure (VMCS). */
143	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
144	AssertRC(rc);
145	if (RT_FAILURE(rc))
146	return rc;
147
148	pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
149	pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
150	ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
151
152	/* Allocate one page for the TSS we need for real mode emulation. */
153	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
154	AssertRC(rc);
155	if (RT_FAILURE(rc))
156	return rc;
157
158	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
159	pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
160
161	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
162	* for I/O operations. */
163	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
164	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
165	/* Bit set to 0 means redirection enabled. */
166	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
167
168	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
169	{
170	/* Allocate one page for the virtual APIC mmio cache. */
171	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
172	AssertRC(rc);
173	if (RT_FAILURE(rc))
174	return rc;
175
176	pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
177	pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
178	ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
179	}
180	else
181	{
182	pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
183	pVM->hwaccm.s.vmx.pAPIC = 0;
184	pVM->hwaccm.s.vmx.pAPICPhys = 0;
185	}
186
187	#ifdef LOG_ENABLED
188	SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
189	#endif
190	return VINF_SUCCESS;
191	}
192
193	/**
194	* Does Ring-0 per VM VT-x termination.
195	*
196	* @returns VBox status code.
197	* @param pVM The VM to operate on.
198	*/
199	HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
200	{
201	if (pVM->hwaccm.s.vmx.pMemObjVMCS)
202	{
203	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
204	pVM->hwaccm.s.vmx.pMemObjVMCS = 0;
205	pVM->hwaccm.s.vmx.pVMCS = 0;
206	pVM->hwaccm.s.vmx.pVMCSPhys = 0;
207	}
208	if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS)
209	{
210	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
211	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = 0;
212	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
213	pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
214	}
215	if (pVM->hwaccm.s.vmx.pMemObjAPIC)
216	{
217	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
218	pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
219	pVM->hwaccm.s.vmx.pAPIC = 0;
220	pVM->hwaccm.s.vmx.pAPICPhys = 0;
221	}
222	return VINF_SUCCESS;
223	}
224
225	/**
226	* Sets up VT-x for the specified VM
227	*
228	* @returns VBox status code.
229	* @param pVM The VM to operate on.
230	*/
231	HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
232	{
233	int rc = VINF_SUCCESS;
234	uint32_t val;
235
236	AssertReturn(pVM, VERR_INVALID_PARAMETER);
237	Assert(pVM->hwaccm.s.vmx.pVMCS);
238
239	/* Set revision dword at the beginning of the VMCS structure. */
240	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
241
242	/* Clear VM Control Structure. */
243	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
244	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
245	if (VBOX_FAILURE(rc))
246	goto vmx_end;
247
248	/* Activate the VM Control Structure. */
249	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
250	if (VBOX_FAILURE(rc))
251	goto vmx_end;
252
253	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
254	* Set required bits to one and zero according to the MSR capabilities.
255	*/
256	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
257	/* External and non-maskable interrupts cause VM-exits. */
258	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
259	val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
260
261	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
262	AssertRC(rc);
263
264	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
265	* Set required bits to one and zero according to the MSR capabilities.
266	*/
267	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
268	/* Program which event cause VM-exits and which features we want to use. */
269	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
270	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
271	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
272	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
273	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
274	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
275
276	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
277
278	#if HC_ARCH_BITS == 64
279	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
280	{
281	/* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
282	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
283	Assert(pVM->hwaccm.s.vmx.pAPIC);
284	}
285	else
286	/* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
287	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
288	#endif
289	/* Mask away the bits that the CPU doesn't support */
290	/** @todo make sure they don't conflict with the above requirements. */
291	val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
292	pVM->hwaccm.s.vmx.proc_ctls = val;
293
294	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
295	AssertRC(rc);
296
297	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
298	* Set required bits to one and zero according to the MSR capabilities.
299	*/
300	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
301	AssertRC(rc);
302
303	/* VMX_VMCS_CTRL_EXIT_CONTROLS
304	* Set required bits to one and zero according to the MSR capabilities.
305	*/
306	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
307	#if HC_ARCH_BITS == 64
308	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
309	#else
310	/* else Must be zero when AMD64 is not available. */
311	#endif
312	val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
313	/* Don't acknowledge external interrupts on VM-exit. */
314	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
315	AssertRC(rc);
316
317	/* Forward all exception except #NM & #PF to the guest.
318	* We always need to check pagefaults since our shadow page table can be out of sync.
319	* And we always lazily sync the FPU & XMM state.
320	*/
321
322	/*
323	* @todo Possible optimization:
324	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
325	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
326	* registers ourselves of course.
327	*
328	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
329	*/
330	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
331	AssertRC(rc);
332
333	/* Don't filter page faults; all of them should cause a switch. */
334	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
335	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
336	AssertRC(rc);
337
338	/* Init TSC offset to zero. */
339	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
340	#if HC_ARCH_BITS == 32
341	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
342	#endif
343	AssertRC(rc);
344
345	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
346	#if HC_ARCH_BITS == 32
347	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
348	#endif
349	AssertRC(rc);
350
351	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
352	#if HC_ARCH_BITS == 32
353	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
354	#endif
355	AssertRC(rc);
356
357	/* Clear MSR controls. */
358	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
359	{
360	/* Optional */
361	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
362	#if HC_ARCH_BITS == 32
363	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
364	#endif
365	AssertRC(rc);
366	}
367	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
368	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
369	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
370	#if HC_ARCH_BITS == 32
371	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
372	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
373	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
374	#endif
375	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
376	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
377	AssertRC(rc);
378
379	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
380	{
381	Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
382	/* Optional */
383	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
384	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
385	#if HC_ARCH_BITS == 32
386	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
387	#endif
388	AssertRC(rc);
389	}
390
391	/* Set link pointer to -1. Not currently used. */
392	#if HC_ARCH_BITS == 32
393	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
394	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
395	#else
396	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
397	#endif
398	AssertRC(rc);
399
400	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
401	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
402	AssertRC(rc);
403
404	vmx_end:
405	VMXR0CheckError(pVM, rc);
406	return rc;
407	}
408
409
410	/**
411	* Injects an event (trap or external interrupt)
412	*
413	* @returns VBox status code.
414	* @param pVM The VM to operate on.
415	* @param pCtx CPU Context
416	* @param intInfo VMX interrupt info
417	* @param cbInstr Opcode length of faulting instruction
418	* @param errCode Error code (optional)
419	*/
420	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
421	{
422	int rc;
423
424	#ifdef VBOX_STRICT
425	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
426	if (iGate == 0xE)
427	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
428	else
429	if (iGate < 0x20)
430	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
431	else
432	{
433	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
434	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
435	Assert(pCtx->eflags.u32 & X86_EFL_IF);
436	}
437	#endif
438
439	/* Set event injection state. */
440	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
441	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
442	);
443
444	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
445	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
446
447	AssertRC(rc);
448	return rc;
449	}
450
451
452	/**
453	* Checks for pending guest interrupts and injects them
454	*
455	* @returns VBox status code.
456	* @param pVM The VM to operate on.
457	* @param pCtx CPU Context
458	*/
459	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
460	{
461	int rc;
462
463	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
464	if (pVM->hwaccm.s.Event.fPending)
465	{
466	Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
467	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
468	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
469	AssertRC(rc);
470
471	pVM->hwaccm.s.Event.fPending = false;
472	return VINF_SUCCESS;
473	}
474
475	/* When external interrupts are pending, we should exit the VM when IF is set. */
476	if ( !TRPMHasTrap(pVM)
477	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
478	{
479	if (!(pCtx->eflags.u32 & X86_EFL_IF))
480	{
481	Log2(("Enable irq window exit!\n"));
482	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
483	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
484	AssertRC(rc);
485	}
486	else
487	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
488	{
489	uint8_t u8Interrupt;
490
491	rc = PDMGetInterrupt(pVM, &u8Interrupt);
492	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
493	if (VBOX_SUCCESS(rc))
494	{
495	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
496	AssertRC(rc);
497	}
498	else
499	{
500	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
501	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
502	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
503	/* Just continue */
504	}
505	}
506	else
507	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
508	}
509
510	#ifdef VBOX_STRICT
511	if (TRPMHasTrap(pVM))
512	{
513	uint8_t u8Vector;
514	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
515	AssertRC(rc);
516	}
517	#endif
518
519	if ( pCtx->eflags.u32 & X86_EFL_IF
520	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
521	&& TRPMHasTrap(pVM)
522	)
523	{
524	uint8_t u8Vector;
525	int rc;
526	TRPMEVENT enmType;
527	RTGCUINTPTR intInfo;
528	RTGCUINT errCode;
529
530	/* If a new event is pending, then dispatch it now. */
531	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
532	AssertRC(rc);
533	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
534	Assert(enmType != TRPM_SOFTWARE_INT);
535
536	/* Clear the pending trap. */
537	rc = TRPMResetTrap(pVM);
538	AssertRC(rc);
539
540	intInfo = u8Vector;
541	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
542
543	if (enmType == TRPM_TRAP)
544	{
545	switch (u8Vector) {
546	case 8:
547	case 10:
548	case 11:
549	case 12:
550	case 13:
551	case 14:
552	case 17:
553	/* Valid error codes. */
554	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
555	break;
556	default:
557	break;
558	}
559	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
560	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
561	else
562	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
563	}
564	else
565	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
566
567	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
568	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
569	AssertRC(rc);
570	} /* if (interrupts can be dispatched) */
571
572	return VINF_SUCCESS;
573	}
574
575	/**
576	* Save the host state
577	*
578	* @returns VBox status code.
579	* @param pVM The VM to operate on.
580	*/
581	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
582	{
583	int rc = VINF_SUCCESS;
584
585	/*
586	* Host CPU Context
587	*/
588	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
589	{
590	RTIDTR idtr;
591	RTGDTR gdtr;
592	RTSEL SelTR;
593	PX86DESCHC pDesc;
594	uintptr_t trBase;
595
596	/* Control registers */
597	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
598	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
599	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
600	AssertRC(rc);
601	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
602	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
603	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
604
605	/* Selector registers. */
606	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
607	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
608	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
609	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
610	#if HC_ARCH_BITS == 32
611	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
612	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
613	#endif
614	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
615	SelTR = ASMGetTR();
616	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
617	AssertRC(rc);
618	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
619	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
620	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
621	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
622	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
623	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
624	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
625
626	/* GDTR & IDTR */
627	ASMGetGDTR(&gdtr);
628	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
629	ASMGetIDTR(&idtr);
630	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
631	AssertRC(rc);
632	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
633	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
634
635	/* Save the base address of the TR selector. */
636	if (SelTR > gdtr.cbGdt)
637	{
638	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
639	return VERR_VMX_INVALID_HOST_STATE;
640	}
641
642	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
643	#if HC_ARCH_BITS == 64
644	trBase = X86DESC64_BASE(*pDesc);
645	#else
646	trBase = X86DESC_BASE(*pDesc);
647	#endif
648	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
649	AssertRC(rc);
650	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
651
652	/* FS and GS base. */
653	#if HC_ARCH_BITS == 64
654	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
655	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
656	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
657	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
658	#endif
659	AssertRC(rc);
660
661	/* Sysenter MSRs. */
662	/** @todo expensive!! */
663	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
664	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
665	#if HC_ARCH_BITS == 32
666	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
667	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
668	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
669	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
670	#else
671	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
672	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
673	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
674	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
675	#endif
676	AssertRC(rc);
677
678	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
679	}
680	return rc;
681	}
682
683
684	/**
685	* Loads the guest state
686	*
687	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
688	*
689	* @returns VBox status code.
690	* @param pVM The VM to operate on.
691	* @param pCtx Guest context
692	*/
693	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
694	{
695	int rc = VINF_SUCCESS;
696	RTGCUINTPTR val;
697	X86EFLAGS eflags;
698
699	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
700	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
701	{
702	VMX_WRITE_SELREG(ES, es);
703	AssertRC(rc);
704
705	VMX_WRITE_SELREG(CS, cs);
706	AssertRC(rc);
707
708	VMX_WRITE_SELREG(SS, ss);
709	AssertRC(rc);
710
711	VMX_WRITE_SELREG(DS, ds);
712	AssertRC(rc);
713
714	/* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
715	VMX_WRITE_SELREG(FS, fs);
716	AssertRC(rc);
717
718	VMX_WRITE_SELREG(GS, gs);
719	AssertRC(rc);
720	}
721
722	/* Guest CPU context: LDTR. */
723	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
724	{
725	if (pCtx->ldtr == 0)
726	{
727	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
728	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
729	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
730	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
731	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
732	}
733	else
734	{
735	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
736	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
737	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
738	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
739	}
740	AssertRC(rc);
741	}
742	/* Guest CPU context: TR. */
743	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
744	{
745	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
746
747	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
748	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
749	{
750	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
751	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
752	}
753	else
754	{
755	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
756	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
757	}
758	val = pCtx->trHid.Attr.u;
759
760	/* The TSS selector must be busy. */
761	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
762	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
763	else
764	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
765	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
766
767	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
768	AssertRC(rc);
769	}
770	/* Guest CPU context: GDTR. */
771	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
772	{
773	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
774	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
775	AssertRC(rc);
776	}
777	/* Guest CPU context: IDTR. */
778	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
779	{
780	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
781	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
782	AssertRC(rc);
783	}
784
785	/*
786	* Sysenter MSRs (unconditional)
787	*/
788	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
789	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
790	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
791	AssertRC(rc);
792
793	/* Control registers */
794	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
795	{
796	val = pCtx->cr0;
797	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
798	Log2(("Guest CR0-shadow %08x\n", val));
799	if (CPUMIsGuestFPUStateActive(pVM) == false)
800	{
801	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
802	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
803	}
804	else
805	{
806	/** @todo check if we support the old style mess correctly. */
807	if (!(val & X86_CR0_NE))
808	{
809	Log(("Forcing X86_CR0_NE!!!\n"));
810
811	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
812	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
813	{
814	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| RT_BIT(X86_XCPT_MF));
815	AssertRC(rc);
816	pVM->hwaccm.s.fFPUOldStyleOverride = true;
817	}
818	}
819
820	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
821	}
822	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
823	val \|= X86_CR0_PE \| X86_CR0_PG;
824	/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
825	val \|= X86_CR0_WP;
826
827	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
828	Log2(("Guest CR0 %08x\n", val));
829	/* CR0 flags owned by the host; if the guests attempts to change them, then
830	* the VM will exit.
831	*/
832	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
833	\| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
834	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
835	\| X86_CR0_TS
836	\| X86_CR0_ET
837	\| X86_CR0_NE
838	\| X86_CR0_MP;
839	pVM->hwaccm.s.vmx.cr0_mask = val;
840
841	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
842	Log2(("Guest CR0-mask %08x\n", val));
843	AssertRC(rc);
844	}
845	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
846	{
847	/* CR4 */
848	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
849	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
850	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
851	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
852	switch(pVM->hwaccm.s.enmShadowMode)
853	{
854	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
855	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
856	case PGMMODE_32_BIT: /* 32-bit paging. */
857	break;
858
859	case PGMMODE_PAE: /* PAE paging. */
860	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
861	/** @todo use normal 32 bits paging */
862	val \|= X86_CR4_PAE;
863	break;
864
865	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
866	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
867	#ifdef VBOX_ENABLE_64_BITS_GUESTS
868	break;
869	#else
870	AssertFailed();
871	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
872	#endif
873	default: /* shut up gcc */
874	AssertFailed();
875	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
876	}
877	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
878	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
879	val \|= X86_CR4_VME;
880
881	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
882	Log2(("Guest CR4 %08x\n", val));
883	/* CR4 flags owned by the host; if the guests attempts to change them, then
884	* the VM will exit.
885	*/
886	val = X86_CR4_PAE
887	\| X86_CR4_PGE
888	\| X86_CR4_PSE
889	\| X86_CR4_VMXE;
890	pVM->hwaccm.s.vmx.cr4_mask = val;
891
892	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
893	Log2(("Guest CR4-mask %08x\n", val));
894	AssertRC(rc);
895	}
896
897	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
898	{
899	/* Save our shadow CR3 register. */
900	val = PGMGetHyperCR3(pVM);
901	Assert(val);
902	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
903	AssertRC(rc);
904	}
905
906	/* Debug registers. */
907	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
908	{
909	/** @todo DR0-6 */
910	val = pCtx->dr7;
911	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
912	val \|= 0x400; /* must be one */
913	#ifdef VBOX_STRICT
914	val = 0x400;
915	#endif
916	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
917	AssertRC(rc);
918
919	/* IA32_DEBUGCTL MSR. */
920	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
921	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
922	AssertRC(rc);
923
924	/** @todo */
925	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
926	AssertRC(rc);
927	}
928
929	/* EIP, ESP and EFLAGS */
930	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
931	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
932	AssertRC(rc);
933
934	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
935	eflags = pCtx->eflags;
936	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
937	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
938
939	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
940	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
941	{
942	eflags.Bits.u1VM = 1;
943	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
944	eflags.Bits.u2IOPL = 3;
945	}
946
947	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
948	AssertRC(rc);
949
950	/** TSC offset. */
951	uint64_t u64TSCOffset;
952
953	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
954	{
955	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
956	#if HC_ARCH_BITS == 64
957	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
958	#else
959	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
960	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
961	#endif
962	AssertRC(rc);
963
964	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
965	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
966	AssertRC(rc);
967	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
968	}
969	else
970	{
971	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
972	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
973	AssertRC(rc);
974	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
975	}
976
977	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
978	* Set required bits to one and zero according to the MSR capabilities.
979	*/
980	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
981	/* 64 bits guest mode? */
982	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
983	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
984	/* else Must be zero when AMD64 is not available. */
985
986	/* Mask away the bits that the CPU doesn't support */
987	val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
988	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
989	AssertRC(rc);
990
991	/* 64 bits guest mode? */
992	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
993	{
994	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
995	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
996	#else
997	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
998	#endif
999	/* Unconditionally update these as wrmsr might have changed them. */
1000	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1001	AssertRC(rc);
1002	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1003	AssertRC(rc);
1004	}
1005	else
1006	{
1007	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1008	}
1009
1010	/* Done. */
1011	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1012
1013	return rc;
1014	}
1015
1016	/**
1017	* Runs guest code in a VT-x VM.
1018	*
1019	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
1020	*
1021	* @returns VBox status code.
1022	* @param pVM The VM to operate on.
1023	* @param pCtx Guest context
1024	*/
1025	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1026	{
1027	int rc = VINF_SUCCESS;
1028	RTCCUINTREG val, valShadow;
1029	RTCCUINTREG exitReason, instrError, cbInstr;
1030	RTGCUINTPTR exitQualification;
1031	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1032	RTGCUINTPTR errCode, instrInfo, uInterruptState;
1033	bool fGuestStateSynced = false;
1034	unsigned cResume = 0;
1035
1036	Log2(("\nE"));
1037
1038	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1039
1040	#ifdef VBOX_STRICT
1041	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1042	AssertRC(rc);
1043	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1044
1045	/* allowed zero */
1046	if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1047	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1048
1049	/* allowed one */
1050	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1051	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1052
1053	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1054	AssertRC(rc);
1055	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1056
1057	/* allowed zero */
1058	if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1059	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1060
1061	/* allowed one */
1062	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1063	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1064
1065	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1066	AssertRC(rc);
1067	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1068
1069	/* allowed zero */
1070	if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1071	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1072
1073	/* allowed one */
1074	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1075	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1076
1077	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1078	AssertRC(rc);
1079	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1080
1081	/* allowed zero */
1082	if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1083	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1084
1085	/* allowed one */
1086	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1087	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1088	#endif
1089
1090	#if 0
1091	/*
1092	* Check if debug registers are armed.
1093	*/
1094	uint32_t u32DR7 = ASMGetDR7();
1095	if (u32DR7 & X86_DR7_ENABLED_MASK)
1096	{
1097	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
1098	}
1099	else
1100	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1101	#endif
1102
1103	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1104	*/
1105	ResumeExecution:
1106	/* Safety precaution; looping for too long here can have a very bad effect on the host */
1107	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1108	{
1109	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1110	rc = VINF_EM_RAW_INTERRUPT;
1111	goto end;
1112	}
1113
1114	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1115	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1116	{
1117	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1118	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1119	{
1120	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1121	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1122	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1123	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1124	*/
1125	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1126	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1127	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1128	AssertRC(rc);
1129	}
1130	}
1131	else
1132	{
1133	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1134	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1135	AssertRC(rc);
1136	}
1137
1138	/* Check for pending actions that force us to go back to ring 3. */
1139	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
1140	{
1141	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1142	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1143	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1144	rc = VINF_EM_RAW_TO_R3;
1145	goto end;
1146	}
1147	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1148	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1149	{
1150	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1151	rc = VINF_EM_PENDING_REQUEST;
1152	goto end;
1153	}
1154
1155	/* When external interrupts are pending, we should exit the VM when IF is set. */
1156	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
1157	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1158	if (VBOX_FAILURE(rc))
1159	{
1160	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1161	goto end;
1162	}
1163
1164	/** @todo check timers?? */
1165
1166	/* Save the host state first. */
1167	rc = VMXR0SaveHostState(pVM);
1168	if (rc != VINF_SUCCESS)
1169	{
1170	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1171	goto end;
1172	}
1173	/* Load the guest state */
1174	rc = VMXR0LoadGuestState(pVM, pCtx);
1175	if (rc != VINF_SUCCESS)
1176	{
1177	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1178	goto end;
1179	}
1180	fGuestStateSynced = true;
1181
1182	/* TPR caching using CR8 is only available in 64 bits mode */
1183	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1184	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock). */
1185	/*
1186	* @todo reduce overhead
1187	*/
1188	if ( pCtx->msrEFER & MSR_K6_EFER_LMA
1189	&& pVM->hwaccm.s.vmx.pAPIC)
1190	{
1191	/* TPR caching in CR8 */
1192	uint8_t u8TPR;
1193	int rc = PDMApicGetTPR(pVM, &u8TPR);
1194	AssertRC(rc);
1195	/* The TPR can be found at offset 0x80 in the APIC mmio page. */
1196	pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1197
1198	/* CR8 updates that lower the TPR value to below the current value should cause an exit. */
1199	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, u8TPR);
1200	AssertRC(rc);
1201	}
1202
1203	/* Non-register state Guest Context */
1204	/** @todo change me according to cpu state */
1205	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1206	AssertRC(rc);
1207
1208	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1209
1210	/* Manual save and restore:
1211	* - General purpose registers except RIP, RSP
1212	*
1213	* Trashed:
1214	* - CR2 (we don't care)
1215	* - LDTR (reset to 0)
1216	* - DRx (presumably not changed at all)
1217	* - DR7 (reset to 0x400)
1218	* - EFLAGS (reset to RT_BIT(1); not relevant)
1219	*
1220	*/
1221
1222	/* All done! Let's start VM execution. */
1223	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1224	rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1225
1226	/* In case we execute a goto ResumeExecution later on. */
1227	pVM->hwaccm.s.vmx.fResumeVM = true;
1228
1229	/**
1230	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1231	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1232	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1233	*/
1234
1235	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1236	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1237
1238	switch (rc)
1239	{
1240	case VINF_SUCCESS:
1241	break;
1242
1243	case VERR_VMX_INVALID_VMXON_PTR:
1244	AssertFailed();
1245	goto end;
1246
1247	case VERR_VMX_UNABLE_TO_START_VM:
1248	case VERR_VMX_UNABLE_TO_RESUME_VM:
1249	{
1250	#ifdef VBOX_STRICT
1251	int rc1;
1252
1253	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1254	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1255	AssertRC(rc1);
1256	if (rc1 == VINF_SUCCESS)
1257	{
1258	RTGDTR gdtr;
1259	PX86DESCHC pDesc;
1260
1261	ASMGetGDTR(&gdtr);
1262
1263	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1264	Log(("Current stack %08x\n", &rc1));
1265
1266
1267	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1268	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1269	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1270	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1271	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1272	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1273	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1274	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1275	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1276	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1277
1278	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1279	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1280
1281	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1282	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1283
1284	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1285	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1286
1287	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1288	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1289	if (val < gdtr.cbGdt)
1290	{
1291	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1292	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1293	}
1294
1295	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1296	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1297	if (val < gdtr.cbGdt)
1298	{
1299	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1300	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1301	}
1302
1303	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1304	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1305	if (val < gdtr.cbGdt)
1306	{
1307	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1308	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1309	}
1310
1311	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1312	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1313	if (val < gdtr.cbGdt)
1314	{
1315	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1316	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1317	}
1318
1319	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1320	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1321	if (val < gdtr.cbGdt)
1322	{
1323	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1324	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1325	}
1326
1327	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1328	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1329	if (val < gdtr.cbGdt)
1330	{
1331	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1332	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1333	}
1334
1335	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1336	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1337	if (val < gdtr.cbGdt)
1338	{
1339	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1340	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1341	}
1342
1343	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1344	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1345
1346	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1347	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1348	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1349	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1350
1351	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1352	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1353
1354	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1355	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1356
1357	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1358	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1359
1360	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1361	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1362	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1363	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1364
1365	#if HC_ARCH_BITS == 64
1366	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1367	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1368	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1369	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1370	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1371	#endif
1372	}
1373	#endif /* VBOX_STRICT */
1374	goto end;
1375	}
1376
1377	default:
1378	/* impossible */
1379	AssertFailed();
1380	goto end;
1381	}
1382	/* Success. Query the guest state and figure out what has happened. */
1383
1384	/* Investigate why there was a VM-exit. */
1385	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1386	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1387
1388	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1389	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1390	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1391	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1392	intInfo = val;
1393	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1394	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1395	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1396	instrInfo = val;
1397	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1398	exitQualification = val;
1399	AssertRC(rc);
1400
1401	/* Let's first sync back eip, esp, and eflags. */
1402	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1403	AssertRC(rc);
1404	pCtx->rip = val;
1405	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1406	AssertRC(rc);
1407	pCtx->rsp = val;
1408	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1409	AssertRC(rc);
1410	pCtx->eflags.u32 = val;
1411
1412	/* Update the APIC with the cached TPR value.
1413	* @todo reduce overhead
1414	*/
1415	if ( pCtx->msrEFER & MSR_K6_EFER_LMA
1416	&& pVM->hwaccm.s.vmx.pAPIC)
1417	{
1418	rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1419	AssertRC(rc);
1420	}
1421
1422	/* Take care of instruction fusing (sti, mov ss) */
1423	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1424	uInterruptState = val;
1425	if (uInterruptState != 0)
1426	{
1427	Assert(uInterruptState <= 2); /* only sti & mov ss */
1428	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1429	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1430	}
1431	else
1432	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1433
1434	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1435	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1436	{
1437	/* Hide our emulation flags */
1438	pCtx->eflags.Bits.u1VM = 0;
1439	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1440	pCtx->eflags.Bits.u1VIF = 0;
1441	pCtx->eflags.Bits.u2IOPL = 0;
1442	}
1443
1444	/* Control registers. */
1445	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1446	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1447	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1448	CPUMSetGuestCR0(pVM, val);
1449
1450	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1451	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1452	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1453	CPUMSetGuestCR4(pVM, val);
1454
1455	CPUMSetGuestCR2(pVM, ASMGetCR2());
1456
1457	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1458	CPUMSetGuestDR7(pVM, val);
1459
1460	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1461	VMX_READ_SELREG(ES, es);
1462	VMX_READ_SELREG(SS, ss);
1463	VMX_READ_SELREG(CS, cs);
1464	VMX_READ_SELREG(DS, ds);
1465	VMX_READ_SELREG(FS, fs);
1466	VMX_READ_SELREG(GS, gs);
1467
1468	/** @note NOW IT'S SAFE FOR LOGGING! */
1469	Log2(("Raw exit reason %08x\n", exitReason));
1470
1471	/* Check if an injected event was interrupted prematurely. */
1472	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1473	AssertRC(rc);
1474	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1475	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1476	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1477	{
1478	pVM->hwaccm.s.Event.fPending = true;
1479	/* Error code present? */
1480	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1481	{
1482	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1483	AssertRC(rc);
1484	pVM->hwaccm.s.Event.errCode = val;
1485	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1486	}
1487	else
1488	{
1489	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1490	pVM->hwaccm.s.Event.errCode = 0;
1491	}
1492	}
1493
1494	#ifdef VBOX_STRICT
1495	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1496	HWACCMDumpRegs(pCtx);
1497	#endif
1498
1499	Log2(("E%d", exitReason));
1500	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1501	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1502	Log2(("Interruption error code %d\n", errCode));
1503	Log2(("IntInfo = %08x\n", intInfo));
1504	Log2(("New EIP=%VGv\n", pCtx->rip));
1505
1506	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1507	switch (exitReason)
1508	{
1509	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1510	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1511	{
1512	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1513
1514	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1515	{
1516	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1517	/* External interrupt; leave to allow it to be dispatched again. */
1518	rc = VINF_EM_RAW_INTERRUPT;
1519	break;
1520	}
1521	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1522	{
1523	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1524	/* External interrupt; leave to allow it to be dispatched again. */
1525	rc = VINF_EM_RAW_INTERRUPT;
1526	break;
1527
1528	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1529	AssertFailed(); /* can't come here; fails the first check. */
1530	break;
1531
1532	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1533	Assert(vector == 3 \|\| vector == 4);
1534	/* no break */
1535	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1536	Log2(("Hardware/software interrupt %d\n", vector));
1537	switch (vector)
1538	{
1539	case X86_XCPT_NM:
1540	{
1541	uint32_t oldCR0;
1542
1543	Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1544
1545	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1546	oldCR0 = ASMGetCR0();
1547	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1548	rc = CPUMHandleLazyFPU(pVM);
1549	if (rc == VINF_SUCCESS)
1550	{
1551	Assert(CPUMIsGuestFPUStateActive(pVM));
1552
1553	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1554	ASMSetCR0(oldCR0);
1555
1556	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1557
1558	/* Continue execution. */
1559	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1560	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1561
1562	goto ResumeExecution;
1563	}
1564
1565	Log(("Forward #NM fault to the guest\n"));
1566	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1567	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1568	AssertRC(rc);
1569	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1570	goto ResumeExecution;
1571	}
1572
1573	case X86_XCPT_PF: /* Page fault */
1574	{
1575	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1576	/* Exit qualification contains the linear address of the page fault. */
1577	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1578	TRPMSetErrorCode(pVM, errCode);
1579	TRPMSetFaultAddress(pVM, exitQualification);
1580
1581	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1582	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1583	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1584	if (rc == VINF_SUCCESS)
1585	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1586	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1587	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1588
1589	TRPMResetTrap(pVM);
1590
1591	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1592	goto ResumeExecution;
1593	}
1594	else
1595	if (rc == VINF_EM_RAW_GUEST_TRAP)
1596	{ /* A genuine pagefault.
1597	* Forward the trap to the guest by injecting the exception and resuming execution.
1598	*/
1599	Log2(("Forward page fault to the guest\n"));
1600	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1601	/* The error code might have been changed. */
1602	errCode = TRPMGetErrorCode(pVM);
1603
1604	TRPMResetTrap(pVM);
1605
1606	/* Now we must update CR2. */
1607	pCtx->cr2 = exitQualification;
1608	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1609	AssertRC(rc);
1610
1611	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1612	goto ResumeExecution;
1613	}
1614	#ifdef VBOX_STRICT
1615	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1616	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1617	#endif
1618	/* Need to go back to the recompiler to emulate the instruction. */
1619	TRPMResetTrap(pVM);
1620	break;
1621	}
1622
1623	case X86_XCPT_MF: /* Floating point exception. */
1624	{
1625	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1626	if (!(pCtx->cr0 & X86_CR0_NE))
1627	{
1628	/* old style FPU error reporting needs some extra work. */
1629	/** @todo don't fall back to the recompiler, but do it manually. */
1630	rc = VINF_EM_RAW_EMULATE_INSTR;
1631	break;
1632	}
1633	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1634	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1635	AssertRC(rc);
1636
1637	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1638	goto ResumeExecution;
1639	}
1640
1641	#ifdef VBOX_STRICT
1642	case X86_XCPT_GP: /* General protection failure exception.*/
1643	case X86_XCPT_UD: /* Unknown opcode exception. */
1644	case X86_XCPT_DE: /* Debug exception. */
1645	case X86_XCPT_SS: /* Stack segment exception. */
1646	case X86_XCPT_NP: /* Segment not present exception. */
1647	{
1648	switch(vector)
1649	{
1650	case X86_XCPT_DE:
1651	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1652	break;
1653	case X86_XCPT_UD:
1654	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1655	break;
1656	case X86_XCPT_SS:
1657	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1658	break;
1659	case X86_XCPT_NP:
1660	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1661	break;
1662	case X86_XCPT_GP:
1663	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1664	break;
1665	}
1666
1667	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1668	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1669	AssertRC(rc);
1670
1671	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1672	goto ResumeExecution;
1673	}
1674	#endif
1675	default:
1676	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1677	rc = VERR_EM_INTERNAL_ERROR;
1678	break;
1679	} /* switch (vector) */
1680
1681	break;
1682
1683	default:
1684	rc = VERR_EM_INTERNAL_ERROR;
1685	AssertFailed();
1686	break;
1687	}
1688
1689	break;
1690	}
1691
1692	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1693	/* Clear VM-exit on IF=1 change. */
1694	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1695	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1696	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1697	AssertRC(rc);
1698	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1699	goto ResumeExecution; /* we check for pending guest interrupts there */
1700
1701	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1702	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1703	/* Skip instruction and continue directly. */
1704	pCtx->rip += cbInstr;
1705	/* Continue execution.*/
1706	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1707	goto ResumeExecution;
1708
1709	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1710	{
1711	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1712	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1713	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1714	if (rc == VINF_SUCCESS)
1715	{
1716	/* Update EIP and continue execution. */
1717	Assert(cbInstr == 2);
1718	pCtx->rip += cbInstr;
1719	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1720	goto ResumeExecution;
1721	}
1722	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1723	rc = VINF_EM_RAW_EMULATE_INSTR;
1724	break;
1725	}
1726
1727	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1728	{
1729	Log2(("VMX: Rdtsc\n"));
1730	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1731	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1732	if (rc == VINF_SUCCESS)
1733	{
1734	/* Update EIP and continue execution. */
1735	Assert(cbInstr == 2);
1736	pCtx->rip += cbInstr;
1737	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1738	goto ResumeExecution;
1739	}
1740	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1741	rc = VINF_EM_RAW_EMULATE_INSTR;
1742	break;
1743	}
1744
1745	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1746	{
1747	Log2(("VMX: invlpg\n"));
1748	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1749	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1750	if (rc == VINF_SUCCESS)
1751	{
1752	/* Update EIP and continue execution. */
1753	pCtx->rip += cbInstr;
1754	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1755	goto ResumeExecution;
1756	}
1757	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1758	break;
1759	}
1760
1761	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1762	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1763	{
1764	uint32_t cbSize;
1765
1766	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1767	Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1768	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1769	if (rc == VINF_SUCCESS)
1770	{
1771	/* EIP has been updated already. */
1772
1773	/* Only resume if successful. */
1774	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1775	goto ResumeExecution;
1776	}
1777	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1778	break;
1779	}
1780
1781	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1782	{
1783	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1784	{
1785	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1786	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1787	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1788	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1789	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1790	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1791
1792	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1793	{
1794	case 0:
1795	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1796	break;
1797	case 2:
1798	break;
1799	case 3:
1800	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1801	break;
1802	case 4:
1803	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1804	break;
1805	case 8:
1806	/* CR8 contains the APIC TPR */
1807	Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1808	break;
1809
1810	default:
1811	AssertFailed();
1812	break;
1813	}
1814	/* Check if a sync operation is pending. */
1815	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1816	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1817	{
1818	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1819	AssertRC(rc);
1820	}
1821	break;
1822
1823	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1824	Log2(("VMX: mov x, crx\n"));
1825	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1826
1827	/* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1828	Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 \|\| !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1829
1830	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1831	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1832	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1833	break;
1834
1835	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1836	Log2(("VMX: clts\n"));
1837	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1838	rc = EMInterpretCLTS(pVM);
1839	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1840	break;
1841
1842	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1843	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1844	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1845	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1846	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1847	break;
1848	}
1849
1850	/* Update EIP if no error occurred. */
1851	if (VBOX_SUCCESS(rc))
1852	pCtx->rip += cbInstr;
1853
1854	if (rc == VINF_SUCCESS)
1855	{
1856	/* Only resume if successful. */
1857	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1858	goto ResumeExecution;
1859	}
1860	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1861	break;
1862	}
1863
1864	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1865	{
1866	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1867	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1868	{
1869	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1870	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1871	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1872	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1873	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1874	Log2(("DR7=%08x\n", pCtx->dr7));
1875	}
1876	else
1877	{
1878	Log2(("VMX: mov x, drx\n"));
1879	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1880	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1881	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1882	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1883	}
1884	/* Update EIP if no error occurred. */
1885	if (VBOX_SUCCESS(rc))
1886	pCtx->rip += cbInstr;
1887
1888	if (rc == VINF_SUCCESS)
1889	{
1890	/* Only resume if successful. */
1891	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1892	goto ResumeExecution;
1893	}
1894	Assert(rc == VERR_EM_INTERPRETER);
1895	break;
1896	}
1897
1898	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1899	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1900	{
1901	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1902	uint32_t uPort;
1903	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1904
1905	/** @todo necessary to make the distinction? */
1906	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1907	{
1908	uPort = pCtx->edx & 0xffff;
1909	}
1910	else
1911	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1912
1913	/* paranoia */
1914	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1915	{
1916	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1917	break;
1918	}
1919
1920	uint32_t cbSize = aIOSize[uIOWidth];
1921
1922	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1923	{
1924	/* ins/outs */
1925	uint32_t prefix = 0;
1926	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1927	prefix \|= PREFIX_REP;
1928
1929	if (fIOWrite)
1930	{
1931	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1932	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1933	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1934	}
1935	else
1936	{
1937	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1938	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1939	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1940	}
1941	}
1942	else
1943	{
1944	/* normal in/out */
1945	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1946
1947	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1948
1949	if (fIOWrite)
1950	{
1951	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1952	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1953	}
1954	else
1955	{
1956	uint32_t u32Val = 0;
1957
1958	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1959	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1960	if (IOM_SUCCESS(rc))
1961	{
1962	/* Write back to the EAX register. */
1963	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1964	}
1965	}
1966	}
1967	/*
1968	* Handled the I/O return codes.
1969	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1970	*/
1971	if (IOM_SUCCESS(rc))
1972	{
1973	/* Update EIP and continue execution. */
1974	pCtx->rip += cbInstr;
1975	if (RT_LIKELY(rc == VINF_SUCCESS))
1976	{
1977	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1978	goto ResumeExecution;
1979	}
1980	break;
1981	}
1982
1983	#ifdef VBOX_STRICT
1984	if (rc == VINF_IOM_HC_IOPORT_READ)
1985	Assert(!fIOWrite);
1986	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1987	Assert(fIOWrite);
1988	else
1989	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1990	#endif
1991	break;
1992	}
1993
1994	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1995	LogFlow(("VMX_EXIT_TPR\n"));
1996	/* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
1997	goto ResumeExecution;
1998
1999	default:
2000	/* The rest is handled after syncing the entire CPU state. */
2001	break;
2002	}
2003
2004	/* Note: the guest state isn't entirely synced back at this stage. */
2005
2006	/* Investigate why there was a VM-exit. (part 2) */
2007	switch (exitReason)
2008	{
2009	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2010	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2011	/* Already handled above. */
2012	break;
2013
2014	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2015	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2016	break;
2017
2018	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2019	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2020	rc = VINF_EM_RAW_INTERRUPT;
2021	AssertFailed(); /* Can't happen. Yet. */
2022	break;
2023
2024	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2025	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2026	rc = VINF_EM_RAW_INTERRUPT;
2027	AssertFailed(); /* Can't happen afaik. */
2028	break;
2029
2030	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2031	rc = VERR_EM_INTERPRETER;
2032	break;
2033
2034	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2035	/** Check if external interrupts are pending; if so, don't switch back. */
2036	if ( pCtx->eflags.Bits.u1IF
2037	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
2038	{
2039	pCtx->rip++; /* skip hlt */
2040	goto ResumeExecution;
2041	}
2042
2043	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
2044	break;
2045
2046	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2047	AssertFailed(); /* can't happen. */
2048	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2049	break;
2050
2051	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2052	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2053	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2054	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2055	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2056	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2057	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2058	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2059	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2060	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2061	/** @todo inject #UD immediately */
2062	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2063	break;
2064
2065	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2066	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2067	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2068	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2069	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2070	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2071	/* already handled above */
2072	AssertMsg( rc == VINF_PGM_CHANGE_MODE
2073	\|\| rc == VINF_EM_RAW_INTERRUPT
2074	\|\| rc == VERR_EM_INTERPRETER
2075	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
2076	\|\| rc == VINF_PGM_SYNC_CR3
2077	\|\| rc == VINF_IOM_HC_IOPORT_READ
2078	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2079	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2080	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
2081	\|\| rc == VINF_EM_RESCHEDULE_REM,
2082	("rc = %d\n", rc));
2083	break;
2084
2085	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2086	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2087	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2088	/* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2089	rc = VERR_EM_INTERPRETER;
2090	break;
2091
2092	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2093	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2094	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2095	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2096	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2097	break;
2098
2099	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2100	Assert(rc == VINF_EM_RAW_INTERRUPT);
2101	break;
2102
2103	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2104	{
2105	#ifdef VBOX_STRICT
2106	Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2107
2108	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2109	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2110
2111	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2112	Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2113
2114	VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2115	Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2116
2117	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2118	Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2119
2120	VMX_LOG_SELREG(CS, "CS");
2121	VMX_LOG_SELREG(DS, "DS");
2122	VMX_LOG_SELREG(ES, "ES");
2123	VMX_LOG_SELREG(FS, "FS");
2124	VMX_LOG_SELREG(GS, "GS");
2125	VMX_LOG_SELREG(SS, "SS");
2126	VMX_LOG_SELREG(TR, "TR");
2127	VMX_LOG_SELREG(LDTR, "LDTR");
2128
2129	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2130	Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2131	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2132	Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2133	#endif /* VBOX_STRICT */
2134	rc = VERR_EM_INTERNAL_ERROR;
2135	break;
2136	}
2137
2138	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2139	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2140	default:
2141	rc = VERR_EM_INTERNAL_ERROR;
2142	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2143	break;
2144
2145	}
2146	end:
2147	if (fGuestStateSynced)
2148	{
2149	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2150	VMX_READ_SELREG(LDTR, ldtr);
2151	VMX_READ_SELREG(TR, tr);
2152
2153	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2154	pCtx->gdtr.cbGdt = val;
2155	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2156	pCtx->gdtr.pGdt = val;
2157
2158	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2159	pCtx->idtr.cbIdt = val;
2160	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2161	pCtx->idtr.pIdt = val;
2162
2163	/*
2164	* System MSRs
2165	*/
2166	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
2167	pCtx->SysEnter.cs = val;
2168	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
2169	pCtx->SysEnter.eip = val;
2170	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
2171	pCtx->SysEnter.esp = val;
2172	}
2173
2174	/* Signal changes for the recompiler. */
2175	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2176
2177	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2178	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2179	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2180	{
2181	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2182	/* On the next entry we'll only sync the host context. */
2183	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2184	}
2185	else
2186	{
2187	/* On the next entry we'll sync everything. */
2188	/** @todo we can do better than this */
2189	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2190	}
2191
2192	/* translate into a less severe return code */
2193	if (rc == VERR_EM_INTERPRETER)
2194	rc = VINF_EM_RAW_EMULATE_INSTR;
2195
2196	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2197	Log2(("X"));
2198	return rc;
2199	}
2200
2201
2202	/**
2203	* Enters the VT-x session
2204	*
2205	* @returns VBox status code.
2206	* @param pVM The VM to operate on.
2207	* @param pCpu CPU info struct
2208	*/
2209	HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2210	{
2211	Assert(pVM->hwaccm.s.vmx.fSupported);
2212
2213	unsigned cr4 = ASMGetCR4();
2214	if (!(cr4 & X86_CR4_VMXE))
2215	{
2216	AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2217	return VERR_VMX_X86_CR4_VMXE_CLEARED;
2218	}
2219
2220	/* Activate the VM Control Structure. */
2221	int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2222	if (VBOX_FAILURE(rc))
2223	return rc;
2224
2225	pVM->hwaccm.s.vmx.fResumeVM = false;
2226	return VINF_SUCCESS;
2227	}
2228
2229
2230	/**
2231	* Leaves the VT-x session
2232	*
2233	* @returns VBox status code.
2234	* @param pVM The VM to operate on.
2235	*/
2236	HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2237	{
2238	Assert(pVM->hwaccm.s.vmx.fSupported);
2239
2240	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2241	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2242	AssertRC(rc);
2243
2244	return VINF_SUCCESS;
2245	}
2246

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 10507

Download in other formats: