HWVMXR0.cpp@ 10832

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1	/* $Id: HWVMXR0.cpp 10832 2008-07-23 14:18:23Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/string.h>
41	#include "HWVMXR0.h"
42
43
44	/* IO operation lookup arrays. */
45	static uint32_t aIOSize[4] = {1, 2, 0, 4};
46	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49	static void VMXR0CheckError(PVM pVM, int rc)
50	{
51	if (rc == VERR_VMX_GENERIC)
52	{
53	RTCCUINTREG instrError;
54
55	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57	}
58	pVM->hwaccm.s.lLastError = rc;
59	}
60
61	/**
62	* Sets up and activates VT-x on the current CPU
63	*
64	* @returns VBox status code.
65	* @param pCpu CPU info struct
66	* @param pVM The VM to operate on.
67	* @param pvPageCpu Pointer to the global cpu page
68	* @param pPageCpuPhys Physical address of the global cpu page
69	*/
70	HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71	{
72	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73	AssertReturn(pVM, VERR_INVALID_PARAMETER);
74	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76	/* Setup Intel VMX. */
77	Assert(pVM->hwaccm.s.vmx.fSupported);
78
79	#ifdef LOG_ENABLED
80	SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81	#endif
82	/* Set revision dword at the beginning of the VMXON structure. */
83	(uint32_t )pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86	* (which can have very bad consequences!!!)
87	*/
88
89	/* Make sure the VMX instructions don't cause #UD faults. */
90	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
91
92	/* Enter VMX Root Mode */
93	int rc = VMXEnable(pPageCpuPhys);
94	if (VBOX_FAILURE(rc))
95	{
96	VMXR0CheckError(pVM, rc);
97	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98	return VERR_VMX_VMXON_FAILED;
99	}
100	return VINF_SUCCESS;
101	}
102
103	/**
104	* Deactivates VT-x on the current CPU
105	*
106	* @returns VBox status code.
107	* @param pCpu CPU info struct
108	* @param pvPageCpu Pointer to the global cpu page
109	* @param pPageCpuPhys Physical address of the global cpu page
110	*/
111	HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112	{
113	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116	/* Leave VMX Root Mode. */
117	VMXDisable();
118
119	/* And clear the X86_CR4_VMXE bit */
120	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122	#ifdef LOG_ENABLED
123	SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124	#endif
125	return VINF_SUCCESS;
126	}
127
128	/**
129	* Does Ring-0 per VM VT-x init.
130	*
131	* @returns VBox status code.
132	* @param pVM The VM to operate on.
133	*/
134	HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135	{
136	int rc;
137
138	#ifdef LOG_ENABLED
139	SUPR0Printf("VMXR0InitVM %x\n", pVM);
140	#endif
141	pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
142	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
143	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
144
145
146	/* Allocate one page for the VM control structure (VMCS). */
147	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
148	AssertRC(rc);
149	if (RT_FAILURE(rc))
150	return rc;
151
152	pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
153	pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
154	ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
155
156	/* Allocate one page for the TSS we need for real mode emulation. */
157	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
158	AssertRC(rc);
159	if (RT_FAILURE(rc))
160	return rc;
161
162	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
163	pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
164
165	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
166	* for I/O operations. */
167	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
168	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
169	/* Bit set to 0 means redirection enabled. */
170	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
171
172	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
173	{
174	/* Allocate one page for the virtual APIC mmio cache. */
175	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
176	AssertRC(rc);
177	if (RT_FAILURE(rc))
178	return rc;
179
180	pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
181	pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
182	ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
183	}
184	else
185	{
186	pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
187	pVM->hwaccm.s.vmx.pAPIC = 0;
188	pVM->hwaccm.s.vmx.pAPICPhys = 0;
189	}
190
191	#ifdef LOG_ENABLED
192	SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
193	#endif
194	return VINF_SUCCESS;
195	}
196
197	/**
198	* Does Ring-0 per VM VT-x termination.
199	*
200	* @returns VBox status code.
201	* @param pVM The VM to operate on.
202	*/
203	HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
204	{
205	if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
206	{
207	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
208	pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
209	pVM->hwaccm.s.vmx.pVMCS = 0;
210	pVM->hwaccm.s.vmx.pVMCSPhys = 0;
211	}
212	if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS != NIL_RTR0MEMOBJ)
213	{
214	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
215	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
216	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
217	pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
218	}
219	if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
220	{
221	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
222	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
223	pVM->hwaccm.s.vmx.pAPIC = 0;
224	pVM->hwaccm.s.vmx.pAPICPhys = 0;
225	}
226	return VINF_SUCCESS;
227	}
228
229	/**
230	* Sets up VT-x for the specified VM
231	*
232	* @returns VBox status code.
233	* @param pVM The VM to operate on.
234	*/
235	HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
236	{
237	int rc = VINF_SUCCESS;
238	uint32_t val;
239
240	AssertReturn(pVM, VERR_INVALID_PARAMETER);
241	Assert(pVM->hwaccm.s.vmx.pVMCS);
242
243	/* Set revision dword at the beginning of the VMCS structure. */
244	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
245
246	/* Clear VM Control Structure. */
247	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
248	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
249	if (VBOX_FAILURE(rc))
250	goto vmx_end;
251
252	/* Activate the VM Control Structure. */
253	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
254	if (VBOX_FAILURE(rc))
255	goto vmx_end;
256
257	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
258	* Set required bits to one and zero according to the MSR capabilities.
259	*/
260	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
261	/* External and non-maskable interrupts cause VM-exits. */
262	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
263	val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
264
265	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
266	AssertRC(rc);
267
268	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
269	* Set required bits to one and zero according to the MSR capabilities.
270	*/
271	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
272	/* Program which event cause VM-exits and which features we want to use. */
273	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
274	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
275	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
276	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
277	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
278	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
279
280	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
281
282	/* Mask away the bits that the CPU doesn't support */
283	/** @todo make sure they don't conflict with the above requirements. */
284	val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
285	pVM->hwaccm.s.vmx.proc_ctls = val;
286
287	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
288	AssertRC(rc);
289
290	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
291	* Set required bits to one and zero according to the MSR capabilities.
292	*/
293	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
294	AssertRC(rc);
295
296	/* VMX_VMCS_CTRL_EXIT_CONTROLS
297	* Set required bits to one and zero according to the MSR capabilities.
298	*/
299	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
300	#if HC_ARCH_BITS == 64
301	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
302	#else
303	/* else Must be zero when AMD64 is not available. */
304	#endif
305	val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
306	/* Don't acknowledge external interrupts on VM-exit. */
307	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
308	AssertRC(rc);
309
310	/* Forward all exception except #NM & #PF to the guest.
311	* We always need to check pagefaults since our shadow page table can be out of sync.
312	* And we always lazily sync the FPU & XMM state.
313	*/
314
315	/*
316	* @todo Possible optimization:
317	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
318	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
319	* registers ourselves of course.
320	*
321	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
322	*/
323	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
324	AssertRC(rc);
325
326	/* Don't filter page faults; all of them should cause a switch. */
327	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
328	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
329	AssertRC(rc);
330
331	/* Init TSC offset to zero. */
332	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
333	#if HC_ARCH_BITS == 32
334	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
335	#endif
336	AssertRC(rc);
337
338	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
339	#if HC_ARCH_BITS == 32
340	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
341	#endif
342	AssertRC(rc);
343
344	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
345	#if HC_ARCH_BITS == 32
346	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
347	#endif
348	AssertRC(rc);
349
350	/* Clear MSR controls. */
351	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
352	{
353	/* Optional */
354	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
355	#if HC_ARCH_BITS == 32
356	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
357	#endif
358	AssertRC(rc);
359	}
360	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
361	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
362	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
363	#if HC_ARCH_BITS == 32
364	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
365	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
366	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
367	#endif
368	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
369	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
370	AssertRC(rc);
371
372	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
373	{
374	Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
375	/* Optional */
376	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
377	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
378	#if HC_ARCH_BITS == 32
379	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
380	#endif
381	AssertRC(rc);
382	}
383
384	/* Set link pointer to -1. Not currently used. */
385	#if HC_ARCH_BITS == 32
386	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
387	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
388	#else
389	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
390	#endif
391	AssertRC(rc);
392
393	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
394	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
395	AssertRC(rc);
396
397	vmx_end:
398	VMXR0CheckError(pVM, rc);
399	return rc;
400	}
401
402
403	/**
404	* Injects an event (trap or external interrupt)
405	*
406	* @returns VBox status code.
407	* @param pVM The VM to operate on.
408	* @param pCtx CPU Context
409	* @param intInfo VMX interrupt info
410	* @param cbInstr Opcode length of faulting instruction
411	* @param errCode Error code (optional)
412	*/
413	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
414	{
415	int rc;
416
417	#ifdef VBOX_STRICT
418	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
419	if (iGate == 0xE)
420	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
421	else
422	if (iGate < 0x20)
423	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
424	else
425	{
426	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
427	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
428	Assert(pCtx->eflags.u32 & X86_EFL_IF);
429	}
430	#endif
431
432	/* Set event injection state. */
433	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
434	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
435	);
436
437	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
438	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
439
440	AssertRC(rc);
441	return rc;
442	}
443
444
445	/**
446	* Checks for pending guest interrupts and injects them
447	*
448	* @returns VBox status code.
449	* @param pVM The VM to operate on.
450	* @param pCtx CPU Context
451	*/
452	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
453	{
454	int rc;
455
456	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
457	if (pVM->hwaccm.s.Event.fPending)
458	{
459	Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
460	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
461	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
462	AssertRC(rc);
463
464	pVM->hwaccm.s.Event.fPending = false;
465	return VINF_SUCCESS;
466	}
467
468	/* When external interrupts are pending, we should exit the VM when IF is set. */
469	if ( !TRPMHasTrap(pVM)
470	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
471	{
472	if (!(pCtx->eflags.u32 & X86_EFL_IF))
473	{
474	Log2(("Enable irq window exit!\n"));
475	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
476	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
477	AssertRC(rc);
478	}
479	else
480	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
481	{
482	uint8_t u8Interrupt;
483
484	rc = PDMGetInterrupt(pVM, &u8Interrupt);
485	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
486	if (VBOX_SUCCESS(rc))
487	{
488	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
489	AssertRC(rc);
490	}
491	else
492	{
493	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
494	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
495	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
496	/* Just continue */
497	}
498	}
499	else
500	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
501	}
502
503	#ifdef VBOX_STRICT
504	if (TRPMHasTrap(pVM))
505	{
506	uint8_t u8Vector;
507	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
508	AssertRC(rc);
509	}
510	#endif
511
512	if ( pCtx->eflags.u32 & X86_EFL_IF
513	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
514	&& TRPMHasTrap(pVM)
515	)
516	{
517	uint8_t u8Vector;
518	int rc;
519	TRPMEVENT enmType;
520	RTGCUINTPTR intInfo;
521	RTGCUINT errCode;
522
523	/* If a new event is pending, then dispatch it now. */
524	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
525	AssertRC(rc);
526	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
527	Assert(enmType != TRPM_SOFTWARE_INT);
528
529	/* Clear the pending trap. */
530	rc = TRPMResetTrap(pVM);
531	AssertRC(rc);
532
533	intInfo = u8Vector;
534	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
535
536	if (enmType == TRPM_TRAP)
537	{
538	switch (u8Vector) {
539	case 8:
540	case 10:
541	case 11:
542	case 12:
543	case 13:
544	case 14:
545	case 17:
546	/* Valid error codes. */
547	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
548	break;
549	default:
550	break;
551	}
552	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
553	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
554	else
555	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
556	}
557	else
558	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
559
560	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
561	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
562	AssertRC(rc);
563	} /* if (interrupts can be dispatched) */
564
565	return VINF_SUCCESS;
566	}
567
568	/**
569	* Save the host state
570	*
571	* @returns VBox status code.
572	* @param pVM The VM to operate on.
573	*/
574	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
575	{
576	int rc = VINF_SUCCESS;
577
578	/*
579	* Host CPU Context
580	*/
581	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
582	{
583	RTIDTR idtr;
584	RTGDTR gdtr;
585	RTSEL SelTR;
586	PX86DESCHC pDesc;
587	uintptr_t trBase;
588
589	/* Control registers */
590	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
591	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
592	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
593	AssertRC(rc);
594	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
595	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
596	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
597
598	/* Selector registers. */
599	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
600	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
601	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
602	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
603	#if HC_ARCH_BITS == 32
604	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
605	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
606	#endif
607	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
608	SelTR = ASMGetTR();
609	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
610	AssertRC(rc);
611	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
612	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
613	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
614	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
615	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
616	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
617	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
618
619	/* GDTR & IDTR */
620	ASMGetGDTR(&gdtr);
621	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
622	ASMGetIDTR(&idtr);
623	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
624	AssertRC(rc);
625	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
626	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
627
628	/* Save the base address of the TR selector. */
629	if (SelTR > gdtr.cbGdt)
630	{
631	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
632	return VERR_VMX_INVALID_HOST_STATE;
633	}
634
635	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
636	#if HC_ARCH_BITS == 64
637	trBase = X86DESC64_BASE(*pDesc);
638	#else
639	trBase = X86DESC_BASE(*pDesc);
640	#endif
641	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
642	AssertRC(rc);
643	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
644
645	/* FS and GS base. */
646	#if HC_ARCH_BITS == 64
647	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
648	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
649	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
650	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
651	#endif
652	AssertRC(rc);
653
654	/* Sysenter MSRs. */
655	/** @todo expensive!! */
656	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
657	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
658	#if HC_ARCH_BITS == 32
659	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
660	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
661	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
662	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
663	#else
664	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
665	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
666	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
667	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
668	#endif
669	AssertRC(rc);
670
671	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
672	}
673	return rc;
674	}
675
676
677	/**
678	* Loads the guest state
679	*
680	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
681	*
682	* @returns VBox status code.
683	* @param pVM The VM to operate on.
684	* @param pCtx Guest context
685	*/
686	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
687	{
688	int rc = VINF_SUCCESS;
689	RTGCUINTPTR val;
690	X86EFLAGS eflags;
691
692	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
693	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
694	{
695	VMX_WRITE_SELREG(ES, es);
696	AssertRC(rc);
697
698	VMX_WRITE_SELREG(CS, cs);
699	AssertRC(rc);
700
701	VMX_WRITE_SELREG(SS, ss);
702	AssertRC(rc);
703
704	VMX_WRITE_SELREG(DS, ds);
705	AssertRC(rc);
706
707	/* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
708	VMX_WRITE_SELREG(FS, fs);
709	AssertRC(rc);
710
711	VMX_WRITE_SELREG(GS, gs);
712	AssertRC(rc);
713	}
714
715	/* Guest CPU context: LDTR. */
716	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
717	{
718	if (pCtx->ldtr == 0)
719	{
720	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
721	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
722	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
723	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
724	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
725	}
726	else
727	{
728	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
729	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
730	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
731	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
732	}
733	AssertRC(rc);
734	}
735	/* Guest CPU context: TR. */
736	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
737	{
738	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
739
740	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
741	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
742	{
743	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
744	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
745	}
746	else
747	{
748	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
749	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
750	}
751	val = pCtx->trHid.Attr.u;
752
753	/* The TSS selector must be busy. */
754	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
755	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
756	else
757	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
758	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
759
760	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
761	AssertRC(rc);
762	}
763	/* Guest CPU context: GDTR. */
764	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
765	{
766	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
767	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
768	AssertRC(rc);
769	}
770	/* Guest CPU context: IDTR. */
771	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
772	{
773	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
774	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
775	AssertRC(rc);
776	}
777
778	/*
779	* Sysenter MSRs (unconditional)
780	*/
781	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
782	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
783	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
784	AssertRC(rc);
785
786	/* Control registers */
787	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
788	{
789	val = pCtx->cr0;
790	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
791	Log2(("Guest CR0-shadow %08x\n", val));
792	if (CPUMIsGuestFPUStateActive(pVM) == false)
793	{
794	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
795	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
796	}
797	else
798	{
799	/** @todo check if we support the old style mess correctly. */
800	if (!(val & X86_CR0_NE))
801	{
802	Log(("Forcing X86_CR0_NE!!!\n"));
803
804	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
805	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
806	{
807	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| RT_BIT(X86_XCPT_MF));
808	AssertRC(rc);
809	pVM->hwaccm.s.fFPUOldStyleOverride = true;
810	}
811	}
812
813	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
814	}
815	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
816	val \|= X86_CR0_PE \| X86_CR0_PG;
817	/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
818	val \|= X86_CR0_WP;
819
820	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
821	Log2(("Guest CR0 %08x\n", val));
822	/* CR0 flags owned by the host; if the guests attempts to change them, then
823	* the VM will exit.
824	*/
825	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
826	\| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
827	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
828	\| X86_CR0_TS
829	\| X86_CR0_ET
830	\| X86_CR0_NE
831	\| X86_CR0_MP;
832	pVM->hwaccm.s.vmx.cr0_mask = val;
833
834	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
835	Log2(("Guest CR0-mask %08x\n", val));
836	AssertRC(rc);
837	}
838	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
839	{
840	/* CR4 */
841	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
842	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
843	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
844	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
845	switch(pVM->hwaccm.s.enmShadowMode)
846	{
847	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
848	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
849	case PGMMODE_32_BIT: /* 32-bit paging. */
850	break;
851
852	case PGMMODE_PAE: /* PAE paging. */
853	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
854	/** @todo use normal 32 bits paging */
855	val \|= X86_CR4_PAE;
856	break;
857
858	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
859	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
860	#ifdef VBOX_ENABLE_64_BITS_GUESTS
861	break;
862	#else
863	AssertFailed();
864	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
865	#endif
866	default: /* shut up gcc */
867	AssertFailed();
868	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
869	}
870	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
871	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
872	val \|= X86_CR4_VME;
873
874	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
875	Log2(("Guest CR4 %08x\n", val));
876	/* CR4 flags owned by the host; if the guests attempts to change them, then
877	* the VM will exit.
878	*/
879	val = X86_CR4_PAE
880	\| X86_CR4_PGE
881	\| X86_CR4_PSE
882	\| X86_CR4_VMXE;
883	pVM->hwaccm.s.vmx.cr4_mask = val;
884
885	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
886	Log2(("Guest CR4-mask %08x\n", val));
887	AssertRC(rc);
888	}
889
890	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
891	{
892	/* Save our shadow CR3 register. */
893	val = PGMGetHyperCR3(pVM);
894	Assert(val);
895	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
896	AssertRC(rc);
897	}
898
899	/* Debug registers. */
900	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
901	{
902	val = pCtx->dr7 & 0xffffffff; /* upper 32 bits reserved */
903	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
904	val \|= 0x400; /* must be one */
905	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
906	AssertRC(rc);
907
908	/* IA32_DEBUGCTL MSR. */
909	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
910	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
911	AssertRC(rc);
912
913	/** @todo do we really ever need this? */
914	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
915	AssertRC(rc);
916	}
917
918	/* EIP, ESP and EFLAGS */
919	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
920	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
921	AssertRC(rc);
922
923	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
924	eflags = pCtx->eflags;
925	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
926	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
927
928	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
929	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
930	{
931	eflags.Bits.u1VM = 1;
932	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
933	eflags.Bits.u2IOPL = 3;
934	}
935
936	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
937	AssertRC(rc);
938
939	/** TSC offset. */
940	uint64_t u64TSCOffset;
941
942	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
943	{
944	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
945	#if HC_ARCH_BITS == 64
946	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
947	#else
948	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
949	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
950	#endif
951	AssertRC(rc);
952
953	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
954	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
955	AssertRC(rc);
956	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
957	}
958	else
959	{
960	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
961	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
962	AssertRC(rc);
963	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
964	}
965
966	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
967	* Set required bits to one and zero according to the MSR capabilities.
968	*/
969	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
970	/* 64 bits guest mode? */
971	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
972	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
973	/* else Must be zero when AMD64 is not available. */
974
975	/* Mask away the bits that the CPU doesn't support */
976	val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
977	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
978	AssertRC(rc);
979
980	/* 64 bits guest mode? */
981	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
982	{
983	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
984	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
985	#else
986	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
987	#endif
988	/* Unconditionally update these as wrmsr might have changed them. */
989	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
990	AssertRC(rc);
991	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
992	AssertRC(rc);
993
994	#if HC_ARCH_BITS == 64
995	if (!(pVM->hwaccm.s.vmx.proc_ctls & (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)))
996	{
997	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
998	{
999	/* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
1000	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
1001	Assert(pVM->hwaccm.s.vmx.pAPIC);
1002	}
1003	else
1004	/* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
1005	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
1006
1007	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1008	AssertRC(rc);
1009	}
1010	#endif
1011
1012	}
1013	else
1014	{
1015	#if HC_ARCH_BITS == 64
1016	if (pVM->hwaccm.s.vmx.proc_ctls & (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT))
1017	{
1018	pVM->hwaccm.s.vmx.proc_ctls &= ~(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT);
1019
1020	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1021	AssertRC(rc);
1022	}
1023	#endif
1024	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1025	}
1026
1027	/* Done. */
1028	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1029
1030	return rc;
1031	}
1032
1033	/**
1034	* Runs guest code in a VT-x VM.
1035	*
1036	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
1037	*
1038	* @returns VBox status code.
1039	* @param pVM The VM to operate on.
1040	* @param pCtx Guest context
1041	*/
1042	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1043	{
1044	int rc = VINF_SUCCESS;
1045	RTCCUINTREG val, valShadow;
1046	RTCCUINTREG exitReason, instrError, cbInstr;
1047	RTGCUINTPTR exitQualification;
1048	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1049	RTGCUINTPTR errCode, instrInfo, uInterruptState;
1050	bool fGuestStateSynced = false;
1051	bool fSyncTPR = false;
1052	unsigned cResume = 0;
1053	#ifdef VBOX_STRICT
1054	RTCPUID idCpuCheck;
1055	#endif
1056
1057	Log2(("\nE"));
1058
1059	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1060
1061	#ifdef VBOX_STRICT
1062	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1063	AssertRC(rc);
1064	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1065
1066	/* allowed zero */
1067	if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1068	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1069
1070	/* allowed one */
1071	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1072	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1073
1074	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1075	AssertRC(rc);
1076	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1077
1078	/* allowed zero */
1079	if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1080	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1081
1082	/* allowed one */
1083	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1084	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1085
1086	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1087	AssertRC(rc);
1088	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1089
1090	/* allowed zero */
1091	if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1092	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1093
1094	/* allowed one */
1095	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1096	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1097
1098	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1099	AssertRC(rc);
1100	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1101
1102	/* allowed zero */
1103	if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1104	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1105
1106	/* allowed one */
1107	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1108	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1109	#endif
1110
1111	#if 0
1112	/*
1113	* Check if debug registers are armed.
1114	*/
1115	uint32_t u32DR7 = ASMGetDR7();
1116	if (u32DR7 & X86_DR7_ENABLED_MASK)
1117	{
1118	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
1119	}
1120	else
1121	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1122	#endif
1123
1124	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1125	*/
1126	ResumeExecution:
1127	/* Safety precaution; looping for too long here can have a very bad effect on the host */
1128	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1129	{
1130	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1131	rc = VINF_EM_RAW_INTERRUPT;
1132	goto end;
1133	}
1134
1135	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1136	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1137	{
1138	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1139	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1140	{
1141	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1142	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1143	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1144	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1145	*/
1146	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1147	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1148	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1149	AssertRC(rc);
1150	}
1151	}
1152	else
1153	{
1154	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1155	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1156	AssertRC(rc);
1157	}
1158
1159	/* Check for pending actions that force us to go back to ring 3. */
1160	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
1161	{
1162	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1163	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1164	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1165	rc = VINF_EM_RAW_TO_R3;
1166	goto end;
1167	}
1168	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1169	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1170	{
1171	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1172	rc = VINF_EM_PENDING_REQUEST;
1173	goto end;
1174	}
1175
1176	/* When external interrupts are pending, we should exit the VM when IF is set. */
1177	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
1178	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1179	if (VBOX_FAILURE(rc))
1180	{
1181	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1182	goto end;
1183	}
1184
1185	/** @todo check timers?? */
1186
1187	/* TPR caching using CR8 is only available in 64 bits mode */
1188	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1189	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1190	/*
1191	* @todo reduce overhead
1192	*/
1193	if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1194	&& pVM->hwaccm.s.vmx.pAPIC)
1195	{
1196	/* TPR caching in CR8 */
1197	uint8_t u8TPR;
1198	bool fPending;
1199
1200	int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1201	AssertRC(rc);
1202	/* The TPR can be found at offset 0x80 in the APIC mmio page. */
1203	pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1204
1205	/* Two options here:
1206	* - external interrupt pending, but masked by the TPR value.
1207	* -> CR8 updates that lower the TPR value to below the current value should cause an exit
1208	* - no pending interrupts
1209	* -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1210	*/
1211	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1212	AssertRC(rc);
1213
1214	fSyncTPR = !fPending;
1215	}
1216
1217	/*
1218	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1219	* (until the actual world switch)
1220	*/
1221	#ifdef VBOX_STRICT
1222	idCpuCheck = RTMpCpuId();
1223	#endif
1224	/* Save the host state first. */
1225	rc = VMXR0SaveHostState(pVM);
1226	if (rc != VINF_SUCCESS)
1227	{
1228	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1229	goto end;
1230	}
1231	/* Load the guest state */
1232	rc = VMXR0LoadGuestState(pVM, pCtx);
1233	if (rc != VINF_SUCCESS)
1234	{
1235	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1236	goto end;
1237	}
1238	fGuestStateSynced = true;
1239
1240	/* Non-register state Guest Context */
1241	/** @todo change me according to cpu state */
1242	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1243	AssertRC(rc);
1244
1245	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1246
1247	/* Manual save and restore:
1248	* - General purpose registers except RIP, RSP
1249	*
1250	* Trashed:
1251	* - CR2 (we don't care)
1252	* - LDTR (reset to 0)
1253	* - DRx (presumably not changed at all)
1254	* - DR7 (reset to 0x400)
1255	* - EFLAGS (reset to RT_BIT(1); not relevant)
1256	*
1257	*/
1258
1259	/* All done! Let's start VM execution. */
1260	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1261	#ifdef VBOX_STRICT
1262	Assert(idCpuCheck == RTMpCpuId());
1263	#endif
1264	rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1265
1266	/* In case we execute a goto ResumeExecution later on. */
1267	pVM->hwaccm.s.vmx.fResumeVM = true;
1268
1269	/**
1270	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1271	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1272	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1273	*/
1274
1275	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1276	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1277
1278	switch (rc)
1279	{
1280	case VINF_SUCCESS:
1281	break;
1282
1283	case VERR_VMX_INVALID_VMXON_PTR:
1284	AssertFailed();
1285	goto end;
1286
1287	case VERR_VMX_UNABLE_TO_START_VM:
1288	case VERR_VMX_UNABLE_TO_RESUME_VM:
1289	{
1290	#ifdef VBOX_STRICT
1291	int rc1;
1292
1293	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1294	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1295	AssertRC(rc1);
1296	if (rc1 == VINF_SUCCESS)
1297	{
1298	RTGDTR gdtr;
1299	PX86DESCHC pDesc;
1300
1301	ASMGetGDTR(&gdtr);
1302
1303	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1304	Log(("Current stack %08x\n", &rc1));
1305
1306
1307	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1308	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1309	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1310	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1311	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1312	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1313	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1314	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1315	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1316	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1317
1318	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1319	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1320
1321	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1322	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1323
1324	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1325	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1326
1327	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1328	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1329	if (val < gdtr.cbGdt)
1330	{
1331	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1332	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1333	}
1334
1335	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1336	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1337	if (val < gdtr.cbGdt)
1338	{
1339	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1340	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1341	}
1342
1343	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1344	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1345	if (val < gdtr.cbGdt)
1346	{
1347	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1348	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1349	}
1350
1351	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1352	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1353	if (val < gdtr.cbGdt)
1354	{
1355	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1356	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1357	}
1358
1359	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1360	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1361	if (val < gdtr.cbGdt)
1362	{
1363	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1364	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1365	}
1366
1367	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1368	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1369	if (val < gdtr.cbGdt)
1370	{
1371	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1372	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1373	}
1374
1375	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1376	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1377	if (val < gdtr.cbGdt)
1378	{
1379	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1380	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1381	}
1382
1383	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1384	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1385
1386	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1387	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1388	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1389	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1390
1391	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1392	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1393
1394	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1395	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1396
1397	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1398	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1399
1400	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1401	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1402	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1403	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1404
1405	#if HC_ARCH_BITS == 64
1406	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1407	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1408	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1409	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1410	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1411	#endif
1412	}
1413	#endif /* VBOX_STRICT */
1414	goto end;
1415	}
1416
1417	default:
1418	/* impossible */
1419	AssertFailed();
1420	goto end;
1421	}
1422	/* Success. Query the guest state and figure out what has happened. */
1423
1424	/* Investigate why there was a VM-exit. */
1425	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1426	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1427
1428	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1429	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1430	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1431	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1432	intInfo = val;
1433	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1434	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1435	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1436	instrInfo = val;
1437	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1438	exitQualification = val;
1439	AssertRC(rc);
1440
1441	/* Let's first sync back eip, esp, and eflags. */
1442	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1443	AssertRC(rc);
1444	pCtx->rip = val;
1445	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1446	AssertRC(rc);
1447	pCtx->rsp = val;
1448	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1449	AssertRC(rc);
1450	pCtx->eflags.u32 = val;
1451
1452	/* Take care of instruction fusing (sti, mov ss) */
1453	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1454	uInterruptState = val;
1455	if (uInterruptState != 0)
1456	{
1457	Assert(uInterruptState <= 2); /* only sti & mov ss */
1458	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1459	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1460	}
1461	else
1462	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1463
1464	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1465	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1466	{
1467	/* Hide our emulation flags */
1468	pCtx->eflags.Bits.u1VM = 0;
1469	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1470	pCtx->eflags.Bits.u1VIF = 0;
1471	pCtx->eflags.Bits.u2IOPL = 0;
1472	}
1473
1474	/* Control registers. */
1475	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1476	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1477	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1478	CPUMSetGuestCR0(pVM, val);
1479
1480	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1481	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1482	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1483	CPUMSetGuestCR4(pVM, val);
1484
1485	CPUMSetGuestCR2(pVM, ASMGetCR2());
1486
1487	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1488	CPUMSetGuestDR7(pVM, val);
1489
1490	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1491	VMX_READ_SELREG(ES, es);
1492	VMX_READ_SELREG(SS, ss);
1493	VMX_READ_SELREG(CS, cs);
1494	VMX_READ_SELREG(DS, ds);
1495	VMX_READ_SELREG(FS, fs);
1496	VMX_READ_SELREG(GS, gs);
1497
1498	/** @note NOW IT'S SAFE FOR LOGGING! */
1499	Log2(("Raw exit reason %08x\n", exitReason));
1500
1501	/* Check if an injected event was interrupted prematurely. */
1502	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1503	AssertRC(rc);
1504	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1505	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1506	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1507	{
1508	pVM->hwaccm.s.Event.fPending = true;
1509	/* Error code present? */
1510	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1511	{
1512	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1513	AssertRC(rc);
1514	pVM->hwaccm.s.Event.errCode = val;
1515	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1516	}
1517	else
1518	{
1519	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1520	pVM->hwaccm.s.Event.errCode = 0;
1521	}
1522	}
1523
1524	#ifdef VBOX_STRICT
1525	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1526	HWACCMDumpRegs(pVM, pCtx);
1527	#endif
1528
1529	Log2(("E%d", exitReason));
1530	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1531	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1532	Log2(("Interruption error code %d\n", errCode));
1533	Log2(("IntInfo = %08x\n", intInfo));
1534	Log2(("New EIP=%VGv\n", pCtx->rip));
1535
1536	if (fSyncTPR)
1537	{
1538	rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1539	AssertRC(rc);
1540	}
1541
1542	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1543	switch (exitReason)
1544	{
1545	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1546	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1547	{
1548	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1549
1550	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1551	{
1552	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1553	/* External interrupt; leave to allow it to be dispatched again. */
1554	rc = VINF_EM_RAW_INTERRUPT;
1555	break;
1556	}
1557	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1558	{
1559	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1560	/* External interrupt; leave to allow it to be dispatched again. */
1561	rc = VINF_EM_RAW_INTERRUPT;
1562	break;
1563
1564	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1565	AssertFailed(); /* can't come here; fails the first check. */
1566	break;
1567
1568	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1569	Assert(vector == 3 \|\| vector == 4);
1570	/* no break */
1571	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1572	Log2(("Hardware/software interrupt %d\n", vector));
1573	switch (vector)
1574	{
1575	case X86_XCPT_NM:
1576	{
1577	Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1578
1579	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1580	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1581	rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1582	if (rc == VINF_SUCCESS)
1583	{
1584	Assert(CPUMIsGuestFPUStateActive(pVM));
1585
1586	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1587
1588	/* Continue execution. */
1589	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1590	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1591
1592	goto ResumeExecution;
1593	}
1594
1595	Log(("Forward #NM fault to the guest\n"));
1596	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1597	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1598	AssertRC(rc);
1599	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1600	goto ResumeExecution;
1601	}
1602
1603	case X86_XCPT_PF: /* Page fault */
1604	{
1605	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1606	/* Exit qualification contains the linear address of the page fault. */
1607	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1608	TRPMSetErrorCode(pVM, errCode);
1609	TRPMSetFaultAddress(pVM, exitQualification);
1610
1611	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1612	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1613	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1614	if (rc == VINF_SUCCESS)
1615	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1616	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1617	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1618
1619	TRPMResetTrap(pVM);
1620
1621	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1622	goto ResumeExecution;
1623	}
1624	else
1625	if (rc == VINF_EM_RAW_GUEST_TRAP)
1626	{ /* A genuine pagefault.
1627	* Forward the trap to the guest by injecting the exception and resuming execution.
1628	*/
1629	Log2(("Forward page fault to the guest\n"));
1630	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1631	/* The error code might have been changed. */
1632	errCode = TRPMGetErrorCode(pVM);
1633
1634	TRPMResetTrap(pVM);
1635
1636	/* Now we must update CR2. */
1637	pCtx->cr2 = exitQualification;
1638	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1639	AssertRC(rc);
1640
1641	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1642	goto ResumeExecution;
1643	}
1644	#ifdef VBOX_STRICT
1645	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1646	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1647	#endif
1648	/* Need to go back to the recompiler to emulate the instruction. */
1649	TRPMResetTrap(pVM);
1650	break;
1651	}
1652
1653	case X86_XCPT_MF: /* Floating point exception. */
1654	{
1655	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1656	if (!(pCtx->cr0 & X86_CR0_NE))
1657	{
1658	/* old style FPU error reporting needs some extra work. */
1659	/** @todo don't fall back to the recompiler, but do it manually. */
1660	rc = VINF_EM_RAW_EMULATE_INSTR;
1661	break;
1662	}
1663	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1664	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1665	AssertRC(rc);
1666
1667	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1668	goto ResumeExecution;
1669	}
1670
1671	#ifdef VBOX_STRICT
1672	case X86_XCPT_GP: /* General protection failure exception.*/
1673	case X86_XCPT_UD: /* Unknown opcode exception. */
1674	case X86_XCPT_DE: /* Debug exception. */
1675	case X86_XCPT_SS: /* Stack segment exception. */
1676	case X86_XCPT_NP: /* Segment not present exception. */
1677	{
1678	switch(vector)
1679	{
1680	case X86_XCPT_DE:
1681	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1682	break;
1683	case X86_XCPT_UD:
1684	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1685	break;
1686	case X86_XCPT_SS:
1687	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1688	break;
1689	case X86_XCPT_NP:
1690	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1691	break;
1692	case X86_XCPT_GP:
1693	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1694	break;
1695	}
1696
1697	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1698	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1699	AssertRC(rc);
1700
1701	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1702	goto ResumeExecution;
1703	}
1704	#endif
1705	default:
1706	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1707	rc = VERR_EM_INTERNAL_ERROR;
1708	break;
1709	} /* switch (vector) */
1710
1711	break;
1712
1713	default:
1714	rc = VERR_EM_INTERNAL_ERROR;
1715	AssertFailed();
1716	break;
1717	}
1718
1719	break;
1720	}
1721
1722	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1723	/* Clear VM-exit on IF=1 change. */
1724	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1725	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1726	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1727	AssertRC(rc);
1728	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1729	goto ResumeExecution; /* we check for pending guest interrupts there */
1730
1731	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1732	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1733	/* Skip instruction and continue directly. */
1734	pCtx->rip += cbInstr;
1735	/* Continue execution.*/
1736	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1737	goto ResumeExecution;
1738
1739	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1740	{
1741	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1742	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1743	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1744	if (rc == VINF_SUCCESS)
1745	{
1746	/* Update EIP and continue execution. */
1747	Assert(cbInstr == 2);
1748	pCtx->rip += cbInstr;
1749	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1750	goto ResumeExecution;
1751	}
1752	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1753	rc = VINF_EM_RAW_EMULATE_INSTR;
1754	break;
1755	}
1756
1757	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1758	{
1759	Log2(("VMX: Rdtsc\n"));
1760	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1761	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1762	if (rc == VINF_SUCCESS)
1763	{
1764	/* Update EIP and continue execution. */
1765	Assert(cbInstr == 2);
1766	pCtx->rip += cbInstr;
1767	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1768	goto ResumeExecution;
1769	}
1770	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1771	rc = VINF_EM_RAW_EMULATE_INSTR;
1772	break;
1773	}
1774
1775	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1776	{
1777	Log2(("VMX: invlpg\n"));
1778	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1779	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1780	if (rc == VINF_SUCCESS)
1781	{
1782	/* Update EIP and continue execution. */
1783	pCtx->rip += cbInstr;
1784	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1785	goto ResumeExecution;
1786	}
1787	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1788	break;
1789	}
1790
1791	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1792	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1793	{
1794	uint32_t cbSize;
1795
1796	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1797	Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1798	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1799	if (rc == VINF_SUCCESS)
1800	{
1801	/* EIP has been updated already. */
1802
1803	/* Only resume if successful. */
1804	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1805	goto ResumeExecution;
1806	}
1807	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1808	break;
1809	}
1810
1811	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1812	{
1813	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1814	{
1815	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1816	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1817	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1818	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1819	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1820	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1821
1822	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1823	{
1824	case 0:
1825	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1826	break;
1827	case 2:
1828	break;
1829	case 3:
1830	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1831	break;
1832	case 4:
1833	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1834	break;
1835	case 8:
1836	/* CR8 contains the APIC TPR */
1837	Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1838	break;
1839
1840	default:
1841	AssertFailed();
1842	break;
1843	}
1844	/* Check if a sync operation is pending. */
1845	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1846	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1847	{
1848	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1849	AssertRC(rc);
1850	}
1851	break;
1852
1853	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1854	Log2(("VMX: mov x, crx\n"));
1855	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1856
1857	/* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1858	Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 \|\| !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1859
1860	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1861	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1862	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1863	break;
1864
1865	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1866	Log2(("VMX: clts\n"));
1867	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1868	rc = EMInterpretCLTS(pVM);
1869	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1870	break;
1871
1872	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1873	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1874	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1875	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1876	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1877	break;
1878	}
1879
1880	/* Update EIP if no error occurred. */
1881	if (VBOX_SUCCESS(rc))
1882	pCtx->rip += cbInstr;
1883
1884	if (rc == VINF_SUCCESS)
1885	{
1886	/* Only resume if successful. */
1887	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1888	goto ResumeExecution;
1889	}
1890	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1891	break;
1892	}
1893
1894	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1895	{
1896	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1897	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1898	{
1899	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1900	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1901	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1902	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1903	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1904	Log2(("DR7=%08x\n", pCtx->dr7));
1905	}
1906	else
1907	{
1908	Log2(("VMX: mov x, drx\n"));
1909	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1910	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1911	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1912	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1913	}
1914	/* Update EIP if no error occurred. */
1915	if (VBOX_SUCCESS(rc))
1916	pCtx->rip += cbInstr;
1917
1918	if (rc == VINF_SUCCESS)
1919	{
1920	/* Only resume if successful. */
1921	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1922	goto ResumeExecution;
1923	}
1924	Assert(rc == VERR_EM_INTERPRETER);
1925	break;
1926	}
1927
1928	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1929	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1930	{
1931	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1932	uint32_t uPort;
1933	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1934
1935	/** @todo necessary to make the distinction? */
1936	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1937	{
1938	uPort = pCtx->edx & 0xffff;
1939	}
1940	else
1941	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1942
1943	/* paranoia */
1944	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1945	{
1946	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1947	break;
1948	}
1949
1950	uint32_t cbSize = aIOSize[uIOWidth];
1951
1952	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1953	{
1954	/* ins/outs */
1955	uint32_t prefix = 0;
1956	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1957	prefix \|= PREFIX_REP;
1958
1959	if (fIOWrite)
1960	{
1961	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1962	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1963	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1964	}
1965	else
1966	{
1967	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1968	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1969	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1970	}
1971	}
1972	else
1973	{
1974	/* normal in/out */
1975	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1976
1977	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1978
1979	if (fIOWrite)
1980	{
1981	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1982	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1983	}
1984	else
1985	{
1986	uint32_t u32Val = 0;
1987
1988	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1989	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1990	if (IOM_SUCCESS(rc))
1991	{
1992	/* Write back to the EAX register. */
1993	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1994	}
1995	}
1996	}
1997	/*
1998	* Handled the I/O return codes.
1999	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2000	*/
2001	if (IOM_SUCCESS(rc))
2002	{
2003	/* Update EIP and continue execution. */
2004	pCtx->rip += cbInstr;
2005	if (RT_LIKELY(rc == VINF_SUCCESS))
2006	{
2007	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2008	goto ResumeExecution;
2009	}
2010	break;
2011	}
2012
2013	#ifdef VBOX_STRICT
2014	if (rc == VINF_IOM_HC_IOPORT_READ)
2015	Assert(!fIOWrite);
2016	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2017	Assert(fIOWrite);
2018	else
2019	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2020	#endif
2021	break;
2022	}
2023
2024	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2025	LogFlow(("VMX_EXIT_TPR\n"));
2026	/* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2027	goto ResumeExecution;
2028
2029	default:
2030	/* The rest is handled after syncing the entire CPU state. */
2031	break;
2032	}
2033
2034	/* Note: the guest state isn't entirely synced back at this stage. */
2035
2036	/* Investigate why there was a VM-exit. (part 2) */
2037	switch (exitReason)
2038	{
2039	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2040	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2041	/* Already handled above. */
2042	break;
2043
2044	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2045	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2046	break;
2047
2048	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2049	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2050	rc = VINF_EM_RAW_INTERRUPT;
2051	AssertFailed(); /* Can't happen. Yet. */
2052	break;
2053
2054	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2055	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2056	rc = VINF_EM_RAW_INTERRUPT;
2057	AssertFailed(); /* Can't happen afaik. */
2058	break;
2059
2060	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2061	rc = VERR_EM_INTERPRETER;
2062	break;
2063
2064	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2065	/** Check if external interrupts are pending; if so, don't switch back. */
2066	pCtx->rip++; /* skip hlt */
2067	if ( pCtx->eflags.Bits.u1IF
2068	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
2069	goto ResumeExecution;
2070
2071	rc = VINF_EM_HALT;
2072	break;
2073
2074	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2075	AssertFailed(); /* can't happen. */
2076	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2077	break;
2078
2079	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2080	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2081	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2082	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2083	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2084	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2085	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2086	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2087	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2088	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2089	/** @todo inject #UD immediately */
2090	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2091	break;
2092
2093	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2094	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2095	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2096	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2097	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2098	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2099	/* already handled above */
2100	AssertMsg( rc == VINF_PGM_CHANGE_MODE
2101	\|\| rc == VINF_EM_RAW_INTERRUPT
2102	\|\| rc == VERR_EM_INTERPRETER
2103	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
2104	\|\| rc == VINF_PGM_SYNC_CR3
2105	\|\| rc == VINF_IOM_HC_IOPORT_READ
2106	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2107	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2108	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
2109	\|\| rc == VINF_EM_RESCHEDULE_REM,
2110	("rc = %d\n", rc));
2111	break;
2112
2113	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2114	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2115	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2116	/* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2117	rc = VERR_EM_INTERPRETER;
2118	break;
2119
2120	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2121	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2122	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2123	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2124	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2125	break;
2126
2127	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2128	Assert(rc == VINF_EM_RAW_INTERRUPT);
2129	break;
2130
2131	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2132	{
2133	#ifdef VBOX_STRICT
2134	Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2135
2136	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2137	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2138
2139	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2140	Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2141
2142	VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2143	Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2144
2145	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2146	Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2147
2148	VMX_LOG_SELREG(CS, "CS");
2149	VMX_LOG_SELREG(DS, "DS");
2150	VMX_LOG_SELREG(ES, "ES");
2151	VMX_LOG_SELREG(FS, "FS");
2152	VMX_LOG_SELREG(GS, "GS");
2153	VMX_LOG_SELREG(SS, "SS");
2154	VMX_LOG_SELREG(TR, "TR");
2155	VMX_LOG_SELREG(LDTR, "LDTR");
2156
2157	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2158	Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2159	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2160	Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2161	#endif /* VBOX_STRICT */
2162	rc = VERR_EM_INTERNAL_ERROR;
2163	break;
2164	}
2165
2166	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2167	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2168	default:
2169	rc = VERR_EM_INTERNAL_ERROR;
2170	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2171	break;
2172
2173	}
2174	end:
2175	if (fGuestStateSynced)
2176	{
2177	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2178	VMX_READ_SELREG(LDTR, ldtr);
2179	VMX_READ_SELREG(TR, tr);
2180
2181	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2182	pCtx->gdtr.cbGdt = val;
2183	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2184	pCtx->gdtr.pGdt = val;
2185
2186	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2187	pCtx->idtr.cbIdt = val;
2188	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2189	pCtx->idtr.pIdt = val;
2190
2191	/*
2192	* System MSRs
2193	*/
2194	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
2195	pCtx->SysEnter.cs = val;
2196	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
2197	pCtx->SysEnter.eip = val;
2198	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
2199	pCtx->SysEnter.esp = val;
2200	}
2201
2202	/* Signal changes for the recompiler. */
2203	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2204
2205	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2206	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2207	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2208	{
2209	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2210	/* On the next entry we'll only sync the host context. */
2211	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2212	}
2213	else
2214	{
2215	/* On the next entry we'll sync everything. */
2216	/** @todo we can do better than this */
2217	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2218	}
2219
2220	/* translate into a less severe return code */
2221	if (rc == VERR_EM_INTERPRETER)
2222	rc = VINF_EM_RAW_EMULATE_INSTR;
2223
2224	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2225	Log2(("X"));
2226	return rc;
2227	}
2228
2229
2230	/**
2231	* Enters the VT-x session
2232	*
2233	* @returns VBox status code.
2234	* @param pVM The VM to operate on.
2235	* @param pCpu CPU info struct
2236	*/
2237	HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2238	{
2239	Assert(pVM->hwaccm.s.vmx.fSupported);
2240
2241	unsigned cr4 = ASMGetCR4();
2242	if (!(cr4 & X86_CR4_VMXE))
2243	{
2244	AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2245	return VERR_VMX_X86_CR4_VMXE_CLEARED;
2246	}
2247
2248	/* Activate the VM Control Structure. */
2249	int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2250	if (VBOX_FAILURE(rc))
2251	return rc;
2252
2253	pVM->hwaccm.s.vmx.fResumeVM = false;
2254	return VINF_SUCCESS;
2255	}
2256
2257
2258	/**
2259	* Leaves the VT-x session
2260	*
2261	* @returns VBox status code.
2262	* @param pVM The VM to operate on.
2263	*/
2264	HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2265	{
2266	Assert(pVM->hwaccm.s.vmx.fSupported);
2267
2268	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2269	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2270	AssertRC(rc);
2271
2272	return VINF_SUCCESS;
2273	}
2274

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 10832

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