HWVMXR0.cpp@ 11696

Last change on this file since 11696 was 11696, checked in by vboxsync, 17 years ago
Enabled MSR bitmap for VT-x.
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File size: 86.6 KB

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1	/* $Id: HWVMXR0.cpp 11696 2008-08-27 12:09:59Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/string.h>
41	#include "HWVMXR0.h"
42
43
44	/* IO operation lookup arrays. */
45	static uint32_t aIOSize[4] = {1, 2, 0, 4};
46	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49	static void VMXR0CheckError(PVM pVM, int rc)
50	{
51	if (rc == VERR_VMX_GENERIC)
52	{
53	RTCCUINTREG instrError;
54
55	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57	}
58	pVM->hwaccm.s.lLastError = rc;
59	}
60
61	/**
62	* Sets up and activates VT-x on the current CPU
63	*
64	* @returns VBox status code.
65	* @param pCpu CPU info struct
66	* @param pVM The VM to operate on.
67	* @param pvPageCpu Pointer to the global cpu page
68	* @param pPageCpuPhys Physical address of the global cpu page
69	*/
70	HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71	{
72	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73	AssertReturn(pVM, VERR_INVALID_PARAMETER);
74	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76	/* Setup Intel VMX. */
77	Assert(pVM->hwaccm.s.vmx.fSupported);
78
79	#ifdef LOG_ENABLED
80	SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81	#endif
82	/* Set revision dword at the beginning of the VMXON structure. */
83	(uint32_t )pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86	* (which can have very bad consequences!!!)
87	*/
88
89	/* Make sure the VMX instructions don't cause #UD faults. */
90	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
91
92	/* Enter VMX Root Mode */
93	int rc = VMXEnable(pPageCpuPhys);
94	if (VBOX_FAILURE(rc))
95	{
96	VMXR0CheckError(pVM, rc);
97	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98	return VERR_VMX_VMXON_FAILED;
99	}
100	return VINF_SUCCESS;
101	}
102
103	/**
104	* Deactivates VT-x on the current CPU
105	*
106	* @returns VBox status code.
107	* @param pCpu CPU info struct
108	* @param pvPageCpu Pointer to the global cpu page
109	* @param pPageCpuPhys Physical address of the global cpu page
110	*/
111	HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112	{
113	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116	/* Leave VMX Root Mode. */
117	VMXDisable();
118
119	/* And clear the X86_CR4_VMXE bit */
120	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122	#ifdef LOG_ENABLED
123	SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124	#endif
125	return VINF_SUCCESS;
126	}
127
128	/**
129	* Does Ring-0 per VM VT-x init.
130	*
131	* @returns VBox status code.
132	* @param pVM The VM to operate on.
133	*/
134	HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135	{
136	int rc;
137
138	#ifdef LOG_ENABLED
139	SUPR0Printf("VMXR0InitVM %x\n", pVM);
140	#endif
141	pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
142	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
143	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
144
145
146	/* Allocate one page for the VM control structure (VMCS). */
147	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
148	AssertRC(rc);
149	if (RT_FAILURE(rc))
150	return rc;
151
152	pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
153	pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
154	ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
155
156	/* Allocate one page for the TSS we need for real mode emulation. */
157	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
158	AssertRC(rc);
159	if (RT_FAILURE(rc))
160	return rc;
161
162	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
163	pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
164
165	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
166	* for I/O operations. */
167	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
168	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
169	/* Bit set to 0 means redirection enabled. */
170	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
171
172	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
173	{
174	/* Allocate one page for the virtual APIC mmio cache. */
175	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
176	AssertRC(rc);
177	if (RT_FAILURE(rc))
178	return rc;
179
180	pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
181	pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
182	ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
183	}
184	else
185	{
186	pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
187	pVM->hwaccm.s.vmx.pAPIC = 0;
188	pVM->hwaccm.s.vmx.pAPICPhys = 0;
189	}
190
191	/* Allocate the MSR bitmap if this feature is supported. */
192	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
193	{
194	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
195	AssertRC(rc);
196	if (RT_FAILURE(rc))
197	return rc;
198
199	pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
200	pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
201	memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
202	}
203	#ifdef LOG_ENABLED
204	SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
205	#endif
206	return VINF_SUCCESS;
207	}
208
209	/**
210	* Does Ring-0 per VM VT-x termination.
211	*
212	* @returns VBox status code.
213	* @param pVM The VM to operate on.
214	*/
215	HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
216	{
217	if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
218	{
219	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
220	pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
221	pVM->hwaccm.s.vmx.pVMCS = 0;
222	pVM->hwaccm.s.vmx.pVMCSPhys = 0;
223	}
224	if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS != NIL_RTR0MEMOBJ)
225	{
226	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
227	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
228	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
229	pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
230	}
231	if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
232	{
233	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
234	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
235	pVM->hwaccm.s.vmx.pAPIC = 0;
236	pVM->hwaccm.s.vmx.pAPICPhys = 0;
237	}
238	if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
239	{
240	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
241	pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
242	pVM->hwaccm.s.vmx.pMSRBitmap = 0;
243	pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
244	}
245	return VINF_SUCCESS;
246	}
247
248	/**
249	* Sets up VT-x for the specified VM
250	*
251	* @returns VBox status code.
252	* @param pVM The VM to operate on.
253	*/
254	HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
255	{
256	int rc = VINF_SUCCESS;
257	uint32_t val;
258
259	AssertReturn(pVM, VERR_INVALID_PARAMETER);
260	Assert(pVM->hwaccm.s.vmx.pVMCS);
261
262	/* Set revision dword at the beginning of the VMCS structure. */
263	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
264
265	/* Clear VM Control Structure. */
266	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
267	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
268	if (VBOX_FAILURE(rc))
269	goto vmx_end;
270
271	/* Activate the VM Control Structure. */
272	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
273	if (VBOX_FAILURE(rc))
274	goto vmx_end;
275
276	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
277	* Set required bits to one and zero according to the MSR capabilities.
278	*/
279	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
280	/* External and non-maskable interrupts cause VM-exits. */
281	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
282	val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
283
284	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
285	AssertRC(rc);
286
287	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
288	* Set required bits to one and zero according to the MSR capabilities.
289	*/
290	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
291	/* Program which event cause VM-exits and which features we want to use. */
292	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
293	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
294	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
295	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
296	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
297	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
298
299	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
300
301	#if HC_ARCH_BITS == 64
302	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
303	{
304	/* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
305	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
306	Assert(pVM->hwaccm.s.vmx.pAPIC);
307	}
308	else
309	/* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
310	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
311	#endif
312
313	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
314	{
315	Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
316	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
317	}
318
319	/* Mask away the bits that the CPU doesn't support */
320	/** @todo make sure they don't conflict with the above requirements. */
321	val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
322	pVM->hwaccm.s.vmx.proc_ctls = val;
323
324	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
325	AssertRC(rc);
326
327	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
328	* Set required bits to one and zero according to the MSR capabilities.
329	*/
330	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
331	AssertRC(rc);
332
333	/* VMX_VMCS_CTRL_EXIT_CONTROLS
334	* Set required bits to one and zero according to the MSR capabilities.
335	*/
336	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
337	#if HC_ARCH_BITS == 64
338	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
339	#else
340	/* else Must be zero when AMD64 is not available. */
341	#endif
342	val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
343	/* Don't acknowledge external interrupts on VM-exit. */
344	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
345	AssertRC(rc);
346
347	/* Forward all exception except #NM & #PF to the guest.
348	* We always need to check pagefaults since our shadow page table can be out of sync.
349	* And we always lazily sync the FPU & XMM state.
350	*/
351
352	/*
353	* @todo Possible optimization:
354	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
355	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
356	* registers ourselves of course.
357	*
358	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
359	*/
360	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
361	AssertRC(rc);
362
363	/* Don't filter page faults; all of them should cause a switch. */
364	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
365	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
366	AssertRC(rc);
367
368	/* Init TSC offset to zero. */
369	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
370	#if HC_ARCH_BITS == 32
371	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
372	#endif
373	AssertRC(rc);
374
375	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
376	#if HC_ARCH_BITS == 32
377	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
378	#endif
379	AssertRC(rc);
380
381	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
382	#if HC_ARCH_BITS == 32
383	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
384	#endif
385	AssertRC(rc);
386
387	/* Clear MSR controls. */
388	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
389	{
390	/* Optional */
391	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
392	#if HC_ARCH_BITS == 32
393	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32);
394	#endif
395	AssertRC(rc);
396	}
397	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
398	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
399	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
400	#if HC_ARCH_BITS == 32
401	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
402	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
403	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
404	#endif
405	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
406	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
407	AssertRC(rc);
408
409	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
410	{
411	Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
412	/* Optional */
413	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
414	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
415	#if HC_ARCH_BITS == 32
416	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
417	#endif
418	AssertRC(rc);
419	}
420
421	/* Set link pointer to -1. Not currently used. */
422	#if HC_ARCH_BITS == 32
423	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
424	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
425	#else
426	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
427	#endif
428	AssertRC(rc);
429
430	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
431	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
432	AssertRC(rc);
433
434	vmx_end:
435	VMXR0CheckError(pVM, rc);
436	return rc;
437	}
438
439
440	/**
441	* Injects an event (trap or external interrupt)
442	*
443	* @returns VBox status code.
444	* @param pVM The VM to operate on.
445	* @param pCtx CPU Context
446	* @param intInfo VMX interrupt info
447	* @param cbInstr Opcode length of faulting instruction
448	* @param errCode Error code (optional)
449	*/
450	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
451	{
452	int rc;
453
454	#ifdef VBOX_STRICT
455	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
456	if (iGate == 0xE)
457	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
458	else
459	if (iGate < 0x20)
460	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
461	else
462	{
463	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
464	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
465	Assert(pCtx->eflags.u32 & X86_EFL_IF);
466	}
467	#endif
468
469	/* Set event injection state. */
470	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
471	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
472	);
473
474	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
475	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
476
477	AssertRC(rc);
478	return rc;
479	}
480
481
482	/**
483	* Checks for pending guest interrupts and injects them
484	*
485	* @returns VBox status code.
486	* @param pVM The VM to operate on.
487	* @param pCtx CPU Context
488	*/
489	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
490	{
491	int rc;
492
493	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
494	if (pVM->hwaccm.s.Event.fPending)
495	{
496	Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
497	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
498	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
499	AssertRC(rc);
500
501	pVM->hwaccm.s.Event.fPending = false;
502	return VINF_SUCCESS;
503	}
504
505	/* When external interrupts are pending, we should exit the VM when IF is set. */
506	if ( !TRPMHasTrap(pVM)
507	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
508	{
509	if (!(pCtx->eflags.u32 & X86_EFL_IF))
510	{
511	Log2(("Enable irq window exit!\n"));
512	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
513	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
514	AssertRC(rc);
515	}
516	else
517	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
518	{
519	uint8_t u8Interrupt;
520
521	rc = PDMGetInterrupt(pVM, &u8Interrupt);
522	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
523	if (VBOX_SUCCESS(rc))
524	{
525	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
526	AssertRC(rc);
527	}
528	else
529	{
530	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
531	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
532	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
533	/* Just continue */
534	}
535	}
536	else
537	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
538	}
539
540	#ifdef VBOX_STRICT
541	if (TRPMHasTrap(pVM))
542	{
543	uint8_t u8Vector;
544	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
545	AssertRC(rc);
546	}
547	#endif
548
549	if ( pCtx->eflags.u32 & X86_EFL_IF
550	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
551	&& TRPMHasTrap(pVM)
552	)
553	{
554	uint8_t u8Vector;
555	int rc;
556	TRPMEVENT enmType;
557	RTGCUINTPTR intInfo;
558	RTGCUINT errCode;
559
560	/* If a new event is pending, then dispatch it now. */
561	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
562	AssertRC(rc);
563	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
564	Assert(enmType != TRPM_SOFTWARE_INT);
565
566	/* Clear the pending trap. */
567	rc = TRPMResetTrap(pVM);
568	AssertRC(rc);
569
570	intInfo = u8Vector;
571	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
572
573	if (enmType == TRPM_TRAP)
574	{
575	switch (u8Vector) {
576	case 8:
577	case 10:
578	case 11:
579	case 12:
580	case 13:
581	case 14:
582	case 17:
583	/* Valid error codes. */
584	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
585	break;
586	default:
587	break;
588	}
589	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
590	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
591	else
592	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
593	}
594	else
595	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
596
597	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
598	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
599	AssertRC(rc);
600	} /* if (interrupts can be dispatched) */
601
602	return VINF_SUCCESS;
603	}
604
605	/**
606	* Save the host state
607	*
608	* @returns VBox status code.
609	* @param pVM The VM to operate on.
610	*/
611	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
612	{
613	int rc = VINF_SUCCESS;
614
615	/*
616	* Host CPU Context
617	*/
618	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
619	{
620	RTIDTR idtr;
621	RTGDTR gdtr;
622	RTSEL SelTR;
623	PX86DESCHC pDesc;
624	uintptr_t trBase;
625
626	/* Control registers */
627	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
628	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
629	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
630	AssertRC(rc);
631	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
632	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
633	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
634
635	/* Selector registers. */
636	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
637	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
638	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
639	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
640	#if HC_ARCH_BITS == 32
641	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
642	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
643	#endif
644	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
645	SelTR = ASMGetTR();
646	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
647	AssertRC(rc);
648	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
649	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
650	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
651	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
652	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
653	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
654	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
655
656	/* GDTR & IDTR */
657	ASMGetGDTR(&gdtr);
658	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
659	ASMGetIDTR(&idtr);
660	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
661	AssertRC(rc);
662	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
663	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
664
665	/* Save the base address of the TR selector. */
666	if (SelTR > gdtr.cbGdt)
667	{
668	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
669	return VERR_VMX_INVALID_HOST_STATE;
670	}
671
672	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
673	#if HC_ARCH_BITS == 64
674	trBase = X86DESC64_BASE(*pDesc);
675	#else
676	trBase = X86DESC_BASE(*pDesc);
677	#endif
678	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
679	AssertRC(rc);
680	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
681
682	/* FS and GS base. */
683	#if HC_ARCH_BITS == 64
684	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
685	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
686	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
687	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
688	#endif
689	AssertRC(rc);
690
691	/* Sysenter MSRs. */
692	/** @todo expensive!! */
693	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
694	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
695	#if HC_ARCH_BITS == 32
696	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
697	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
698	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
699	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
700	#else
701	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
702	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
703	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
704	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
705	#endif
706	AssertRC(rc);
707
708	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
709	}
710	return rc;
711	}
712
713
714	/**
715	* Loads the guest state
716	*
717	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
718	*
719	* @returns VBox status code.
720	* @param pVM The VM to operate on.
721	* @param pCtx Guest context
722	*/
723	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
724	{
725	int rc = VINF_SUCCESS;
726	RTGCUINTPTR val;
727	X86EFLAGS eflags;
728
729	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
730	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
731	{
732	VMX_WRITE_SELREG(ES, es);
733	AssertRC(rc);
734
735	VMX_WRITE_SELREG(CS, cs);
736	AssertRC(rc);
737
738	VMX_WRITE_SELREG(SS, ss);
739	AssertRC(rc);
740
741	VMX_WRITE_SELREG(DS, ds);
742	AssertRC(rc);
743
744	/* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
745	VMX_WRITE_SELREG(FS, fs);
746	AssertRC(rc);
747
748	VMX_WRITE_SELREG(GS, gs);
749	AssertRC(rc);
750	}
751
752	/* Guest CPU context: LDTR. */
753	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
754	{
755	if (pCtx->ldtr == 0)
756	{
757	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
758	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
759	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
760	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
761	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
762	}
763	else
764	{
765	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
766	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
767	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
768	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
769	}
770	AssertRC(rc);
771	}
772	/* Guest CPU context: TR. */
773	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
774	{
775	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
776
777	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
778	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
779	{
780	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
781	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
782	}
783	else
784	{
785	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
786	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
787	}
788	val = pCtx->trHid.Attr.u;
789
790	/* The TSS selector must be busy. */
791	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
792	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
793	else
794	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
795	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
796
797	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
798	AssertRC(rc);
799	}
800	/* Guest CPU context: GDTR. */
801	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
802	{
803	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
804	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
805	AssertRC(rc);
806	}
807	/* Guest CPU context: IDTR. */
808	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
809	{
810	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
811	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
812	AssertRC(rc);
813	}
814
815	/*
816	* Sysenter MSRs (unconditional)
817	*/
818	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
819	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
820	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
821	AssertRC(rc);
822
823	/* Control registers */
824	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
825	{
826	val = pCtx->cr0;
827	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
828	Log2(("Guest CR0-shadow %08x\n", val));
829	if (CPUMIsGuestFPUStateActive(pVM) == false)
830	{
831	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
832	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
833	}
834	else
835	{
836	/** @todo check if we support the old style mess correctly. */
837	if (!(val & X86_CR0_NE))
838	{
839	Log(("Forcing X86_CR0_NE!!!\n"));
840
841	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
842	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
843	{
844	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| RT_BIT(X86_XCPT_MF));
845	AssertRC(rc);
846	pVM->hwaccm.s.fFPUOldStyleOverride = true;
847	}
848	}
849
850	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
851	}
852	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
853	val \|= X86_CR0_PE \| X86_CR0_PG;
854	/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
855	val \|= X86_CR0_WP;
856
857	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
858	Log2(("Guest CR0 %08x\n", val));
859	/* CR0 flags owned by the host; if the guests attempts to change them, then
860	* the VM will exit.
861	*/
862	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
863	\| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
864	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
865	\| X86_CR0_TS
866	\| X86_CR0_ET
867	\| X86_CR0_NE
868	\| X86_CR0_MP;
869	pVM->hwaccm.s.vmx.cr0_mask = val;
870
871	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
872	Log2(("Guest CR0-mask %08x\n", val));
873	AssertRC(rc);
874	}
875	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
876	{
877	/* CR4 */
878	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
879	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
880	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
881	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
882	switch(pVM->hwaccm.s.enmShadowMode)
883	{
884	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
885	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
886	case PGMMODE_32_BIT: /* 32-bit paging. */
887	break;
888
889	case PGMMODE_PAE: /* PAE paging. */
890	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
891	/** @todo use normal 32 bits paging */
892	val \|= X86_CR4_PAE;
893	break;
894
895	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
896	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
897	#ifdef VBOX_ENABLE_64_BITS_GUESTS
898	break;
899	#else
900	AssertFailed();
901	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
902	#endif
903	default: /* shut up gcc */
904	AssertFailed();
905	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
906	}
907	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
908	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
909	val \|= X86_CR4_VME;
910
911	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
912	Log2(("Guest CR4 %08x\n", val));
913	/* CR4 flags owned by the host; if the guests attempts to change them, then
914	* the VM will exit.
915	*/
916	val = X86_CR4_PAE
917	\| X86_CR4_PGE
918	\| X86_CR4_PSE
919	\| X86_CR4_VMXE;
920	pVM->hwaccm.s.vmx.cr4_mask = val;
921
922	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
923	Log2(("Guest CR4-mask %08x\n", val));
924	AssertRC(rc);
925	}
926
927	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
928	{
929	/* Save our shadow CR3 register. */
930	val = PGMGetHyperCR3(pVM);
931	Assert(val);
932	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
933	AssertRC(rc);
934	}
935
936	/* Debug registers. */
937	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
938	{
939	val = pCtx->dr7 & 0xffffffff; /* upper 32 bits reserved */
940	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
941	val \|= 0x400; /* must be one */
942	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
943	AssertRC(rc);
944
945	/* IA32_DEBUGCTL MSR. */
946	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
947	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
948	AssertRC(rc);
949
950	/** @todo do we really ever need this? */
951	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
952	AssertRC(rc);
953	}
954
955	/* EIP, ESP and EFLAGS */
956	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
957	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
958	AssertRC(rc);
959
960	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
961	eflags = pCtx->eflags;
962	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
963	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
964
965	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
966	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
967	{
968	eflags.Bits.u1VM = 1;
969	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
970	eflags.Bits.u2IOPL = 3;
971	}
972
973	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
974	AssertRC(rc);
975
976	/** TSC offset. */
977	uint64_t u64TSCOffset;
978
979	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
980	{
981	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
982	#if HC_ARCH_BITS == 64
983	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
984	#else
985	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
986	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
987	#endif
988	AssertRC(rc);
989
990	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
991	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
992	AssertRC(rc);
993	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
994	}
995	else
996	{
997	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
998	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
999	AssertRC(rc);
1000	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1001	}
1002
1003	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
1004	* Set required bits to one and zero according to the MSR capabilities.
1005	*/
1006	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1007	/* 64 bits guest mode? */
1008	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1009	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1010	/* else Must be zero when AMD64 is not available. */
1011
1012	/* Mask away the bits that the CPU doesn't support */
1013	val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1014	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1015	AssertRC(rc);
1016
1017	/* 64 bits guest mode? */
1018	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1019	{
1020	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
1021	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1022	#else
1023	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1024	#endif
1025	/* Unconditionally update these as wrmsr might have changed them. */
1026	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1027	AssertRC(rc);
1028	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1029	AssertRC(rc);
1030	}
1031	else
1032	{
1033	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1034	}
1035
1036	/* Done. */
1037	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1038
1039	return rc;
1040	}
1041
1042	/**
1043	* Runs guest code in a VT-x VM.
1044	*
1045	* @returns VBox status code.
1046	* @param pVM The VM to operate on.
1047	* @param pCtx Guest context
1048	*/
1049	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1050	{
1051	int rc = VINF_SUCCESS;
1052	RTCCUINTREG val, valShadow;
1053	RTCCUINTREG exitReason, instrError, cbInstr;
1054	RTGCUINTPTR exitQualification;
1055	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1056	RTGCUINTPTR errCode, instrInfo, uInterruptState;
1057	bool fGuestStateSynced = false;
1058	bool fSyncTPR = false;
1059	unsigned cResume = 0;
1060	#ifdef VBOX_STRICT
1061	RTCPUID idCpuCheck;
1062	#endif
1063
1064	Log2(("\nE"));
1065
1066	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1067
1068	#ifdef VBOX_STRICT
1069	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1070	AssertRC(rc);
1071	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1072
1073	/* allowed zero */
1074	if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1075	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1076
1077	/* allowed one */
1078	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1079	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1080
1081	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1082	AssertRC(rc);
1083	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1084
1085	/* allowed zero */
1086	if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1087	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1088
1089	/* allowed one */
1090	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1091	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1092
1093	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1094	AssertRC(rc);
1095	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1096
1097	/* allowed zero */
1098	if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1099	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1100
1101	/* allowed one */
1102	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1103	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1104
1105	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1106	AssertRC(rc);
1107	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1108
1109	/* allowed zero */
1110	if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1111	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1112
1113	/* allowed one */
1114	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1115	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1116	#endif
1117
1118	#if 0
1119	/*
1120	* Check if debug registers are armed.
1121	*/
1122	uint32_t u32DR7 = ASMGetDR7();
1123	if (u32DR7 & X86_DR7_ENABLED_MASK)
1124	{
1125	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
1126	}
1127	else
1128	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1129	#endif
1130
1131	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1132	*/
1133	ResumeExecution:
1134	/* Safety precaution; looping for too long here can have a very bad effect on the host */
1135	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1136	{
1137	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1138	rc = VINF_EM_RAW_INTERRUPT;
1139	goto end;
1140	}
1141
1142	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1143	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1144	{
1145	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1146	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1147	{
1148	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1149	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1150	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1151	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1152	*/
1153	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1154	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1155	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1156	AssertRC(rc);
1157	}
1158	}
1159	else
1160	{
1161	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1162	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1163	AssertRC(rc);
1164	}
1165
1166	/* Check for pending actions that force us to go back to ring 3. */
1167	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
1168	{
1169	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1170	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1171	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1172	rc = VINF_EM_RAW_TO_R3;
1173	goto end;
1174	}
1175	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1176	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1177	{
1178	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1179	rc = VINF_EM_PENDING_REQUEST;
1180	goto end;
1181	}
1182
1183	/* When external interrupts are pending, we should exit the VM when IF is set. */
1184	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
1185	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1186	if (VBOX_FAILURE(rc))
1187	{
1188	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1189	goto end;
1190	}
1191
1192	/** @todo check timers?? */
1193
1194	/* TPR caching using CR8 is only available in 64 bits mode */
1195	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1196	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1197	/*
1198	* @todo reduce overhead
1199	*/
1200	if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1201	&& pVM->hwaccm.s.vmx.pAPIC)
1202	{
1203	/* TPR caching in CR8 */
1204	uint8_t u8TPR;
1205	bool fPending;
1206
1207	int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1208	AssertRC(rc);
1209	/* The TPR can be found at offset 0x80 in the APIC mmio page. */
1210	pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1211
1212	/* Two options here:
1213	* - external interrupt pending, but masked by the TPR value.
1214	* -> a CR8 update that lower the current TPR value should cause an exit
1215	* - no pending interrupts
1216	* -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1217	*/
1218	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1219	AssertRC(rc);
1220
1221	/* Always sync back the TPR; we should optimize this though (@todo) */
1222	fSyncTPR = true;
1223	}
1224
1225	/*
1226	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1227	* (until the actual world switch)
1228	*/
1229	#ifdef VBOX_STRICT
1230	idCpuCheck = RTMpCpuId();
1231	#endif
1232	/* Save the host state first. */
1233	rc = VMXR0SaveHostState(pVM);
1234	if (rc != VINF_SUCCESS)
1235	{
1236	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1237	goto end;
1238	}
1239	/* Load the guest state */
1240	rc = VMXR0LoadGuestState(pVM, pCtx);
1241	if (rc != VINF_SUCCESS)
1242	{
1243	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1244	goto end;
1245	}
1246	fGuestStateSynced = true;
1247
1248	/* Non-register state Guest Context */
1249	/** @todo change me according to cpu state */
1250	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1251	AssertRC(rc);
1252
1253	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1254
1255	/* Manual save and restore:
1256	* - General purpose registers except RIP, RSP
1257	*
1258	* Trashed:
1259	* - CR2 (we don't care)
1260	* - LDTR (reset to 0)
1261	* - DRx (presumably not changed at all)
1262	* - DR7 (reset to 0x400)
1263	* - EFLAGS (reset to RT_BIT(1); not relevant)
1264	*
1265	*/
1266
1267	/* All done! Let's start VM execution. */
1268	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1269	#ifdef VBOX_STRICT
1270	Assert(idCpuCheck == RTMpCpuId());
1271	#endif
1272	rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1273
1274	/* In case we execute a goto ResumeExecution later on. */
1275	pVM->hwaccm.s.vmx.fResumeVM = true;
1276
1277	/**
1278	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1279	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1280	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1281	*/
1282
1283	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1284	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1285
1286	switch (rc)
1287	{
1288	case VINF_SUCCESS:
1289	break;
1290
1291	case VERR_VMX_INVALID_VMXON_PTR:
1292	AssertFailed();
1293	goto end;
1294
1295	case VERR_VMX_UNABLE_TO_START_VM:
1296	case VERR_VMX_UNABLE_TO_RESUME_VM:
1297	{
1298	#ifdef VBOX_STRICT
1299	int rc1;
1300
1301	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1302	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1303	AssertRC(rc1);
1304	if (rc1 == VINF_SUCCESS)
1305	{
1306	RTGDTR gdtr;
1307	PX86DESCHC pDesc;
1308
1309	ASMGetGDTR(&gdtr);
1310
1311	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1312	Log(("Current stack %08x\n", &rc1));
1313
1314
1315	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1316	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1317	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1318	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1319	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1320	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1321	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1322	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1323	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1324	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1325
1326	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1327	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1328
1329	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1330	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1331
1332	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1333	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1334
1335	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1336	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1337	if (val < gdtr.cbGdt)
1338	{
1339	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1340	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1341	}
1342
1343	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1344	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1345	if (val < gdtr.cbGdt)
1346	{
1347	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1348	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1349	}
1350
1351	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1352	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1353	if (val < gdtr.cbGdt)
1354	{
1355	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1356	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1357	}
1358
1359	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1360	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1361	if (val < gdtr.cbGdt)
1362	{
1363	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1364	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1365	}
1366
1367	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1368	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1369	if (val < gdtr.cbGdt)
1370	{
1371	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1372	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1373	}
1374
1375	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1376	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1377	if (val < gdtr.cbGdt)
1378	{
1379	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1380	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1381	}
1382
1383	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1384	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1385	if (val < gdtr.cbGdt)
1386	{
1387	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1388	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1389	}
1390
1391	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1392	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1393
1394	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1395	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1396	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1397	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1398
1399	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1400	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1401
1402	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1403	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1404
1405	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1406	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1407
1408	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1409	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1410	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1411	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1412
1413	#if HC_ARCH_BITS == 64
1414	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1415	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1416	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1417	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1418	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1419	#endif
1420	}
1421	#endif /* VBOX_STRICT */
1422	goto end;
1423	}
1424
1425	default:
1426	/* impossible */
1427	AssertFailed();
1428	goto end;
1429	}
1430	/* Success. Query the guest state and figure out what has happened. */
1431
1432	/* Investigate why there was a VM-exit. */
1433	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1434	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1435
1436	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1437	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1438	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1439	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1440	intInfo = val;
1441	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1442	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1443	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1444	instrInfo = val;
1445	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1446	exitQualification = val;
1447	AssertRC(rc);
1448
1449	/* Let's first sync back eip, esp, and eflags. */
1450	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1451	AssertRC(rc);
1452	pCtx->rip = val;
1453	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1454	AssertRC(rc);
1455	pCtx->rsp = val;
1456	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1457	AssertRC(rc);
1458	pCtx->eflags.u32 = val;
1459
1460	/* Take care of instruction fusing (sti, mov ss) */
1461	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1462	uInterruptState = val;
1463	if (uInterruptState != 0)
1464	{
1465	Assert(uInterruptState <= 2); /* only sti & mov ss */
1466	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1467	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1468	}
1469	else
1470	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1471
1472	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1473	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1474	{
1475	/* Hide our emulation flags */
1476	pCtx->eflags.Bits.u1VM = 0;
1477	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1478	pCtx->eflags.Bits.u1VIF = 0;
1479	pCtx->eflags.Bits.u2IOPL = 0;
1480	}
1481
1482	/* Control registers. */
1483	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1484	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1485	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1486	CPUMSetGuestCR0(pVM, val);
1487
1488	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1489	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1490	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1491	CPUMSetGuestCR4(pVM, val);
1492
1493	CPUMSetGuestCR2(pVM, ASMGetCR2());
1494
1495	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1496	CPUMSetGuestDR7(pVM, val);
1497
1498	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1499	VMX_READ_SELREG(ES, es);
1500	VMX_READ_SELREG(SS, ss);
1501	VMX_READ_SELREG(CS, cs);
1502	VMX_READ_SELREG(DS, ds);
1503	VMX_READ_SELREG(FS, fs);
1504	VMX_READ_SELREG(GS, gs);
1505
1506	/*
1507	* System MSRs
1508	*/
1509	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1510	pCtx->SysEnter.cs = val;
1511	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1512	pCtx->SysEnter.eip = val;
1513	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1514	pCtx->SysEnter.esp = val;
1515
1516	/** @note NOW IT'S SAFE FOR LOGGING! */
1517	Log2(("Raw exit reason %08x\n", exitReason));
1518
1519	/* Check if an injected event was interrupted prematurely. */
1520	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1521	AssertRC(rc);
1522	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1523	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1524	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1525	{
1526	pVM->hwaccm.s.Event.fPending = true;
1527	/* Error code present? */
1528	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1529	{
1530	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1531	AssertRC(rc);
1532	pVM->hwaccm.s.Event.errCode = val;
1533	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1534	}
1535	else
1536	{
1537	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1538	pVM->hwaccm.s.Event.errCode = 0;
1539	}
1540	}
1541
1542	#ifdef VBOX_STRICT
1543	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1544	HWACCMDumpRegs(pVM, pCtx);
1545	#endif
1546
1547	Log2(("E%d", exitReason));
1548	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1549	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1550	Log2(("Interruption error code %d\n", errCode));
1551	Log2(("IntInfo = %08x\n", intInfo));
1552	Log2(("New EIP=%VGv\n", pCtx->rip));
1553
1554	if (fSyncTPR)
1555	{
1556	rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1557	AssertRC(rc);
1558	}
1559
1560	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1561	switch (exitReason)
1562	{
1563	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1564	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1565	{
1566	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1567
1568	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1569	{
1570	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1571	/* External interrupt; leave to allow it to be dispatched again. */
1572	rc = VINF_EM_RAW_INTERRUPT;
1573	break;
1574	}
1575	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1576	{
1577	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1578	/* External interrupt; leave to allow it to be dispatched again. */
1579	rc = VINF_EM_RAW_INTERRUPT;
1580	break;
1581
1582	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1583	AssertFailed(); /* can't come here; fails the first check. */
1584	break;
1585
1586	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1587	Assert(vector == 3 \|\| vector == 4);
1588	/* no break */
1589	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1590	Log2(("Hardware/software interrupt %d\n", vector));
1591	switch (vector)
1592	{
1593	case X86_XCPT_NM:
1594	{
1595	Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1596
1597	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1598	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1599	rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1600	if (rc == VINF_SUCCESS)
1601	{
1602	Assert(CPUMIsGuestFPUStateActive(pVM));
1603
1604	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1605
1606	/* Continue execution. */
1607	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1608	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1609
1610	goto ResumeExecution;
1611	}
1612
1613	Log(("Forward #NM fault to the guest\n"));
1614	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1615	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1616	AssertRC(rc);
1617	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1618	goto ResumeExecution;
1619	}
1620
1621	case X86_XCPT_PF: /* Page fault */
1622	{
1623	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1624	/* Exit qualification contains the linear address of the page fault. */
1625	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1626	TRPMSetErrorCode(pVM, errCode);
1627	TRPMSetFaultAddress(pVM, exitQualification);
1628
1629	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1630	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1631	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1632	if (rc == VINF_SUCCESS)
1633	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1634	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1635	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1636
1637	TRPMResetTrap(pVM);
1638
1639	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1640	goto ResumeExecution;
1641	}
1642	else
1643	if (rc == VINF_EM_RAW_GUEST_TRAP)
1644	{ /* A genuine pagefault.
1645	* Forward the trap to the guest by injecting the exception and resuming execution.
1646	*/
1647	Log2(("Forward page fault to the guest\n"));
1648	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1649	/* The error code might have been changed. */
1650	errCode = TRPMGetErrorCode(pVM);
1651
1652	TRPMResetTrap(pVM);
1653
1654	/* Now we must update CR2. */
1655	pCtx->cr2 = exitQualification;
1656	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1657	AssertRC(rc);
1658
1659	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1660	goto ResumeExecution;
1661	}
1662	#ifdef VBOX_STRICT
1663	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1664	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1665	#endif
1666	/* Need to go back to the recompiler to emulate the instruction. */
1667	TRPMResetTrap(pVM);
1668	break;
1669	}
1670
1671	case X86_XCPT_MF: /* Floating point exception. */
1672	{
1673	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1674	if (!(pCtx->cr0 & X86_CR0_NE))
1675	{
1676	/* old style FPU error reporting needs some extra work. */
1677	/** @todo don't fall back to the recompiler, but do it manually. */
1678	rc = VINF_EM_RAW_EMULATE_INSTR;
1679	break;
1680	}
1681	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1682	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1683	AssertRC(rc);
1684
1685	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1686	goto ResumeExecution;
1687	}
1688
1689	#ifdef VBOX_STRICT
1690	case X86_XCPT_GP: /* General protection failure exception.*/
1691	case X86_XCPT_UD: /* Unknown opcode exception. */
1692	case X86_XCPT_DE: /* Debug exception. */
1693	case X86_XCPT_SS: /* Stack segment exception. */
1694	case X86_XCPT_NP: /* Segment not present exception. */
1695	{
1696	switch(vector)
1697	{
1698	case X86_XCPT_DE:
1699	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1700	break;
1701	case X86_XCPT_UD:
1702	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1703	break;
1704	case X86_XCPT_SS:
1705	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1706	break;
1707	case X86_XCPT_NP:
1708	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1709	break;
1710	case X86_XCPT_GP:
1711	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1712	break;
1713	}
1714
1715	Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
1716	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1717	AssertRC(rc);
1718
1719	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1720	goto ResumeExecution;
1721	}
1722	#endif
1723	default:
1724	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1725	rc = VERR_EM_INTERNAL_ERROR;
1726	break;
1727	} /* switch (vector) */
1728
1729	break;
1730
1731	default:
1732	rc = VERR_EM_INTERNAL_ERROR;
1733	AssertFailed();
1734	break;
1735	}
1736
1737	break;
1738	}
1739
1740	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1741	/* Clear VM-exit on IF=1 change. */
1742	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1743	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1744	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1745	AssertRC(rc);
1746	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1747	goto ResumeExecution; /* we check for pending guest interrupts there */
1748
1749	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1750	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1751	/* Skip instruction and continue directly. */
1752	pCtx->rip += cbInstr;
1753	/* Continue execution.*/
1754	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1755	goto ResumeExecution;
1756
1757	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1758	{
1759	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1760	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1761	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1762	if (rc == VINF_SUCCESS)
1763	{
1764	/* Update EIP and continue execution. */
1765	Assert(cbInstr == 2);
1766	pCtx->rip += cbInstr;
1767	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1768	goto ResumeExecution;
1769	}
1770	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1771	rc = VINF_EM_RAW_EMULATE_INSTR;
1772	break;
1773	}
1774
1775	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1776	{
1777	Log2(("VMX: Rdtsc\n"));
1778	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1779	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1780	if (rc == VINF_SUCCESS)
1781	{
1782	/* Update EIP and continue execution. */
1783	Assert(cbInstr == 2);
1784	pCtx->rip += cbInstr;
1785	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1786	goto ResumeExecution;
1787	}
1788	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1789	rc = VINF_EM_RAW_EMULATE_INSTR;
1790	break;
1791	}
1792
1793	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1794	{
1795	Log2(("VMX: invlpg\n"));
1796	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1797	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1798	if (rc == VINF_SUCCESS)
1799	{
1800	/* Update EIP and continue execution. */
1801	pCtx->rip += cbInstr;
1802	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1803	goto ResumeExecution;
1804	}
1805	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1806	break;
1807	}
1808
1809	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1810	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1811	{
1812	uint32_t cbSize;
1813
1814	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1815	Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1816	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1817	if (rc == VINF_SUCCESS)
1818	{
1819	/* EIP has been updated already. */
1820
1821	/* Only resume if successful. */
1822	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1823	goto ResumeExecution;
1824	}
1825	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1826	break;
1827	}
1828
1829	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1830	{
1831	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1832	{
1833	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1834	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1835	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1836	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1837	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1838	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1839
1840	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1841	{
1842	case 0:
1843	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1844	break;
1845	case 2:
1846	break;
1847	case 3:
1848	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1849	break;
1850	case 4:
1851	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1852	break;
1853	case 8:
1854	/* CR8 contains the APIC TPR */
1855	Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1856	break;
1857
1858	default:
1859	AssertFailed();
1860	break;
1861	}
1862	/* Check if a sync operation is pending. */
1863	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1864	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1865	{
1866	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1867	AssertRC(rc);
1868	}
1869	break;
1870
1871	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1872	Log2(("VMX: mov x, crx\n"));
1873	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1874
1875	/* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1876	Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 \|\| !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1877
1878	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1879	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1880	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1881	break;
1882
1883	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1884	Log2(("VMX: clts\n"));
1885	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1886	rc = EMInterpretCLTS(pVM);
1887	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1888	break;
1889
1890	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1891	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1892	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1893	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1894	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1895	break;
1896	}
1897
1898	/* Update EIP if no error occurred. */
1899	if (VBOX_SUCCESS(rc))
1900	pCtx->rip += cbInstr;
1901
1902	if (rc == VINF_SUCCESS)
1903	{
1904	/* Only resume if successful. */
1905	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1906	goto ResumeExecution;
1907	}
1908	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1909	break;
1910	}
1911
1912	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1913	{
1914	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1915	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1916	{
1917	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1918	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1919	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1920	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1921	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1922	Log2(("DR7=%08x\n", pCtx->dr7));
1923	}
1924	else
1925	{
1926	Log2(("VMX: mov x, drx\n"));
1927	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1928	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1929	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1930	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1931	}
1932	/* Update EIP if no error occurred. */
1933	if (VBOX_SUCCESS(rc))
1934	pCtx->rip += cbInstr;
1935
1936	if (rc == VINF_SUCCESS)
1937	{
1938	/* Only resume if successful. */
1939	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1940	goto ResumeExecution;
1941	}
1942	Assert(rc == VERR_EM_INTERPRETER);
1943	break;
1944	}
1945
1946	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1947	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1948	{
1949	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1950	uint32_t uPort;
1951	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1952
1953	/** @todo necessary to make the distinction? */
1954	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1955	{
1956	uPort = pCtx->edx & 0xffff;
1957	}
1958	else
1959	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1960
1961	/* paranoia */
1962	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1963	{
1964	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1965	break;
1966	}
1967
1968	uint32_t cbSize = aIOSize[uIOWidth];
1969
1970	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1971	{
1972	/* ins/outs */
1973	uint32_t prefix = 0;
1974	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1975	prefix \|= PREFIX_REP;
1976
1977	if (fIOWrite)
1978	{
1979	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1980	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1981	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1982	}
1983	else
1984	{
1985	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1986	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1987	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1988	}
1989	}
1990	else
1991	{
1992	/* normal in/out */
1993	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1994
1995	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1996
1997	if (fIOWrite)
1998	{
1999	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2000	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2001	}
2002	else
2003	{
2004	uint32_t u32Val = 0;
2005
2006	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2007	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2008	if (IOM_SUCCESS(rc))
2009	{
2010	/* Write back to the EAX register. */
2011	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
2012	}
2013	}
2014	}
2015	/*
2016	* Handled the I/O return codes.
2017	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2018	*/
2019	if (IOM_SUCCESS(rc))
2020	{
2021	/* Update EIP and continue execution. */
2022	pCtx->rip += cbInstr;
2023	if (RT_LIKELY(rc == VINF_SUCCESS))
2024	{
2025	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2026	goto ResumeExecution;
2027	}
2028	break;
2029	}
2030
2031	#ifdef VBOX_STRICT
2032	if (rc == VINF_IOM_HC_IOPORT_READ)
2033	Assert(!fIOWrite);
2034	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2035	Assert(fIOWrite);
2036	else
2037	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2038	#endif
2039	break;
2040	}
2041
2042	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2043	LogFlow(("VMX_EXIT_TPR\n"));
2044	/* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2045	goto ResumeExecution;
2046
2047	default:
2048	/* The rest is handled after syncing the entire CPU state. */
2049	break;
2050	}
2051
2052	/* Note: the guest state isn't entirely synced back at this stage. */
2053
2054	/* Investigate why there was a VM-exit. (part 2) */
2055	switch (exitReason)
2056	{
2057	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2058	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2059	/* Already handled above. */
2060	break;
2061
2062	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2063	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2064	break;
2065
2066	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2067	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2068	rc = VINF_EM_RAW_INTERRUPT;
2069	AssertFailed(); /* Can't happen. Yet. */
2070	break;
2071
2072	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2073	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2074	rc = VINF_EM_RAW_INTERRUPT;
2075	AssertFailed(); /* Can't happen afaik. */
2076	break;
2077
2078	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2079	rc = VERR_EM_INTERPRETER;
2080	break;
2081
2082	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2083	/** Check if external interrupts are pending; if so, don't switch back. */
2084	pCtx->rip++; /* skip hlt */
2085	if ( pCtx->eflags.Bits.u1IF
2086	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
2087	goto ResumeExecution;
2088
2089	rc = VINF_EM_HALT;
2090	break;
2091
2092	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2093	AssertFailed(); /* can't happen. */
2094	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2095	break;
2096
2097	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2098	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2099	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2100	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2101	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2102	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2103	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2104	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2105	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2106	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2107	/** @todo inject #UD immediately */
2108	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2109	break;
2110
2111	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2112	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2113	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2114	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2115	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2116	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2117	/* already handled above */
2118	AssertMsg( rc == VINF_PGM_CHANGE_MODE
2119	\|\| rc == VINF_EM_RAW_INTERRUPT
2120	\|\| rc == VERR_EM_INTERPRETER
2121	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
2122	\|\| rc == VINF_PGM_SYNC_CR3
2123	\|\| rc == VINF_IOM_HC_IOPORT_READ
2124	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2125	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2126	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
2127	\|\| rc == VINF_EM_RESCHEDULE_REM,
2128	("rc = %d\n", rc));
2129	break;
2130
2131	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2132	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2133	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2134	/* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2135	rc = VERR_EM_INTERPRETER;
2136	break;
2137
2138	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2139	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2140	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2141	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2142	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2143	break;
2144
2145	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2146	Assert(rc == VINF_EM_RAW_INTERRUPT);
2147	break;
2148
2149	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2150	{
2151	#ifdef VBOX_STRICT
2152	Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2153
2154	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2155	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2156
2157	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2158	Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2159
2160	VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2161	Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2162
2163	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2164	Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2165
2166	VMX_LOG_SELREG(CS, "CS");
2167	VMX_LOG_SELREG(DS, "DS");
2168	VMX_LOG_SELREG(ES, "ES");
2169	VMX_LOG_SELREG(FS, "FS");
2170	VMX_LOG_SELREG(GS, "GS");
2171	VMX_LOG_SELREG(SS, "SS");
2172	VMX_LOG_SELREG(TR, "TR");
2173	VMX_LOG_SELREG(LDTR, "LDTR");
2174
2175	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2176	Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2177	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2178	Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2179	#endif /* VBOX_STRICT */
2180	rc = VERR_EM_INTERNAL_ERROR;
2181	break;
2182	}
2183
2184	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2185	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2186	default:
2187	rc = VERR_EM_INTERNAL_ERROR;
2188	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2189	break;
2190
2191	}
2192	end:
2193	if (fGuestStateSynced)
2194	{
2195	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2196	VMX_READ_SELREG(LDTR, ldtr);
2197	VMX_READ_SELREG(TR, tr);
2198
2199	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2200	pCtx->gdtr.cbGdt = val;
2201	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2202	pCtx->gdtr.pGdt = val;
2203
2204	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2205	pCtx->idtr.cbIdt = val;
2206	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2207	pCtx->idtr.pIdt = val;
2208	}
2209
2210	/* Signal changes for the recompiler. */
2211	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2212
2213	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2214	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2215	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2216	{
2217	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2218	/* On the next entry we'll only sync the host context. */
2219	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2220	}
2221	else
2222	{
2223	/* On the next entry we'll sync everything. */
2224	/** @todo we can do better than this */
2225	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2226	}
2227
2228	/* translate into a less severe return code */
2229	if (rc == VERR_EM_INTERPRETER)
2230	rc = VINF_EM_RAW_EMULATE_INSTR;
2231
2232	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2233	Log2(("X"));
2234	return rc;
2235	}
2236
2237
2238	/**
2239	* Enters the VT-x session
2240	*
2241	* @returns VBox status code.
2242	* @param pVM The VM to operate on.
2243	* @param pCpu CPU info struct
2244	*/
2245	HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2246	{
2247	Assert(pVM->hwaccm.s.vmx.fSupported);
2248
2249	unsigned cr4 = ASMGetCR4();
2250	if (!(cr4 & X86_CR4_VMXE))
2251	{
2252	AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2253	return VERR_VMX_X86_CR4_VMXE_CLEARED;
2254	}
2255
2256	/* Activate the VM Control Structure. */
2257	int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2258	if (VBOX_FAILURE(rc))
2259	return rc;
2260
2261	pVM->hwaccm.s.vmx.fResumeVM = false;
2262	return VINF_SUCCESS;
2263	}
2264
2265
2266	/**
2267	* Leaves the VT-x session
2268	*
2269	* @returns VBox status code.
2270	* @param pVM The VM to operate on.
2271	*/
2272	HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2273	{
2274	Assert(pVM->hwaccm.s.vmx.fSupported);
2275
2276	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2277	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2278	AssertRC(rc);
2279
2280	return VINF_SUCCESS;
2281	}
2282

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 11696

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