VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 11697

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1/* $Id: HWVMXR0.cpp 11697 2008-08-27 12:12:04Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43
44/* IO operation lookup arrays. */
45static uint32_t aIOSize[4] = {1, 2, 0, 4};
46static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49static void VMXR0CheckError(PVM pVM, int rc)
50{
51 if (rc == VERR_VMX_GENERIC)
52 {
53 RTCCUINTREG instrError;
54
55 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57 }
58 pVM->hwaccm.s.lLastError = rc;
59}
60
61/**
62 * Sets up and activates VT-x on the current CPU
63 *
64 * @returns VBox status code.
65 * @param pCpu CPU info struct
66 * @param pVM The VM to operate on.
67 * @param pvPageCpu Pointer to the global cpu page
68 * @param pPageCpuPhys Physical address of the global cpu page
69 */
70HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71{
72 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73 AssertReturn(pVM, VERR_INVALID_PARAMETER);
74 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76 /* Setup Intel VMX. */
77 Assert(pVM->hwaccm.s.vmx.fSupported);
78
79#ifdef LOG_ENABLED
80 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81#endif
82 /* Set revision dword at the beginning of the VMXON structure. */
83 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85 /* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86 * (which can have very bad consequences!!!)
87 */
88
89 /* Make sure the VMX instructions don't cause #UD faults. */
90 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
91
92 /* Enter VMX Root Mode */
93 int rc = VMXEnable(pPageCpuPhys);
94 if (VBOX_FAILURE(rc))
95 {
96 VMXR0CheckError(pVM, rc);
97 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98 return VERR_VMX_VMXON_FAILED;
99 }
100 return VINF_SUCCESS;
101}
102
103/**
104 * Deactivates VT-x on the current CPU
105 *
106 * @returns VBox status code.
107 * @param pCpu CPU info struct
108 * @param pvPageCpu Pointer to the global cpu page
109 * @param pPageCpuPhys Physical address of the global cpu page
110 */
111HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112{
113 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116 /* Leave VMX Root Mode. */
117 VMXDisable();
118
119 /* And clear the X86_CR4_VMXE bit */
120 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122#ifdef LOG_ENABLED
123 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124#endif
125 return VINF_SUCCESS;
126}
127
128/**
129 * Does Ring-0 per VM VT-x init.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135{
136 int rc;
137
138#ifdef LOG_ENABLED
139 SUPR0Printf("VMXR0InitVM %x\n", pVM);
140#endif
141 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
142 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
143 pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
144
145
146 /* Allocate one page for the VM control structure (VMCS). */
147 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
148 AssertRC(rc);
149 if (RT_FAILURE(rc))
150 return rc;
151
152 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
153 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
154 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
155
156 /* Allocate one page for the TSS we need for real mode emulation. */
157 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
158 AssertRC(rc);
159 if (RT_FAILURE(rc))
160 return rc;
161
162 pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
163 pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
164
165 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
166 * for I/O operations. */
167 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
168 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
169 /* Bit set to 0 means redirection enabled. */
170 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
171
172 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
173 {
174 /* Allocate one page for the virtual APIC mmio cache. */
175 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
176 AssertRC(rc);
177 if (RT_FAILURE(rc))
178 return rc;
179
180 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
181 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
182 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
183 }
184 else
185 {
186 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
187 pVM->hwaccm.s.vmx.pAPIC = 0;
188 pVM->hwaccm.s.vmx.pAPICPhys = 0;
189 }
190
191 /* Allocate the MSR bitmap if this feature is supported. */
192 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
193 {
194 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
195 AssertRC(rc);
196 if (RT_FAILURE(rc))
197 return rc;
198
199 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
200 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
201 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
202 }
203#ifdef LOG_ENABLED
204 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
205#endif
206 return VINF_SUCCESS;
207}
208
209/**
210 * Does Ring-0 per VM VT-x termination.
211 *
212 * @returns VBox status code.
213 * @param pVM The VM to operate on.
214 */
215HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
216{
217 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
218 {
219 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
220 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
221 pVM->hwaccm.s.vmx.pVMCS = 0;
222 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
223 }
224 if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS != NIL_RTR0MEMOBJ)
225 {
226 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
227 pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
228 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
229 pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
230 }
231 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
232 {
233 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
234 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
235 pVM->hwaccm.s.vmx.pAPIC = 0;
236 pVM->hwaccm.s.vmx.pAPICPhys = 0;
237 }
238 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
239 {
240 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
241 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
242 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
243 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
244 }
245 return VINF_SUCCESS;
246}
247
248/**
249 * Sets up VT-x for the specified VM
250 *
251 * @returns VBox status code.
252 * @param pVM The VM to operate on.
253 */
254HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
255{
256 int rc = VINF_SUCCESS;
257 uint32_t val;
258
259 AssertReturn(pVM, VERR_INVALID_PARAMETER);
260 Assert(pVM->hwaccm.s.vmx.pVMCS);
261
262 /* Set revision dword at the beginning of the VMCS structure. */
263 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
264
265 /* Clear VM Control Structure. */
266 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
267 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
268 if (VBOX_FAILURE(rc))
269 goto vmx_end;
270
271 /* Activate the VM Control Structure. */
272 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
273 if (VBOX_FAILURE(rc))
274 goto vmx_end;
275
276 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
277 * Set required bits to one and zero according to the MSR capabilities.
278 */
279 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
280 /* External and non-maskable interrupts cause VM-exits. */
281 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
282 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
283
284 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
285 AssertRC(rc);
286
287 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
288 * Set required bits to one and zero according to the MSR capabilities.
289 */
290 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
291 /* Program which event cause VM-exits and which features we want to use. */
292 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
293 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
294 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
295 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
296 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
297 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
298
299 /** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
300
301#if HC_ARCH_BITS == 64
302 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
303 {
304 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
305 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
306 Assert(pVM->hwaccm.s.vmx.pAPIC);
307 }
308 else
309 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
310 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
311#endif
312
313 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
314 {
315 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
316 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
317 }
318
319 /* Mask away the bits that the CPU doesn't support */
320 /** @todo make sure they don't conflict with the above requirements. */
321 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
322 pVM->hwaccm.s.vmx.proc_ctls = val;
323
324 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
325 AssertRC(rc);
326
327 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
328 * Set required bits to one and zero according to the MSR capabilities.
329 */
330 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
331 AssertRC(rc);
332
333 /* VMX_VMCS_CTRL_EXIT_CONTROLS
334 * Set required bits to one and zero according to the MSR capabilities.
335 */
336 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
337#if HC_ARCH_BITS == 64
338 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
339#else
340 /* else Must be zero when AMD64 is not available. */
341#endif
342 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
343 /* Don't acknowledge external interrupts on VM-exit. */
344 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
345 AssertRC(rc);
346
347 /* Forward all exception except #NM & #PF to the guest.
348 * We always need to check pagefaults since our shadow page table can be out of sync.
349 * And we always lazily sync the FPU & XMM state.
350 */
351
352 /*
353 * @todo Possible optimization:
354 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
355 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
356 * registers ourselves of course.
357 *
358 * @note only possible if the current state is actually ours (X86_CR0_TS flag)
359 */
360 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
361 AssertRC(rc);
362
363 /* Don't filter page faults; all of them should cause a switch. */
364 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
365 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
366 AssertRC(rc);
367
368 /* Init TSC offset to zero. */
369 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
370#if HC_ARCH_BITS == 32
371 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
372#endif
373 AssertRC(rc);
374
375 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
376#if HC_ARCH_BITS == 32
377 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
378#endif
379 AssertRC(rc);
380
381 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
382#if HC_ARCH_BITS == 32
383 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
384#endif
385 AssertRC(rc);
386
387 /* Set the MSR bitmap address. */
388 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
389 {
390 /* Optional */
391 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
392#if HC_ARCH_BITS == 32
393 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32);
394#endif
395 AssertRC(rc);
396 }
397
398 /* Clear MSR controls. */
399 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
400 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
401 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
402#if HC_ARCH_BITS == 32
403 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
404 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
405 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
406#endif
407 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
408 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
409 AssertRC(rc);
410
411 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
412 {
413 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
414 /* Optional */
415 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
416 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
417#if HC_ARCH_BITS == 32
418 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
419#endif
420 AssertRC(rc);
421 }
422
423 /* Set link pointer to -1. Not currently used. */
424#if HC_ARCH_BITS == 32
425 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
426 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
427#else
428 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
429#endif
430 AssertRC(rc);
431
432 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
433 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
434 AssertRC(rc);
435
436vmx_end:
437 VMXR0CheckError(pVM, rc);
438 return rc;
439}
440
441
442/**
443 * Injects an event (trap or external interrupt)
444 *
445 * @returns VBox status code.
446 * @param pVM The VM to operate on.
447 * @param pCtx CPU Context
448 * @param intInfo VMX interrupt info
449 * @param cbInstr Opcode length of faulting instruction
450 * @param errCode Error code (optional)
451 */
452static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
453{
454 int rc;
455
456#ifdef VBOX_STRICT
457 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
458 if (iGate == 0xE)
459 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
460 else
461 if (iGate < 0x20)
462 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
463 else
464 {
465 Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
466 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
467 Assert(pCtx->eflags.u32 & X86_EFL_IF);
468 }
469#endif
470
471 /* Set event injection state. */
472 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
473 intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
474 );
475
476 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
477 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
478
479 AssertRC(rc);
480 return rc;
481}
482
483
484/**
485 * Checks for pending guest interrupts and injects them
486 *
487 * @returns VBox status code.
488 * @param pVM The VM to operate on.
489 * @param pCtx CPU Context
490 */
491static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
492{
493 int rc;
494
495 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
496 if (pVM->hwaccm.s.Event.fPending)
497 {
498 Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
499 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
500 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
501 AssertRC(rc);
502
503 pVM->hwaccm.s.Event.fPending = false;
504 return VINF_SUCCESS;
505 }
506
507 /* When external interrupts are pending, we should exit the VM when IF is set. */
508 if ( !TRPMHasTrap(pVM)
509 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
510 {
511 if (!(pCtx->eflags.u32 & X86_EFL_IF))
512 {
513 Log2(("Enable irq window exit!\n"));
514 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
515 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
516 AssertRC(rc);
517 }
518 else
519 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
520 {
521 uint8_t u8Interrupt;
522
523 rc = PDMGetInterrupt(pVM, &u8Interrupt);
524 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
525 if (VBOX_SUCCESS(rc))
526 {
527 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
528 AssertRC(rc);
529 }
530 else
531 {
532 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
533 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
534 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
535 /* Just continue */
536 }
537 }
538 else
539 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
540 }
541
542#ifdef VBOX_STRICT
543 if (TRPMHasTrap(pVM))
544 {
545 uint8_t u8Vector;
546 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
547 AssertRC(rc);
548 }
549#endif
550
551 if ( pCtx->eflags.u32 & X86_EFL_IF
552 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
553 && TRPMHasTrap(pVM)
554 )
555 {
556 uint8_t u8Vector;
557 int rc;
558 TRPMEVENT enmType;
559 RTGCUINTPTR intInfo;
560 RTGCUINT errCode;
561
562 /* If a new event is pending, then dispatch it now. */
563 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
564 AssertRC(rc);
565 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
566 Assert(enmType != TRPM_SOFTWARE_INT);
567
568 /* Clear the pending trap. */
569 rc = TRPMResetTrap(pVM);
570 AssertRC(rc);
571
572 intInfo = u8Vector;
573 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
574
575 if (enmType == TRPM_TRAP)
576 {
577 switch (u8Vector) {
578 case 8:
579 case 10:
580 case 11:
581 case 12:
582 case 13:
583 case 14:
584 case 17:
585 /* Valid error codes. */
586 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
587 break;
588 default:
589 break;
590 }
591 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
592 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
593 else
594 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
595 }
596 else
597 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
598
599 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
600 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
601 AssertRC(rc);
602 } /* if (interrupts can be dispatched) */
603
604 return VINF_SUCCESS;
605}
606
607/**
608 * Save the host state
609 *
610 * @returns VBox status code.
611 * @param pVM The VM to operate on.
612 */
613HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
614{
615 int rc = VINF_SUCCESS;
616
617 /*
618 * Host CPU Context
619 */
620 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
621 {
622 RTIDTR idtr;
623 RTGDTR gdtr;
624 RTSEL SelTR;
625 PX86DESCHC pDesc;
626 uintptr_t trBase;
627
628 /* Control registers */
629 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
630 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
631 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
632 AssertRC(rc);
633 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
634 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
635 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
636
637 /* Selector registers. */
638 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
639 /** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
640 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
641 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
642#if HC_ARCH_BITS == 32
643 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
644 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
645#endif
646 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
647 SelTR = ASMGetTR();
648 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
649 AssertRC(rc);
650 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
651 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
652 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
653 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
654 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
655 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
656 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
657
658 /* GDTR & IDTR */
659 ASMGetGDTR(&gdtr);
660 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
661 ASMGetIDTR(&idtr);
662 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
663 AssertRC(rc);
664 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
665 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
666
667 /* Save the base address of the TR selector. */
668 if (SelTR > gdtr.cbGdt)
669 {
670 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
671 return VERR_VMX_INVALID_HOST_STATE;
672 }
673
674 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
675#if HC_ARCH_BITS == 64
676 trBase = X86DESC64_BASE(*pDesc);
677#else
678 trBase = X86DESC_BASE(*pDesc);
679#endif
680 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
681 AssertRC(rc);
682 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
683
684 /* FS and GS base. */
685#if HC_ARCH_BITS == 64
686 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
687 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
688 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
689 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
690#endif
691 AssertRC(rc);
692
693 /* Sysenter MSRs. */
694 /** @todo expensive!! */
695 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
696 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
697#if HC_ARCH_BITS == 32
698 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
699 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
700 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
701 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
702#else
703 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
704 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
705 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
706 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
707#endif
708 AssertRC(rc);
709
710 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
711 }
712 return rc;
713}
714
715
716/**
717 * Loads the guest state
718 *
719 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
720 *
721 * @returns VBox status code.
722 * @param pVM The VM to operate on.
723 * @param pCtx Guest context
724 */
725HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
726{
727 int rc = VINF_SUCCESS;
728 RTGCUINTPTR val;
729 X86EFLAGS eflags;
730
731 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
732 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
733 {
734 VMX_WRITE_SELREG(ES, es);
735 AssertRC(rc);
736
737 VMX_WRITE_SELREG(CS, cs);
738 AssertRC(rc);
739
740 VMX_WRITE_SELREG(SS, ss);
741 AssertRC(rc);
742
743 VMX_WRITE_SELREG(DS, ds);
744 AssertRC(rc);
745
746 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
747 VMX_WRITE_SELREG(FS, fs);
748 AssertRC(rc);
749
750 VMX_WRITE_SELREG(GS, gs);
751 AssertRC(rc);
752 }
753
754 /* Guest CPU context: LDTR. */
755 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
756 {
757 if (pCtx->ldtr == 0)
758 {
759 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
760 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
761 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
762 /** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
763 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
764 }
765 else
766 {
767 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
768 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
769 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
770 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
771 }
772 AssertRC(rc);
773 }
774 /* Guest CPU context: TR. */
775 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
776 {
777 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
778
779 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
780 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
781 {
782 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
783 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
784 }
785 else
786 {
787 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
788 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
789 }
790 val = pCtx->trHid.Attr.u;
791
792 /* The TSS selector must be busy. */
793 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
794 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
795 else
796 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
797 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
798
799 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
800 AssertRC(rc);
801 }
802 /* Guest CPU context: GDTR. */
803 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
804 {
805 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
806 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
807 AssertRC(rc);
808 }
809 /* Guest CPU context: IDTR. */
810 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
811 {
812 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
813 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
814 AssertRC(rc);
815 }
816
817 /*
818 * Sysenter MSRs (unconditional)
819 */
820 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
821 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
822 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
823 AssertRC(rc);
824
825 /* Control registers */
826 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
827 {
828 val = pCtx->cr0;
829 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
830 Log2(("Guest CR0-shadow %08x\n", val));
831 if (CPUMIsGuestFPUStateActive(pVM) == false)
832 {
833 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
834 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
835 }
836 else
837 {
838 /** @todo check if we support the old style mess correctly. */
839 if (!(val & X86_CR0_NE))
840 {
841 Log(("Forcing X86_CR0_NE!!!\n"));
842
843 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
844 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
845 {
846 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK | RT_BIT(X86_XCPT_MF));
847 AssertRC(rc);
848 pVM->hwaccm.s.fFPUOldStyleOverride = true;
849 }
850 }
851
852 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
853 }
854 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
855 val |= X86_CR0_PE | X86_CR0_PG;
856 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
857 val |= X86_CR0_WP;
858
859 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
860 Log2(("Guest CR0 %08x\n", val));
861 /* CR0 flags owned by the host; if the guests attempts to change them, then
862 * the VM will exit.
863 */
864 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
865 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
866 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
867 | X86_CR0_TS
868 | X86_CR0_ET
869 | X86_CR0_NE
870 | X86_CR0_MP;
871 pVM->hwaccm.s.vmx.cr0_mask = val;
872
873 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
874 Log2(("Guest CR0-mask %08x\n", val));
875 AssertRC(rc);
876 }
877 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
878 {
879 /* CR4 */
880 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
881 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
882 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
883 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
884 switch(pVM->hwaccm.s.enmShadowMode)
885 {
886 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
887 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
888 case PGMMODE_32_BIT: /* 32-bit paging. */
889 break;
890
891 case PGMMODE_PAE: /* PAE paging. */
892 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
893 /** @todo use normal 32 bits paging */
894 val |= X86_CR4_PAE;
895 break;
896
897 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
898 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
899#ifdef VBOX_ENABLE_64_BITS_GUESTS
900 break;
901#else
902 AssertFailed();
903 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
904#endif
905 default: /* shut up gcc */
906 AssertFailed();
907 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
908 }
909 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
910 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
911 val |= X86_CR4_VME;
912
913 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
914 Log2(("Guest CR4 %08x\n", val));
915 /* CR4 flags owned by the host; if the guests attempts to change them, then
916 * the VM will exit.
917 */
918 val = X86_CR4_PAE
919 | X86_CR4_PGE
920 | X86_CR4_PSE
921 | X86_CR4_VMXE;
922 pVM->hwaccm.s.vmx.cr4_mask = val;
923
924 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
925 Log2(("Guest CR4-mask %08x\n", val));
926 AssertRC(rc);
927 }
928
929 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
930 {
931 /* Save our shadow CR3 register. */
932 val = PGMGetHyperCR3(pVM);
933 Assert(val);
934 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
935 AssertRC(rc);
936 }
937
938 /* Debug registers. */
939 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
940 {
941 val = pCtx->dr7 & 0xffffffff; /* upper 32 bits reserved */
942 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
943 val |= 0x400; /* must be one */
944 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
945 AssertRC(rc);
946
947 /* IA32_DEBUGCTL MSR. */
948 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
949 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
950 AssertRC(rc);
951
952 /** @todo do we really ever need this? */
953 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
954 AssertRC(rc);
955 }
956
957 /* EIP, ESP and EFLAGS */
958 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
959 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
960 AssertRC(rc);
961
962 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
963 eflags = pCtx->eflags;
964 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
965 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
966
967 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
968 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
969 {
970 eflags.Bits.u1VM = 1;
971 eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
972 eflags.Bits.u2IOPL = 3;
973 }
974
975 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
976 AssertRC(rc);
977
978 /** TSC offset. */
979 uint64_t u64TSCOffset;
980
981 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
982 {
983 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
984#if HC_ARCH_BITS == 64
985 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
986#else
987 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
988 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
989#endif
990 AssertRC(rc);
991
992 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
993 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
994 AssertRC(rc);
995 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
996 }
997 else
998 {
999 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1000 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1001 AssertRC(rc);
1002 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1003 }
1004
1005 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1006 * Set required bits to one and zero according to the MSR capabilities.
1007 */
1008 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1009 /* 64 bits guest mode? */
1010 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1011 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1012 /* else Must be zero when AMD64 is not available. */
1013
1014 /* Mask away the bits that the CPU doesn't support */
1015 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1016 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1017 AssertRC(rc);
1018
1019 /* 64 bits guest mode? */
1020 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1021 {
1022#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
1023 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1024#else
1025 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1026#endif
1027 /* Unconditionally update these as wrmsr might have changed them. */
1028 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1029 AssertRC(rc);
1030 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1031 AssertRC(rc);
1032 }
1033 else
1034 {
1035 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1036 }
1037
1038 /* Done. */
1039 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1040
1041 return rc;
1042}
1043
1044/**
1045 * Runs guest code in a VT-x VM.
1046 *
1047 * @returns VBox status code.
1048 * @param pVM The VM to operate on.
1049 * @param pCtx Guest context
1050 */
1051HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1052{
1053 int rc = VINF_SUCCESS;
1054 RTCCUINTREG val, valShadow;
1055 RTCCUINTREG exitReason, instrError, cbInstr;
1056 RTGCUINTPTR exitQualification;
1057 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1058 RTGCUINTPTR errCode, instrInfo, uInterruptState;
1059 bool fGuestStateSynced = false;
1060 bool fSyncTPR = false;
1061 unsigned cResume = 0;
1062#ifdef VBOX_STRICT
1063 RTCPUID idCpuCheck;
1064#endif
1065
1066 Log2(("\nE"));
1067
1068 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1069
1070#ifdef VBOX_STRICT
1071 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1072 AssertRC(rc);
1073 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1074
1075 /* allowed zero */
1076 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1077 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1078
1079 /* allowed one */
1080 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1081 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1082
1083 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1084 AssertRC(rc);
1085 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1086
1087 /* allowed zero */
1088 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1089 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1090
1091 /* allowed one */
1092 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1093 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1094
1095 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1096 AssertRC(rc);
1097 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1098
1099 /* allowed zero */
1100 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1101 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1102
1103 /* allowed one */
1104 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1105 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1106
1107 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1108 AssertRC(rc);
1109 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1110
1111 /* allowed zero */
1112 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1113 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1114
1115 /* allowed one */
1116 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1117 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1118#endif
1119
1120#if 0
1121 /*
1122 * Check if debug registers are armed.
1123 */
1124 uint32_t u32DR7 = ASMGetDR7();
1125 if (u32DR7 & X86_DR7_ENABLED_MASK)
1126 {
1127 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
1128 }
1129 else
1130 pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1131#endif
1132
1133 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1134 */
1135ResumeExecution:
1136 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1137 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1138 {
1139 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1140 rc = VINF_EM_RAW_INTERRUPT;
1141 goto end;
1142 }
1143
1144 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1145 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1146 {
1147 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1148 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1149 {
1150 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1151 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1152 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1153 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1154 */
1155 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1156 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1157 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1158 AssertRC(rc);
1159 }
1160 }
1161 else
1162 {
1163 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1164 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1165 AssertRC(rc);
1166 }
1167
1168 /* Check for pending actions that force us to go back to ring 3. */
1169 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1170 {
1171 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1172 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1173 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1174 rc = VINF_EM_RAW_TO_R3;
1175 goto end;
1176 }
1177 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1178 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1179 {
1180 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1181 rc = VINF_EM_PENDING_REQUEST;
1182 goto end;
1183 }
1184
1185 /* When external interrupts are pending, we should exit the VM when IF is set. */
1186 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
1187 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1188 if (VBOX_FAILURE(rc))
1189 {
1190 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1191 goto end;
1192 }
1193
1194 /** @todo check timers?? */
1195
1196 /* TPR caching using CR8 is only available in 64 bits mode */
1197 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1198 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1199 /*
1200 * @todo reduce overhead
1201 */
1202 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1203 && pVM->hwaccm.s.vmx.pAPIC)
1204 {
1205 /* TPR caching in CR8 */
1206 uint8_t u8TPR;
1207 bool fPending;
1208
1209 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1210 AssertRC(rc);
1211 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1212 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1213
1214 /* Two options here:
1215 * - external interrupt pending, but masked by the TPR value.
1216 * -> a CR8 update that lower the current TPR value should cause an exit
1217 * - no pending interrupts
1218 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1219 */
1220 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1221 AssertRC(rc);
1222
1223 /* Always sync back the TPR; we should optimize this though (@todo) */
1224 fSyncTPR = true;
1225 }
1226
1227 /*
1228 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1229 * (until the actual world switch)
1230 */
1231#ifdef VBOX_STRICT
1232 idCpuCheck = RTMpCpuId();
1233#endif
1234 /* Save the host state first. */
1235 rc = VMXR0SaveHostState(pVM);
1236 if (rc != VINF_SUCCESS)
1237 {
1238 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1239 goto end;
1240 }
1241 /* Load the guest state */
1242 rc = VMXR0LoadGuestState(pVM, pCtx);
1243 if (rc != VINF_SUCCESS)
1244 {
1245 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1246 goto end;
1247 }
1248 fGuestStateSynced = true;
1249
1250 /* Non-register state Guest Context */
1251 /** @todo change me according to cpu state */
1252 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1253 AssertRC(rc);
1254
1255 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1256
1257 /* Manual save and restore:
1258 * - General purpose registers except RIP, RSP
1259 *
1260 * Trashed:
1261 * - CR2 (we don't care)
1262 * - LDTR (reset to 0)
1263 * - DRx (presumably not changed at all)
1264 * - DR7 (reset to 0x400)
1265 * - EFLAGS (reset to RT_BIT(1); not relevant)
1266 *
1267 */
1268
1269 /* All done! Let's start VM execution. */
1270 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1271#ifdef VBOX_STRICT
1272 Assert(idCpuCheck == RTMpCpuId());
1273#endif
1274 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1275
1276 /* In case we execute a goto ResumeExecution later on. */
1277 pVM->hwaccm.s.vmx.fResumeVM = true;
1278
1279 /**
1280 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1281 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1282 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1283 */
1284
1285 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1286 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1287
1288 switch (rc)
1289 {
1290 case VINF_SUCCESS:
1291 break;
1292
1293 case VERR_VMX_INVALID_VMXON_PTR:
1294 AssertFailed();
1295 goto end;
1296
1297 case VERR_VMX_UNABLE_TO_START_VM:
1298 case VERR_VMX_UNABLE_TO_RESUME_VM:
1299 {
1300#ifdef VBOX_STRICT
1301 int rc1;
1302
1303 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1304 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1305 AssertRC(rc1);
1306 if (rc1 == VINF_SUCCESS)
1307 {
1308 RTGDTR gdtr;
1309 PX86DESCHC pDesc;
1310
1311 ASMGetGDTR(&gdtr);
1312
1313 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1314 Log(("Current stack %08x\n", &rc1));
1315
1316
1317 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1318 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1319 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1320 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1321 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1322 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1323 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1324 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1325 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1326 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1327
1328 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1329 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1330
1331 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1332 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1333
1334 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1335 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1336
1337 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1338 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1339 if (val < gdtr.cbGdt)
1340 {
1341 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1342 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1343 }
1344
1345 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1346 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1347 if (val < gdtr.cbGdt)
1348 {
1349 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1350 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1351 }
1352
1353 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1354 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1355 if (val < gdtr.cbGdt)
1356 {
1357 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1358 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1359 }
1360
1361 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1362 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1363 if (val < gdtr.cbGdt)
1364 {
1365 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1366 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1367 }
1368
1369 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1370 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1371 if (val < gdtr.cbGdt)
1372 {
1373 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1374 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1375 }
1376
1377 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1378 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1379 if (val < gdtr.cbGdt)
1380 {
1381 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1382 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1383 }
1384
1385 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1386 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1387 if (val < gdtr.cbGdt)
1388 {
1389 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1390 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1391 }
1392
1393 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1394 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1395
1396 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1397 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1398 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1399 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1400
1401 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1402 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1403
1404 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1405 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1406
1407 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1408 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1409
1410 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1411 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1412 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1413 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1414
1415#if HC_ARCH_BITS == 64
1416 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1417 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1418 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1419 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1420 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1421#endif
1422 }
1423#endif /* VBOX_STRICT */
1424 goto end;
1425 }
1426
1427 default:
1428 /* impossible */
1429 AssertFailed();
1430 goto end;
1431 }
1432 /* Success. Query the guest state and figure out what has happened. */
1433
1434 /* Investigate why there was a VM-exit. */
1435 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1436 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1437
1438 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1439 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1440 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1441 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1442 intInfo = val;
1443 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1444 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1445 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1446 instrInfo = val;
1447 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1448 exitQualification = val;
1449 AssertRC(rc);
1450
1451 /* Let's first sync back eip, esp, and eflags. */
1452 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1453 AssertRC(rc);
1454 pCtx->rip = val;
1455 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1456 AssertRC(rc);
1457 pCtx->rsp = val;
1458 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1459 AssertRC(rc);
1460 pCtx->eflags.u32 = val;
1461
1462 /* Take care of instruction fusing (sti, mov ss) */
1463 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1464 uInterruptState = val;
1465 if (uInterruptState != 0)
1466 {
1467 Assert(uInterruptState <= 2); /* only sti & mov ss */
1468 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1469 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1470 }
1471 else
1472 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1473
1474 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1475 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1476 {
1477 /* Hide our emulation flags */
1478 pCtx->eflags.Bits.u1VM = 0;
1479 pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1480 pCtx->eflags.Bits.u1VIF = 0;
1481 pCtx->eflags.Bits.u2IOPL = 0;
1482 }
1483
1484 /* Control registers. */
1485 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1486 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1487 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1488 CPUMSetGuestCR0(pVM, val);
1489
1490 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1491 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1492 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1493 CPUMSetGuestCR4(pVM, val);
1494
1495 CPUMSetGuestCR2(pVM, ASMGetCR2());
1496
1497 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1498 CPUMSetGuestDR7(pVM, val);
1499
1500 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1501 VMX_READ_SELREG(ES, es);
1502 VMX_READ_SELREG(SS, ss);
1503 VMX_READ_SELREG(CS, cs);
1504 VMX_READ_SELREG(DS, ds);
1505 VMX_READ_SELREG(FS, fs);
1506 VMX_READ_SELREG(GS, gs);
1507
1508 /*
1509 * System MSRs
1510 */
1511 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1512 pCtx->SysEnter.cs = val;
1513 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1514 pCtx->SysEnter.eip = val;
1515 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1516 pCtx->SysEnter.esp = val;
1517
1518 /** @note NOW IT'S SAFE FOR LOGGING! */
1519 Log2(("Raw exit reason %08x\n", exitReason));
1520
1521 /* Check if an injected event was interrupted prematurely. */
1522 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1523 AssertRC(rc);
1524 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1525 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1526 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1527 {
1528 pVM->hwaccm.s.Event.fPending = true;
1529 /* Error code present? */
1530 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1531 {
1532 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1533 AssertRC(rc);
1534 pVM->hwaccm.s.Event.errCode = val;
1535 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1536 }
1537 else
1538 {
1539 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1540 pVM->hwaccm.s.Event.errCode = 0;
1541 }
1542 }
1543
1544#ifdef VBOX_STRICT
1545 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1546 HWACCMDumpRegs(pVM, pCtx);
1547#endif
1548
1549 Log2(("E%d", exitReason));
1550 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1551 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1552 Log2(("Interruption error code %d\n", errCode));
1553 Log2(("IntInfo = %08x\n", intInfo));
1554 Log2(("New EIP=%VGv\n", pCtx->rip));
1555
1556 if (fSyncTPR)
1557 {
1558 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1559 AssertRC(rc);
1560 }
1561
1562 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1563 switch (exitReason)
1564 {
1565 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1566 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1567 {
1568 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1569
1570 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1571 {
1572 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1573 /* External interrupt; leave to allow it to be dispatched again. */
1574 rc = VINF_EM_RAW_INTERRUPT;
1575 break;
1576 }
1577 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1578 {
1579 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1580 /* External interrupt; leave to allow it to be dispatched again. */
1581 rc = VINF_EM_RAW_INTERRUPT;
1582 break;
1583
1584 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1585 AssertFailed(); /* can't come here; fails the first check. */
1586 break;
1587
1588 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1589 Assert(vector == 3 || vector == 4);
1590 /* no break */
1591 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1592 Log2(("Hardware/software interrupt %d\n", vector));
1593 switch (vector)
1594 {
1595 case X86_XCPT_NM:
1596 {
1597 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1598
1599 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1600 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1601 rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1602 if (rc == VINF_SUCCESS)
1603 {
1604 Assert(CPUMIsGuestFPUStateActive(pVM));
1605
1606 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1607
1608 /* Continue execution. */
1609 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1610 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1611
1612 goto ResumeExecution;
1613 }
1614
1615 Log(("Forward #NM fault to the guest\n"));
1616 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1617 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1618 AssertRC(rc);
1619 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1620 goto ResumeExecution;
1621 }
1622
1623 case X86_XCPT_PF: /* Page fault */
1624 {
1625 Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1626 /* Exit qualification contains the linear address of the page fault. */
1627 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1628 TRPMSetErrorCode(pVM, errCode);
1629 TRPMSetFaultAddress(pVM, exitQualification);
1630
1631 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1632 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1633 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1634 if (rc == VINF_SUCCESS)
1635 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1636 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1637 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1638
1639 TRPMResetTrap(pVM);
1640
1641 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1642 goto ResumeExecution;
1643 }
1644 else
1645 if (rc == VINF_EM_RAW_GUEST_TRAP)
1646 { /* A genuine pagefault.
1647 * Forward the trap to the guest by injecting the exception and resuming execution.
1648 */
1649 Log2(("Forward page fault to the guest\n"));
1650 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1651 /* The error code might have been changed. */
1652 errCode = TRPMGetErrorCode(pVM);
1653
1654 TRPMResetTrap(pVM);
1655
1656 /* Now we must update CR2. */
1657 pCtx->cr2 = exitQualification;
1658 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1659 AssertRC(rc);
1660
1661 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1662 goto ResumeExecution;
1663 }
1664#ifdef VBOX_STRICT
1665 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1666 Log2(("PGMTrap0eHandler failed with %d\n", rc));
1667#endif
1668 /* Need to go back to the recompiler to emulate the instruction. */
1669 TRPMResetTrap(pVM);
1670 break;
1671 }
1672
1673 case X86_XCPT_MF: /* Floating point exception. */
1674 {
1675 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1676 if (!(pCtx->cr0 & X86_CR0_NE))
1677 {
1678 /* old style FPU error reporting needs some extra work. */
1679 /** @todo don't fall back to the recompiler, but do it manually. */
1680 rc = VINF_EM_RAW_EMULATE_INSTR;
1681 break;
1682 }
1683 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1684 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1685 AssertRC(rc);
1686
1687 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1688 goto ResumeExecution;
1689 }
1690
1691#ifdef VBOX_STRICT
1692 case X86_XCPT_GP: /* General protection failure exception.*/
1693 case X86_XCPT_UD: /* Unknown opcode exception. */
1694 case X86_XCPT_DE: /* Debug exception. */
1695 case X86_XCPT_SS: /* Stack segment exception. */
1696 case X86_XCPT_NP: /* Segment not present exception. */
1697 {
1698 switch(vector)
1699 {
1700 case X86_XCPT_DE:
1701 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1702 break;
1703 case X86_XCPT_UD:
1704 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1705 break;
1706 case X86_XCPT_SS:
1707 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1708 break;
1709 case X86_XCPT_NP:
1710 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1711 break;
1712 case X86_XCPT_GP:
1713 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1714 break;
1715 }
1716
1717 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
1718 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1719 AssertRC(rc);
1720
1721 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1722 goto ResumeExecution;
1723 }
1724#endif
1725 default:
1726 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1727 rc = VERR_EM_INTERNAL_ERROR;
1728 break;
1729 } /* switch (vector) */
1730
1731 break;
1732
1733 default:
1734 rc = VERR_EM_INTERNAL_ERROR;
1735 AssertFailed();
1736 break;
1737 }
1738
1739 break;
1740 }
1741
1742 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1743 /* Clear VM-exit on IF=1 change. */
1744 Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1745 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1746 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1747 AssertRC(rc);
1748 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1749 goto ResumeExecution; /* we check for pending guest interrupts there */
1750
1751 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1752 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1753 /* Skip instruction and continue directly. */
1754 pCtx->rip += cbInstr;
1755 /* Continue execution.*/
1756 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1757 goto ResumeExecution;
1758
1759 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1760 {
1761 Log2(("VMX: Cpuid %x\n", pCtx->eax));
1762 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1763 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1764 if (rc == VINF_SUCCESS)
1765 {
1766 /* Update EIP and continue execution. */
1767 Assert(cbInstr == 2);
1768 pCtx->rip += cbInstr;
1769 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1770 goto ResumeExecution;
1771 }
1772 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1773 rc = VINF_EM_RAW_EMULATE_INSTR;
1774 break;
1775 }
1776
1777 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1778 {
1779 Log2(("VMX: Rdtsc\n"));
1780 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1781 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1782 if (rc == VINF_SUCCESS)
1783 {
1784 /* Update EIP and continue execution. */
1785 Assert(cbInstr == 2);
1786 pCtx->rip += cbInstr;
1787 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1788 goto ResumeExecution;
1789 }
1790 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1791 rc = VINF_EM_RAW_EMULATE_INSTR;
1792 break;
1793 }
1794
1795 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1796 {
1797 Log2(("VMX: invlpg\n"));
1798 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1799 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1800 if (rc == VINF_SUCCESS)
1801 {
1802 /* Update EIP and continue execution. */
1803 pCtx->rip += cbInstr;
1804 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1805 goto ResumeExecution;
1806 }
1807 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1808 break;
1809 }
1810
1811 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1812 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1813 {
1814 uint32_t cbSize;
1815
1816 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1817 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1818 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1819 if (rc == VINF_SUCCESS)
1820 {
1821 /* EIP has been updated already. */
1822
1823 /* Only resume if successful. */
1824 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1825 goto ResumeExecution;
1826 }
1827 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1828 break;
1829 }
1830
1831 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1832 {
1833 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1834 {
1835 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1836 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1837 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1838 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1839 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1840 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1841
1842 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1843 {
1844 case 0:
1845 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1846 break;
1847 case 2:
1848 break;
1849 case 3:
1850 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1851 break;
1852 case 4:
1853 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1854 break;
1855 case 8:
1856 /* CR8 contains the APIC TPR */
1857 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1858 break;
1859
1860 default:
1861 AssertFailed();
1862 break;
1863 }
1864 /* Check if a sync operation is pending. */
1865 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1866 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1867 {
1868 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1869 AssertRC(rc);
1870 }
1871 break;
1872
1873 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1874 Log2(("VMX: mov x, crx\n"));
1875 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1876
1877 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1878 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1879
1880 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1881 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1882 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1883 break;
1884
1885 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1886 Log2(("VMX: clts\n"));
1887 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1888 rc = EMInterpretCLTS(pVM);
1889 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1890 break;
1891
1892 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1893 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1894 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1895 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1896 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1897 break;
1898 }
1899
1900 /* Update EIP if no error occurred. */
1901 if (VBOX_SUCCESS(rc))
1902 pCtx->rip += cbInstr;
1903
1904 if (rc == VINF_SUCCESS)
1905 {
1906 /* Only resume if successful. */
1907 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1908 goto ResumeExecution;
1909 }
1910 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1911 break;
1912 }
1913
1914 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1915 {
1916 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1917 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1918 {
1919 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1920 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1921 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1922 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1923 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1924 Log2(("DR7=%08x\n", pCtx->dr7));
1925 }
1926 else
1927 {
1928 Log2(("VMX: mov x, drx\n"));
1929 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1930 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1931 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1932 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1933 }
1934 /* Update EIP if no error occurred. */
1935 if (VBOX_SUCCESS(rc))
1936 pCtx->rip += cbInstr;
1937
1938 if (rc == VINF_SUCCESS)
1939 {
1940 /* Only resume if successful. */
1941 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1942 goto ResumeExecution;
1943 }
1944 Assert(rc == VERR_EM_INTERPRETER);
1945 break;
1946 }
1947
1948 /** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1949 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1950 {
1951 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1952 uint32_t uPort;
1953 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1954
1955 /** @todo necessary to make the distinction? */
1956 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1957 {
1958 uPort = pCtx->edx & 0xffff;
1959 }
1960 else
1961 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1962
1963 /* paranoia */
1964 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
1965 {
1966 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1967 break;
1968 }
1969
1970 uint32_t cbSize = aIOSize[uIOWidth];
1971
1972 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1973 {
1974 /* ins/outs */
1975 uint32_t prefix = 0;
1976 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1977 prefix |= PREFIX_REP;
1978
1979 if (fIOWrite)
1980 {
1981 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1982 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1983 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1984 }
1985 else
1986 {
1987 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1988 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1989 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1990 }
1991 }
1992 else
1993 {
1994 /* normal in/out */
1995 uint32_t uAndVal = aIOOpAnd[uIOWidth];
1996
1997 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1998
1999 if (fIOWrite)
2000 {
2001 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2002 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2003 }
2004 else
2005 {
2006 uint32_t u32Val = 0;
2007
2008 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2009 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2010 if (IOM_SUCCESS(rc))
2011 {
2012 /* Write back to the EAX register. */
2013 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2014 }
2015 }
2016 }
2017 /*
2018 * Handled the I/O return codes.
2019 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2020 */
2021 if (IOM_SUCCESS(rc))
2022 {
2023 /* Update EIP and continue execution. */
2024 pCtx->rip += cbInstr;
2025 if (RT_LIKELY(rc == VINF_SUCCESS))
2026 {
2027 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2028 goto ResumeExecution;
2029 }
2030 break;
2031 }
2032
2033#ifdef VBOX_STRICT
2034 if (rc == VINF_IOM_HC_IOPORT_READ)
2035 Assert(!fIOWrite);
2036 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2037 Assert(fIOWrite);
2038 else
2039 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2040#endif
2041 break;
2042 }
2043
2044 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2045 LogFlow(("VMX_EXIT_TPR\n"));
2046 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2047 goto ResumeExecution;
2048
2049 default:
2050 /* The rest is handled after syncing the entire CPU state. */
2051 break;
2052 }
2053
2054 /* Note: the guest state isn't entirely synced back at this stage. */
2055
2056 /* Investigate why there was a VM-exit. (part 2) */
2057 switch (exitReason)
2058 {
2059 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2060 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2061 /* Already handled above. */
2062 break;
2063
2064 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2065 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2066 break;
2067
2068 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2069 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2070 rc = VINF_EM_RAW_INTERRUPT;
2071 AssertFailed(); /* Can't happen. Yet. */
2072 break;
2073
2074 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2075 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2076 rc = VINF_EM_RAW_INTERRUPT;
2077 AssertFailed(); /* Can't happen afaik. */
2078 break;
2079
2080 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2081 rc = VERR_EM_INTERPRETER;
2082 break;
2083
2084 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2085 /** Check if external interrupts are pending; if so, don't switch back. */
2086 pCtx->rip++; /* skip hlt */
2087 if ( pCtx->eflags.Bits.u1IF
2088 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2089 goto ResumeExecution;
2090
2091 rc = VINF_EM_HALT;
2092 break;
2093
2094 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2095 AssertFailed(); /* can't happen. */
2096 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2097 break;
2098
2099 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2100 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2101 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2102 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2103 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2104 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2105 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2106 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2107 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2108 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2109 /** @todo inject #UD immediately */
2110 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2111 break;
2112
2113 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2114 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2115 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2116 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2117 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2118 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2119 /* already handled above */
2120 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2121 || rc == VINF_EM_RAW_INTERRUPT
2122 || rc == VERR_EM_INTERPRETER
2123 || rc == VINF_EM_RAW_EMULATE_INSTR
2124 || rc == VINF_PGM_SYNC_CR3
2125 || rc == VINF_IOM_HC_IOPORT_READ
2126 || rc == VINF_IOM_HC_IOPORT_WRITE
2127 || rc == VINF_EM_RAW_GUEST_TRAP
2128 || rc == VINF_TRPM_XCPT_DISPATCHED
2129 || rc == VINF_EM_RESCHEDULE_REM,
2130 ("rc = %d\n", rc));
2131 break;
2132
2133 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2134 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2135 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2136 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2137 rc = VERR_EM_INTERPRETER;
2138 break;
2139
2140 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2141 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2142 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2143 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2144 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2145 break;
2146
2147 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2148 Assert(rc == VINF_EM_RAW_INTERRUPT);
2149 break;
2150
2151 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2152 {
2153#ifdef VBOX_STRICT
2154 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2155
2156 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2157 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2158
2159 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2160 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2161
2162 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2163 Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2164
2165 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2166 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2167
2168 VMX_LOG_SELREG(CS, "CS");
2169 VMX_LOG_SELREG(DS, "DS");
2170 VMX_LOG_SELREG(ES, "ES");
2171 VMX_LOG_SELREG(FS, "FS");
2172 VMX_LOG_SELREG(GS, "GS");
2173 VMX_LOG_SELREG(SS, "SS");
2174 VMX_LOG_SELREG(TR, "TR");
2175 VMX_LOG_SELREG(LDTR, "LDTR");
2176
2177 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2178 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2179 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2180 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2181#endif /* VBOX_STRICT */
2182 rc = VERR_EM_INTERNAL_ERROR;
2183 break;
2184 }
2185
2186 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2187 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2188 default:
2189 rc = VERR_EM_INTERNAL_ERROR;
2190 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2191 break;
2192
2193 }
2194end:
2195 if (fGuestStateSynced)
2196 {
2197 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2198 VMX_READ_SELREG(LDTR, ldtr);
2199 VMX_READ_SELREG(TR, tr);
2200
2201 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2202 pCtx->gdtr.cbGdt = val;
2203 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2204 pCtx->gdtr.pGdt = val;
2205
2206 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2207 pCtx->idtr.cbIdt = val;
2208 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2209 pCtx->idtr.pIdt = val;
2210 }
2211
2212 /* Signal changes for the recompiler. */
2213 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2214
2215 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2216 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2217 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2218 {
2219 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2220 /* On the next entry we'll only sync the host context. */
2221 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2222 }
2223 else
2224 {
2225 /* On the next entry we'll sync everything. */
2226 /** @todo we can do better than this */
2227 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2228 }
2229
2230 /* translate into a less severe return code */
2231 if (rc == VERR_EM_INTERPRETER)
2232 rc = VINF_EM_RAW_EMULATE_INSTR;
2233
2234 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2235 Log2(("X"));
2236 return rc;
2237}
2238
2239
2240/**
2241 * Enters the VT-x session
2242 *
2243 * @returns VBox status code.
2244 * @param pVM The VM to operate on.
2245 * @param pCpu CPU info struct
2246 */
2247HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2248{
2249 Assert(pVM->hwaccm.s.vmx.fSupported);
2250
2251 unsigned cr4 = ASMGetCR4();
2252 if (!(cr4 & X86_CR4_VMXE))
2253 {
2254 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2255 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2256 }
2257
2258 /* Activate the VM Control Structure. */
2259 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2260 if (VBOX_FAILURE(rc))
2261 return rc;
2262
2263 pVM->hwaccm.s.vmx.fResumeVM = false;
2264 return VINF_SUCCESS;
2265}
2266
2267
2268/**
2269 * Leaves the VT-x session
2270 *
2271 * @returns VBox status code.
2272 * @param pVM The VM to operate on.
2273 */
2274HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2275{
2276 Assert(pVM->hwaccm.s.vmx.fSupported);
2277
2278 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2279 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2280 AssertRC(rc);
2281
2282 return VINF_SUCCESS;
2283}
2284
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