VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 11763

Last change on this file since 11763 was 11763, checked in by vboxsync, 17 years ago

Host CR0 CD, NW & ET bits are not restored after a VM exit. We must not allow the guest to change them.
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1/* $Id: HWVMXR0.cpp 11763 2008-08-28 14:27:11Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43
44/* IO operation lookup arrays. */
45static uint32_t aIOSize[4] = {1, 2, 0, 4};
46static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49static void VMXR0CheckError(PVM pVM, int rc)
50{
51 if (rc == VERR_VMX_GENERIC)
52 {
53 RTCCUINTREG instrError;
54
55 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57 }
58 pVM->hwaccm.s.lLastError = rc;
59}
60
61/**
62 * Sets up and activates VT-x on the current CPU
63 *
64 * @returns VBox status code.
65 * @param pCpu CPU info struct
66 * @param pVM The VM to operate on.
67 * @param pvPageCpu Pointer to the global cpu page
68 * @param pPageCpuPhys Physical address of the global cpu page
69 */
70HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71{
72 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73 AssertReturn(pVM, VERR_INVALID_PARAMETER);
74 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76 /* Setup Intel VMX. */
77 Assert(pVM->hwaccm.s.vmx.fSupported);
78
79#ifdef LOG_ENABLED
80 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81#endif
82 /* Set revision dword at the beginning of the VMXON structure. */
83 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85 /* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86 * (which can have very bad consequences!!!)
87 */
88
89 /* Make sure the VMX instructions don't cause #UD faults. */
90 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
91
92 /* Enter VMX Root Mode */
93 int rc = VMXEnable(pPageCpuPhys);
94 if (VBOX_FAILURE(rc))
95 {
96 VMXR0CheckError(pVM, rc);
97 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98 return VERR_VMX_VMXON_FAILED;
99 }
100 return VINF_SUCCESS;
101}
102
103/**
104 * Deactivates VT-x on the current CPU
105 *
106 * @returns VBox status code.
107 * @param pCpu CPU info struct
108 * @param pvPageCpu Pointer to the global cpu page
109 * @param pPageCpuPhys Physical address of the global cpu page
110 */
111HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112{
113 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116 /* Leave VMX Root Mode. */
117 VMXDisable();
118
119 /* And clear the X86_CR4_VMXE bit */
120 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122#ifdef LOG_ENABLED
123 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124#endif
125 return VINF_SUCCESS;
126}
127
128/**
129 * Does Ring-0 per VM VT-x init.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135{
136 int rc;
137
138#ifdef LOG_ENABLED
139 SUPR0Printf("VMXR0InitVM %x\n", pVM);
140#endif
141 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
142 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
143 pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
144
145
146 /* Allocate one page for the VM control structure (VMCS). */
147 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
148 AssertRC(rc);
149 if (RT_FAILURE(rc))
150 return rc;
151
152 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
153 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
154 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
155
156 /* Allocate one page for the TSS we need for real mode emulation. */
157 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
158 AssertRC(rc);
159 if (RT_FAILURE(rc))
160 return rc;
161
162 pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
163 pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
164
165 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
166 * for I/O operations. */
167 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
168 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
169 /* Bit set to 0 means redirection enabled. */
170 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
171
172 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
173 {
174 /* Allocate one page for the virtual APIC mmio cache. */
175 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
176 AssertRC(rc);
177 if (RT_FAILURE(rc))
178 return rc;
179
180 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
181 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
182 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
183 }
184 else
185 {
186 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
187 pVM->hwaccm.s.vmx.pAPIC = 0;
188 pVM->hwaccm.s.vmx.pAPICPhys = 0;
189 }
190
191 /* Allocate the MSR bitmap if this feature is supported. */
192 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
193 {
194 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
195 AssertRC(rc);
196 if (RT_FAILURE(rc))
197 return rc;
198
199 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
200 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
201 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
202 }
203
204#ifdef LOG_ENABLED
205 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
206#endif
207 return VINF_SUCCESS;
208}
209
210/**
211 * Does Ring-0 per VM VT-x termination.
212 *
213 * @returns VBox status code.
214 * @param pVM The VM to operate on.
215 */
216HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
217{
218 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
219 {
220 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
221 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
222 pVM->hwaccm.s.vmx.pVMCS = 0;
223 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
224 }
225 if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS != NIL_RTR0MEMOBJ)
226 {
227 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
228 pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
229 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
230 pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
231 }
232 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
233 {
234 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
235 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
236 pVM->hwaccm.s.vmx.pAPIC = 0;
237 pVM->hwaccm.s.vmx.pAPICPhys = 0;
238 }
239 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
240 {
241 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
242 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
243 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
244 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
245 }
246 return VINF_SUCCESS;
247}
248
249/**
250 * Sets up VT-x for the specified VM
251 *
252 * @returns VBox status code.
253 * @param pVM The VM to operate on.
254 */
255HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
256{
257 int rc = VINF_SUCCESS;
258 uint32_t val;
259
260 AssertReturn(pVM, VERR_INVALID_PARAMETER);
261 Assert(pVM->hwaccm.s.vmx.pVMCS);
262
263 /* Set revision dword at the beginning of the VMCS structure. */
264 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
265
266 /* Clear VM Control Structure. */
267 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
268 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
269 if (VBOX_FAILURE(rc))
270 goto vmx_end;
271
272 /* Activate the VM Control Structure. */
273 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
274 if (VBOX_FAILURE(rc))
275 goto vmx_end;
276
277 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
278 * Set required bits to one and zero according to the MSR capabilities.
279 */
280 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
281 /* External and non-maskable interrupts cause VM-exits. */
282 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
283 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
284
285 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
286 AssertRC(rc);
287
288 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
289 * Set required bits to one and zero according to the MSR capabilities.
290 */
291 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
292 /* Program which event cause VM-exits and which features we want to use. */
293 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
294 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
295 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
296 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
297 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
298 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
299
300 /** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
301
302#if HC_ARCH_BITS == 64
303 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
304 {
305 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
306 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
307 Assert(pVM->hwaccm.s.vmx.pAPIC);
308 }
309 else
310 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
311 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
312#endif
313
314#ifdef VBOX_WITH_VTX_MSR_BITMAPS
315 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
316 {
317 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
318 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
319 }
320#endif
321
322 /* We will use the secondary control if it's present. */
323 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
324
325 /* Mask away the bits that the CPU doesn't support */
326 /** @todo make sure they don't conflict with the above requirements. */
327 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
328 pVM->hwaccm.s.vmx.proc_ctls = val;
329
330 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
331 AssertRC(rc);
332
333 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
334 {
335 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
336 * Set required bits to one and zero according to the MSR capabilities.
337 */
338 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
339 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
340
341 /* Mask away the bits that the CPU doesn't support */
342 /** @todo make sure they don't conflict with the above requirements. */
343 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
344
345 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
346 AssertRC(rc);
347 }
348
349 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
350 * Set required bits to one and zero according to the MSR capabilities.
351 */
352 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
353 AssertRC(rc);
354
355 /* VMX_VMCS_CTRL_EXIT_CONTROLS
356 * Set required bits to one and zero according to the MSR capabilities.
357 */
358 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
359#if HC_ARCH_BITS == 64
360 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
361#else
362 /* else Must be zero when AMD64 is not available. */
363#endif
364 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
365 /* Don't acknowledge external interrupts on VM-exit. */
366 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
367 AssertRC(rc);
368
369 /* Forward all exception except #NM & #PF to the guest.
370 * We always need to check pagefaults since our shadow page table can be out of sync.
371 * And we always lazily sync the FPU & XMM state.
372 */
373
374 /*
375 * @todo Possible optimization:
376 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
377 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
378 * registers ourselves of course.
379 *
380 * @note only possible if the current state is actually ours (X86_CR0_TS flag)
381 */
382 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
383 AssertRC(rc);
384
385 /* Don't filter page faults; all of them should cause a switch. */
386 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
387 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
388 AssertRC(rc);
389
390 /* Init TSC offset to zero. */
391 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
392#if HC_ARCH_BITS == 32
393 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
394#endif
395 AssertRC(rc);
396
397 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
398#if HC_ARCH_BITS == 32
399 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
400#endif
401 AssertRC(rc);
402
403 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
404#if HC_ARCH_BITS == 32
405 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
406#endif
407 AssertRC(rc);
408
409 /* Set the MSR bitmap address. */
410 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
411 {
412 /* Optional */
413 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
414#if HC_ARCH_BITS == 32
415 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32);
416#endif
417 AssertRC(rc);
418 }
419
420 /* Clear MSR controls. */
421 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
422 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
423 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
424#if HC_ARCH_BITS == 32
425 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
426 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
427 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
428#endif
429 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
430 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
431 AssertRC(rc);
432
433 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
434 {
435 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
436 /* Optional */
437 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
438 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
439#if HC_ARCH_BITS == 32
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
441#endif
442 AssertRC(rc);
443 }
444
445 /* Set link pointer to -1. Not currently used. */
446#if HC_ARCH_BITS == 32
447 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
448 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
449#else
450 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
451#endif
452 AssertRC(rc);
453
454 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
455 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
456 AssertRC(rc);
457
458vmx_end:
459 VMXR0CheckError(pVM, rc);
460 return rc;
461}
462
463
464/**
465 * Injects an event (trap or external interrupt)
466 *
467 * @returns VBox status code.
468 * @param pVM The VM to operate on.
469 * @param pCtx CPU Context
470 * @param intInfo VMX interrupt info
471 * @param cbInstr Opcode length of faulting instruction
472 * @param errCode Error code (optional)
473 */
474static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
475{
476 int rc;
477
478#ifdef VBOX_STRICT
479 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
480 if (iGate == 0xE)
481 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
482 else
483 if (iGate < 0x20)
484 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
485 else
486 {
487 Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
488 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
489 Assert(pCtx->eflags.u32 & X86_EFL_IF);
490 }
491#endif
492
493 /* Set event injection state. */
494 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
495 intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
496 );
497
498 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
499 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
500
501 AssertRC(rc);
502 return rc;
503}
504
505
506/**
507 * Checks for pending guest interrupts and injects them
508 *
509 * @returns VBox status code.
510 * @param pVM The VM to operate on.
511 * @param pCtx CPU Context
512 */
513static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
514{
515 int rc;
516
517 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
518 if (pVM->hwaccm.s.Event.fPending)
519 {
520 Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
521 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
522 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
523 AssertRC(rc);
524
525 pVM->hwaccm.s.Event.fPending = false;
526 return VINF_SUCCESS;
527 }
528
529 /* When external interrupts are pending, we should exit the VM when IF is set. */
530 if ( !TRPMHasTrap(pVM)
531 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
532 {
533 if (!(pCtx->eflags.u32 & X86_EFL_IF))
534 {
535 Log2(("Enable irq window exit!\n"));
536 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
537 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
538 AssertRC(rc);
539 }
540 else
541 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
542 {
543 uint8_t u8Interrupt;
544
545 rc = PDMGetInterrupt(pVM, &u8Interrupt);
546 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
547 if (VBOX_SUCCESS(rc))
548 {
549 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
550 AssertRC(rc);
551 }
552 else
553 {
554 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
555 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
556 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
557 /* Just continue */
558 }
559 }
560 else
561 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
562 }
563
564#ifdef VBOX_STRICT
565 if (TRPMHasTrap(pVM))
566 {
567 uint8_t u8Vector;
568 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
569 AssertRC(rc);
570 }
571#endif
572
573 if ( pCtx->eflags.u32 & X86_EFL_IF
574 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
575 && TRPMHasTrap(pVM)
576 )
577 {
578 uint8_t u8Vector;
579 int rc;
580 TRPMEVENT enmType;
581 RTGCUINTPTR intInfo;
582 RTGCUINT errCode;
583
584 /* If a new event is pending, then dispatch it now. */
585 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
586 AssertRC(rc);
587 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
588 Assert(enmType != TRPM_SOFTWARE_INT);
589
590 /* Clear the pending trap. */
591 rc = TRPMResetTrap(pVM);
592 AssertRC(rc);
593
594 intInfo = u8Vector;
595 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
596
597 if (enmType == TRPM_TRAP)
598 {
599 switch (u8Vector) {
600 case 8:
601 case 10:
602 case 11:
603 case 12:
604 case 13:
605 case 14:
606 case 17:
607 /* Valid error codes. */
608 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
609 break;
610 default:
611 break;
612 }
613 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
614 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
615 else
616 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
617 }
618 else
619 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
620
621 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
622 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
623 AssertRC(rc);
624 } /* if (interrupts can be dispatched) */
625
626 return VINF_SUCCESS;
627}
628
629/**
630 * Save the host state
631 *
632 * @returns VBox status code.
633 * @param pVM The VM to operate on.
634 */
635HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
636{
637 int rc = VINF_SUCCESS;
638
639 /*
640 * Host CPU Context
641 */
642 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
643 {
644 RTIDTR idtr;
645 RTGDTR gdtr;
646 RTSEL SelTR;
647 PX86DESCHC pDesc;
648 uintptr_t trBase;
649
650 /* Control registers */
651 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
652 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
653 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
654 AssertRC(rc);
655 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
656 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
657 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
658
659 /* Selector registers. */
660 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
661 /** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
662 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
663 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
664#if HC_ARCH_BITS == 32
665 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
666 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
667#endif
668 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
669 SelTR = ASMGetTR();
670 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
671 AssertRC(rc);
672 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
673 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
674 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
675 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
676 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
677 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
678 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
679
680 /* GDTR & IDTR */
681 ASMGetGDTR(&gdtr);
682 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
683 ASMGetIDTR(&idtr);
684 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
685 AssertRC(rc);
686 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
687 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
688
689 /* Save the base address of the TR selector. */
690 if (SelTR > gdtr.cbGdt)
691 {
692 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
693 return VERR_VMX_INVALID_HOST_STATE;
694 }
695
696 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
697#if HC_ARCH_BITS == 64
698 trBase = X86DESC64_BASE(*pDesc);
699#else
700 trBase = X86DESC_BASE(*pDesc);
701#endif
702 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
703 AssertRC(rc);
704 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
705
706 /* FS and GS base. */
707#if HC_ARCH_BITS == 64
708 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
709 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
710 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
711 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
712#endif
713 AssertRC(rc);
714
715 /* Sysenter MSRs. */
716 /** @todo expensive!! */
717 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
718 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
719#if HC_ARCH_BITS == 32
720 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
721 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
722 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
723 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
724#else
725 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
726 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
727 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
728 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
729#endif
730 AssertRC(rc);
731
732 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
733 }
734 return rc;
735}
736
737
738/**
739 * Loads the guest state
740 *
741 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
742 *
743 * @returns VBox status code.
744 * @param pVM The VM to operate on.
745 * @param pCtx Guest context
746 */
747HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
748{
749 int rc = VINF_SUCCESS;
750 RTGCUINTPTR val;
751 X86EFLAGS eflags;
752
753 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
754 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
755 {
756 VMX_WRITE_SELREG(ES, es);
757 AssertRC(rc);
758
759 VMX_WRITE_SELREG(CS, cs);
760 AssertRC(rc);
761
762 VMX_WRITE_SELREG(SS, ss);
763 AssertRC(rc);
764
765 VMX_WRITE_SELREG(DS, ds);
766 AssertRC(rc);
767
768 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
769 VMX_WRITE_SELREG(FS, fs);
770 AssertRC(rc);
771
772 VMX_WRITE_SELREG(GS, gs);
773 AssertRC(rc);
774 }
775
776 /* Guest CPU context: LDTR. */
777 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
778 {
779 if (pCtx->ldtr == 0)
780 {
781 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
782 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
783 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
784 /** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
785 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
786 }
787 else
788 {
789 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
790 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
791 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
792 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
793 }
794 AssertRC(rc);
795 }
796 /* Guest CPU context: TR. */
797 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
798 {
799 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
800
801 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
802 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
803 {
804 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
805 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
806 }
807 else
808 {
809 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
810 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
811 }
812 val = pCtx->trHid.Attr.u;
813
814 /* The TSS selector must be busy. */
815 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
816 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
817 else
818 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
819 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
820
821 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
822 AssertRC(rc);
823 }
824 /* Guest CPU context: GDTR. */
825 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
826 {
827 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
828 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
829 AssertRC(rc);
830 }
831 /* Guest CPU context: IDTR. */
832 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
833 {
834 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
835 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
836 AssertRC(rc);
837 }
838
839 /*
840 * Sysenter MSRs (unconditional)
841 */
842 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
843 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
844 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
845 AssertRC(rc);
846
847 /* Control registers */
848 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
849 {
850 val = pCtx->cr0;
851 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
852 Log2(("Guest CR0-shadow %08x\n", val));
853 if (CPUMIsGuestFPUStateActive(pVM) == false)
854 {
855 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
856 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
857 }
858 else
859 {
860 /** @todo check if we support the old style mess correctly. */
861 if (!(val & X86_CR0_NE))
862 {
863 Log(("Forcing X86_CR0_NE!!!\n"));
864
865 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
866 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
867 {
868 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK | RT_BIT(X86_XCPT_MF));
869 AssertRC(rc);
870 pVM->hwaccm.s.fFPUOldStyleOverride = true;
871 }
872 }
873
874 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
875 }
876 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
877 val |= X86_CR0_PE | X86_CR0_PG;
878 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
879 val |= X86_CR0_WP;
880
881 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
882 Log2(("Guest CR0 %08x\n", val));
883 /* CR0 flags owned by the host; if the guests attempts to change them, then
884 * the VM will exit.
885 */
886 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
887 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
888 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
889 | X86_CR0_TS
890 | X86_CR0_ET /* Bit not restored during VM-exit! */
891 | X86_CR0_CD /* Bit not restored during VM-exit! */
892 | X86_CR0_NW /* Bit not restored during VM-exit! */
893 | X86_CR0_NE
894 | X86_CR0_MP;
895 pVM->hwaccm.s.vmx.cr0_mask = val;
896
897 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
898 Log2(("Guest CR0-mask %08x\n", val));
899 AssertRC(rc);
900 }
901 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
902 {
903 /* CR4 */
904 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
905 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
906 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
907 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
908 switch(pVM->hwaccm.s.enmShadowMode)
909 {
910 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
911 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
912 case PGMMODE_32_BIT: /* 32-bit paging. */
913 break;
914
915 case PGMMODE_PAE: /* PAE paging. */
916 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
917 /** @todo use normal 32 bits paging */
918 val |= X86_CR4_PAE;
919 break;
920
921 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
922 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
923#ifdef VBOX_ENABLE_64_BITS_GUESTS
924 break;
925#else
926 AssertFailed();
927 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
928#endif
929 default: /* shut up gcc */
930 AssertFailed();
931 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
932 }
933 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
934 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
935 val |= X86_CR4_VME;
936
937 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
938 Log2(("Guest CR4 %08x\n", val));
939 /* CR4 flags owned by the host; if the guests attempts to change them, then
940 * the VM will exit.
941 */
942 val = X86_CR4_PAE
943 | X86_CR4_PGE
944 | X86_CR4_PSE
945 | X86_CR4_VMXE;
946 pVM->hwaccm.s.vmx.cr4_mask = val;
947
948 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
949 Log2(("Guest CR4-mask %08x\n", val));
950 AssertRC(rc);
951 }
952
953 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
954 {
955 /* Save our shadow CR3 register. */
956 val = PGMGetHyperCR3(pVM);
957 Assert(val);
958 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
959 AssertRC(rc);
960 }
961
962 /* Debug registers. */
963 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
964 {
965 val = pCtx->dr7 & 0xffffffff; /* upper 32 bits reserved */
966 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
967 val |= 0x400; /* must be one */
968 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
969 AssertRC(rc);
970
971 /* IA32_DEBUGCTL MSR. */
972 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
973 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
974 AssertRC(rc);
975
976 /** @todo do we really ever need this? */
977 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
978 AssertRC(rc);
979 }
980
981 /* EIP, ESP and EFLAGS */
982 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
983 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
984 AssertRC(rc);
985
986 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
987 eflags = pCtx->eflags;
988 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
989 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
990
991 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
992 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
993 {
994 eflags.Bits.u1VM = 1;
995 eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
996 eflags.Bits.u2IOPL = 3;
997 }
998
999 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1000 AssertRC(rc);
1001
1002 /** TSC offset. */
1003 uint64_t u64TSCOffset;
1004
1005 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1006 {
1007 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1008#if HC_ARCH_BITS == 64
1009 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1010#else
1011 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
1012 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
1013#endif
1014 AssertRC(rc);
1015
1016 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1017 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1018 AssertRC(rc);
1019 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
1020 }
1021 else
1022 {
1023 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1024 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1025 AssertRC(rc);
1026 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1027 }
1028
1029 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1030 * Set required bits to one and zero according to the MSR capabilities.
1031 */
1032 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1033 /* 64 bits guest mode? */
1034 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1035 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1036 /* else Must be zero when AMD64 is not available. */
1037
1038 /* Mask away the bits that the CPU doesn't support */
1039 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1040 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1041 AssertRC(rc);
1042
1043 /* 64 bits guest mode? */
1044 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1045 {
1046#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
1047 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1048#else
1049 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1050#endif
1051 /* Unconditionally update these as wrmsr might have changed them. */
1052 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1053 AssertRC(rc);
1054 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1055 AssertRC(rc);
1056 }
1057 else
1058 {
1059 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1060 }
1061
1062 /* Done. */
1063 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1064
1065 return rc;
1066}
1067
1068/**
1069 * Runs guest code in a VT-x VM.
1070 *
1071 * @returns VBox status code.
1072 * @param pVM The VM to operate on.
1073 * @param pCtx Guest context
1074 */
1075HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1076{
1077 int rc = VINF_SUCCESS;
1078 RTCCUINTREG val, valShadow;
1079 RTCCUINTREG exitReason, instrError, cbInstr;
1080 RTGCUINTPTR exitQualification;
1081 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1082 RTGCUINTPTR errCode, instrInfo, uInterruptState;
1083 bool fGuestStateSynced = false;
1084 bool fSyncTPR = false;
1085 unsigned cResume = 0;
1086#ifdef VBOX_STRICT
1087 RTCPUID idCpuCheck;
1088#endif
1089
1090 Log2(("\nE"));
1091
1092 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1093
1094#ifdef VBOX_STRICT
1095 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1096 AssertRC(rc);
1097 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1098
1099 /* allowed zero */
1100 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1101 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1102
1103 /* allowed one */
1104 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1105 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1106
1107 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1108 AssertRC(rc);
1109 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1110
1111 /* allowed zero */
1112 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1113 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1114
1115 /* allowed one */
1116 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1117 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1118
1119 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1120 AssertRC(rc);
1121 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1122
1123 /* allowed zero */
1124 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1125 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1126
1127 /* allowed one */
1128 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1129 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1130
1131 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1132 AssertRC(rc);
1133 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1134
1135 /* allowed zero */
1136 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1137 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1138
1139 /* allowed one */
1140 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1141 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1142#endif
1143
1144#if 0
1145 /*
1146 * Check if debug registers are armed.
1147 */
1148 uint32_t u32DR7 = ASMGetDR7();
1149 if (u32DR7 & X86_DR7_ENABLED_MASK)
1150 {
1151 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
1152 }
1153 else
1154 pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1155#endif
1156
1157 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1158 */
1159ResumeExecution:
1160 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1161 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1162 {
1163 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1164 rc = VINF_EM_RAW_INTERRUPT;
1165 goto end;
1166 }
1167
1168 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1169 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1170 {
1171 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1172 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1173 {
1174 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1175 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1176 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1177 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1178 */
1179 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1180 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1181 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1182 AssertRC(rc);
1183 }
1184 }
1185 else
1186 {
1187 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1188 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1189 AssertRC(rc);
1190 }
1191
1192 /* Check for pending actions that force us to go back to ring 3. */
1193 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1194 {
1195 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1196 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1197 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1198 rc = VINF_EM_RAW_TO_R3;
1199 goto end;
1200 }
1201 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1202 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1203 {
1204 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1205 rc = VINF_EM_PENDING_REQUEST;
1206 goto end;
1207 }
1208
1209 /* When external interrupts are pending, we should exit the VM when IF is set. */
1210 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
1211 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1212 if (VBOX_FAILURE(rc))
1213 {
1214 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1215 goto end;
1216 }
1217
1218 /** @todo check timers?? */
1219
1220 /* TPR caching using CR8 is only available in 64 bits mode */
1221 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1222 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1223 /*
1224 * @todo reduce overhead
1225 */
1226 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1227 && pVM->hwaccm.s.vmx.pAPIC)
1228 {
1229 /* TPR caching in CR8 */
1230 uint8_t u8TPR;
1231 bool fPending;
1232
1233 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1234 AssertRC(rc);
1235 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1236 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1237
1238 /* Two options here:
1239 * - external interrupt pending, but masked by the TPR value.
1240 * -> a CR8 update that lower the current TPR value should cause an exit
1241 * - no pending interrupts
1242 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1243 */
1244 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1245 AssertRC(rc);
1246
1247 /* Always sync back the TPR; we should optimize this though (@todo) */
1248 fSyncTPR = true;
1249 }
1250
1251 /*
1252 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1253 * (until the actual world switch)
1254 */
1255#ifdef VBOX_STRICT
1256 idCpuCheck = RTMpCpuId();
1257#endif
1258 /* Save the host state first. */
1259 rc = VMXR0SaveHostState(pVM);
1260 if (rc != VINF_SUCCESS)
1261 {
1262 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1263 goto end;
1264 }
1265 /* Load the guest state */
1266 rc = VMXR0LoadGuestState(pVM, pCtx);
1267 if (rc != VINF_SUCCESS)
1268 {
1269 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1270 goto end;
1271 }
1272 fGuestStateSynced = true;
1273
1274 /* Non-register state Guest Context */
1275 /** @todo change me according to cpu state */
1276 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1277 AssertRC(rc);
1278
1279 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1280
1281 /* Manual save and restore:
1282 * - General purpose registers except RIP, RSP
1283 *
1284 * Trashed:
1285 * - CR2 (we don't care)
1286 * - LDTR (reset to 0)
1287 * - DRx (presumably not changed at all)
1288 * - DR7 (reset to 0x400)
1289 * - EFLAGS (reset to RT_BIT(1); not relevant)
1290 *
1291 */
1292
1293 /* All done! Let's start VM execution. */
1294 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1295#ifdef VBOX_STRICT
1296 Assert(idCpuCheck == RTMpCpuId());
1297#endif
1298 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1299
1300 /* In case we execute a goto ResumeExecution later on. */
1301 pVM->hwaccm.s.vmx.fResumeVM = true;
1302
1303 /**
1304 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1305 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1306 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1307 */
1308
1309 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1310 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1311
1312 switch (rc)
1313 {
1314 case VINF_SUCCESS:
1315 break;
1316
1317 case VERR_VMX_INVALID_VMXON_PTR:
1318 AssertFailed();
1319 goto end;
1320
1321 case VERR_VMX_UNABLE_TO_START_VM:
1322 case VERR_VMX_UNABLE_TO_RESUME_VM:
1323 {
1324#ifdef VBOX_STRICT
1325 int rc1;
1326
1327 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1328 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1329 AssertRC(rc1);
1330 if (rc1 == VINF_SUCCESS)
1331 {
1332 RTGDTR gdtr;
1333 PX86DESCHC pDesc;
1334
1335 ASMGetGDTR(&gdtr);
1336
1337 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1338 Log(("Current stack %08x\n", &rc1));
1339
1340
1341 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1342 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1343 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1344 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1345 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1346 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1347 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1348 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1349 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1350 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1351
1352 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1353 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1354
1355 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1356 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1357
1358 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1359 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1360
1361 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1362 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1363 if (val < gdtr.cbGdt)
1364 {
1365 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1366 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1367 }
1368
1369 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1370 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1371 if (val < gdtr.cbGdt)
1372 {
1373 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1374 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1375 }
1376
1377 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1378 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1379 if (val < gdtr.cbGdt)
1380 {
1381 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1382 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1383 }
1384
1385 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1386 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1387 if (val < gdtr.cbGdt)
1388 {
1389 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1390 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1391 }
1392
1393 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1394 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1395 if (val < gdtr.cbGdt)
1396 {
1397 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1398 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1399 }
1400
1401 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1402 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1403 if (val < gdtr.cbGdt)
1404 {
1405 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1406 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1407 }
1408
1409 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1410 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1411 if (val < gdtr.cbGdt)
1412 {
1413 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1414 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1415 }
1416
1417 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1418 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1419
1420 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1421 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1422 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1423 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1424
1425 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1426 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1427
1428 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1429 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1430
1431 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1432 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1433
1434 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1435 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1436 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1437 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1438
1439#if HC_ARCH_BITS == 64
1440 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1441 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1442 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1443 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1444 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1445#endif
1446 }
1447#endif /* VBOX_STRICT */
1448 goto end;
1449 }
1450
1451 default:
1452 /* impossible */
1453 AssertFailed();
1454 goto end;
1455 }
1456 /* Success. Query the guest state and figure out what has happened. */
1457
1458 /* Investigate why there was a VM-exit. */
1459 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1460 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1461
1462 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1463 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1464 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1465 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1466 intInfo = val;
1467 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1468 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1469 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1470 instrInfo = val;
1471 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1472 exitQualification = val;
1473 AssertRC(rc);
1474
1475 /* Let's first sync back eip, esp, and eflags. */
1476 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1477 AssertRC(rc);
1478 pCtx->rip = val;
1479 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1480 AssertRC(rc);
1481 pCtx->rsp = val;
1482 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1483 AssertRC(rc);
1484 pCtx->eflags.u32 = val;
1485
1486 /* Take care of instruction fusing (sti, mov ss) */
1487 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1488 uInterruptState = val;
1489 if (uInterruptState != 0)
1490 {
1491 Assert(uInterruptState <= 2); /* only sti & mov ss */
1492 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1493 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1494 }
1495 else
1496 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1497
1498 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1499 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1500 {
1501 /* Hide our emulation flags */
1502 pCtx->eflags.Bits.u1VM = 0;
1503 pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1504 pCtx->eflags.Bits.u1VIF = 0;
1505 pCtx->eflags.Bits.u2IOPL = 0;
1506 }
1507
1508 /* Control registers. */
1509 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1510 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1511 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1512 CPUMSetGuestCR0(pVM, val);
1513
1514 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1515 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1516 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1517 CPUMSetGuestCR4(pVM, val);
1518
1519 CPUMSetGuestCR2(pVM, ASMGetCR2());
1520
1521 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1522 CPUMSetGuestDR7(pVM, val);
1523
1524 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1525 VMX_READ_SELREG(ES, es);
1526 VMX_READ_SELREG(SS, ss);
1527 VMX_READ_SELREG(CS, cs);
1528 VMX_READ_SELREG(DS, ds);
1529 VMX_READ_SELREG(FS, fs);
1530 VMX_READ_SELREG(GS, gs);
1531
1532 /*
1533 * System MSRs
1534 */
1535 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1536 pCtx->SysEnter.cs = val;
1537 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1538 pCtx->SysEnter.eip = val;
1539 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1540 pCtx->SysEnter.esp = val;
1541
1542 /** @note NOW IT'S SAFE FOR LOGGING! */
1543 Log2(("Raw exit reason %08x\n", exitReason));
1544
1545 /* Check if an injected event was interrupted prematurely. */
1546 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1547 AssertRC(rc);
1548 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1549 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1550 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1551 {
1552 pVM->hwaccm.s.Event.fPending = true;
1553 /* Error code present? */
1554 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1555 {
1556 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1557 AssertRC(rc);
1558 pVM->hwaccm.s.Event.errCode = val;
1559 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1560 }
1561 else
1562 {
1563 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1564 pVM->hwaccm.s.Event.errCode = 0;
1565 }
1566 }
1567
1568#ifdef VBOX_STRICT
1569 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1570 HWACCMDumpRegs(pVM, pCtx);
1571#endif
1572
1573 Log2(("E%d", exitReason));
1574 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1575 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1576 Log2(("Interruption error code %d\n", errCode));
1577 Log2(("IntInfo = %08x\n", intInfo));
1578 Log2(("New EIP=%VGv\n", pCtx->rip));
1579
1580 if (fSyncTPR)
1581 {
1582 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1583 AssertRC(rc);
1584 }
1585
1586 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1587 switch (exitReason)
1588 {
1589 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1590 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1591 {
1592 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1593
1594 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1595 {
1596 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1597 /* External interrupt; leave to allow it to be dispatched again. */
1598 rc = VINF_EM_RAW_INTERRUPT;
1599 break;
1600 }
1601 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1602 {
1603 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1604 /* External interrupt; leave to allow it to be dispatched again. */
1605 rc = VINF_EM_RAW_INTERRUPT;
1606 break;
1607
1608 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1609 AssertFailed(); /* can't come here; fails the first check. */
1610 break;
1611
1612 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1613 Assert(vector == 3 || vector == 4);
1614 /* no break */
1615 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1616 Log2(("Hardware/software interrupt %d\n", vector));
1617 switch (vector)
1618 {
1619 case X86_XCPT_NM:
1620 {
1621 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1622
1623 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1624 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1625 rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1626 if (rc == VINF_SUCCESS)
1627 {
1628 Assert(CPUMIsGuestFPUStateActive(pVM));
1629
1630 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1631
1632 /* Continue execution. */
1633 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1634 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1635
1636 goto ResumeExecution;
1637 }
1638
1639 Log(("Forward #NM fault to the guest\n"));
1640 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1641 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1642 AssertRC(rc);
1643 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1644 goto ResumeExecution;
1645 }
1646
1647 case X86_XCPT_PF: /* Page fault */
1648 {
1649 Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1650 /* Exit qualification contains the linear address of the page fault. */
1651 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1652 TRPMSetErrorCode(pVM, errCode);
1653 TRPMSetFaultAddress(pVM, exitQualification);
1654
1655 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1656 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1657 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1658 if (rc == VINF_SUCCESS)
1659 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1660 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1661 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1662
1663 TRPMResetTrap(pVM);
1664
1665 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1666 goto ResumeExecution;
1667 }
1668 else
1669 if (rc == VINF_EM_RAW_GUEST_TRAP)
1670 { /* A genuine pagefault.
1671 * Forward the trap to the guest by injecting the exception and resuming execution.
1672 */
1673 Log2(("Forward page fault to the guest\n"));
1674 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1675 /* The error code might have been changed. */
1676 errCode = TRPMGetErrorCode(pVM);
1677
1678 TRPMResetTrap(pVM);
1679
1680 /* Now we must update CR2. */
1681 pCtx->cr2 = exitQualification;
1682 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1683 AssertRC(rc);
1684
1685 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1686 goto ResumeExecution;
1687 }
1688#ifdef VBOX_STRICT
1689 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1690 Log2(("PGMTrap0eHandler failed with %d\n", rc));
1691#endif
1692 /* Need to go back to the recompiler to emulate the instruction. */
1693 TRPMResetTrap(pVM);
1694 break;
1695 }
1696
1697 case X86_XCPT_MF: /* Floating point exception. */
1698 {
1699 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1700 if (!(pCtx->cr0 & X86_CR0_NE))
1701 {
1702 /* old style FPU error reporting needs some extra work. */
1703 /** @todo don't fall back to the recompiler, but do it manually. */
1704 rc = VINF_EM_RAW_EMULATE_INSTR;
1705 break;
1706 }
1707 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1708 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1709 AssertRC(rc);
1710
1711 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1712 goto ResumeExecution;
1713 }
1714
1715#ifdef VBOX_STRICT
1716 case X86_XCPT_GP: /* General protection failure exception.*/
1717 case X86_XCPT_UD: /* Unknown opcode exception. */
1718 case X86_XCPT_DE: /* Debug exception. */
1719 case X86_XCPT_SS: /* Stack segment exception. */
1720 case X86_XCPT_NP: /* Segment not present exception. */
1721 {
1722 switch(vector)
1723 {
1724 case X86_XCPT_DE:
1725 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1726 break;
1727 case X86_XCPT_UD:
1728 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1729 break;
1730 case X86_XCPT_SS:
1731 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1732 break;
1733 case X86_XCPT_NP:
1734 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1735 break;
1736 case X86_XCPT_GP:
1737 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1738 break;
1739 }
1740
1741 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
1742 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1743 AssertRC(rc);
1744
1745 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1746 goto ResumeExecution;
1747 }
1748#endif
1749 default:
1750 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1751 rc = VERR_EM_INTERNAL_ERROR;
1752 break;
1753 } /* switch (vector) */
1754
1755 break;
1756
1757 default:
1758 rc = VERR_EM_INTERNAL_ERROR;
1759 AssertFailed();
1760 break;
1761 }
1762
1763 break;
1764 }
1765
1766 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1767 /* Clear VM-exit on IF=1 change. */
1768 Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1769 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1770 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1771 AssertRC(rc);
1772 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1773 goto ResumeExecution; /* we check for pending guest interrupts there */
1774
1775 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
1776 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
1777 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1778 /* Skip instruction and continue directly. */
1779 pCtx->rip += cbInstr;
1780 /* Continue execution.*/
1781 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1782 goto ResumeExecution;
1783
1784 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1785 {
1786 Log2(("VMX: Cpuid %x\n", pCtx->eax));
1787 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1788 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1789 if (rc == VINF_SUCCESS)
1790 {
1791 /* Update EIP and continue execution. */
1792 Assert(cbInstr == 2);
1793 pCtx->rip += cbInstr;
1794 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1795 goto ResumeExecution;
1796 }
1797 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1798 rc = VINF_EM_RAW_EMULATE_INSTR;
1799 break;
1800 }
1801
1802 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1803 {
1804 Log2(("VMX: Rdtsc\n"));
1805 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1806 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1807 if (rc == VINF_SUCCESS)
1808 {
1809 /* Update EIP and continue execution. */
1810 Assert(cbInstr == 2);
1811 pCtx->rip += cbInstr;
1812 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1813 goto ResumeExecution;
1814 }
1815 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1816 rc = VINF_EM_RAW_EMULATE_INSTR;
1817 break;
1818 }
1819
1820 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1821 {
1822 Log2(("VMX: invlpg\n"));
1823 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1824 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1825 if (rc == VINF_SUCCESS)
1826 {
1827 /* Update EIP and continue execution. */
1828 pCtx->rip += cbInstr;
1829 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1830 goto ResumeExecution;
1831 }
1832 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1833 break;
1834 }
1835
1836 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1837 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1838 {
1839 uint32_t cbSize;
1840
1841 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1842 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1843 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1844 if (rc == VINF_SUCCESS)
1845 {
1846 /* EIP has been updated already. */
1847
1848 /* Only resume if successful. */
1849 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1850 goto ResumeExecution;
1851 }
1852 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1853 break;
1854 }
1855
1856 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1857 {
1858 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1859 {
1860 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1861 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1862 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1863 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1864 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1865 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1866
1867 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1868 {
1869 case 0:
1870 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1871 break;
1872 case 2:
1873 break;
1874 case 3:
1875 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1876 break;
1877 case 4:
1878 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1879 break;
1880 case 8:
1881 /* CR8 contains the APIC TPR */
1882 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1883 break;
1884
1885 default:
1886 AssertFailed();
1887 break;
1888 }
1889 /* Check if a sync operation is pending. */
1890 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1891 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1892 {
1893 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1894 AssertRC(rc);
1895 }
1896 break;
1897
1898 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1899 Log2(("VMX: mov x, crx\n"));
1900 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1901
1902 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1903 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1904
1905 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1906 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1907 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1908 break;
1909
1910 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1911 Log2(("VMX: clts\n"));
1912 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1913 rc = EMInterpretCLTS(pVM);
1914 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1915 break;
1916
1917 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1918 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1919 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1920 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1921 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1922 break;
1923 }
1924
1925 /* Update EIP if no error occurred. */
1926 if (VBOX_SUCCESS(rc))
1927 pCtx->rip += cbInstr;
1928
1929 if (rc == VINF_SUCCESS)
1930 {
1931 /* Only resume if successful. */
1932 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1933 goto ResumeExecution;
1934 }
1935 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1936 break;
1937 }
1938
1939 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1940 {
1941 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1942 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1943 {
1944 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1945 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1946 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1947 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1948 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1949 Log2(("DR7=%08x\n", pCtx->dr7));
1950 }
1951 else
1952 {
1953 Log2(("VMX: mov x, drx\n"));
1954 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1955 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1956 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1957 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1958 }
1959 /* Update EIP if no error occurred. */
1960 if (VBOX_SUCCESS(rc))
1961 pCtx->rip += cbInstr;
1962
1963 if (rc == VINF_SUCCESS)
1964 {
1965 /* Only resume if successful. */
1966 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1967 goto ResumeExecution;
1968 }
1969 Assert(rc == VERR_EM_INTERPRETER);
1970 break;
1971 }
1972
1973 /** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1974 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1975 {
1976 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1977 uint32_t uPort;
1978 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1979
1980 /** @todo necessary to make the distinction? */
1981 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1982 {
1983 uPort = pCtx->edx & 0xffff;
1984 }
1985 else
1986 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1987
1988 /* paranoia */
1989 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
1990 {
1991 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1992 break;
1993 }
1994
1995 uint32_t cbSize = aIOSize[uIOWidth];
1996
1997 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1998 {
1999 /* ins/outs */
2000 uint32_t prefix = 0;
2001 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
2002 prefix |= PREFIX_REP;
2003
2004 if (fIOWrite)
2005 {
2006 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2007 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
2008 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2009 }
2010 else
2011 {
2012 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2013 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
2014 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2015 }
2016 }
2017 else
2018 {
2019 /* normal in/out */
2020 uint32_t uAndVal = aIOOpAnd[uIOWidth];
2021
2022 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2023
2024 if (fIOWrite)
2025 {
2026 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2027 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2028 }
2029 else
2030 {
2031 uint32_t u32Val = 0;
2032
2033 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2034 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2035 if (IOM_SUCCESS(rc))
2036 {
2037 /* Write back to the EAX register. */
2038 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2039 }
2040 }
2041 }
2042 /*
2043 * Handled the I/O return codes.
2044 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2045 */
2046 if (IOM_SUCCESS(rc))
2047 {
2048 /* Update EIP and continue execution. */
2049 pCtx->rip += cbInstr;
2050 if (RT_LIKELY(rc == VINF_SUCCESS))
2051 {
2052 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2053 goto ResumeExecution;
2054 }
2055 break;
2056 }
2057
2058#ifdef VBOX_STRICT
2059 if (rc == VINF_IOM_HC_IOPORT_READ)
2060 Assert(!fIOWrite);
2061 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2062 Assert(fIOWrite);
2063 else
2064 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2065#endif
2066 break;
2067 }
2068
2069 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2070 LogFlow(("VMX_EXIT_TPR\n"));
2071 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2072 goto ResumeExecution;
2073
2074 default:
2075 /* The rest is handled after syncing the entire CPU state. */
2076 break;
2077 }
2078
2079 /* Note: the guest state isn't entirely synced back at this stage. */
2080
2081 /* Investigate why there was a VM-exit. (part 2) */
2082 switch (exitReason)
2083 {
2084 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2085 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2086 /* Already handled above. */
2087 break;
2088
2089 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2090 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2091 break;
2092
2093 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2094 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2095 rc = VINF_EM_RAW_INTERRUPT;
2096 AssertFailed(); /* Can't happen. Yet. */
2097 break;
2098
2099 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2100 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2101 rc = VINF_EM_RAW_INTERRUPT;
2102 AssertFailed(); /* Can't happen afaik. */
2103 break;
2104
2105 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2106 rc = VERR_EM_INTERPRETER;
2107 break;
2108
2109 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2110 /** Check if external interrupts are pending; if so, don't switch back. */
2111 pCtx->rip++; /* skip hlt */
2112 if ( pCtx->eflags.Bits.u1IF
2113 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2114 goto ResumeExecution;
2115
2116 rc = VINF_EM_HALT;
2117 break;
2118
2119 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2120 AssertFailed(); /* can't happen. */
2121 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2122 break;
2123
2124 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2125 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2126 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2127 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2128 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2129 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2130 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2131 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2132 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2133 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2134 /** @todo inject #UD immediately */
2135 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2136 break;
2137
2138 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2139 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2140 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2141 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2142 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2143 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2144 /* already handled above */
2145 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2146 || rc == VINF_EM_RAW_INTERRUPT
2147 || rc == VERR_EM_INTERPRETER
2148 || rc == VINF_EM_RAW_EMULATE_INSTR
2149 || rc == VINF_PGM_SYNC_CR3
2150 || rc == VINF_IOM_HC_IOPORT_READ
2151 || rc == VINF_IOM_HC_IOPORT_WRITE
2152 || rc == VINF_EM_RAW_GUEST_TRAP
2153 || rc == VINF_TRPM_XCPT_DISPATCHED
2154 || rc == VINF_EM_RESCHEDULE_REM,
2155 ("rc = %d\n", rc));
2156 break;
2157
2158 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2159 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2160 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2161 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2162 rc = VERR_EM_INTERPRETER;
2163 break;
2164
2165 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2166 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2167 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2168 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2169 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2170 break;
2171
2172 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2173 Assert(rc == VINF_EM_RAW_INTERRUPT);
2174 break;
2175
2176 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2177 {
2178#ifdef VBOX_STRICT
2179 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2180
2181 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2182 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2183
2184 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2185 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2186
2187 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2188 Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2189
2190 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2191 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2192
2193 VMX_LOG_SELREG(CS, "CS");
2194 VMX_LOG_SELREG(DS, "DS");
2195 VMX_LOG_SELREG(ES, "ES");
2196 VMX_LOG_SELREG(FS, "FS");
2197 VMX_LOG_SELREG(GS, "GS");
2198 VMX_LOG_SELREG(SS, "SS");
2199 VMX_LOG_SELREG(TR, "TR");
2200 VMX_LOG_SELREG(LDTR, "LDTR");
2201
2202 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2203 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2204 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2205 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2206#endif /* VBOX_STRICT */
2207 rc = VERR_EM_INTERNAL_ERROR;
2208 break;
2209 }
2210
2211 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2212 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2213 default:
2214 rc = VERR_EM_INTERNAL_ERROR;
2215 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2216 break;
2217
2218 }
2219end:
2220 if (fGuestStateSynced)
2221 {
2222 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2223 VMX_READ_SELREG(LDTR, ldtr);
2224 VMX_READ_SELREG(TR, tr);
2225
2226 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2227 pCtx->gdtr.cbGdt = val;
2228 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2229 pCtx->gdtr.pGdt = val;
2230
2231 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2232 pCtx->idtr.cbIdt = val;
2233 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2234 pCtx->idtr.pIdt = val;
2235 }
2236
2237 /* Signal changes for the recompiler. */
2238 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2239
2240 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2241 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2242 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2243 {
2244 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2245 /* On the next entry we'll only sync the host context. */
2246 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2247 }
2248 else
2249 {
2250 /* On the next entry we'll sync everything. */
2251 /** @todo we can do better than this */
2252 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2253 }
2254
2255 /* translate into a less severe return code */
2256 if (rc == VERR_EM_INTERPRETER)
2257 rc = VINF_EM_RAW_EMULATE_INSTR;
2258
2259 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2260 Log2(("X"));
2261 return rc;
2262}
2263
2264
2265/**
2266 * Enters the VT-x session
2267 *
2268 * @returns VBox status code.
2269 * @param pVM The VM to operate on.
2270 * @param pCpu CPU info struct
2271 */
2272HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2273{
2274 Assert(pVM->hwaccm.s.vmx.fSupported);
2275
2276 unsigned cr4 = ASMGetCR4();
2277 if (!(cr4 & X86_CR4_VMXE))
2278 {
2279 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2280 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2281 }
2282
2283 /* Activate the VM Control Structure. */
2284 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2285 if (VBOX_FAILURE(rc))
2286 return rc;
2287
2288 pVM->hwaccm.s.vmx.fResumeVM = false;
2289 return VINF_SUCCESS;
2290}
2291
2292
2293/**
2294 * Leaves the VT-x session
2295 *
2296 * @returns VBox status code.
2297 * @param pVM The VM to operate on.
2298 */
2299HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2300{
2301 Assert(pVM->hwaccm.s.vmx.fSupported);
2302
2303 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2304 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2305 AssertRC(rc);
2306
2307 return VINF_SUCCESS;
2308}
2309
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