HWVMXR0.cpp@ 12121

Last change on this file since 12121 was 12121, checked in by vboxsync, 16 years ago
Committed hardware breakpoint support for VT-x and AMD-V. Untested and disabled.
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File size: 91.5 KB

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1	/* $Id: HWVMXR0.cpp 12121 2008-09-05 09:41:05Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/string.h>
41	#include "HWVMXR0.h"
42
43
44	/* IO operation lookup arrays. */
45	static uint32_t aIOSize[4] = {1, 2, 0, 4};
46	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49	static void VMXR0CheckError(PVM pVM, int rc)
50	{
51	if (rc == VERR_VMX_GENERIC)
52	{
53	RTCCUINTREG instrError;
54
55	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57	}
58	pVM->hwaccm.s.lLastError = rc;
59	}
60
61	/**
62	* Sets up and activates VT-x on the current CPU
63	*
64	* @returns VBox status code.
65	* @param pCpu CPU info struct
66	* @param pVM The VM to operate on.
67	* @param pvPageCpu Pointer to the global cpu page
68	* @param pPageCpuPhys Physical address of the global cpu page
69	*/
70	HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71	{
72	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73	AssertReturn(pVM, VERR_INVALID_PARAMETER);
74	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76	/* Setup Intel VMX. */
77	Assert(pVM->hwaccm.s.vmx.fSupported);
78
79	#ifdef LOG_ENABLED
80	SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81	#endif
82	/* Set revision dword at the beginning of the VMXON structure. */
83	(uint32_t )pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86	* (which can have very bad consequences!!!)
87	*/
88
89	/* Make sure the VMX instructions don't cause #UD faults. */
90	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
91
92	/* Enter VMX Root Mode */
93	int rc = VMXEnable(pPageCpuPhys);
94	if (VBOX_FAILURE(rc))
95	{
96	VMXR0CheckError(pVM, rc);
97	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98	return VERR_VMX_VMXON_FAILED;
99	}
100	return VINF_SUCCESS;
101	}
102
103	/**
104	* Deactivates VT-x on the current CPU
105	*
106	* @returns VBox status code.
107	* @param pCpu CPU info struct
108	* @param pvPageCpu Pointer to the global cpu page
109	* @param pPageCpuPhys Physical address of the global cpu page
110	*/
111	HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112	{
113	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116	/* Leave VMX Root Mode. */
117	VMXDisable();
118
119	/* And clear the X86_CR4_VMXE bit */
120	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122	#ifdef LOG_ENABLED
123	SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124	#endif
125	return VINF_SUCCESS;
126	}
127
128	/**
129	* Does Ring-0 per VM VT-x init.
130	*
131	* @returns VBox status code.
132	* @param pVM The VM to operate on.
133	*/
134	HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135	{
136	int rc;
137
138	#ifdef LOG_ENABLED
139	SUPR0Printf("VMXR0InitVM %x\n", pVM);
140	#endif
141	pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
142	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
143	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
144
145
146	/* Allocate one page for the VM control structure (VMCS). */
147	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
148	AssertRC(rc);
149	if (RT_FAILURE(rc))
150	return rc;
151
152	pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
153	pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
154	ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
155
156	/* Allocate one page for the TSS we need for real mode emulation. */
157	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
158	AssertRC(rc);
159	if (RT_FAILURE(rc))
160	return rc;
161
162	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
163	pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
164
165	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
166	* for I/O operations. */
167	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
168	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
169	/* Bit set to 0 means redirection enabled. */
170	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
171
172	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
173	{
174	/* Allocate one page for the virtual APIC mmio cache. */
175	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
176	AssertRC(rc);
177	if (RT_FAILURE(rc))
178	return rc;
179
180	pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
181	pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
182	ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
183	}
184	else
185	{
186	pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
187	pVM->hwaccm.s.vmx.pAPIC = 0;
188	pVM->hwaccm.s.vmx.pAPICPhys = 0;
189	}
190
191	/* Allocate the MSR bitmap if this feature is supported. */
192	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
193	{
194	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
195	AssertRC(rc);
196	if (RT_FAILURE(rc))
197	return rc;
198
199	pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
200	pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
201	memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
202	}
203
204	#ifdef LOG_ENABLED
205	SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
206	#endif
207	return VINF_SUCCESS;
208	}
209
210	/**
211	* Does Ring-0 per VM VT-x termination.
212	*
213	* @returns VBox status code.
214	* @param pVM The VM to operate on.
215	*/
216	HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
217	{
218	if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
219	{
220	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
221	pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
222	pVM->hwaccm.s.vmx.pVMCS = 0;
223	pVM->hwaccm.s.vmx.pVMCSPhys = 0;
224	}
225	if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS != NIL_RTR0MEMOBJ)
226	{
227	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
228	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
229	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
230	pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
231	}
232	if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
233	{
234	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
235	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
236	pVM->hwaccm.s.vmx.pAPIC = 0;
237	pVM->hwaccm.s.vmx.pAPICPhys = 0;
238	}
239	if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
240	{
241	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
242	pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
243	pVM->hwaccm.s.vmx.pMSRBitmap = 0;
244	pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
245	}
246	return VINF_SUCCESS;
247	}
248
249	/**
250	* Sets up VT-x for the specified VM
251	*
252	* @returns VBox status code.
253	* @param pVM The VM to operate on.
254	*/
255	HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
256	{
257	int rc = VINF_SUCCESS;
258	uint32_t val;
259
260	AssertReturn(pVM, VERR_INVALID_PARAMETER);
261	Assert(pVM->hwaccm.s.vmx.pVMCS);
262
263	/* Set revision dword at the beginning of the VMCS structure. */
264	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
265
266	/* Clear VM Control Structure. */
267	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
268	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
269	if (VBOX_FAILURE(rc))
270	goto vmx_end;
271
272	/* Activate the VM Control Structure. */
273	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
274	if (VBOX_FAILURE(rc))
275	goto vmx_end;
276
277	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
278	* Set required bits to one and zero according to the MSR capabilities.
279	*/
280	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
281	/* External and non-maskable interrupts cause VM-exits. */
282	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
283	val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
284
285	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
286	AssertRC(rc);
287
288	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
289	* Set required bits to one and zero according to the MSR capabilities.
290	*/
291	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
292	/* Program which event cause VM-exits and which features we want to use. */
293	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
294	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
295	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
296	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
297	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
298	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
299
300	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
301
302	#if HC_ARCH_BITS == 64
303	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
304	{
305	/* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
306	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
307	Assert(pVM->hwaccm.s.vmx.pAPIC);
308	}
309	else
310	/* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
311	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
312	#endif
313
314	#ifdef VBOX_WITH_VTX_MSR_BITMAPS
315	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
316	{
317	Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
318	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
319	}
320	#endif
321
322	/* We will use the secondary control if it's present. */
323	val \|= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
324
325	/* Mask away the bits that the CPU doesn't support */
326	/** @todo make sure they don't conflict with the above requirements. */
327	val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
328	pVM->hwaccm.s.vmx.proc_ctls = val;
329
330	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
331	AssertRC(rc);
332
333	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
334	{
335	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
336	* Set required bits to one and zero according to the MSR capabilities.
337	*/
338	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
339	val \|= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
340
341	/* Mask away the bits that the CPU doesn't support */
342	/** @todo make sure they don't conflict with the above requirements. */
343	val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
344
345	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
346	AssertRC(rc);
347	}
348
349	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
350	* Set required bits to one and zero according to the MSR capabilities.
351	*/
352	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
353	AssertRC(rc);
354
355	/* VMX_VMCS_CTRL_EXIT_CONTROLS
356	* Set required bits to one and zero according to the MSR capabilities.
357	*/
358	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
359	#if HC_ARCH_BITS == 64
360	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
361	#else
362	/* else Must be zero when AMD64 is not available. */
363	#endif
364	val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
365	/* Don't acknowledge external interrupts on VM-exit. */
366	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
367	AssertRC(rc);
368
369	/* Forward all exception except #NM & #PF to the guest.
370	* We always need to check pagefaults since our shadow page table can be out of sync.
371	* And we always lazily sync the FPU & XMM state.
372	*/
373
374	/*
375	* @todo Possible optimization:
376	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
377	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
378	* registers ourselves of course.
379	*
380	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
381	*/
382	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
383	AssertRC(rc);
384
385	/* Don't filter page faults; all of them should cause a switch. */
386	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
387	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
388	AssertRC(rc);
389
390	/* Init TSC offset to zero. */
391	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
392	#if HC_ARCH_BITS == 32
393	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
394	#endif
395	AssertRC(rc);
396
397	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
398	#if HC_ARCH_BITS == 32
399	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
400	#endif
401	AssertRC(rc);
402
403	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
404	#if HC_ARCH_BITS == 32
405	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
406	#endif
407	AssertRC(rc);
408
409	/* Set the MSR bitmap address. */
410	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
411	{
412	/* Optional */
413	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
414	#if HC_ARCH_BITS == 32
415	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32);
416	#endif
417	AssertRC(rc);
418	}
419
420	/* Clear MSR controls. */
421	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
422	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
423	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
424	#if HC_ARCH_BITS == 32
425	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
426	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
427	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
428	#endif
429	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
430	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
431	AssertRC(rc);
432
433	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
434	{
435	Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
436	/* Optional */
437	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
438	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
439	#if HC_ARCH_BITS == 32
440	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
441	#endif
442	AssertRC(rc);
443	}
444
445	/* Set link pointer to -1. Not currently used. */
446	#if HC_ARCH_BITS == 32
447	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
448	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
449	#else
450	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
451	#endif
452	AssertRC(rc);
453
454	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
455	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
456	AssertRC(rc);
457
458	vmx_end:
459	VMXR0CheckError(pVM, rc);
460	return rc;
461	}
462
463
464	/**
465	* Injects an event (trap or external interrupt)
466	*
467	* @returns VBox status code.
468	* @param pVM The VM to operate on.
469	* @param pCtx CPU Context
470	* @param intInfo VMX interrupt info
471	* @param cbInstr Opcode length of faulting instruction
472	* @param errCode Error code (optional)
473	*/
474	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
475	{
476	int rc;
477
478	#ifdef VBOX_STRICT
479	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
480	if (iGate == 0xE)
481	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
482	else
483	if (iGate < 0x20)
484	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
485	else
486	{
487	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
488	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
489	Assert(pCtx->eflags.u32 & X86_EFL_IF);
490	}
491	#endif
492
493	/* Set event injection state. */
494	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
495	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
496	);
497
498	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
499	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
500
501	AssertRC(rc);
502	return rc;
503	}
504
505
506	/**
507	* Checks for pending guest interrupts and injects them
508	*
509	* @returns VBox status code.
510	* @param pVM The VM to operate on.
511	* @param pCtx CPU Context
512	*/
513	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
514	{
515	int rc;
516
517	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
518	if (pVM->hwaccm.s.Event.fPending)
519	{
520	Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
521	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
522	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
523	AssertRC(rc);
524
525	pVM->hwaccm.s.Event.fPending = false;
526	return VINF_SUCCESS;
527	}
528
529	/* When external interrupts are pending, we should exit the VM when IF is set. */
530	if ( !TRPMHasTrap(pVM)
531	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
532	{
533	if (!(pCtx->eflags.u32 & X86_EFL_IF))
534	{
535	Log2(("Enable irq window exit!\n"));
536	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
537	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
538	AssertRC(rc);
539	}
540	else
541	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
542	{
543	uint8_t u8Interrupt;
544
545	rc = PDMGetInterrupt(pVM, &u8Interrupt);
546	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
547	if (VBOX_SUCCESS(rc))
548	{
549	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
550	AssertRC(rc);
551	}
552	else
553	{
554	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
555	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
556	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
557	/* Just continue */
558	}
559	}
560	else
561	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
562	}
563
564	#ifdef VBOX_STRICT
565	if (TRPMHasTrap(pVM))
566	{
567	uint8_t u8Vector;
568	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
569	AssertRC(rc);
570	}
571	#endif
572
573	if ( pCtx->eflags.u32 & X86_EFL_IF
574	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
575	&& TRPMHasTrap(pVM)
576	)
577	{
578	uint8_t u8Vector;
579	int rc;
580	TRPMEVENT enmType;
581	RTGCUINTPTR intInfo;
582	RTGCUINT errCode;
583
584	/* If a new event is pending, then dispatch it now. */
585	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
586	AssertRC(rc);
587	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
588	Assert(enmType != TRPM_SOFTWARE_INT);
589
590	/* Clear the pending trap. */
591	rc = TRPMResetTrap(pVM);
592	AssertRC(rc);
593
594	intInfo = u8Vector;
595	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
596
597	if (enmType == TRPM_TRAP)
598	{
599	switch (u8Vector) {
600	case 8:
601	case 10:
602	case 11:
603	case 12:
604	case 13:
605	case 14:
606	case 17:
607	/* Valid error codes. */
608	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
609	break;
610	default:
611	break;
612	}
613	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
614	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
615	else
616	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
617	}
618	else
619	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
620
621	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
622	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
623	AssertRC(rc);
624	} /* if (interrupts can be dispatched) */
625
626	return VINF_SUCCESS;
627	}
628
629	/**
630	* Save the host state
631	*
632	* @returns VBox status code.
633	* @param pVM The VM to operate on.
634	*/
635	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
636	{
637	int rc = VINF_SUCCESS;
638
639	/*
640	* Host CPU Context
641	*/
642	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
643	{
644	RTIDTR idtr;
645	RTGDTR gdtr;
646	RTSEL SelTR;
647	PX86DESCHC pDesc;
648	uintptr_t trBase;
649
650	/* Control registers */
651	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
652	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
653	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
654	AssertRC(rc);
655	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
656	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
657	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
658
659	/* Selector registers. */
660	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
661	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
662	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
663	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
664	#if HC_ARCH_BITS == 32
665	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
666	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
667	#endif
668	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
669	SelTR = ASMGetTR();
670	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
671	AssertRC(rc);
672	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
673	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
674	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
675	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
676	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
677	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
678	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
679
680	/* GDTR & IDTR */
681	ASMGetGDTR(&gdtr);
682	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
683	ASMGetIDTR(&idtr);
684	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
685	AssertRC(rc);
686	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
687	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
688
689	/* Save the base address of the TR selector. */
690	if (SelTR > gdtr.cbGdt)
691	{
692	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
693	return VERR_VMX_INVALID_HOST_STATE;
694	}
695
696	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
697	#if HC_ARCH_BITS == 64
698	trBase = X86DESC64_BASE(*pDesc);
699	#else
700	trBase = X86DESC_BASE(*pDesc);
701	#endif
702	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
703	AssertRC(rc);
704	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
705
706	/* FS and GS base. */
707	#if HC_ARCH_BITS == 64
708	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
709	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
710	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
711	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
712	#endif
713	AssertRC(rc);
714
715	/* Sysenter MSRs. */
716	/** @todo expensive!! */
717	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
718	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
719	#if HC_ARCH_BITS == 32
720	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
721	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
722	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
723	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
724	#else
725	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
726	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
727	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
728	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
729	#endif
730	AssertRC(rc);
731
732	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
733	}
734	return rc;
735	}
736
737
738	/**
739	* Loads the guest state
740	*
741	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
742	*
743	* @returns VBox status code.
744	* @param pVM The VM to operate on.
745	* @param pCtx Guest context
746	*/
747	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
748	{
749	int rc = VINF_SUCCESS;
750	RTGCUINTPTR val;
751	X86EFLAGS eflags;
752
753	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
754	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
755	{
756	VMX_WRITE_SELREG(ES, es);
757	AssertRC(rc);
758
759	VMX_WRITE_SELREG(CS, cs);
760	AssertRC(rc);
761
762	VMX_WRITE_SELREG(SS, ss);
763	AssertRC(rc);
764
765	VMX_WRITE_SELREG(DS, ds);
766	AssertRC(rc);
767
768	/* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
769	VMX_WRITE_SELREG(FS, fs);
770	AssertRC(rc);
771
772	VMX_WRITE_SELREG(GS, gs);
773	AssertRC(rc);
774	}
775
776	/* Guest CPU context: LDTR. */
777	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
778	{
779	if (pCtx->ldtr == 0)
780	{
781	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
782	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
783	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
784	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
785	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
786	}
787	else
788	{
789	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
790	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
791	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
792	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
793	}
794	AssertRC(rc);
795	}
796	/* Guest CPU context: TR. */
797	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
798	{
799	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
800
801	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
802	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
803	{
804	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
805	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
806	}
807	else
808	{
809	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
810	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
811	}
812	val = pCtx->trHid.Attr.u;
813
814	/* The TSS selector must be busy. */
815	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
816	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
817	else
818	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
819	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
820
821	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
822	AssertRC(rc);
823	}
824	/* Guest CPU context: GDTR. */
825	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
826	{
827	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
828	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
829	AssertRC(rc);
830	}
831	/* Guest CPU context: IDTR. */
832	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
833	{
834	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
835	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
836	AssertRC(rc);
837	}
838
839	/*
840	* Sysenter MSRs (unconditional)
841	*/
842	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
843	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
844	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
845	AssertRC(rc);
846
847	/* Control registers */
848	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
849	{
850	val = pCtx->cr0;
851	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
852	Log2(("Guest CR0-shadow %08x\n", val));
853	if (CPUMIsGuestFPUStateActive(pVM) == false)
854	{
855	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
856	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
857	}
858	else
859	{
860	/** @todo check if we support the old style mess correctly. */
861	if (!(val & X86_CR0_NE))
862	{
863	Log(("Forcing X86_CR0_NE!!!\n"));
864
865	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
866	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
867	{
868	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| RT_BIT(X86_XCPT_MF));
869	AssertRC(rc);
870	pVM->hwaccm.s.fFPUOldStyleOverride = true;
871	}
872	}
873
874	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
875	}
876	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
877	val \|= X86_CR0_PE \| X86_CR0_PG;
878	/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
879	val \|= X86_CR0_WP;
880
881	/* Always enable caching. */
882	val &= ~(X86_CR0_CD\|X86_CR0_NW);
883
884	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
885	Log2(("Guest CR0 %08x\n", val));
886	/* CR0 flags owned by the host; if the guests attempts to change them, then
887	* the VM will exit.
888	*/
889	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
890	\| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
891	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
892	\| X86_CR0_TS
893	\| X86_CR0_ET /* Bit not restored during VM-exit! */
894	\| X86_CR0_CD /* Bit not restored during VM-exit! */
895	\| X86_CR0_NW /* Bit not restored during VM-exit! */
896	\| X86_CR0_NE
897	\| X86_CR0_MP;
898	pVM->hwaccm.s.vmx.cr0_mask = val;
899
900	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
901	Log2(("Guest CR0-mask %08x\n", val));
902	AssertRC(rc);
903	}
904	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
905	{
906	/* CR4 */
907	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
908	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
909	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
910	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
911	switch(pVM->hwaccm.s.enmShadowMode)
912	{
913	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
914	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
915	case PGMMODE_32_BIT: /* 32-bit paging. */
916	break;
917
918	case PGMMODE_PAE: /* PAE paging. */
919	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
920	/** @todo use normal 32 bits paging */
921	val \|= X86_CR4_PAE;
922	break;
923
924	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
925	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
926	#ifdef VBOX_ENABLE_64_BITS_GUESTS
927	break;
928	#else
929	AssertFailed();
930	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
931	#endif
932	default: /* shut up gcc */
933	AssertFailed();
934	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
935	}
936	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
937	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
938	val \|= X86_CR4_VME;
939
940	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
941	Log2(("Guest CR4 %08x\n", val));
942	/* CR4 flags owned by the host; if the guests attempts to change them, then
943	* the VM will exit.
944	*/
945	val = X86_CR4_PAE
946	\| X86_CR4_PGE
947	\| X86_CR4_PSE
948	\| X86_CR4_VMXE;
949	pVM->hwaccm.s.vmx.cr4_mask = val;
950
951	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
952	Log2(("Guest CR4-mask %08x\n", val));
953	AssertRC(rc);
954	}
955
956	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
957	{
958	/* Save our shadow CR3 register. */
959	val = PGMGetHyperCR3(pVM);
960	Assert(val);
961	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
962	AssertRC(rc);
963	}
964
965	/* Debug registers. */
966	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
967	{
968	pCtx->dr7 &= 0xffffffff; /* upper 32 bits reserved */
969	pCtx->dr7 &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
970	pCtx->dr7 \|= 0x400; /* must be one */
971	#ifdef VBOX_WITH_HWACCM_DEBUG_REGISTER_SUPPORT
972	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr7);
973	#else
974	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, 0x400);
975	#endif
976	AssertRC(rc);
977
978	#ifdef VBOX_WITH_HWACCM_DEBUG_REGISTER_SUPPORT
979	/* Any guest breakpoints enabled? */
980	if ( (pCtx->dr7 & X86_DR7_ENABLED_MASK)
981	&& !pVM->hwaccm.s.savedhoststate.fHostDebugRegsSaved)
982	{
983	/* Save the host debug register; a bit paranoid if the host has no active breakpoints set in dr7, but we
984	* do not want anything from the guest to leak into the host!
985	*/
986	pVM->hwaccm.s.savedhoststate.dr0 = ASMGetDR0();
987	pVM->hwaccm.s.savedhoststate.dr1 = ASMGetDR1();
988	pVM->hwaccm.s.savedhoststate.dr2 = ASMGetDR2();
989	pVM->hwaccm.s.savedhoststate.dr3 = ASMGetDR3();
990	pVM->hwaccm.s.savedhoststate.dr6 = ASMGetDR6();
991	pVM->hwaccm.s.savedhoststate.fHostDebugRegsSaved = true;
992
993	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
994	ASMSetDR7(0x400);
995	}
996
997	if (pCtx->dr7 & (X86_DR7_L0\|X86_DR7_G0))
998	{
999	ASMSetDR0(pCtx->dr0);
1000	Assert(pVM->hwaccm.s.savedhoststate.fHostDebugRegsSaved);
1001	}
1002	if (pCtx->dr7 & (X86_DR7_L1\|X86_DR7_G1))
1003	{
1004	ASMSetDR1(pCtx->dr1);
1005	Assert(pVM->hwaccm.s.savedhoststate.fHostDebugRegsSaved);
1006	}
1007	if (pCtx->dr7 & (X86_DR7_L2\|X86_DR7_G2))
1008	{
1009	ASMSetDR2(pCtx->dr2);
1010	Assert(pVM->hwaccm.s.savedhoststate.fHostDebugRegsSaved);
1011	}
1012	if (pCtx->dr7 & (X86_DR7_L3\|X86_DR7_G3))
1013	{
1014	ASMSetDR3(pCtx->dr3);
1015	Assert(pVM->hwaccm.s.savedhoststate.fHostDebugRegsSaved);
1016	}
1017
1018	/* No need to sync DR6; all DR6 reads are intercepted. */
1019	#endif /* VBOX_WITH_HWACCM_DEBUG_REGISTER_SUPPORT */
1020
1021	/* IA32_DEBUGCTL MSR. */
1022	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1023	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
1024	AssertRC(rc);
1025
1026	/** @todo do we really ever need this? */
1027	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1028	AssertRC(rc);
1029	}
1030
1031	/* EIP, ESP and EFLAGS */
1032	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
1033	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
1034	AssertRC(rc);
1035
1036	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1037	eflags = pCtx->eflags;
1038	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1039	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
1040
1041	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1042	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1043	{
1044	eflags.Bits.u1VM = 1;
1045	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
1046	eflags.Bits.u2IOPL = 3;
1047	}
1048
1049	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1050	AssertRC(rc);
1051
1052	/** TSC offset. */
1053	uint64_t u64TSCOffset;
1054
1055	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1056	{
1057	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1058	#if HC_ARCH_BITS == 64
1059	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1060	#else
1061	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
1062	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
1063	#endif
1064	AssertRC(rc);
1065
1066	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1067	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1068	AssertRC(rc);
1069	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
1070	}
1071	else
1072	{
1073	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1074	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1075	AssertRC(rc);
1076	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1077	}
1078
1079	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
1080	* Set required bits to one and zero according to the MSR capabilities.
1081	*/
1082	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1083	/* 64 bits guest mode? */
1084	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1085	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1086	/* else Must be zero when AMD64 is not available. */
1087
1088	/* Mask away the bits that the CPU doesn't support */
1089	val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1090	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1091	AssertRC(rc);
1092
1093	/* 64 bits guest mode? */
1094	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1095	{
1096	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
1097	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1098	#else
1099	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1100	#endif
1101	/* Unconditionally update these as wrmsr might have changed them. */
1102	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1103	AssertRC(rc);
1104	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1105	AssertRC(rc);
1106	}
1107	else
1108	{
1109	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1110	}
1111
1112	/* Done. */
1113	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1114
1115	return rc;
1116	}
1117
1118	/**
1119	* Runs guest code in a VT-x VM.
1120	*
1121	* @returns VBox status code.
1122	* @param pVM The VM to operate on.
1123	* @param pCtx Guest context
1124	*/
1125	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1126	{
1127	int rc = VINF_SUCCESS;
1128	RTCCUINTREG val, valShadow;
1129	RTCCUINTREG exitReason, instrError, cbInstr;
1130	RTGCUINTPTR exitQualification;
1131	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1132	RTGCUINTPTR errCode, instrInfo, uInterruptState;
1133	bool fGuestStateSynced = false;
1134	bool fSyncTPR = false;
1135	unsigned cResume = 0;
1136	#ifdef VBOX_STRICT
1137	RTCPUID idCpuCheck;
1138	#endif
1139
1140	Log2(("\nE"));
1141
1142	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1143
1144	#ifdef VBOX_STRICT
1145	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1146	AssertRC(rc);
1147	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1148
1149	/* allowed zero */
1150	if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1151	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1152
1153	/* allowed one */
1154	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1155	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1156
1157	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1158	AssertRC(rc);
1159	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1160
1161	/* allowed zero */
1162	if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1163	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1164
1165	/* allowed one */
1166	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1167	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1168
1169	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1170	AssertRC(rc);
1171	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1172
1173	/* allowed zero */
1174	if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1175	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1176
1177	/* allowed one */
1178	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1179	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1180
1181	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1182	AssertRC(rc);
1183	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1184
1185	/* allowed zero */
1186	if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1187	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1188
1189	/* allowed one */
1190	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1191	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1192	#endif
1193
1194	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1195	*/
1196	ResumeExecution:
1197	/* Safety precaution; looping for too long here can have a very bad effect on the host */
1198	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1199	{
1200	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1201	rc = VINF_EM_RAW_INTERRUPT;
1202	goto end;
1203	}
1204
1205	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1206	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1207	{
1208	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1209	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1210	{
1211	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1212	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1213	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1214	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1215	*/
1216	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1217	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1218	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1219	AssertRC(rc);
1220	}
1221	}
1222	else
1223	{
1224	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1225	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1226	AssertRC(rc);
1227	}
1228
1229	/* Check for pending actions that force us to go back to ring 3. */
1230	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
1231	{
1232	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1233	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1234	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1235	rc = VINF_EM_RAW_TO_R3;
1236	goto end;
1237	}
1238	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1239	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1240	{
1241	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1242	rc = VINF_EM_PENDING_REQUEST;
1243	goto end;
1244	}
1245
1246	/* When external interrupts are pending, we should exit the VM when IF is set. */
1247	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
1248	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1249	if (VBOX_FAILURE(rc))
1250	{
1251	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1252	goto end;
1253	}
1254
1255	/** @todo check timers?? */
1256
1257	/* TPR caching using CR8 is only available in 64 bits mode */
1258	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1259	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1260	/*
1261	* @todo reduce overhead
1262	*/
1263	if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1264	&& pVM->hwaccm.s.vmx.pAPIC)
1265	{
1266	/* TPR caching in CR8 */
1267	uint8_t u8TPR;
1268	bool fPending;
1269
1270	int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1271	AssertRC(rc);
1272	/* The TPR can be found at offset 0x80 in the APIC mmio page. */
1273	pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1274
1275	/* Two options here:
1276	* - external interrupt pending, but masked by the TPR value.
1277	* -> a CR8 update that lower the current TPR value should cause an exit
1278	* - no pending interrupts
1279	* -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1280	*/
1281	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1282	AssertRC(rc);
1283
1284	/* Always sync back the TPR; we should optimize this though (@todo) */
1285	fSyncTPR = true;
1286	}
1287
1288	/*
1289	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1290	* (until the actual world switch)
1291	*/
1292	#ifdef VBOX_STRICT
1293	idCpuCheck = RTMpCpuId();
1294	#endif
1295	/* Save the host state first. */
1296	rc = VMXR0SaveHostState(pVM);
1297	if (rc != VINF_SUCCESS)
1298	{
1299	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1300	goto end;
1301	}
1302	/* Load the guest state */
1303	rc = VMXR0LoadGuestState(pVM, pCtx);
1304	if (rc != VINF_SUCCESS)
1305	{
1306	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1307	goto end;
1308	}
1309	fGuestStateSynced = true;
1310
1311	/* Non-register state Guest Context */
1312	/** @todo change me according to cpu state */
1313	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1314	AssertRC(rc);
1315
1316	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1317
1318	/* Manual save and restore:
1319	* - General purpose registers except RIP, RSP
1320	*
1321	* Trashed:
1322	* - CR2 (we don't care)
1323	* - LDTR (reset to 0)
1324	* - DRx (presumably not changed at all)
1325	* - DR7 (reset to 0x400)
1326	* - EFLAGS (reset to RT_BIT(1); not relevant)
1327	*
1328	*/
1329
1330	/* All done! Let's start VM execution. */
1331	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1332	#ifdef VBOX_STRICT
1333	Assert(idCpuCheck == RTMpCpuId());
1334	#endif
1335	rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1336
1337	/* In case we execute a goto ResumeExecution later on. */
1338	pVM->hwaccm.s.vmx.fResumeVM = true;
1339
1340	/**
1341	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1342	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1343	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1344	*/
1345
1346	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1347	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1348
1349	switch (rc)
1350	{
1351	case VINF_SUCCESS:
1352	break;
1353
1354	case VERR_VMX_INVALID_VMXON_PTR:
1355	AssertFailed();
1356	goto end;
1357
1358	case VERR_VMX_UNABLE_TO_START_VM:
1359	case VERR_VMX_UNABLE_TO_RESUME_VM:
1360	{
1361	#ifdef VBOX_STRICT
1362	int rc1;
1363
1364	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1365	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1366	AssertRC(rc1);
1367	if (rc1 == VINF_SUCCESS)
1368	{
1369	RTGDTR gdtr;
1370	PX86DESCHC pDesc;
1371
1372	ASMGetGDTR(&gdtr);
1373
1374	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1375	Log(("Current stack %08x\n", &rc1));
1376
1377
1378	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1379	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1380	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1381	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1382	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1383	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1384	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1385	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1386	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1387	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1388
1389	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1390	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1391
1392	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1393	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1394
1395	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1396	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1397
1398	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1399	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1400	if (val < gdtr.cbGdt)
1401	{
1402	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1403	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1404	}
1405
1406	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1407	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1408	if (val < gdtr.cbGdt)
1409	{
1410	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1411	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1412	}
1413
1414	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1415	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1416	if (val < gdtr.cbGdt)
1417	{
1418	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1419	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1420	}
1421
1422	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1423	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1424	if (val < gdtr.cbGdt)
1425	{
1426	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1427	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1428	}
1429
1430	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1431	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1432	if (val < gdtr.cbGdt)
1433	{
1434	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1435	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1436	}
1437
1438	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1439	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1440	if (val < gdtr.cbGdt)
1441	{
1442	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1443	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1444	}
1445
1446	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1447	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1448	if (val < gdtr.cbGdt)
1449	{
1450	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1451	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1452	}
1453
1454	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1455	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1456
1457	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1458	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1459	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1460	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1461
1462	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1463	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1464
1465	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1466	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1467
1468	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1469	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1470
1471	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1472	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1473	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1474	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1475
1476	#if HC_ARCH_BITS == 64
1477	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1478	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1479	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1480	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1481	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1482	#endif
1483	}
1484	#endif /* VBOX_STRICT */
1485	goto end;
1486	}
1487
1488	default:
1489	/* impossible */
1490	AssertFailed();
1491	goto end;
1492	}
1493	/* Success. Query the guest state and figure out what has happened. */
1494
1495	/* Investigate why there was a VM-exit. */
1496	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1497	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1498
1499	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1500	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1501	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1502	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1503	intInfo = val;
1504	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1505	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1506	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1507	instrInfo = val;
1508	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1509	exitQualification = val;
1510	AssertRC(rc);
1511
1512	/* Let's first sync back eip, esp, and eflags. */
1513	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1514	AssertRC(rc);
1515	pCtx->rip = val;
1516	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1517	AssertRC(rc);
1518	pCtx->rsp = val;
1519	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1520	AssertRC(rc);
1521	pCtx->eflags.u32 = val;
1522
1523	/* Take care of instruction fusing (sti, mov ss) */
1524	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1525	uInterruptState = val;
1526	if (uInterruptState != 0)
1527	{
1528	Assert(uInterruptState <= 2); /* only sti & mov ss */
1529	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1530	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1531	}
1532	else
1533	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1534
1535	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1536	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1537	{
1538	/* Hide our emulation flags */
1539	pCtx->eflags.Bits.u1VM = 0;
1540	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1541	pCtx->eflags.Bits.u1VIF = 0;
1542	pCtx->eflags.Bits.u2IOPL = 0;
1543	}
1544
1545	/* Control registers. */
1546	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1547	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1548	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1549	CPUMSetGuestCR0(pVM, val);
1550
1551	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1552	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1553	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1554	CPUMSetGuestCR4(pVM, val);
1555
1556	CPUMSetGuestCR2(pVM, ASMGetCR2());
1557
1558	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1559	VMX_READ_SELREG(ES, es);
1560	VMX_READ_SELREG(SS, ss);
1561	VMX_READ_SELREG(CS, cs);
1562	VMX_READ_SELREG(DS, ds);
1563	VMX_READ_SELREG(FS, fs);
1564	VMX_READ_SELREG(GS, gs);
1565
1566	/*
1567	* System MSRs
1568	*/
1569	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1570	pCtx->SysEnter.cs = val;
1571	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1572	pCtx->SysEnter.eip = val;
1573	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1574	pCtx->SysEnter.esp = val;
1575
1576	/* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1577	VMX_READ_SELREG(LDTR, ldtr);
1578	VMX_READ_SELREG(TR, tr);
1579
1580	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1581	pCtx->gdtr.cbGdt = val;
1582	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1583	pCtx->gdtr.pGdt = val;
1584
1585	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1586	pCtx->idtr.cbIdt = val;
1587	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1588	pCtx->idtr.pIdt = val;
1589
1590	/** @note NOW IT'S SAFE FOR LOGGING! */
1591	Log2(("Raw exit reason %08x\n", exitReason));
1592
1593	/* Check if an injected event was interrupted prematurely. */
1594	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1595	AssertRC(rc);
1596	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1597	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1598	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1599	{
1600	pVM->hwaccm.s.Event.fPending = true;
1601	/* Error code present? */
1602	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1603	{
1604	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1605	AssertRC(rc);
1606	pVM->hwaccm.s.Event.errCode = val;
1607	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1608	}
1609	else
1610	{
1611	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1612	pVM->hwaccm.s.Event.errCode = 0;
1613	}
1614	}
1615
1616	#ifdef VBOX_STRICT
1617	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1618	HWACCMDumpRegs(pVM, pCtx);
1619	#endif
1620
1621	Log2(("E%d", exitReason));
1622	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1623	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1624	Log2(("Interruption error code %d\n", errCode));
1625	Log2(("IntInfo = %08x\n", intInfo));
1626	Log2(("New EIP=%VGv\n", pCtx->rip));
1627
1628	if (fSyncTPR)
1629	{
1630	rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1631	AssertRC(rc);
1632	}
1633
1634	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1635	switch (exitReason)
1636	{
1637	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1638	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1639	{
1640	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1641
1642	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1643	{
1644	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1645	/* External interrupt; leave to allow it to be dispatched again. */
1646	rc = VINF_EM_RAW_INTERRUPT;
1647	break;
1648	}
1649	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1650	{
1651	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1652	/* External interrupt; leave to allow it to be dispatched again. */
1653	rc = VINF_EM_RAW_INTERRUPT;
1654	break;
1655
1656	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1657	AssertFailed(); /* can't come here; fails the first check. */
1658	break;
1659
1660	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1661	Assert(vector == 3 \|\| vector == 4);
1662	/* no break */
1663	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1664	Log2(("Hardware/software interrupt %d\n", vector));
1665	switch (vector)
1666	{
1667	case X86_XCPT_NM:
1668	{
1669	Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1670
1671	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1672	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1673	rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1674	if (rc == VINF_SUCCESS)
1675	{
1676	Assert(CPUMIsGuestFPUStateActive(pVM));
1677
1678	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1679
1680	/* Continue execution. */
1681	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1682	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1683
1684	goto ResumeExecution;
1685	}
1686
1687	Log(("Forward #NM fault to the guest\n"));
1688	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1689	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1690	AssertRC(rc);
1691	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1692	goto ResumeExecution;
1693	}
1694
1695	case X86_XCPT_PF: /* Page fault */
1696	{
1697	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1698	/* Exit qualification contains the linear address of the page fault. */
1699	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1700	TRPMSetErrorCode(pVM, errCode);
1701	TRPMSetFaultAddress(pVM, exitQualification);
1702
1703	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1704	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1705	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1706	if (rc == VINF_SUCCESS)
1707	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1708	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1709	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1710
1711	TRPMResetTrap(pVM);
1712
1713	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1714	goto ResumeExecution;
1715	}
1716	else
1717	if (rc == VINF_EM_RAW_GUEST_TRAP)
1718	{ /* A genuine pagefault.
1719	* Forward the trap to the guest by injecting the exception and resuming execution.
1720	*/
1721	Log2(("Forward page fault to the guest\n"));
1722	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1723	/* The error code might have been changed. */
1724	errCode = TRPMGetErrorCode(pVM);
1725
1726	TRPMResetTrap(pVM);
1727
1728	/* Now we must update CR2. */
1729	pCtx->cr2 = exitQualification;
1730	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1731	AssertRC(rc);
1732
1733	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1734	goto ResumeExecution;
1735	}
1736	#ifdef VBOX_STRICT
1737	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1738	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1739	#endif
1740	/* Need to go back to the recompiler to emulate the instruction. */
1741	TRPMResetTrap(pVM);
1742	break;
1743	}
1744
1745	case X86_XCPT_MF: /* Floating point exception. */
1746	{
1747	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1748	if (!(pCtx->cr0 & X86_CR0_NE))
1749	{
1750	/* old style FPU error reporting needs some extra work. */
1751	/** @todo don't fall back to the recompiler, but do it manually. */
1752	rc = VINF_EM_RAW_EMULATE_INSTR;
1753	break;
1754	}
1755	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1756	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1757	AssertRC(rc);
1758
1759	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1760	goto ResumeExecution;
1761	}
1762
1763	case X86_XCPT_DB: /* Debug exception. */
1764	{
1765	/* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
1766	*
1767	* Exit qualification bits:
1768	* 3:0 B0-B3 which breakpoint condition was met
1769	* 12:4 Reserved (0)
1770	* 13 BD - debug register access detected
1771	* 14 BS - single step execution or branch taken
1772	* 63:15 Reserved (0)
1773	*/
1774
1775	#ifdef VBOX_WITH_HWACCM_DEBUG_REGISTER_SUPPORT
1776	/* Update DR6 here. */
1777	pCtx->dr6 = X86_DR6_INIT_VAL;
1778	pCtx->dr6 \|= (exitQualification & (X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3\|X86_DR6_BD\|X86_DR6_BS));
1779
1780	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
1781	pCtx->dr7 &= ~X86_DR7_GD;
1782
1783	/* Paranoia. */
1784	pCtx->dr7 &= 0xffffffff; /* upper 32 bits reserved */
1785	pCtx->dr7 &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
1786	pCtx->dr7 \|= 0x400; /* must be one */
1787
1788	/* Resync DR7 */
1789	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr7);
1790	AssertRC(rc);
1791	#endif /* VBOX_WITH_HWACCM_DEBUG_REGISTER_SUPPORT */
1792
1793	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDB);
1794	Log(("Trap %x (debug) at %VGv exit qualification %VX64\n", vector, pCtx->rip, exitQualification));
1795	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1796	AssertRC(rc);
1797
1798	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1799	goto ResumeExecution;
1800	}
1801
1802	#ifdef VBOX_STRICT
1803	case X86_XCPT_DE: /* Divide error. */
1804	case X86_XCPT_GP: /* General protection failure exception.*/
1805	case X86_XCPT_UD: /* Unknown opcode exception. */
1806	case X86_XCPT_SS: /* Stack segment exception. */
1807	case X86_XCPT_NP: /* Segment not present exception. */
1808	{
1809	switch(vector)
1810	{
1811	case X86_XCPT_DE:
1812	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1813	break;
1814	case X86_XCPT_UD:
1815	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1816	break;
1817	case X86_XCPT_SS:
1818	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1819	break;
1820	case X86_XCPT_NP:
1821	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1822	break;
1823	case X86_XCPT_GP:
1824	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1825	break;
1826	}
1827
1828	Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
1829	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1830	AssertRC(rc);
1831
1832	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1833	goto ResumeExecution;
1834	}
1835	#endif
1836	default:
1837	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1838	rc = VERR_VMX_UNEXPECTED_EXCEPTION;
1839	break;
1840	} /* switch (vector) */
1841
1842	break;
1843
1844	default:
1845	rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
1846	AssertFailed();
1847	break;
1848	}
1849
1850	break;
1851	}
1852
1853	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1854	/* Clear VM-exit on IF=1 change. */
1855	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1856	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1857	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1858	AssertRC(rc);
1859	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1860	goto ResumeExecution; /* we check for pending guest interrupts there */
1861
1862	case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
1863	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
1864	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1865	/* Skip instruction and continue directly. */
1866	pCtx->rip += cbInstr;
1867	/* Continue execution.*/
1868	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1869	goto ResumeExecution;
1870
1871	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1872	{
1873	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1874	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1875	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1876	if (rc == VINF_SUCCESS)
1877	{
1878	/* Update EIP and continue execution. */
1879	Assert(cbInstr == 2);
1880	pCtx->rip += cbInstr;
1881	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1882	goto ResumeExecution;
1883	}
1884	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1885	rc = VINF_EM_RAW_EMULATE_INSTR;
1886	break;
1887	}
1888
1889	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1890	{
1891	Log2(("VMX: Rdtsc\n"));
1892	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1893	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1894	if (rc == VINF_SUCCESS)
1895	{
1896	/* Update EIP and continue execution. */
1897	Assert(cbInstr == 2);
1898	pCtx->rip += cbInstr;
1899	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1900	goto ResumeExecution;
1901	}
1902	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1903	rc = VINF_EM_RAW_EMULATE_INSTR;
1904	break;
1905	}
1906
1907	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1908	{
1909	Log2(("VMX: invlpg\n"));
1910	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1911	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1912	if (rc == VINF_SUCCESS)
1913	{
1914	/* Update EIP and continue execution. */
1915	pCtx->rip += cbInstr;
1916	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1917	goto ResumeExecution;
1918	}
1919	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1920	break;
1921	}
1922
1923	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1924	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1925	{
1926	uint32_t cbSize;
1927
1928	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1929	Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1930	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1931	if (rc == VINF_SUCCESS)
1932	{
1933	/* EIP has been updated already. */
1934
1935	/* Only resume if successful. */
1936	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1937	goto ResumeExecution;
1938	}
1939	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1940	break;
1941	}
1942
1943	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1944	{
1945	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1946	{
1947	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1948	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1949	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1950	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1951	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1952	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1953
1954	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1955	{
1956	case 0:
1957	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1958	break;
1959	case 2:
1960	break;
1961	case 3:
1962	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1963	break;
1964	case 4:
1965	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1966	break;
1967	case 8:
1968	/* CR8 contains the APIC TPR */
1969	Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1970	break;
1971
1972	default:
1973	AssertFailed();
1974	break;
1975	}
1976	/* Check if a sync operation is pending. */
1977	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1978	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1979	{
1980	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1981	AssertRC(rc);
1982	}
1983	break;
1984
1985	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1986	Log2(("VMX: mov x, crx\n"));
1987	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1988
1989	/* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1990	Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 \|\| !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1991
1992	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1993	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1994	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1995	break;
1996
1997	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1998	Log2(("VMX: clts\n"));
1999	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
2000	rc = EMInterpretCLTS(pVM);
2001	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
2002	break;
2003
2004	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2005	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2006	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
2007	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2008	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
2009	break;
2010	}
2011
2012	/* Update EIP if no error occurred. */
2013	if (VBOX_SUCCESS(rc))
2014	pCtx->rip += cbInstr;
2015
2016	if (rc == VINF_SUCCESS)
2017	{
2018	/* Only resume if successful. */
2019	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2020	goto ResumeExecution;
2021	}
2022	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2023	break;
2024	}
2025
2026	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2027	{
2028	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2029	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2030	{
2031	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2032	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2033	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2034	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2035	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2036	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2037	Log2(("DR7=%08x\n", pCtx->dr7));
2038	}
2039	else
2040	{
2041	Log2(("VMX: mov x, drx\n"));
2042	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2043	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2044	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2045	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2046	}
2047	/* Update EIP if no error occurred. */
2048	if (VBOX_SUCCESS(rc))
2049	pCtx->rip += cbInstr;
2050
2051	if (rc == VINF_SUCCESS)
2052	{
2053	/* Only resume if successful. */
2054	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2055	goto ResumeExecution;
2056	}
2057	Assert(rc == VERR_EM_INTERPRETER);
2058	break;
2059	}
2060
2061	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2062	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2063	{
2064	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2065	uint32_t uPort;
2066	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2067
2068	/** @todo necessary to make the distinction? */
2069	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2070	{
2071	uPort = pCtx->edx & 0xffff;
2072	}
2073	else
2074	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2075
2076	/* paranoia */
2077	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
2078	{
2079	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2080	break;
2081	}
2082
2083	uint32_t cbSize = aIOSize[uIOWidth];
2084
2085	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2086	{
2087	/* ins/outs */
2088	uint32_t prefix = 0;
2089	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
2090	prefix \|= PREFIX_REP;
2091
2092	if (fIOWrite)
2093	{
2094	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2095	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
2096	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2097	}
2098	else
2099	{
2100	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2101	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
2102	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2103	}
2104	}
2105	else
2106	{
2107	/* normal in/out */
2108	uint32_t uAndVal = aIOOpAnd[uIOWidth];
2109
2110	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2111
2112	if (fIOWrite)
2113	{
2114	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2115	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2116	}
2117	else
2118	{
2119	uint32_t u32Val = 0;
2120
2121	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2122	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2123	if (IOM_SUCCESS(rc))
2124	{
2125	/* Write back to the EAX register. */
2126	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
2127	}
2128	}
2129	}
2130	/*
2131	* Handled the I/O return codes.
2132	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2133	*/
2134	if (IOM_SUCCESS(rc))
2135	{
2136	/* Update EIP and continue execution. */
2137	pCtx->rip += cbInstr;
2138	if (RT_LIKELY(rc == VINF_SUCCESS))
2139	{
2140	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2141	goto ResumeExecution;
2142	}
2143	break;
2144	}
2145
2146	#ifdef VBOX_STRICT
2147	if (rc == VINF_IOM_HC_IOPORT_READ)
2148	Assert(!fIOWrite);
2149	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2150	Assert(fIOWrite);
2151	else
2152	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2153	#endif
2154	break;
2155	}
2156
2157	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2158	LogFlow(("VMX_EXIT_TPR\n"));
2159	/* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2160	goto ResumeExecution;
2161
2162	default:
2163	/* The rest is handled after syncing the entire CPU state. */
2164	break;
2165	}
2166
2167	/* Note: the guest state isn't entirely synced back at this stage. */
2168
2169	/* Investigate why there was a VM-exit. (part 2) */
2170	switch (exitReason)
2171	{
2172	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2173	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2174	/* Already handled above. */
2175	break;
2176
2177	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2178	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2179	break;
2180
2181	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2182	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2183	rc = VINF_EM_RAW_INTERRUPT;
2184	AssertFailed(); /* Can't happen. Yet. */
2185	break;
2186
2187	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2188	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2189	rc = VINF_EM_RAW_INTERRUPT;
2190	AssertFailed(); /* Can't happen afaik. */
2191	break;
2192
2193	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2194	rc = VERR_EM_INTERPRETER;
2195	break;
2196
2197	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2198	/** Check if external interrupts are pending; if so, don't switch back. */
2199	pCtx->rip++; /* skip hlt */
2200	if ( pCtx->eflags.Bits.u1IF
2201	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
2202	goto ResumeExecution;
2203
2204	rc = VINF_EM_HALT;
2205	break;
2206
2207	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2208	AssertFailed(); /* can't happen. */
2209	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2210	break;
2211
2212	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2213	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2214	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2215	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2216	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2217	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2218	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2219	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2220	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2221	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2222	/** @todo inject #UD immediately */
2223	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2224	break;
2225
2226	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2227	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2228	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2229	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2230	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2231	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2232	/* already handled above */
2233	AssertMsg( rc == VINF_PGM_CHANGE_MODE
2234	\|\| rc == VINF_EM_RAW_INTERRUPT
2235	\|\| rc == VERR_EM_INTERPRETER
2236	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
2237	\|\| rc == VINF_PGM_SYNC_CR3
2238	\|\| rc == VINF_IOM_HC_IOPORT_READ
2239	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2240	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2241	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
2242	\|\| rc == VINF_EM_RESCHEDULE_REM,
2243	("rc = %d\n", rc));
2244	break;
2245
2246	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2247	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2248	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2249	/* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2250	rc = VERR_EM_INTERPRETER;
2251	break;
2252
2253	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2254	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2255	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2256	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2257	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2258	break;
2259
2260	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2261	Assert(rc == VINF_EM_RAW_INTERRUPT);
2262	break;
2263
2264	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2265	{
2266	#ifdef VBOX_STRICT
2267	Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2268
2269	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2270	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2271
2272	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2273	Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2274
2275	VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2276	Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2277
2278	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2279	Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2280
2281	VMX_LOG_SELREG(CS, "CS");
2282	VMX_LOG_SELREG(DS, "DS");
2283	VMX_LOG_SELREG(ES, "ES");
2284	VMX_LOG_SELREG(FS, "FS");
2285	VMX_LOG_SELREG(GS, "GS");
2286	VMX_LOG_SELREG(SS, "SS");
2287	VMX_LOG_SELREG(TR, "TR");
2288	VMX_LOG_SELREG(LDTR, "LDTR");
2289
2290	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2291	Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2292	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2293	Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2294	#endif /* VBOX_STRICT */
2295	rc = VERR_VMX_INVALID_GUEST_STATE;
2296	break;
2297	}
2298
2299	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2300	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2301	default:
2302	rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
2303	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2304	break;
2305
2306	}
2307	end:
2308
2309	/* Signal changes for the recompiler. */
2310	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2311
2312	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2313	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2314	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2315	{
2316	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2317	/* On the next entry we'll only sync the host context. */
2318	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2319	}
2320	else
2321	{
2322	/* On the next entry we'll sync everything. */
2323	/** @todo we can do better than this */
2324	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2325	}
2326
2327	/* translate into a less severe return code */
2328	if (rc == VERR_EM_INTERPRETER)
2329	rc = VINF_EM_RAW_EMULATE_INSTR;
2330	else
2331	/* Try to extract more information about what might have gone wrong here. */
2332	if (rc == VERR_VMX_INVALID_VMCS_PTR)
2333	{
2334	VMXGetActivateVMCS(&pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys);
2335	pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision = (uint32_t )pVM->hwaccm.s.vmx.pVMCS;
2336	}
2337
2338	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2339
2340	Log2(("X"));
2341	return rc;
2342	}
2343
2344
2345	/**
2346	* Enters the VT-x session
2347	*
2348	* @returns VBox status code.
2349	* @param pVM The VM to operate on.
2350	* @param pCpu CPU info struct
2351	*/
2352	HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2353	{
2354	Assert(pVM->hwaccm.s.vmx.fSupported);
2355
2356	unsigned cr4 = ASMGetCR4();
2357	if (!(cr4 & X86_CR4_VMXE))
2358	{
2359	AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2360	return VERR_VMX_X86_CR4_VMXE_CLEARED;
2361	}
2362
2363	/* Activate the VM Control Structure. */
2364	int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2365	if (VBOX_FAILURE(rc))
2366	return rc;
2367
2368	pVM->hwaccm.s.vmx.fResumeVM = false;
2369	return VINF_SUCCESS;
2370	}
2371
2372
2373	/**
2374	* Leaves the VT-x session
2375	*
2376	* @returns VBox status code.
2377	* @param pVM The VM to operate on.
2378	*/
2379	HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2380	{
2381	Assert(pVM->hwaccm.s.vmx.fSupported);
2382
2383	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2384	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2385	AssertRC(rc);
2386
2387	return VINF_SUCCESS;
2388	}
2389

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 12121

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