VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 12692

Last change on this file since 12692 was 12692, checked in by vboxsync, 17 years ago

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1/* $Id: HWVMXR0.cpp 12692 2008-09-24 14:54:14Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43
44/* IO operation lookup arrays. */
45static uint32_t aIOSize[4] = {1, 2, 0, 4};
46static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49static void VMXR0CheckError(PVM pVM, int rc)
50{
51 if (rc == VERR_VMX_GENERIC)
52 {
53 RTCCUINTREG instrError;
54
55 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57 }
58 pVM->hwaccm.s.lLastError = rc;
59}
60
61/**
62 * Sets up and activates VT-x on the current CPU
63 *
64 * @returns VBox status code.
65 * @param pCpu CPU info struct
66 * @param pVM The VM to operate on.
67 * @param pvPageCpu Pointer to the global cpu page
68 * @param pPageCpuPhys Physical address of the global cpu page
69 */
70HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71{
72 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73 AssertReturn(pVM, VERR_INVALID_PARAMETER);
74 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76 /* Setup Intel VMX. */
77 Assert(pVM->hwaccm.s.vmx.fSupported);
78
79#ifdef LOG_ENABLED
80 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81#endif
82 /* Set revision dword at the beginning of the VMXON structure. */
83 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85 /* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86 * (which can have very bad consequences!!!)
87 */
88
89 /* Make sure the VMX instructions don't cause #UD faults. */
90 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
91
92 /* Enter VMX Root Mode */
93 int rc = VMXEnable(pPageCpuPhys);
94 if (VBOX_FAILURE(rc))
95 {
96 VMXR0CheckError(pVM, rc);
97 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98 return VERR_VMX_VMXON_FAILED;
99 }
100 return VINF_SUCCESS;
101}
102
103/**
104 * Deactivates VT-x on the current CPU
105 *
106 * @returns VBox status code.
107 * @param pCpu CPU info struct
108 * @param pvPageCpu Pointer to the global cpu page
109 * @param pPageCpuPhys Physical address of the global cpu page
110 */
111HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112{
113 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116 /* Leave VMX Root Mode. */
117 VMXDisable();
118
119 /* And clear the X86_CR4_VMXE bit */
120 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122#ifdef LOG_ENABLED
123 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124#endif
125 return VINF_SUCCESS;
126}
127
128/**
129 * Does Ring-0 per VM VT-x init.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135{
136 int rc;
137
138#ifdef LOG_ENABLED
139 SUPR0Printf("VMXR0InitVM %x\n", pVM);
140#endif
141 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
142 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
143
144
145 /* Allocate one page for the VM control structure (VMCS). */
146 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
147 AssertRC(rc);
148 if (RT_FAILURE(rc))
149 return rc;
150
151 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
152 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
153 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
154
155 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
156 {
157 /* Allocate one page for the virtual APIC mmio cache. */
158 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
159 AssertRC(rc);
160 if (RT_FAILURE(rc))
161 return rc;
162
163 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
164 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
165 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
166 }
167 else
168 {
169 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
170 pVM->hwaccm.s.vmx.pAPIC = 0;
171 pVM->hwaccm.s.vmx.pAPICPhys = 0;
172 }
173
174 /* Allocate the MSR bitmap if this feature is supported. */
175 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
176 {
177 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
178 AssertRC(rc);
179 if (RT_FAILURE(rc))
180 return rc;
181
182 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
183 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
184 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
185 }
186
187#ifdef LOG_ENABLED
188 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys);
189#endif
190 return VINF_SUCCESS;
191}
192
193/**
194 * Does Ring-0 per VM VT-x termination.
195 *
196 * @returns VBox status code.
197 * @param pVM The VM to operate on.
198 */
199HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
200{
201 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
202 {
203 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
204 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
205 pVM->hwaccm.s.vmx.pVMCS = 0;
206 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
207 }
208 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
209 {
210 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
211 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
212 pVM->hwaccm.s.vmx.pAPIC = 0;
213 pVM->hwaccm.s.vmx.pAPICPhys = 0;
214 }
215 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
216 {
217 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
218 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
219 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
220 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
221 }
222 return VINF_SUCCESS;
223}
224
225/**
226 * Sets up VT-x for the specified VM
227 *
228 * @returns VBox status code.
229 * @param pVM The VM to operate on.
230 */
231HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
232{
233 int rc = VINF_SUCCESS;
234 uint32_t val;
235
236 AssertReturn(pVM, VERR_INVALID_PARAMETER);
237 Assert(pVM->hwaccm.s.vmx.pVMCS);
238
239 /* Set revision dword at the beginning of the VMCS structure. */
240 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
241
242 /* Clear VM Control Structure. */
243 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
244 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
245 if (VBOX_FAILURE(rc))
246 goto vmx_end;
247
248 /* Activate the VM Control Structure. */
249 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
250 if (VBOX_FAILURE(rc))
251 goto vmx_end;
252
253 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
254 * Set required bits to one and zero according to the MSR capabilities.
255 */
256 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
257 /* External and non-maskable interrupts cause VM-exits. */
258 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
259 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
260
261 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
262 AssertRC(rc);
263
264 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
265 * Set required bits to one and zero according to the MSR capabilities.
266 */
267 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
268 /* Program which event cause VM-exits and which features we want to use. */
269 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
270 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
271 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
272 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
273 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
274 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
275
276 /** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
277
278#if HC_ARCH_BITS == 64
279 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
280 {
281 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
282 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
283 Assert(pVM->hwaccm.s.vmx.pAPIC);
284 }
285 else
286 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
287 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
288#endif
289
290#ifdef VBOX_WITH_VTX_MSR_BITMAPS
291 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
292 {
293 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
294 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
295 }
296#endif
297
298 /* We will use the secondary control if it's present. */
299 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
300
301 /* Mask away the bits that the CPU doesn't support */
302 /** @todo make sure they don't conflict with the above requirements. */
303 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
304 pVM->hwaccm.s.vmx.proc_ctls = val;
305
306 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
307 AssertRC(rc);
308
309 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
310 {
311 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
312 * Set required bits to one and zero according to the MSR capabilities.
313 */
314 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
315 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
316
317 /* Mask away the bits that the CPU doesn't support */
318 /** @todo make sure they don't conflict with the above requirements. */
319 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
320
321 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
322 AssertRC(rc);
323 }
324
325 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
326 * Set required bits to one and zero according to the MSR capabilities.
327 */
328 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
329 AssertRC(rc);
330
331 /* VMX_VMCS_CTRL_EXIT_CONTROLS
332 * Set required bits to one and zero according to the MSR capabilities.
333 */
334 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
335#if HC_ARCH_BITS == 64
336 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
337#else
338 /* else Must be zero when AMD64 is not available. */
339#endif
340 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
341 /* Don't acknowledge external interrupts on VM-exit. */
342 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
343 AssertRC(rc);
344
345 /* Forward all exception except #NM & #PF to the guest.
346 * We always need to check pagefaults since our shadow page table can be out of sync.
347 * And we always lazily sync the FPU & XMM state.
348 */
349
350 /*
351 * @todo Possible optimization:
352 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
353 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
354 * registers ourselves of course.
355 *
356 * @note only possible if the current state is actually ours (X86_CR0_TS flag)
357 */
358 pVM->hwaccm.s.vmx.u32TrapMask = HWACCM_VMX_TRAP_MASK;
359 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
360 AssertRC(rc);
361
362 /* Don't filter page faults; all of them should cause a switch. */
363 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
364 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
365 AssertRC(rc);
366
367 /* Init TSC offset to zero. */
368 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
369#if HC_ARCH_BITS == 32
370 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
371#endif
372 AssertRC(rc);
373
374 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
375#if HC_ARCH_BITS == 32
376 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
377#endif
378 AssertRC(rc);
379
380 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
381#if HC_ARCH_BITS == 32
382 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
383#endif
384 AssertRC(rc);
385
386 /* Set the MSR bitmap address. */
387 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
388 {
389 /* Optional */
390 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
391#if HC_ARCH_BITS == 32
392 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32);
393#endif
394 AssertRC(rc);
395 }
396
397 /* Clear MSR controls. */
398 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
399 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
400 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
401#if HC_ARCH_BITS == 32
402 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
403 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
404 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
405#endif
406 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
407 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
408 AssertRC(rc);
409
410 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
411 {
412 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
413 /* Optional */
414 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
415 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
416#if HC_ARCH_BITS == 32
417 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
418#endif
419 AssertRC(rc);
420 }
421
422 /* Set link pointer to -1. Not currently used. */
423#if HC_ARCH_BITS == 32
424 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
425 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
426#else
427 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
428#endif
429 AssertRC(rc);
430
431 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
432 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
433 AssertRC(rc);
434
435vmx_end:
436 VMXR0CheckError(pVM, rc);
437 return rc;
438}
439
440
441/**
442 * Injects an event (trap or external interrupt)
443 *
444 * @returns VBox status code.
445 * @param pVM The VM to operate on.
446 * @param pCtx CPU Context
447 * @param intInfo VMX interrupt info
448 * @param cbInstr Opcode length of faulting instruction
449 * @param errCode Error code (optional)
450 */
451static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
452{
453 int rc;
454
455#ifdef VBOX_STRICT
456 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
457 if (iGate == 0xE)
458 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
459 else
460 if (iGate < 0x20)
461 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
462 else
463 {
464 Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
465 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
466 Assert(pCtx->eflags.u32 & X86_EFL_IF);
467 }
468#endif
469
470 /* Set event injection state. */
471 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
472 intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
473 );
474
475 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
476 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
477
478 AssertRC(rc);
479 return rc;
480}
481
482
483/**
484 * Checks for pending guest interrupts and injects them
485 *
486 * @returns VBox status code.
487 * @param pVM The VM to operate on.
488 * @param pCtx CPU Context
489 */
490static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
491{
492 int rc;
493
494 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
495 if (pVM->hwaccm.s.Event.fPending)
496 {
497 Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
498 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
499 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
500 AssertRC(rc);
501
502 pVM->hwaccm.s.Event.fPending = false;
503 return VINF_SUCCESS;
504 }
505
506 /* When external interrupts are pending, we should exit the VM when IF is set. */
507 if ( !TRPMHasTrap(pVM)
508 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
509 {
510 if (!(pCtx->eflags.u32 & X86_EFL_IF))
511 {
512 Log2(("Enable irq window exit!\n"));
513 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
514 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
515 AssertRC(rc);
516 }
517 else
518 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
519 {
520 uint8_t u8Interrupt;
521
522 rc = PDMGetInterrupt(pVM, &u8Interrupt);
523 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
524 if (VBOX_SUCCESS(rc))
525 {
526 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
527 AssertRC(rc);
528 }
529 else
530 {
531 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
532 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
533 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
534 /* Just continue */
535 }
536 }
537 else
538 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
539 }
540
541#ifdef VBOX_STRICT
542 if (TRPMHasTrap(pVM))
543 {
544 uint8_t u8Vector;
545 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
546 AssertRC(rc);
547 }
548#endif
549
550 if ( pCtx->eflags.u32 & X86_EFL_IF
551 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
552 && TRPMHasTrap(pVM)
553 )
554 {
555 uint8_t u8Vector;
556 int rc;
557 TRPMEVENT enmType;
558 RTGCUINTPTR intInfo;
559 RTGCUINT errCode;
560
561 /* If a new event is pending, then dispatch it now. */
562 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
563 AssertRC(rc);
564 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
565 Assert(enmType != TRPM_SOFTWARE_INT);
566
567 /* Clear the pending trap. */
568 rc = TRPMResetTrap(pVM);
569 AssertRC(rc);
570
571 intInfo = u8Vector;
572 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
573
574 if (enmType == TRPM_TRAP)
575 {
576 switch (u8Vector) {
577 case 8:
578 case 10:
579 case 11:
580 case 12:
581 case 13:
582 case 14:
583 case 17:
584 /* Valid error codes. */
585 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
586 break;
587 default:
588 break;
589 }
590 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
591 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
592 else
593 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
594 }
595 else
596 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
597
598 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
599 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
600 AssertRC(rc);
601 } /* if (interrupts can be dispatched) */
602
603 return VINF_SUCCESS;
604}
605
606/**
607 * Save the host state
608 *
609 * @returns VBox status code.
610 * @param pVM The VM to operate on.
611 */
612HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
613{
614 int rc = VINF_SUCCESS;
615
616 /*
617 * Host CPU Context
618 */
619 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
620 {
621 RTIDTR idtr;
622 RTGDTR gdtr;
623 RTSEL SelTR;
624 PX86DESCHC pDesc;
625 uintptr_t trBase;
626
627 /* Control registers */
628 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
629 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
630 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
631 AssertRC(rc);
632 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
633 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
634 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
635
636 /* Selector registers. */
637 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
638 /** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
639 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
640 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
641#if HC_ARCH_BITS == 32
642 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
643 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
644#endif
645 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
646 SelTR = ASMGetTR();
647 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
648 AssertRC(rc);
649 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
650 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
651 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
652 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
653 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
654 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
655 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
656
657 /* GDTR & IDTR */
658 ASMGetGDTR(&gdtr);
659 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
660 ASMGetIDTR(&idtr);
661 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
662 AssertRC(rc);
663 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
664 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
665
666 /* Save the base address of the TR selector. */
667 if (SelTR > gdtr.cbGdt)
668 {
669 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
670 return VERR_VMX_INVALID_HOST_STATE;
671 }
672
673 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
674#if HC_ARCH_BITS == 64
675 trBase = X86DESC64_BASE(*pDesc);
676#else
677 trBase = X86DESC_BASE(*pDesc);
678#endif
679 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
680 AssertRC(rc);
681 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
682
683 /* FS and GS base. */
684#if HC_ARCH_BITS == 64
685 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
686 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
687 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
688 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
689#endif
690 AssertRC(rc);
691
692 /* Sysenter MSRs. */
693 /** @todo expensive!! */
694 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
695 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
696#if HC_ARCH_BITS == 32
697 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
698 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
699 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
700 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
701#else
702 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
703 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
704 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
705 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
706#endif
707 AssertRC(rc);
708
709 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
710 }
711 return rc;
712}
713
714
715/**
716 * Loads the guest state
717 *
718 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
719 *
720 * @returns VBox status code.
721 * @param pVM The VM to operate on.
722 * @param pCtx Guest context
723 */
724HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
725{
726 int rc = VINF_SUCCESS;
727 RTGCUINTPTR val;
728 X86EFLAGS eflags;
729
730 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
731 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
732 {
733 VMX_WRITE_SELREG(ES, es);
734 AssertRC(rc);
735
736 VMX_WRITE_SELREG(CS, cs);
737 AssertRC(rc);
738
739 VMX_WRITE_SELREG(SS, ss);
740 AssertRC(rc);
741
742 VMX_WRITE_SELREG(DS, ds);
743 AssertRC(rc);
744
745 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
746 VMX_WRITE_SELREG(FS, fs);
747 AssertRC(rc);
748
749 VMX_WRITE_SELREG(GS, gs);
750 AssertRC(rc);
751 }
752
753 /* Guest CPU context: LDTR. */
754 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
755 {
756 if (pCtx->ldtr == 0)
757 {
758 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
759 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
760 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
761 /** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
762 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
763 }
764 else
765 {
766 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
767 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
768 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
769 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
770 }
771 AssertRC(rc);
772 }
773 /* Guest CPU context: TR. */
774 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
775 {
776 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
777
778 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
779 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
780 {
781 RTGCPHYS GCPhys;
782
783 /* We convert it here every time as pci regions could be reconfigured. */
784 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
785 AssertRC(rc);
786
787 Assert(pCtx->tr == 0);
788 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(VBOXTSS));
789 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
790 }
791 else
792 {
793 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
794 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
795 }
796 val = pCtx->trHid.Attr.u;
797
798 /* The TSS selector must be busy. */
799 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
800 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
801 else
802 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
803 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
804
805 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
806 AssertRC(rc);
807 }
808 /* Guest CPU context: GDTR. */
809 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
810 {
811 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
812 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
813 AssertRC(rc);
814 }
815 /* Guest CPU context: IDTR. */
816 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
817 {
818 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
819 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
820 AssertRC(rc);
821 }
822
823 /*
824 * Sysenter MSRs (unconditional)
825 */
826 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
827 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
828 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
829 AssertRC(rc);
830
831 /* Control registers */
832 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
833 {
834 val = pCtx->cr0;
835 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
836 Log2(("Guest CR0-shadow %08x\n", val));
837 if (CPUMIsGuestFPUStateActive(pVM) == false)
838 {
839 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
840 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
841 }
842 else
843 {
844 /** @todo check if we support the old style mess correctly. */
845 if (!(val & X86_CR0_NE))
846 {
847 Log(("Forcing X86_CR0_NE!!!\n"));
848
849 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
850 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
851 {
852 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_MF);
853 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
854 AssertRC(rc);
855 pVM->hwaccm.s.fFPUOldStyleOverride = true;
856 }
857 }
858
859 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
860 }
861 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
862 val |= X86_CR0_PE | X86_CR0_PG;
863 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
864 val |= X86_CR0_WP;
865
866 /* Always enable caching. */
867 val &= ~(X86_CR0_CD|X86_CR0_NW);
868
869 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
870 Log2(("Guest CR0 %08x\n", val));
871 /* CR0 flags owned by the host; if the guests attempts to change them, then
872 * the VM will exit.
873 */
874 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
875 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
876 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
877 | X86_CR0_TS
878 | X86_CR0_ET /* Bit not restored during VM-exit! */
879 | X86_CR0_CD /* Bit not restored during VM-exit! */
880 | X86_CR0_NW /* Bit not restored during VM-exit! */
881 | X86_CR0_NE
882 | X86_CR0_MP;
883 pVM->hwaccm.s.vmx.cr0_mask = val;
884
885 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
886 Log2(("Guest CR0-mask %08x\n", val));
887 AssertRC(rc);
888 }
889 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
890 {
891 /* CR4 */
892 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
893 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
894 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
895 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
896 switch(pVM->hwaccm.s.enmShadowMode)
897 {
898 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
899 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
900 case PGMMODE_32_BIT: /* 32-bit paging. */
901 break;
902
903 case PGMMODE_PAE: /* PAE paging. */
904 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
905 /** @todo use normal 32 bits paging */
906 val |= X86_CR4_PAE;
907 break;
908
909 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
910 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
911#ifdef VBOX_ENABLE_64_BITS_GUESTS
912 break;
913#else
914 AssertFailed();
915 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
916#endif
917 default: /* shut up gcc */
918 AssertFailed();
919 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
920 }
921 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
922 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
923 val |= X86_CR4_VME;
924
925 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
926 Log2(("Guest CR4 %08x\n", val));
927 /* CR4 flags owned by the host; if the guests attempts to change them, then
928 * the VM will exit.
929 */
930 val = X86_CR4_PAE
931 | X86_CR4_PGE
932 | X86_CR4_PSE
933 | X86_CR4_VMXE;
934 pVM->hwaccm.s.vmx.cr4_mask = val;
935
936 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
937 Log2(("Guest CR4-mask %08x\n", val));
938 AssertRC(rc);
939 }
940
941 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
942 {
943 /* Save our shadow CR3 register. */
944 val = PGMGetHyperCR3(pVM);
945 Assert(val);
946 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
947 AssertRC(rc);
948 }
949
950 /* Debug registers. */
951 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
952 {
953 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
954 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
955
956 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
957 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
958 pCtx->dr[7] |= 0x400; /* must be one */
959
960 /* Resync DR7 */
961 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
962 AssertRC(rc);
963
964 /* Sync the debug state now if any breakpoint is armed. */
965 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
966 && !CPUMIsGuestDebugStateActive(pVM)
967 && !DBGFIsStepping(pVM))
968 {
969 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxArmed);
970
971 /* Disable drx move intercepts. */
972 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
973 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
974 AssertRC(rc);
975
976 /* Save the host and load the guest debug state. */
977 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
978 AssertRC(rc);
979 }
980
981 /* IA32_DEBUGCTL MSR. */
982 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
983 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
984 AssertRC(rc);
985
986 /** @todo do we really ever need this? */
987 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
988 AssertRC(rc);
989 }
990
991 /* EIP, ESP and EFLAGS */
992 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
993 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
994 AssertRC(rc);
995
996 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
997 eflags = pCtx->eflags;
998 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
999 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1000
1001 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1002 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1003 {
1004 eflags.Bits.u1VM = 1;
1005 eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
1006 eflags.Bits.u2IOPL = 3;
1007 }
1008
1009 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1010 AssertRC(rc);
1011
1012 /* TSC offset. */
1013 uint64_t u64TSCOffset;
1014
1015 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1016 {
1017 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1018#if HC_ARCH_BITS == 64
1019 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1020#else
1021 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
1022 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
1023#endif
1024 AssertRC(rc);
1025
1026 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1027 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1028 AssertRC(rc);
1029 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
1030 }
1031 else
1032 {
1033 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1034 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1035 AssertRC(rc);
1036 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1037 }
1038
1039 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1040 * Set required bits to one and zero according to the MSR capabilities.
1041 */
1042 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1043 /* 64 bits guest mode? */
1044 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1045 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1046 /* else Must be zero when AMD64 is not available. */
1047
1048 /* Mask away the bits that the CPU doesn't support */
1049 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1050 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1051 AssertRC(rc);
1052
1053 /* 64 bits guest mode? */
1054 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1055 {
1056#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
1057 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1058#else
1059 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1060#endif
1061 /* Unconditionally update these as wrmsr might have changed them. */
1062 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1063 AssertRC(rc);
1064 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1065 AssertRC(rc);
1066 }
1067 else
1068 {
1069 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1070 }
1071
1072#ifdef DEBUG
1073 /* Intercept X86_XCPT_DB if stepping is enabled */
1074 if (DBGFIsStepping(pVM))
1075 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_DB);
1076 else
1077 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_DB);
1078
1079 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1080#endif
1081
1082 /* Done. */
1083 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1084
1085 return rc;
1086}
1087
1088/**
1089 * Runs guest code in a VT-x VM.
1090 *
1091 * @returns VBox status code.
1092 * @param pVM The VM to operate on.
1093 * @param pCtx Guest context
1094 */
1095HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1096{
1097 int rc = VINF_SUCCESS;
1098 RTCCUINTREG val, valShadow;
1099 RTCCUINTREG exitReason, instrError, cbInstr;
1100 RTGCUINTPTR exitQualification;
1101 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1102 RTGCUINTPTR errCode, instrInfo, uInterruptState;
1103 bool fSyncTPR = false;
1104 unsigned cResume = 0;
1105#ifdef VBOX_STRICT
1106 RTCPUID idCpuCheck;
1107#endif
1108
1109 Log2(("\nE"));
1110
1111 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1112
1113#ifdef VBOX_STRICT
1114 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1115 AssertRC(rc);
1116 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1117
1118 /* allowed zero */
1119 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1120 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1121
1122 /* allowed one */
1123 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1124 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1125
1126 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1127 AssertRC(rc);
1128 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1129
1130 /* allowed zero */
1131 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1132 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1133
1134 /* allowed one */
1135 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1136 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1137
1138 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1139 AssertRC(rc);
1140 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1141
1142 /* allowed zero */
1143 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1144 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1145
1146 /* allowed one */
1147 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1148 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1149
1150 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1151 AssertRC(rc);
1152 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1153
1154 /* allowed zero */
1155 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1156 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1157
1158 /* allowed one */
1159 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1160 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1161#endif
1162
1163 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1164 */
1165ResumeExecution:
1166 AssertMsg(pVM->hwaccm.s.idEnteredCpu == RTMpCpuId(),
1167 ("Expected %d, I'm %d; cResume=%d exitReason=%RTreg exitQualification=%RTreg\n",
1168 (int)pVM->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
1169
1170 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1171 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1172 {
1173 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1174 rc = VINF_EM_RAW_INTERRUPT;
1175 goto end;
1176 }
1177
1178 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1179 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1180 {
1181 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1182 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1183 {
1184 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1185 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1186 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1187 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1188 */
1189 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1190 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1191 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1192 AssertRC(rc);
1193 }
1194 }
1195 else
1196 {
1197 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1198 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1199 AssertRC(rc);
1200 }
1201
1202 /* Check for pending actions that force us to go back to ring 3. */
1203 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1204 {
1205 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1206 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1207 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1208 rc = VINF_EM_RAW_TO_R3;
1209 goto end;
1210 }
1211 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1212 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1213 {
1214 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1215 rc = VINF_EM_PENDING_REQUEST;
1216 goto end;
1217 }
1218
1219 /* When external interrupts are pending, we should exit the VM when IF is set. */
1220 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
1221 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1222 if (VBOX_FAILURE(rc))
1223 {
1224 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1225 goto end;
1226 }
1227
1228 /** @todo check timers?? */
1229
1230 /* TPR caching using CR8 is only available in 64 bits mode */
1231 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1232 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1233 /*
1234 * @todo reduce overhead
1235 */
1236 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1237 && pVM->hwaccm.s.vmx.pAPIC)
1238 {
1239 /* TPR caching in CR8 */
1240 uint8_t u8TPR;
1241 bool fPending;
1242
1243 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1244 AssertRC(rc);
1245 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1246 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1247
1248 /* Two options here:
1249 * - external interrupt pending, but masked by the TPR value.
1250 * -> a CR8 update that lower the current TPR value should cause an exit
1251 * - no pending interrupts
1252 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1253 */
1254 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1255 AssertRC(rc);
1256
1257 /* Always sync back the TPR; we should optimize this though (@todo) */
1258 fSyncTPR = true;
1259 }
1260
1261 /*
1262 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1263 * (until the actual world switch)
1264 */
1265#ifdef VBOX_STRICT
1266 idCpuCheck = RTMpCpuId();
1267#endif
1268 /* Save the host state first. */
1269 rc = VMXR0SaveHostState(pVM);
1270 if (rc != VINF_SUCCESS)
1271 {
1272 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1273 goto end;
1274 }
1275 /* Load the guest state */
1276 rc = VMXR0LoadGuestState(pVM, pCtx);
1277 if (rc != VINF_SUCCESS)
1278 {
1279 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1280 goto end;
1281 }
1282
1283 /* Non-register state Guest Context */
1284 /** @todo change me according to cpu state */
1285 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1286 AssertRC(rc);
1287
1288 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1289
1290 /* Manual save and restore:
1291 * - General purpose registers except RIP, RSP
1292 *
1293 * Trashed:
1294 * - CR2 (we don't care)
1295 * - LDTR (reset to 0)
1296 * - DRx (presumably not changed at all)
1297 * - DR7 (reset to 0x400)
1298 * - EFLAGS (reset to RT_BIT(1); not relevant)
1299 *
1300 */
1301
1302 /* All done! Let's start VM execution. */
1303 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1304#ifdef VBOX_STRICT
1305 Assert(idCpuCheck == RTMpCpuId());
1306#endif
1307 TMNotifyStartOfExecution(pVM);
1308 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1309 TMNotifyEndOfExecution(pVM);
1310
1311 /* In case we execute a goto ResumeExecution later on. */
1312 pVM->hwaccm.s.vmx.fResumeVM = true;
1313
1314 /*
1315 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1316 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1317 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1318 */
1319
1320 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1321 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1322
1323 switch (rc)
1324 {
1325 case VINF_SUCCESS:
1326 break;
1327
1328 case VERR_VMX_INVALID_VMXON_PTR:
1329 AssertFailed();
1330 goto end;
1331
1332 case VERR_VMX_UNABLE_TO_START_VM:
1333 case VERR_VMX_UNABLE_TO_RESUME_VM:
1334 {
1335#ifdef VBOX_STRICT
1336 int rc1;
1337
1338 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1339 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1340 AssertRC(rc1);
1341 if (rc1 == VINF_SUCCESS)
1342 {
1343 RTGDTR gdtr;
1344 PX86DESCHC pDesc;
1345
1346 ASMGetGDTR(&gdtr);
1347
1348 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1349 Log(("Current stack %08x\n", &rc1));
1350
1351
1352 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1353 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1354 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1355 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1356 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1357 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1358 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1359 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1360 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1361 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1362
1363 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1364 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1365
1366 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1367 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1368
1369 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1370 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1371
1372 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1373 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1374 if (val < gdtr.cbGdt)
1375 {
1376 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1377 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1378 }
1379
1380 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1381 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1382 if (val < gdtr.cbGdt)
1383 {
1384 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1385 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1386 }
1387
1388 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1389 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1390 if (val < gdtr.cbGdt)
1391 {
1392 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1393 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1394 }
1395
1396 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1397 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1398 if (val < gdtr.cbGdt)
1399 {
1400 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1401 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1402 }
1403
1404 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1405 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1406 if (val < gdtr.cbGdt)
1407 {
1408 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1409 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1410 }
1411
1412 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1413 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1414 if (val < gdtr.cbGdt)
1415 {
1416 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1417 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1418 }
1419
1420 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1421 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1422 if (val < gdtr.cbGdt)
1423 {
1424 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1425 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1426 }
1427
1428 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1429 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1430
1431 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1432 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1433 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1434 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1435
1436 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1437 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1438
1439 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1440 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1441
1442 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1443 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1444
1445 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1446 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1447 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1448 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1449
1450#if HC_ARCH_BITS == 64
1451 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1452 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1453 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1454 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1455 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1456#endif
1457 }
1458#endif /* VBOX_STRICT */
1459 goto end;
1460 }
1461
1462 default:
1463 /* impossible */
1464 AssertFailed();
1465 goto end;
1466 }
1467 /* Success. Query the guest state and figure out what has happened. */
1468
1469 /* Investigate why there was a VM-exit. */
1470 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1471 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1472
1473 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1474 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1475 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1476 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1477 intInfo = val;
1478 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1479 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1480 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1481 instrInfo = val;
1482 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1483 exitQualification = val;
1484 AssertRC(rc);
1485
1486 /* Let's first sync back eip, esp, and eflags. */
1487 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1488 AssertRC(rc);
1489 pCtx->rip = val;
1490 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1491 AssertRC(rc);
1492 pCtx->rsp = val;
1493 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1494 AssertRC(rc);
1495 pCtx->eflags.u32 = val;
1496
1497 /* Take care of instruction fusing (sti, mov ss) */
1498 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1499 uInterruptState = val;
1500 if (uInterruptState != 0)
1501 {
1502 Assert(uInterruptState <= 2); /* only sti & mov ss */
1503 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1504 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1505 }
1506 else
1507 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1508
1509 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1510 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1511 {
1512 /* Hide our emulation flags */
1513 pCtx->eflags.Bits.u1VM = 0;
1514 pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1515 pCtx->eflags.Bits.u1VIF = 0;
1516 pCtx->eflags.Bits.u2IOPL = 0;
1517 }
1518
1519 /* Control registers. */
1520 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1521 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1522 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1523 CPUMSetGuestCR0(pVM, val);
1524
1525 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1526 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1527 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1528 CPUMSetGuestCR4(pVM, val);
1529
1530 CPUMSetGuestCR2(pVM, ASMGetCR2());
1531
1532 /* Sync back DR7 here. */
1533 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1534 pCtx->dr[7] = val;
1535
1536 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1537 VMX_READ_SELREG(ES, es);
1538 VMX_READ_SELREG(SS, ss);
1539 VMX_READ_SELREG(CS, cs);
1540 VMX_READ_SELREG(DS, ds);
1541 VMX_READ_SELREG(FS, fs);
1542 VMX_READ_SELREG(GS, gs);
1543
1544 /*
1545 * System MSRs
1546 */
1547 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1548 pCtx->SysEnter.cs = val;
1549 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1550 pCtx->SysEnter.eip = val;
1551 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1552 pCtx->SysEnter.esp = val;
1553
1554 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1555 VMX_READ_SELREG(LDTR, ldtr);
1556 VMX_READ_SELREG(TR, tr);
1557
1558 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1559 pCtx->gdtr.cbGdt = val;
1560 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1561 pCtx->gdtr.pGdt = val;
1562
1563 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1564 pCtx->idtr.cbIdt = val;
1565 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1566 pCtx->idtr.pIdt = val;
1567
1568 /** @note NOW IT'S SAFE FOR LOGGING! */
1569 Log2(("Raw exit reason %08x\n", exitReason));
1570
1571 /* Check if an injected event was interrupted prematurely. */
1572 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1573 AssertRC(rc);
1574 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1575 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1576 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1577 {
1578 pVM->hwaccm.s.Event.fPending = true;
1579 /* Error code present? */
1580 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1581 {
1582 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1583 AssertRC(rc);
1584 pVM->hwaccm.s.Event.errCode = val;
1585 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1586 }
1587 else
1588 {
1589 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1590 pVM->hwaccm.s.Event.errCode = 0;
1591 }
1592 }
1593
1594#ifdef VBOX_STRICT
1595 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1596 HWACCMDumpRegs(pVM, pCtx);
1597#endif
1598
1599 Log2(("E%d", exitReason));
1600 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1601 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1602 Log2(("Interruption error code %d\n", errCode));
1603 Log2(("IntInfo = %08x\n", intInfo));
1604 Log2(("New EIP=%VGv\n", pCtx->rip));
1605
1606 if (fSyncTPR)
1607 {
1608 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1609 AssertRC(rc);
1610 }
1611
1612 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1613 switch (exitReason)
1614 {
1615 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1616 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1617 {
1618 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1619
1620 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1621 {
1622 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1623 /* External interrupt; leave to allow it to be dispatched again. */
1624 rc = VINF_EM_RAW_INTERRUPT;
1625 break;
1626 }
1627 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1628 {
1629 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1630 /* External interrupt; leave to allow it to be dispatched again. */
1631 rc = VINF_EM_RAW_INTERRUPT;
1632 break;
1633
1634 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1635 AssertFailed(); /* can't come here; fails the first check. */
1636 break;
1637
1638 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1639 Assert(vector == 3 || vector == 4);
1640 /* no break */
1641 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1642 Log2(("Hardware/software interrupt %d\n", vector));
1643 switch (vector)
1644 {
1645 case X86_XCPT_NM:
1646 {
1647 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1648
1649 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1650 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1651 rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1652 if (rc == VINF_SUCCESS)
1653 {
1654 Assert(CPUMIsGuestFPUStateActive(pVM));
1655
1656 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1657
1658 /* Continue execution. */
1659 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1660 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1661
1662 goto ResumeExecution;
1663 }
1664
1665 Log(("Forward #NM fault to the guest\n"));
1666 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1667 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1668 AssertRC(rc);
1669 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1670 goto ResumeExecution;
1671 }
1672
1673 case X86_XCPT_PF: /* Page fault */
1674 {
1675 Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1676 /* Exit qualification contains the linear address of the page fault. */
1677 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1678 TRPMSetErrorCode(pVM, errCode);
1679 TRPMSetFaultAddress(pVM, exitQualification);
1680
1681 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1682 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1683 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1684 if (rc == VINF_SUCCESS)
1685 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1686 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1687 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1688
1689 TRPMResetTrap(pVM);
1690
1691 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1692 goto ResumeExecution;
1693 }
1694 else
1695 if (rc == VINF_EM_RAW_GUEST_TRAP)
1696 { /* A genuine pagefault.
1697 * Forward the trap to the guest by injecting the exception and resuming execution.
1698 */
1699 Log2(("Forward page fault to the guest\n"));
1700 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1701 /* The error code might have been changed. */
1702 errCode = TRPMGetErrorCode(pVM);
1703
1704 TRPMResetTrap(pVM);
1705
1706 /* Now we must update CR2. */
1707 pCtx->cr2 = exitQualification;
1708 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1709 AssertRC(rc);
1710
1711 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1712 goto ResumeExecution;
1713 }
1714#ifdef VBOX_STRICT
1715 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1716 Log2(("PGMTrap0eHandler failed with %d\n", rc));
1717#endif
1718 /* Need to go back to the recompiler to emulate the instruction. */
1719 TRPMResetTrap(pVM);
1720 break;
1721 }
1722
1723 case X86_XCPT_MF: /* Floating point exception. */
1724 {
1725 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1726 if (!(pCtx->cr0 & X86_CR0_NE))
1727 {
1728 /* old style FPU error reporting needs some extra work. */
1729 /** @todo don't fall back to the recompiler, but do it manually. */
1730 rc = VINF_EM_RAW_EMULATE_INSTR;
1731 break;
1732 }
1733 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1734 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1735 AssertRC(rc);
1736
1737 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1738 goto ResumeExecution;
1739 }
1740
1741 case X86_XCPT_DB: /* Debug exception. */
1742 {
1743 uint64_t uDR6;
1744
1745 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
1746 *
1747 * Exit qualification bits:
1748 * 3:0 B0-B3 which breakpoint condition was met
1749 * 12:4 Reserved (0)
1750 * 13 BD - debug register access detected
1751 * 14 BS - single step execution or branch taken
1752 * 63:15 Reserved (0)
1753 */
1754 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDB);
1755
1756 /* Note that we don't support guest and host-initiated debugging at the same time. */
1757 Assert(DBGFIsStepping(pVM));
1758
1759 uDR6 = X86_DR6_INIT_VAL;
1760 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
1761 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
1762 if (rc == VINF_EM_RAW_GUEST_TRAP)
1763 {
1764 /* @todo this isn't working, but we'll never get here normally. */
1765
1766 /* Update DR6 here. */
1767 pCtx->dr[6] = uDR6;
1768
1769 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
1770 pCtx->dr[7] &= ~X86_DR7_GD;
1771
1772 /* Paranoia. */
1773 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1774 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1775 pCtx->dr[7] |= 0x400; /* must be one */
1776
1777 /* Resync DR7 */
1778 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
1779 AssertRC(rc);
1780
1781 Log(("Trap %x (debug) at %VGv exit qualification %VX64\n", vector, pCtx->rip, exitQualification));
1782 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1783 AssertRC(rc);
1784
1785 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1786 goto ResumeExecution;
1787 }
1788 /* Return to ring 3 to deal with the debug exit code. */
1789 break;
1790 }
1791
1792#ifdef VBOX_STRICT
1793 case X86_XCPT_DE: /* Divide error. */
1794 case X86_XCPT_GP: /* General protection failure exception.*/
1795 case X86_XCPT_UD: /* Unknown opcode exception. */
1796 case X86_XCPT_SS: /* Stack segment exception. */
1797 case X86_XCPT_NP: /* Segment not present exception. */
1798 {
1799 switch(vector)
1800 {
1801 case X86_XCPT_DE:
1802 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1803 break;
1804 case X86_XCPT_UD:
1805 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1806 break;
1807 case X86_XCPT_SS:
1808 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1809 break;
1810 case X86_XCPT_NP:
1811 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1812 break;
1813 case X86_XCPT_GP:
1814 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1815 break;
1816 }
1817
1818 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
1819 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1820 AssertRC(rc);
1821
1822 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1823 goto ResumeExecution;
1824 }
1825#endif
1826 default:
1827 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1828 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
1829 break;
1830 } /* switch (vector) */
1831
1832 break;
1833
1834 default:
1835 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
1836 AssertFailed();
1837 break;
1838 }
1839
1840 break;
1841 }
1842
1843 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1844 /* Clear VM-exit on IF=1 change. */
1845 Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1846 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1847 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1848 AssertRC(rc);
1849 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1850 goto ResumeExecution; /* we check for pending guest interrupts there */
1851
1852 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
1853 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
1854 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1855 /* Skip instruction and continue directly. */
1856 pCtx->rip += cbInstr;
1857 /* Continue execution.*/
1858 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1859 goto ResumeExecution;
1860
1861 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1862 {
1863 Log2(("VMX: Cpuid %x\n", pCtx->eax));
1864 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1865 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1866 if (rc == VINF_SUCCESS)
1867 {
1868 /* Update EIP and continue execution. */
1869 Assert(cbInstr == 2);
1870 pCtx->rip += cbInstr;
1871 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1872 goto ResumeExecution;
1873 }
1874 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1875 rc = VINF_EM_RAW_EMULATE_INSTR;
1876 break;
1877 }
1878
1879 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1880 {
1881 Log2(("VMX: Rdtsc\n"));
1882 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1883 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1884 if (rc == VINF_SUCCESS)
1885 {
1886 /* Update EIP and continue execution. */
1887 Assert(cbInstr == 2);
1888 pCtx->rip += cbInstr;
1889 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1890 goto ResumeExecution;
1891 }
1892 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1893 rc = VINF_EM_RAW_EMULATE_INSTR;
1894 break;
1895 }
1896
1897 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1898 {
1899 Log2(("VMX: invlpg\n"));
1900 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1901 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1902 if (rc == VINF_SUCCESS)
1903 {
1904 /* Update EIP and continue execution. */
1905 pCtx->rip += cbInstr;
1906 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1907 goto ResumeExecution;
1908 }
1909 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1910 break;
1911 }
1912
1913 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1914 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1915 {
1916 uint32_t cbSize;
1917
1918 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1919 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1920 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1921 if (rc == VINF_SUCCESS)
1922 {
1923 /* EIP has been updated already. */
1924
1925 /* Only resume if successful. */
1926 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1927 goto ResumeExecution;
1928 }
1929 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1930 break;
1931 }
1932
1933 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1934 {
1935 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1936 {
1937 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1938 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1939 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1940 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1941 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1942 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1943
1944 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1945 {
1946 case 0:
1947 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1948 break;
1949 case 2:
1950 break;
1951 case 3:
1952 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1953 break;
1954 case 4:
1955 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1956 break;
1957 case 8:
1958 /* CR8 contains the APIC TPR */
1959 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1960 break;
1961
1962 default:
1963 AssertFailed();
1964 break;
1965 }
1966 /* Check if a sync operation is pending. */
1967 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1968 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1969 {
1970 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1971 AssertRC(rc);
1972 }
1973 break;
1974
1975 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1976 Log2(("VMX: mov x, crx\n"));
1977 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1978
1979 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1980 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1981
1982 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1983 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1984 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1985 break;
1986
1987 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1988 Log2(("VMX: clts\n"));
1989 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1990 rc = EMInterpretCLTS(pVM);
1991 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1992 break;
1993
1994 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1995 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1996 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1997 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1998 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1999 break;
2000 }
2001
2002 /* Update EIP if no error occurred. */
2003 if (VBOX_SUCCESS(rc))
2004 pCtx->rip += cbInstr;
2005
2006 if (rc == VINF_SUCCESS)
2007 {
2008 /* Only resume if successful. */
2009 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2010 goto ResumeExecution;
2011 }
2012 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2013 break;
2014 }
2015
2016 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2017 {
2018 if (!DBGFIsStepping(pVM))
2019 {
2020 /* Disable drx move intercepts. */
2021 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2022 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2023 AssertRC(rc);
2024
2025 /* Save the host and load the guest debug state. */
2026 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
2027 AssertRC(rc);
2028
2029#ifdef VBOX_WITH_STATISTICS
2030 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
2031 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2032 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2033 else
2034 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2035#endif
2036
2037 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2038 goto ResumeExecution;
2039 }
2040
2041 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2042 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2043 {
2044 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2045 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2046 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2047 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2048 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2049 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2050 Log2(("DR7=%08x\n", pCtx->dr[7]));
2051 }
2052 else
2053 {
2054 Log2(("VMX: mov x, drx\n"));
2055 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2056 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2057 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2058 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2059 }
2060 /* Update EIP if no error occurred. */
2061 if (VBOX_SUCCESS(rc))
2062 pCtx->rip += cbInstr;
2063
2064 if (rc == VINF_SUCCESS)
2065 {
2066 /* Only resume if successful. */
2067 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2068 goto ResumeExecution;
2069 }
2070 Assert(rc == VERR_EM_INTERPRETER);
2071 break;
2072 }
2073
2074 /** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2075 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2076 {
2077 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2078 uint32_t uPort;
2079 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2080
2081 /** @todo necessary to make the distinction? */
2082 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2083 {
2084 uPort = pCtx->edx & 0xffff;
2085 }
2086 else
2087 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2088
2089 /* paranoia */
2090 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2091 {
2092 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2093 break;
2094 }
2095
2096 uint32_t cbSize = aIOSize[uIOWidth];
2097
2098 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2099 {
2100 /* ins/outs */
2101 uint32_t prefix = 0;
2102 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
2103 prefix |= PREFIX_REP;
2104
2105 if (fIOWrite)
2106 {
2107 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2108 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
2109 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2110 }
2111 else
2112 {
2113 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2114 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
2115 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2116 }
2117 }
2118 else
2119 {
2120 /* normal in/out */
2121 uint32_t uAndVal = aIOOpAnd[uIOWidth];
2122
2123 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2124
2125 if (fIOWrite)
2126 {
2127 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2128 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2129 }
2130 else
2131 {
2132 uint32_t u32Val = 0;
2133
2134 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2135 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2136 if (IOM_SUCCESS(rc))
2137 {
2138 /* Write back to the EAX register. */
2139 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2140 }
2141 }
2142 }
2143 /*
2144 * Handled the I/O return codes.
2145 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2146 */
2147 if (IOM_SUCCESS(rc))
2148 {
2149 /* Update EIP and continue execution. */
2150 pCtx->rip += cbInstr;
2151 if (RT_LIKELY(rc == VINF_SUCCESS))
2152 {
2153 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2154 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2155 {
2156 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxIOCheck);
2157 for (unsigned i=0;i<4;i++)
2158 {
2159 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2160
2161 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
2162 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2163 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2164 {
2165 uint64_t uDR6;
2166
2167 Assert(CPUMIsGuestDebugStateActive(pVM));
2168
2169 uDR6 = ASMGetDR6();
2170
2171 /* Clear all breakpoint status flags and set the one we just hit. */
2172 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2173 uDR6 |= RT_BIT(i);
2174
2175 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2176 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2177 * the contents have been read.
2178 */
2179 ASMSetDR6(uDR6);
2180
2181 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2182 pCtx->dr[7] &= ~X86_DR7_GD;
2183
2184 /* Paranoia. */
2185 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2186 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2187 pCtx->dr[7] |= 0x400; /* must be one */
2188
2189 /* Resync DR7 */
2190 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2191 AssertRC(rc);
2192
2193 /* Construct inject info. */
2194 intInfo = X86_XCPT_DB;
2195 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2196 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2197
2198 Log(("Inject IO debug trap at %VGv\n", pCtx->rip));
2199 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
2200 AssertRC(rc);
2201
2202 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2203 goto ResumeExecution;
2204 }
2205 }
2206 }
2207
2208 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2209 goto ResumeExecution;
2210 }
2211 break;
2212 }
2213
2214#ifdef VBOX_STRICT
2215 if (rc == VINF_IOM_HC_IOPORT_READ)
2216 Assert(!fIOWrite);
2217 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2218 Assert(fIOWrite);
2219 else
2220 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2221#endif
2222 break;
2223 }
2224
2225 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2226 LogFlow(("VMX_EXIT_TPR\n"));
2227 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2228 goto ResumeExecution;
2229
2230 default:
2231 /* The rest is handled after syncing the entire CPU state. */
2232 break;
2233 }
2234
2235 /* Note: the guest state isn't entirely synced back at this stage. */
2236
2237 /* Investigate why there was a VM-exit. (part 2) */
2238 switch (exitReason)
2239 {
2240 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2241 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2242 /* Already handled above. */
2243 break;
2244
2245 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2246 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2247 break;
2248
2249 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2250 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2251 rc = VINF_EM_RAW_INTERRUPT;
2252 AssertFailed(); /* Can't happen. Yet. */
2253 break;
2254
2255 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2256 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2257 rc = VINF_EM_RAW_INTERRUPT;
2258 AssertFailed(); /* Can't happen afaik. */
2259 break;
2260
2261 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2262 rc = VERR_EM_INTERPRETER;
2263 break;
2264
2265 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2266 /** Check if external interrupts are pending; if so, don't switch back. */
2267 pCtx->rip++; /* skip hlt */
2268 if ( pCtx->eflags.Bits.u1IF
2269 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2270 goto ResumeExecution;
2271
2272 rc = VINF_EM_HALT;
2273 break;
2274
2275 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2276 AssertFailed(); /* can't happen. */
2277 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2278 break;
2279
2280 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2281 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2282 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2283 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2284 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2285 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2286 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2287 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2288 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2289 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2290 /** @todo inject #UD immediately */
2291 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2292 break;
2293
2294 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2295 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2296 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2297 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2298 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2299 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2300 /* already handled above */
2301 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2302 || rc == VINF_EM_RAW_INTERRUPT
2303 || rc == VERR_EM_INTERPRETER
2304 || rc == VINF_EM_RAW_EMULATE_INSTR
2305 || rc == VINF_PGM_SYNC_CR3
2306 || rc == VINF_IOM_HC_IOPORT_READ
2307 || rc == VINF_IOM_HC_IOPORT_WRITE
2308 || rc == VINF_EM_RAW_GUEST_TRAP
2309 || rc == VINF_TRPM_XCPT_DISPATCHED
2310 || rc == VINF_EM_RESCHEDULE_REM,
2311 ("rc = %d\n", rc));
2312 break;
2313
2314 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2315 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2316 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2317 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2318 rc = VERR_EM_INTERPRETER;
2319 break;
2320
2321 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2322 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2323 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2324 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2325 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2326 break;
2327
2328 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2329 Assert(rc == VINF_EM_RAW_INTERRUPT);
2330 break;
2331
2332 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2333 {
2334#ifdef VBOX_STRICT
2335 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2336
2337 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2338 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2339
2340 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2341 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2342
2343 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2344 Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2345
2346 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2347 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2348
2349 VMX_LOG_SELREG(CS, "CS");
2350 VMX_LOG_SELREG(DS, "DS");
2351 VMX_LOG_SELREG(ES, "ES");
2352 VMX_LOG_SELREG(FS, "FS");
2353 VMX_LOG_SELREG(GS, "GS");
2354 VMX_LOG_SELREG(SS, "SS");
2355 VMX_LOG_SELREG(TR, "TR");
2356 VMX_LOG_SELREG(LDTR, "LDTR");
2357
2358 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2359 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2360 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2361 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2362#endif /* VBOX_STRICT */
2363 rc = VERR_VMX_INVALID_GUEST_STATE;
2364 break;
2365 }
2366
2367 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2368 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2369 default:
2370 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
2371 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2372 break;
2373
2374 }
2375end:
2376
2377 /* Signal changes for the recompiler. */
2378 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2379
2380 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2381 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2382 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2383 {
2384 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2385 /* On the next entry we'll only sync the host context. */
2386 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2387 }
2388 else
2389 {
2390 /* On the next entry we'll sync everything. */
2391 /** @todo we can do better than this */
2392 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2393 }
2394
2395 /* translate into a less severe return code */
2396 if (rc == VERR_EM_INTERPRETER)
2397 rc = VINF_EM_RAW_EMULATE_INSTR;
2398 else
2399 /* Try to extract more information about what might have gone wrong here. */
2400 if (rc == VERR_VMX_INVALID_VMCS_PTR)
2401 {
2402 VMXGetActivateVMCS(&pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys);
2403 pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS;
2404 }
2405
2406 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2407
2408 Log2(("X"));
2409 return rc;
2410}
2411
2412
2413/**
2414 * Enters the VT-x session
2415 *
2416 * @returns VBox status code.
2417 * @param pVM The VM to operate on.
2418 * @param pCpu CPU info struct
2419 */
2420HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2421{
2422 Assert(pVM->hwaccm.s.vmx.fSupported);
2423
2424 unsigned cr4 = ASMGetCR4();
2425 if (!(cr4 & X86_CR4_VMXE))
2426 {
2427 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2428 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2429 }
2430
2431 /* Activate the VM Control Structure. */
2432 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2433 if (VBOX_FAILURE(rc))
2434 return rc;
2435
2436 pVM->hwaccm.s.vmx.fResumeVM = false;
2437 return VINF_SUCCESS;
2438}
2439
2440
2441/**
2442 * Leaves the VT-x session
2443 *
2444 * @returns VBox status code.
2445 * @param pVM The VM to operate on.
2446 * @param pCtx CPU context
2447 */
2448HWACCMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx)
2449{
2450 Assert(pVM->hwaccm.s.vmx.fSupported);
2451
2452 /* Save the guest debug state if necessary. */
2453 if (CPUMIsGuestDebugStateActive(pVM))
2454 {
2455 CPUMR0SaveGuestDebugState(pVM, pCtx, true /* save DR6 */);
2456
2457 /* Enable drx move intercepts again. */
2458 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2459 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2460 AssertRC(rc);
2461
2462 /* Resync the debug registers the next time. */
2463 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2464 }
2465 else
2466 Assert(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
2467
2468 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2469 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2470 AssertRC(rc);
2471
2472 return VINF_SUCCESS;
2473}
2474
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