VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 12711

Last change on this file since 12711 was 12711, checked in by vboxsync, 16 years ago

More logging
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 96.1 KB
Line 
1/* $Id: HWVMXR0.cpp 12711 2008-09-25 09:32:13Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43
44/*******************************************************************************
45* Global Variables *
46*******************************************************************************/
47/* IO operation lookup arrays. */
48static uint32_t aIOSize[4] = {1, 2, 0, 4};
49static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
50
51
52static void VMXR0CheckError(PVM pVM, int rc)
53{
54 if (rc == VERR_VMX_GENERIC)
55 {
56 RTCCUINTREG instrError;
57
58 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
59 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
60 }
61 pVM->hwaccm.s.lLastError = rc;
62}
63
64/**
65 * Sets up and activates VT-x on the current CPU
66 *
67 * @returns VBox status code.
68 * @param pCpu CPU info struct
69 * @param pVM The VM to operate on.
70 * @param pvPageCpu Pointer to the global cpu page
71 * @param pPageCpuPhys Physical address of the global cpu page
72 */
73HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
74{
75 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
76 AssertReturn(pVM, VERR_INVALID_PARAMETER);
77 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
78
79 /* Setup Intel VMX. */
80 Assert(pVM->hwaccm.s.vmx.fSupported);
81
82#ifdef LOG_ENABLED
83 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
84#endif
85 /* Set revision dword at the beginning of the VMXON structure. */
86 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
87
88 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
89 * (which can have very bad consequences!!!)
90 */
91
92 /* Make sure the VMX instructions don't cause #UD faults. */
93 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
94
95 /* Enter VMX Root Mode */
96 int rc = VMXEnable(pPageCpuPhys);
97 if (VBOX_FAILURE(rc))
98 {
99 VMXR0CheckError(pVM, rc);
100 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
101 return VERR_VMX_VMXON_FAILED;
102 }
103 return VINF_SUCCESS;
104}
105
106/**
107 * Deactivates VT-x on the current CPU
108 *
109 * @returns VBox status code.
110 * @param pCpu CPU info struct
111 * @param pvPageCpu Pointer to the global cpu page
112 * @param pPageCpuPhys Physical address of the global cpu page
113 */
114HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
115{
116 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
117 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
118
119 /* Leave VMX Root Mode. */
120 VMXDisable();
121
122 /* And clear the X86_CR4_VMXE bit */
123 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
124
125#ifdef LOG_ENABLED
126 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
127#endif
128 return VINF_SUCCESS;
129}
130
131/**
132 * Does Ring-0 per VM VT-x init.
133 *
134 * @returns VBox status code.
135 * @param pVM The VM to operate on.
136 */
137HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
138{
139 int rc;
140
141#ifdef LOG_ENABLED
142 SUPR0Printf("VMXR0InitVM %x\n", pVM);
143#endif
144 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
145 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
146
147
148 /* Allocate one page for the VM control structure (VMCS). */
149 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
150 AssertRC(rc);
151 if (RT_FAILURE(rc))
152 return rc;
153
154 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
155 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
156 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
157
158 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
159 {
160 /* Allocate one page for the virtual APIC mmio cache. */
161 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
162 AssertRC(rc);
163 if (RT_FAILURE(rc))
164 return rc;
165
166 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
167 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
168 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
169 }
170 else
171 {
172 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
173 pVM->hwaccm.s.vmx.pAPIC = 0;
174 pVM->hwaccm.s.vmx.pAPICPhys = 0;
175 }
176
177 /* Allocate the MSR bitmap if this feature is supported. */
178 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
179 {
180 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
181 AssertRC(rc);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
186 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
187 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
188 }
189
190#ifdef LOG_ENABLED
191 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys);
192#endif
193 return VINF_SUCCESS;
194}
195
196/**
197 * Does Ring-0 per VM VT-x termination.
198 *
199 * @returns VBox status code.
200 * @param pVM The VM to operate on.
201 */
202HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
203{
204 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
205 {
206 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
207 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
208 pVM->hwaccm.s.vmx.pVMCS = 0;
209 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
210 }
211 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
212 {
213 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
214 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
215 pVM->hwaccm.s.vmx.pAPIC = 0;
216 pVM->hwaccm.s.vmx.pAPICPhys = 0;
217 }
218 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
219 {
220 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
221 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
222 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
223 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
224 }
225 return VINF_SUCCESS;
226}
227
228/**
229 * Sets up VT-x for the specified VM
230 *
231 * @returns VBox status code.
232 * @param pVM The VM to operate on.
233 */
234HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
235{
236 int rc = VINF_SUCCESS;
237 uint32_t val;
238
239 AssertReturn(pVM, VERR_INVALID_PARAMETER);
240 Assert(pVM->hwaccm.s.vmx.pVMCS);
241
242 /* Set revision dword at the beginning of the VMCS structure. */
243 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
244
245 /* Clear VM Control Structure. */
246 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
247 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
248 if (VBOX_FAILURE(rc))
249 goto vmx_end;
250
251 /* Activate the VM Control Structure. */
252 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
253 if (VBOX_FAILURE(rc))
254 goto vmx_end;
255
256 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
257 * Set required bits to one and zero according to the MSR capabilities.
258 */
259 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
260 /* External and non-maskable interrupts cause VM-exits. */
261 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
262 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
263
264 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
265 AssertRC(rc);
266
267 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
268 * Set required bits to one and zero according to the MSR capabilities.
269 */
270 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
271 /* Program which event cause VM-exits and which features we want to use. */
272 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
273 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
274 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
275 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
276 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
277 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
278
279 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
280
281#if HC_ARCH_BITS == 64
282 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
283 {
284 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
285 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
286 Assert(pVM->hwaccm.s.vmx.pAPIC);
287 }
288 else
289 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
290 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
291#endif
292
293#ifdef VBOX_WITH_VTX_MSR_BITMAPS
294 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
295 {
296 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
297 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
298 }
299#endif
300
301 /* We will use the secondary control if it's present. */
302 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
303
304 /* Mask away the bits that the CPU doesn't support */
305 /** @todo make sure they don't conflict with the above requirements. */
306 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
307 pVM->hwaccm.s.vmx.proc_ctls = val;
308
309 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
310 AssertRC(rc);
311
312 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
313 {
314 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
315 * Set required bits to one and zero according to the MSR capabilities.
316 */
317 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
318 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
319
320 /* Mask away the bits that the CPU doesn't support */
321 /** @todo make sure they don't conflict with the above requirements. */
322 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
323
324 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
325 AssertRC(rc);
326 }
327
328 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
329 * Set required bits to one and zero according to the MSR capabilities.
330 */
331 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
332 AssertRC(rc);
333
334 /* VMX_VMCS_CTRL_EXIT_CONTROLS
335 * Set required bits to one and zero according to the MSR capabilities.
336 */
337 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
338#if HC_ARCH_BITS == 64
339 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
340#else
341 /* else Must be zero when AMD64 is not available. */
342#endif
343 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
344 /* Don't acknowledge external interrupts on VM-exit. */
345 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
346 AssertRC(rc);
347
348 /* Forward all exception except #NM & #PF to the guest.
349 * We always need to check pagefaults since our shadow page table can be out of sync.
350 * And we always lazily sync the FPU & XMM state.
351 */
352
353 /** @todo Possible optimization:
354 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
355 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
356 * registers ourselves of course.
357 *
358 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
359 */
360 pVM->hwaccm.s.vmx.u32TrapMask = HWACCM_VMX_TRAP_MASK;
361 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
362 AssertRC(rc);
363
364 /* Don't filter page faults; all of them should cause a switch. */
365 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
366 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
367 AssertRC(rc);
368
369 /* Init TSC offset to zero. */
370 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
371#if HC_ARCH_BITS == 32
372 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
373#endif
374 AssertRC(rc);
375
376 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
377#if HC_ARCH_BITS == 32
378 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
379#endif
380 AssertRC(rc);
381
382 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
383#if HC_ARCH_BITS == 32
384 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
385#endif
386 AssertRC(rc);
387
388 /* Set the MSR bitmap address. */
389 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
390 {
391 /* Optional */
392 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
393#if HC_ARCH_BITS == 32
394 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32);
395#endif
396 AssertRC(rc);
397 }
398
399 /* Clear MSR controls. */
400 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
401 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
402 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
403#if HC_ARCH_BITS == 32
404 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
405 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
406 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
407#endif
408 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
409 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
410 AssertRC(rc);
411
412 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
413 {
414 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
415 /* Optional */
416 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
417 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
418#if HC_ARCH_BITS == 32
419 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
420#endif
421 AssertRC(rc);
422 }
423
424 /* Set link pointer to -1. Not currently used. */
425#if HC_ARCH_BITS == 32
426 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
427 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
428#else
429 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
430#endif
431 AssertRC(rc);
432
433 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
434 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
435 AssertRC(rc);
436
437vmx_end:
438 VMXR0CheckError(pVM, rc);
439 return rc;
440}
441
442
443/**
444 * Injects an event (trap or external interrupt)
445 *
446 * @returns VBox status code.
447 * @param pVM The VM to operate on.
448 * @param pCtx CPU Context
449 * @param intInfo VMX interrupt info
450 * @param cbInstr Opcode length of faulting instruction
451 * @param errCode Error code (optional)
452 */
453static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
454{
455 int rc;
456
457#ifdef VBOX_STRICT
458 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
459 if (iGate == 0xE)
460 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
461 else
462 if (iGate < 0x20)
463 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
464 else
465 {
466 Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
467 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
468 Assert(pCtx->eflags.u32 & X86_EFL_IF);
469 }
470#endif
471
472 /* Set event injection state. */
473 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
474 intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
475 );
476
477 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
478 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
479
480 AssertRC(rc);
481 return rc;
482}
483
484
485/**
486 * Checks for pending guest interrupts and injects them
487 *
488 * @returns VBox status code.
489 * @param pVM The VM to operate on.
490 * @param pCtx CPU Context
491 */
492static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
493{
494 int rc;
495
496 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
497 if (pVM->hwaccm.s.Event.fPending)
498 {
499 Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
500 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
501 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
502 AssertRC(rc);
503
504 pVM->hwaccm.s.Event.fPending = false;
505 return VINF_SUCCESS;
506 }
507
508 /* When external interrupts are pending, we should exit the VM when IF is set. */
509 if ( !TRPMHasTrap(pVM)
510 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
511 {
512 if (!(pCtx->eflags.u32 & X86_EFL_IF))
513 {
514 Log2(("Enable irq window exit!\n"));
515 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
516 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
517 AssertRC(rc);
518 }
519 else
520 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
521 {
522 uint8_t u8Interrupt;
523
524 rc = PDMGetInterrupt(pVM, &u8Interrupt);
525 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
526 if (VBOX_SUCCESS(rc))
527 {
528 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
529 AssertRC(rc);
530 }
531 else
532 {
533 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
534 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
535 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
536 /* Just continue */
537 }
538 }
539 else
540 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
541 }
542
543#ifdef VBOX_STRICT
544 if (TRPMHasTrap(pVM))
545 {
546 uint8_t u8Vector;
547 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
548 AssertRC(rc);
549 }
550#endif
551
552 if ( pCtx->eflags.u32 & X86_EFL_IF
553 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
554 && TRPMHasTrap(pVM)
555 )
556 {
557 uint8_t u8Vector;
558 int rc;
559 TRPMEVENT enmType;
560 RTGCUINTPTR intInfo;
561 RTGCUINT errCode;
562
563 /* If a new event is pending, then dispatch it now. */
564 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
565 AssertRC(rc);
566 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
567 Assert(enmType != TRPM_SOFTWARE_INT);
568
569 /* Clear the pending trap. */
570 rc = TRPMResetTrap(pVM);
571 AssertRC(rc);
572
573 intInfo = u8Vector;
574 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
575
576 if (enmType == TRPM_TRAP)
577 {
578 switch (u8Vector) {
579 case 8:
580 case 10:
581 case 11:
582 case 12:
583 case 13:
584 case 14:
585 case 17:
586 /* Valid error codes. */
587 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
588 break;
589 default:
590 break;
591 }
592 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
593 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
594 else
595 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
596 }
597 else
598 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
599
600 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
601 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
602 AssertRC(rc);
603 } /* if (interrupts can be dispatched) */
604
605 return VINF_SUCCESS;
606}
607
608/**
609 * Save the host state
610 *
611 * @returns VBox status code.
612 * @param pVM The VM to operate on.
613 */
614HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
615{
616 int rc = VINF_SUCCESS;
617
618 /*
619 * Host CPU Context
620 */
621 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
622 {
623 RTIDTR idtr;
624 RTGDTR gdtr;
625 RTSEL SelTR;
626 PX86DESCHC pDesc;
627 uintptr_t trBase;
628
629 /* Control registers */
630 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
631 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
632 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
633 AssertRC(rc);
634 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
635 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
636 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
637
638 /* Selector registers. */
639 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
640 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
641 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
642 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
643#if HC_ARCH_BITS == 32
644 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
645 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
646#endif
647 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
648 SelTR = ASMGetTR();
649 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
650 AssertRC(rc);
651 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
652 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
653 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
654 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
655 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
656 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
657 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
658
659 /* GDTR & IDTR */
660 ASMGetGDTR(&gdtr);
661 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
662 ASMGetIDTR(&idtr);
663 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
664 AssertRC(rc);
665 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
666 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
667
668 /* Save the base address of the TR selector. */
669 if (SelTR > gdtr.cbGdt)
670 {
671 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
672 return VERR_VMX_INVALID_HOST_STATE;
673 }
674
675 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
676#if HC_ARCH_BITS == 64
677 trBase = X86DESC64_BASE(*pDesc);
678#else
679 trBase = X86DESC_BASE(*pDesc);
680#endif
681 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
682 AssertRC(rc);
683 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
684
685 /* FS and GS base. */
686#if HC_ARCH_BITS == 64
687 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
688 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
689 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
690 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
691#endif
692 AssertRC(rc);
693
694 /* Sysenter MSRs. */
695 /** @todo expensive!! */
696 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
697 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
698#if HC_ARCH_BITS == 32
699 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
700 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
701 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
702 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
703#else
704 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
705 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
706 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
707 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
708#endif
709 AssertRC(rc);
710
711 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
712 }
713 return rc;
714}
715
716
717/**
718 * Loads the guest state
719 *
720 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
721 *
722 * @returns VBox status code.
723 * @param pVM The VM to operate on.
724 * @param pCtx Guest context
725 */
726HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
727{
728 int rc = VINF_SUCCESS;
729 RTGCUINTPTR val;
730 X86EFLAGS eflags;
731
732 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
733 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
734 {
735 VMX_WRITE_SELREG(ES, es);
736 AssertRC(rc);
737
738 VMX_WRITE_SELREG(CS, cs);
739 AssertRC(rc);
740
741 VMX_WRITE_SELREG(SS, ss);
742 AssertRC(rc);
743
744 VMX_WRITE_SELREG(DS, ds);
745 AssertRC(rc);
746
747 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
748 VMX_WRITE_SELREG(FS, fs);
749 AssertRC(rc);
750
751 VMX_WRITE_SELREG(GS, gs);
752 AssertRC(rc);
753 }
754
755 /* Guest CPU context: LDTR. */
756 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
757 {
758 if (pCtx->ldtr == 0)
759 {
760 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
761 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
762 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
763 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
764 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
765 }
766 else
767 {
768 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
769 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
770 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
771 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
772 }
773 AssertRC(rc);
774 }
775 /* Guest CPU context: TR. */
776 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
777 {
778 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
779 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
780 {
781 RTGCPHYS GCPhys;
782
783 /* We convert it here every time as pci regions could be reconfigured. */
784 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
785 AssertRC(rc);
786
787 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, 0);
788 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(VBOXTSS));
789 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
790 }
791 else
792 {
793 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
794 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
795 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
796 }
797 val = pCtx->trHid.Attr.u;
798
799 /* The TSS selector must be busy. */
800 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
801 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
802 else
803 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
804 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
805
806 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
807 AssertRC(rc);
808 }
809 /* Guest CPU context: GDTR. */
810 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
811 {
812 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
813 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
814 AssertRC(rc);
815 }
816 /* Guest CPU context: IDTR. */
817 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
818 {
819 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
820 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
821 AssertRC(rc);
822 }
823
824 /*
825 * Sysenter MSRs (unconditional)
826 */
827 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
828 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
829 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
830 AssertRC(rc);
831
832 /* Control registers */
833 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
834 {
835 val = pCtx->cr0;
836 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
837 Log2(("Guest CR0-shadow %08x\n", val));
838 if (CPUMIsGuestFPUStateActive(pVM) == false)
839 {
840 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
841 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
842 }
843 else
844 {
845 /** @todo check if we support the old style mess correctly. */
846 if (!(val & X86_CR0_NE))
847 {
848 Log(("Forcing X86_CR0_NE!!!\n"));
849
850 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
851 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
852 {
853 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_MF);
854 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
855 AssertRC(rc);
856 pVM->hwaccm.s.fFPUOldStyleOverride = true;
857 }
858 }
859
860 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
861 }
862 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
863 val |= X86_CR0_PE | X86_CR0_PG;
864 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
865 val |= X86_CR0_WP;
866
867 /* Always enable caching. */
868 val &= ~(X86_CR0_CD|X86_CR0_NW);
869
870 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
871 Log2(("Guest CR0 %08x\n", val));
872 /* CR0 flags owned by the host; if the guests attempts to change them, then
873 * the VM will exit.
874 */
875 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
876 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
877 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
878 | X86_CR0_TS
879 | X86_CR0_ET /* Bit not restored during VM-exit! */
880 | X86_CR0_CD /* Bit not restored during VM-exit! */
881 | X86_CR0_NW /* Bit not restored during VM-exit! */
882 | X86_CR0_NE
883 | X86_CR0_MP;
884 pVM->hwaccm.s.vmx.cr0_mask = val;
885
886 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
887 Log2(("Guest CR0-mask %08x\n", val));
888 AssertRC(rc);
889 }
890 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
891 {
892 /* CR4 */
893 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
894 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
895 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
896 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
897 switch(pVM->hwaccm.s.enmShadowMode)
898 {
899 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
900 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
901 case PGMMODE_32_BIT: /* 32-bit paging. */
902 break;
903
904 case PGMMODE_PAE: /* PAE paging. */
905 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
906 /** @todo use normal 32 bits paging */
907 val |= X86_CR4_PAE;
908 break;
909
910 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
911 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
912#ifdef VBOX_ENABLE_64_BITS_GUESTS
913 break;
914#else
915 AssertFailed();
916 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
917#endif
918 default: /* shut up gcc */
919 AssertFailed();
920 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
921 }
922 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
923 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
924 val |= X86_CR4_VME;
925
926 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
927 Log2(("Guest CR4 %08x\n", val));
928 /* CR4 flags owned by the host; if the guests attempts to change them, then
929 * the VM will exit.
930 */
931 val = X86_CR4_PAE
932 | X86_CR4_PGE
933 | X86_CR4_PSE
934 | X86_CR4_VMXE;
935 pVM->hwaccm.s.vmx.cr4_mask = val;
936
937 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
938 Log2(("Guest CR4-mask %08x\n", val));
939 AssertRC(rc);
940 }
941
942 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
943 {
944 /* Save our shadow CR3 register. */
945 val = PGMGetHyperCR3(pVM);
946 Assert(val);
947 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
948 AssertRC(rc);
949 }
950
951 /* Debug registers. */
952 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
953 {
954 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
955 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
956
957 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
958 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
959 pCtx->dr[7] |= 0x400; /* must be one */
960
961 /* Resync DR7 */
962 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
963 AssertRC(rc);
964
965 /* Sync the debug state now if any breakpoint is armed. */
966 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
967 && !CPUMIsGuestDebugStateActive(pVM)
968 && !DBGFIsStepping(pVM))
969 {
970 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxArmed);
971
972 /* Disable drx move intercepts. */
973 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
974 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
975 AssertRC(rc);
976
977 /* Save the host and load the guest debug state. */
978 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
979 AssertRC(rc);
980 }
981
982 /* IA32_DEBUGCTL MSR. */
983 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
984 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
985 AssertRC(rc);
986
987 /** @todo do we really ever need this? */
988 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
989 AssertRC(rc);
990 }
991
992 /* EIP, ESP and EFLAGS */
993 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
994 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
995 AssertRC(rc);
996
997 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
998 eflags = pCtx->eflags;
999 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1000 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1001
1002 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1003 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1004 {
1005 eflags.Bits.u1VM = 1;
1006 eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
1007 eflags.Bits.u2IOPL = 3;
1008 }
1009
1010 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1011 AssertRC(rc);
1012
1013 /* TSC offset. */
1014 uint64_t u64TSCOffset;
1015
1016 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1017 {
1018 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1019#if HC_ARCH_BITS == 64
1020 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1021#else
1022 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
1023 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
1024#endif
1025 AssertRC(rc);
1026
1027 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1028 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1029 AssertRC(rc);
1030 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
1031 }
1032 else
1033 {
1034 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1035 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1036 AssertRC(rc);
1037 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1038 }
1039
1040 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1041 * Set required bits to one and zero according to the MSR capabilities.
1042 */
1043 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1044 /* 64 bits guest mode? */
1045 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1046 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1047 /* else Must be zero when AMD64 is not available. */
1048
1049 /* Mask away the bits that the CPU doesn't support */
1050 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1051 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1052 AssertRC(rc);
1053
1054 /* 64 bits guest mode? */
1055 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1056 {
1057#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
1058 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1059#else
1060 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1061#endif
1062 /* Unconditionally update these as wrmsr might have changed them. */
1063 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1064 AssertRC(rc);
1065 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1066 AssertRC(rc);
1067 }
1068 else
1069 {
1070 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1071 }
1072
1073#ifdef DEBUG
1074 /* Intercept X86_XCPT_DB if stepping is enabled */
1075 if (DBGFIsStepping(pVM))
1076 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_DB);
1077 else
1078 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_DB);
1079
1080 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1081#endif
1082
1083 /* Done. */
1084 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1085
1086 return rc;
1087}
1088
1089/**
1090 * Runs guest code in a VT-x VM.
1091 *
1092 * @returns VBox status code.
1093 * @param pVM The VM to operate on.
1094 * @param pCtx Guest context
1095 */
1096HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1097{
1098 int rc = VINF_SUCCESS;
1099 RTCCUINTREG val, valShadow;
1100 RTCCUINTREG exitReason, instrError, cbInstr;
1101 RTGCUINTPTR exitQualification;
1102 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1103 RTGCUINTPTR errCode, instrInfo, uInterruptState;
1104 bool fSyncTPR = false;
1105 unsigned cResume = 0;
1106#ifdef VBOX_STRICT
1107 RTCPUID idCpuCheck;
1108#endif
1109
1110 Log2(("\nE"));
1111
1112 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1113
1114#ifdef VBOX_STRICT
1115 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1116 AssertRC(rc);
1117 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1118
1119 /* allowed zero */
1120 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1121 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1122
1123 /* allowed one */
1124 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1125 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1126
1127 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1128 AssertRC(rc);
1129 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1130
1131 /* allowed zero */
1132 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1133 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1134
1135 /* allowed one */
1136 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1137 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1138
1139 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1140 AssertRC(rc);
1141 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1142
1143 /* allowed zero */
1144 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1145 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1146
1147 /* allowed one */
1148 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1149 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1150
1151 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1152 AssertRC(rc);
1153 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1154
1155 /* allowed zero */
1156 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1157 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1158
1159 /* allowed one */
1160 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1161 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1162#endif
1163
1164 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1165 */
1166ResumeExecution:
1167 AssertMsg(pVM->hwaccm.s.idEnteredCpu == RTMpCpuId(),
1168 ("Expected %d, I'm %d; cResume=%d exitReason=%RTreg exitQualification=%RTreg\n",
1169 (int)pVM->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
1170
1171 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1172 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1173 {
1174 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1175 rc = VINF_EM_RAW_INTERRUPT;
1176 goto end;
1177 }
1178
1179 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1180 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1181 {
1182 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1183 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1184 {
1185 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1186 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1187 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1188 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1189 */
1190 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1191 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1192 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1193 AssertRC(rc);
1194 }
1195 }
1196 else
1197 {
1198 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1199 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1200 AssertRC(rc);
1201 }
1202
1203 /* Check for pending actions that force us to go back to ring 3. */
1204 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1205 {
1206 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1207 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1208 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1209 rc = VINF_EM_RAW_TO_R3;
1210 goto end;
1211 }
1212 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1213 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1214 {
1215 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1216 rc = VINF_EM_PENDING_REQUEST;
1217 goto end;
1218 }
1219
1220 /* When external interrupts are pending, we should exit the VM when IF is set. */
1221 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1222 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1223 if (VBOX_FAILURE(rc))
1224 {
1225 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1226 goto end;
1227 }
1228
1229 /** @todo check timers?? */
1230
1231 /* TPR caching using CR8 is only available in 64 bits mode */
1232 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1233 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1234 /**
1235 * @todo reduce overhead
1236 */
1237 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1238 && pVM->hwaccm.s.vmx.pAPIC)
1239 {
1240 /* TPR caching in CR8 */
1241 uint8_t u8TPR;
1242 bool fPending;
1243
1244 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1245 AssertRC(rc);
1246 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1247 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1248
1249 /* Two options here:
1250 * - external interrupt pending, but masked by the TPR value.
1251 * -> a CR8 update that lower the current TPR value should cause an exit
1252 * - no pending interrupts
1253 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1254 */
1255 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1256 AssertRC(rc);
1257
1258 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
1259 fSyncTPR = true;
1260 }
1261
1262 /*
1263 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1264 * (until the actual world switch)
1265 */
1266#ifdef VBOX_STRICT
1267 idCpuCheck = RTMpCpuId();
1268#endif
1269 /* Save the host state first. */
1270 rc = VMXR0SaveHostState(pVM);
1271 if (rc != VINF_SUCCESS)
1272 {
1273 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1274 goto end;
1275 }
1276 /* Load the guest state */
1277 rc = VMXR0LoadGuestState(pVM, pCtx);
1278 if (rc != VINF_SUCCESS)
1279 {
1280 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1281 goto end;
1282 }
1283
1284 /* Non-register state Guest Context */
1285 /** @todo change me according to cpu state */
1286 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1287 AssertRC(rc);
1288
1289 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1290
1291 /* Manual save and restore:
1292 * - General purpose registers except RIP, RSP
1293 *
1294 * Trashed:
1295 * - CR2 (we don't care)
1296 * - LDTR (reset to 0)
1297 * - DRx (presumably not changed at all)
1298 * - DR7 (reset to 0x400)
1299 * - EFLAGS (reset to RT_BIT(1); not relevant)
1300 *
1301 */
1302
1303 /* All done! Let's start VM execution. */
1304 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1305#ifdef VBOX_STRICT
1306 Assert(idCpuCheck == RTMpCpuId());
1307#endif
1308 TMNotifyStartOfExecution(pVM);
1309 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1310 TMNotifyEndOfExecution(pVM);
1311
1312 /* In case we execute a goto ResumeExecution later on. */
1313 pVM->hwaccm.s.vmx.fResumeVM = true;
1314
1315 /*
1316 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1317 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1318 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1319 */
1320
1321 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1322 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1323
1324 switch (rc)
1325 {
1326 case VINF_SUCCESS:
1327 break;
1328
1329 case VERR_VMX_INVALID_VMXON_PTR:
1330 AssertFailed();
1331 goto end;
1332
1333 case VERR_VMX_UNABLE_TO_START_VM:
1334 case VERR_VMX_UNABLE_TO_RESUME_VM:
1335 {
1336#ifdef VBOX_STRICT
1337 int rc1;
1338
1339 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1340 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1341 AssertRC(rc1);
1342 if (rc1 == VINF_SUCCESS)
1343 {
1344 RTGDTR gdtr;
1345 PX86DESCHC pDesc;
1346
1347 ASMGetGDTR(&gdtr);
1348
1349 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1350 Log(("Current stack %08x\n", &rc1));
1351
1352
1353 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1354 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1355 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1356 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1357 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1358 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1359 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1360 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1361 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1362 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1363
1364 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1365 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1366
1367 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1368 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1369
1370 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1371 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1372
1373 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1374 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1375
1376 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1377 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
1378
1379 if (val < gdtr.cbGdt)
1380 {
1381 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1382 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1383 }
1384
1385 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1386 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1387 if (val < gdtr.cbGdt)
1388 {
1389 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1390 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1391 }
1392
1393 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1394 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1395 if (val < gdtr.cbGdt)
1396 {
1397 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1398 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1399 }
1400
1401 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1402 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1403 if (val < gdtr.cbGdt)
1404 {
1405 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1406 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1407 }
1408
1409 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1410 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1411 if (val < gdtr.cbGdt)
1412 {
1413 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1414 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1415 }
1416
1417 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1418 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1419 if (val < gdtr.cbGdt)
1420 {
1421 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1422 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1423 }
1424
1425 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1426 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1427 if (val < gdtr.cbGdt)
1428 {
1429 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1430 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1431 }
1432
1433 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1434 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1435
1436 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1437 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1438 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1439 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1440
1441 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1442 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1443
1444 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1445 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1446
1447 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1448 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1449
1450 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1451 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1452 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1453 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1454
1455#if HC_ARCH_BITS == 64
1456 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1457 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1458 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1459 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1460 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1461#endif
1462 }
1463#endif /* VBOX_STRICT */
1464 goto end;
1465 }
1466
1467 default:
1468 /* impossible */
1469 AssertFailed();
1470 goto end;
1471 }
1472 /* Success. Query the guest state and figure out what has happened. */
1473
1474 /* Investigate why there was a VM-exit. */
1475 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1476 STAM_COUNTER_INC(&pVM->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1477
1478 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1479 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1480 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1481 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1482 intInfo = val;
1483 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1484 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1485 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1486 instrInfo = val;
1487 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1488 exitQualification = val;
1489 AssertRC(rc);
1490
1491 /* Let's first sync back eip, esp, and eflags. */
1492 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1493 AssertRC(rc);
1494 pCtx->rip = val;
1495 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1496 AssertRC(rc);
1497 pCtx->rsp = val;
1498 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1499 AssertRC(rc);
1500 pCtx->eflags.u32 = val;
1501
1502 /* Take care of instruction fusing (sti, mov ss) */
1503 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1504 uInterruptState = val;
1505 if (uInterruptState != 0)
1506 {
1507 Assert(uInterruptState <= 2); /* only sti & mov ss */
1508 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1509 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1510 }
1511 else
1512 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1513
1514 /* Control registers. */
1515 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1516 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1517 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1518 CPUMSetGuestCR0(pVM, val);
1519
1520 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1521 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1522 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1523 CPUMSetGuestCR4(pVM, val);
1524
1525 CPUMSetGuestCR2(pVM, ASMGetCR2());
1526
1527 /* Sync back DR7 here. */
1528 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1529 pCtx->dr[7] = val;
1530
1531 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1532 VMX_READ_SELREG(ES, es);
1533 VMX_READ_SELREG(SS, ss);
1534 VMX_READ_SELREG(CS, cs);
1535 VMX_READ_SELREG(DS, ds);
1536 VMX_READ_SELREG(FS, fs);
1537 VMX_READ_SELREG(GS, gs);
1538
1539 /*
1540 * System MSRs
1541 */
1542 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1543 pCtx->SysEnter.cs = val;
1544 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1545 pCtx->SysEnter.eip = val;
1546 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1547 pCtx->SysEnter.esp = val;
1548
1549 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1550 VMX_READ_SELREG(LDTR, ldtr);
1551
1552 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1553 pCtx->gdtr.cbGdt = val;
1554 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1555 pCtx->gdtr.pGdt = val;
1556
1557 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1558 pCtx->idtr.cbIdt = val;
1559 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1560 pCtx->idtr.pIdt = val;
1561
1562 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1563 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1564 {
1565 /* Hide our emulation flags */
1566 pCtx->eflags.Bits.u1VM = 0;
1567 pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1568 pCtx->eflags.Bits.u1VIF = 0;
1569 pCtx->eflags.Bits.u2IOPL = 0;
1570
1571 /* Force a TR resync every time in case we switch modes. */
1572 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1573 }
1574 else
1575 {
1576 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1577 VMX_READ_SELREG(TR, tr);
1578 }
1579
1580 /* Note! NOW IT'S SAFE FOR LOGGING! */
1581 Log2(("Raw exit reason %08x\n", exitReason));
1582
1583 /* Check if an injected event was interrupted prematurely. */
1584 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1585 AssertRC(rc);
1586 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1587 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1588 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1589 {
1590 pVM->hwaccm.s.Event.fPending = true;
1591 /* Error code present? */
1592 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1593 {
1594 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1595 AssertRC(rc);
1596 pVM->hwaccm.s.Event.errCode = val;
1597 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1598 }
1599 else
1600 {
1601 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1602 pVM->hwaccm.s.Event.errCode = 0;
1603 }
1604 }
1605
1606#ifdef VBOX_STRICT
1607 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1608 HWACCMDumpRegs(pVM, pCtx);
1609#endif
1610
1611 Log2(("E%d", exitReason));
1612 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1613 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1614 Log2(("Interruption error code %d\n", errCode));
1615 Log2(("IntInfo = %08x\n", intInfo));
1616 Log2(("New EIP=%VGv\n", pCtx->rip));
1617
1618 if (fSyncTPR)
1619 {
1620 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1621 AssertRC(rc);
1622 }
1623
1624 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1625 switch (exitReason)
1626 {
1627 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1628 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1629 {
1630 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1631
1632 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1633 {
1634 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1635 /* External interrupt; leave to allow it to be dispatched again. */
1636 rc = VINF_EM_RAW_INTERRUPT;
1637 break;
1638 }
1639 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1640 {
1641 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1642 /* External interrupt; leave to allow it to be dispatched again. */
1643 rc = VINF_EM_RAW_INTERRUPT;
1644 break;
1645
1646 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1647 AssertFailed(); /* can't come here; fails the first check. */
1648 break;
1649
1650 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1651 Assert(vector == 3 || vector == 4);
1652 /* no break */
1653 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1654 Log2(("Hardware/software interrupt %d\n", vector));
1655 switch (vector)
1656 {
1657 case X86_XCPT_NM:
1658 {
1659 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1660
1661 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1662 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1663 rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1664 if (rc == VINF_SUCCESS)
1665 {
1666 Assert(CPUMIsGuestFPUStateActive(pVM));
1667
1668 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1669
1670 /* Continue execution. */
1671 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1672 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1673
1674 goto ResumeExecution;
1675 }
1676
1677 Log(("Forward #NM fault to the guest\n"));
1678 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1679 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1680 AssertRC(rc);
1681 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1682 goto ResumeExecution;
1683 }
1684
1685 case X86_XCPT_PF: /* Page fault */
1686 {
1687 Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1688 /* Exit qualification contains the linear address of the page fault. */
1689 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1690 TRPMSetErrorCode(pVM, errCode);
1691 TRPMSetFaultAddress(pVM, exitQualification);
1692
1693 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1694 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1695 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1696 if (rc == VINF_SUCCESS)
1697 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1698 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1699 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1700
1701 TRPMResetTrap(pVM);
1702
1703 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1704 goto ResumeExecution;
1705 }
1706 else
1707 if (rc == VINF_EM_RAW_GUEST_TRAP)
1708 { /* A genuine pagefault.
1709 * Forward the trap to the guest by injecting the exception and resuming execution.
1710 */
1711 Log2(("Forward page fault to the guest\n"));
1712 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1713 /* The error code might have been changed. */
1714 errCode = TRPMGetErrorCode(pVM);
1715
1716 TRPMResetTrap(pVM);
1717
1718 /* Now we must update CR2. */
1719 pCtx->cr2 = exitQualification;
1720 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1721 AssertRC(rc);
1722
1723 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1724 goto ResumeExecution;
1725 }
1726#ifdef VBOX_STRICT
1727 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1728 Log2(("PGMTrap0eHandler failed with %d\n", rc));
1729#endif
1730 /* Need to go back to the recompiler to emulate the instruction. */
1731 TRPMResetTrap(pVM);
1732 break;
1733 }
1734
1735 case X86_XCPT_MF: /* Floating point exception. */
1736 {
1737 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1738 if (!(pCtx->cr0 & X86_CR0_NE))
1739 {
1740 /* old style FPU error reporting needs some extra work. */
1741 /** @todo don't fall back to the recompiler, but do it manually. */
1742 rc = VINF_EM_RAW_EMULATE_INSTR;
1743 break;
1744 }
1745 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1746 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1747 AssertRC(rc);
1748
1749 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1750 goto ResumeExecution;
1751 }
1752
1753 case X86_XCPT_DB: /* Debug exception. */
1754 {
1755 uint64_t uDR6;
1756
1757 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
1758 *
1759 * Exit qualification bits:
1760 * 3:0 B0-B3 which breakpoint condition was met
1761 * 12:4 Reserved (0)
1762 * 13 BD - debug register access detected
1763 * 14 BS - single step execution or branch taken
1764 * 63:15 Reserved (0)
1765 */
1766 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDB);
1767
1768 /* Note that we don't support guest and host-initiated debugging at the same time. */
1769 Assert(DBGFIsStepping(pVM));
1770
1771 uDR6 = X86_DR6_INIT_VAL;
1772 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
1773 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
1774 if (rc == VINF_EM_RAW_GUEST_TRAP)
1775 {
1776 /** @todo this isn't working, but we'll never get here normally. */
1777
1778 /* Update DR6 here. */
1779 pCtx->dr[6] = uDR6;
1780
1781 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
1782 pCtx->dr[7] &= ~X86_DR7_GD;
1783
1784 /* Paranoia. */
1785 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1786 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1787 pCtx->dr[7] |= 0x400; /* must be one */
1788
1789 /* Resync DR7 */
1790 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
1791 AssertRC(rc);
1792
1793 Log(("Trap %x (debug) at %VGv exit qualification %VX64\n", vector, pCtx->rip, exitQualification));
1794 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1795 AssertRC(rc);
1796
1797 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1798 goto ResumeExecution;
1799 }
1800 /* Return to ring 3 to deal with the debug exit code. */
1801 break;
1802 }
1803
1804#ifdef VBOX_STRICT
1805 case X86_XCPT_DE: /* Divide error. */
1806 case X86_XCPT_GP: /* General protection failure exception.*/
1807 case X86_XCPT_UD: /* Unknown opcode exception. */
1808 case X86_XCPT_SS: /* Stack segment exception. */
1809 case X86_XCPT_NP: /* Segment not present exception. */
1810 {
1811 switch(vector)
1812 {
1813 case X86_XCPT_DE:
1814 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1815 break;
1816 case X86_XCPT_UD:
1817 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1818 break;
1819 case X86_XCPT_SS:
1820 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1821 break;
1822 case X86_XCPT_NP:
1823 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1824 break;
1825 case X86_XCPT_GP:
1826 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1827 break;
1828 }
1829
1830 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
1831 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1832 AssertRC(rc);
1833
1834 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1835 goto ResumeExecution;
1836 }
1837#endif
1838 default:
1839 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1840 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
1841 break;
1842 } /* switch (vector) */
1843
1844 break;
1845
1846 default:
1847 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
1848 AssertFailed();
1849 break;
1850 }
1851
1852 break;
1853 }
1854
1855 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1856 /* Clear VM-exit on IF=1 change. */
1857 Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1858 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1859 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1860 AssertRC(rc);
1861 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1862 goto ResumeExecution; /* we check for pending guest interrupts there */
1863
1864 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
1865 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
1866 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1867 /* Skip instruction and continue directly. */
1868 pCtx->rip += cbInstr;
1869 /* Continue execution.*/
1870 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1871 goto ResumeExecution;
1872
1873 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1874 {
1875 Log2(("VMX: Cpuid %x\n", pCtx->eax));
1876 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1877 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1878 if (rc == VINF_SUCCESS)
1879 {
1880 /* Update EIP and continue execution. */
1881 Assert(cbInstr == 2);
1882 pCtx->rip += cbInstr;
1883 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1884 goto ResumeExecution;
1885 }
1886 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1887 rc = VINF_EM_RAW_EMULATE_INSTR;
1888 break;
1889 }
1890
1891 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1892 {
1893 Log2(("VMX: Rdtsc\n"));
1894 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1895 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1896 if (rc == VINF_SUCCESS)
1897 {
1898 /* Update EIP and continue execution. */
1899 Assert(cbInstr == 2);
1900 pCtx->rip += cbInstr;
1901 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1902 goto ResumeExecution;
1903 }
1904 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1905 rc = VINF_EM_RAW_EMULATE_INSTR;
1906 break;
1907 }
1908
1909 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1910 {
1911 Log2(("VMX: invlpg\n"));
1912 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1913 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1914 if (rc == VINF_SUCCESS)
1915 {
1916 /* Update EIP and continue execution. */
1917 pCtx->rip += cbInstr;
1918 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1919 goto ResumeExecution;
1920 }
1921 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1922 break;
1923 }
1924
1925 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1926 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1927 {
1928 uint32_t cbSize;
1929
1930 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1931 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1932 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1933 if (rc == VINF_SUCCESS)
1934 {
1935 /* EIP has been updated already. */
1936
1937 /* Only resume if successful. */
1938 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1939 goto ResumeExecution;
1940 }
1941 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1942 break;
1943 }
1944
1945 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1946 {
1947 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1948 {
1949 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1950 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1951 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1952 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1953 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1954 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1955
1956 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1957 {
1958 case 0:
1959 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1960 break;
1961 case 2:
1962 break;
1963 case 3:
1964 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1965 break;
1966 case 4:
1967 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1968 break;
1969 case 8:
1970 /* CR8 contains the APIC TPR */
1971 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1972 break;
1973
1974 default:
1975 AssertFailed();
1976 break;
1977 }
1978 /* Check if a sync operation is pending. */
1979 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1980 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1981 {
1982 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1983 AssertRC(rc);
1984 }
1985 break;
1986
1987 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1988 Log2(("VMX: mov x, crx\n"));
1989 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1990
1991 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1992 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1993
1994 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1995 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1996 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1997 break;
1998
1999 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2000 Log2(("VMX: clts\n"));
2001 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
2002 rc = EMInterpretCLTS(pVM);
2003 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2004 break;
2005
2006 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2007 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2008 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
2009 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2010 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2011 break;
2012 }
2013
2014 /* Update EIP if no error occurred. */
2015 if (VBOX_SUCCESS(rc))
2016 pCtx->rip += cbInstr;
2017
2018 if (rc == VINF_SUCCESS)
2019 {
2020 /* Only resume if successful. */
2021 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2022 goto ResumeExecution;
2023 }
2024 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2025 break;
2026 }
2027
2028 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2029 {
2030 if (!DBGFIsStepping(pVM))
2031 {
2032 /* Disable drx move intercepts. */
2033 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2034 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2035 AssertRC(rc);
2036
2037 /* Save the host and load the guest debug state. */
2038 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
2039 AssertRC(rc);
2040
2041#ifdef VBOX_WITH_STATISTICS
2042 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
2043 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2044 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2045 else
2046 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2047#endif
2048
2049 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2050 goto ResumeExecution;
2051 }
2052
2053 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2054 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2055 {
2056 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2057 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2058 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2059 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2060 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2061 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2062 Log2(("DR7=%08x\n", pCtx->dr[7]));
2063 }
2064 else
2065 {
2066 Log2(("VMX: mov x, drx\n"));
2067 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2068 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2069 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2070 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2071 }
2072 /* Update EIP if no error occurred. */
2073 if (VBOX_SUCCESS(rc))
2074 pCtx->rip += cbInstr;
2075
2076 if (rc == VINF_SUCCESS)
2077 {
2078 /* Only resume if successful. */
2079 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2080 goto ResumeExecution;
2081 }
2082 Assert(rc == VERR_EM_INTERPRETER);
2083 break;
2084 }
2085
2086 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2087 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2088 {
2089 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2090 uint32_t uPort;
2091 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2092
2093 /** @todo necessary to make the distinction? */
2094 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2095 {
2096 uPort = pCtx->edx & 0xffff;
2097 }
2098 else
2099 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2100
2101 /* paranoia */
2102 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2103 {
2104 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2105 break;
2106 }
2107
2108 uint32_t cbSize = aIOSize[uIOWidth];
2109
2110 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2111 {
2112 /* ins/outs */
2113 uint32_t prefix = 0;
2114 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
2115 prefix |= PREFIX_REP;
2116
2117 if (fIOWrite)
2118 {
2119 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2120 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
2121 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2122 }
2123 else
2124 {
2125 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2126 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
2127 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2128 }
2129 }
2130 else
2131 {
2132 /* normal in/out */
2133 uint32_t uAndVal = aIOOpAnd[uIOWidth];
2134
2135 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2136
2137 if (fIOWrite)
2138 {
2139 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2140 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2141 }
2142 else
2143 {
2144 uint32_t u32Val = 0;
2145
2146 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2147 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2148 if (IOM_SUCCESS(rc))
2149 {
2150 /* Write back to the EAX register. */
2151 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2152 }
2153 }
2154 }
2155 /*
2156 * Handled the I/O return codes.
2157 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2158 */
2159 if (IOM_SUCCESS(rc))
2160 {
2161 /* Update EIP and continue execution. */
2162 pCtx->rip += cbInstr;
2163 if (RT_LIKELY(rc == VINF_SUCCESS))
2164 {
2165 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2166 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2167 {
2168 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxIOCheck);
2169 for (unsigned i=0;i<4;i++)
2170 {
2171 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2172
2173 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
2174 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2175 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2176 {
2177 uint64_t uDR6;
2178
2179 Assert(CPUMIsGuestDebugStateActive(pVM));
2180
2181 uDR6 = ASMGetDR6();
2182
2183 /* Clear all breakpoint status flags and set the one we just hit. */
2184 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2185 uDR6 |= RT_BIT(i);
2186
2187 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2188 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2189 * the contents have been read.
2190 */
2191 ASMSetDR6(uDR6);
2192
2193 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2194 pCtx->dr[7] &= ~X86_DR7_GD;
2195
2196 /* Paranoia. */
2197 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2198 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2199 pCtx->dr[7] |= 0x400; /* must be one */
2200
2201 /* Resync DR7 */
2202 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2203 AssertRC(rc);
2204
2205 /* Construct inject info. */
2206 intInfo = X86_XCPT_DB;
2207 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2208 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2209
2210 Log(("Inject IO debug trap at %VGv\n", pCtx->rip));
2211 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
2212 AssertRC(rc);
2213
2214 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2215 goto ResumeExecution;
2216 }
2217 }
2218 }
2219
2220 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2221 goto ResumeExecution;
2222 }
2223 break;
2224 }
2225
2226#ifdef VBOX_STRICT
2227 if (rc == VINF_IOM_HC_IOPORT_READ)
2228 Assert(!fIOWrite);
2229 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2230 Assert(fIOWrite);
2231 else
2232 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2233#endif
2234 break;
2235 }
2236
2237 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2238 LogFlow(("VMX_EXIT_TPR\n"));
2239 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2240 goto ResumeExecution;
2241
2242 default:
2243 /* The rest is handled after syncing the entire CPU state. */
2244 break;
2245 }
2246
2247 /* Note: the guest state isn't entirely synced back at this stage. */
2248
2249 /* Investigate why there was a VM-exit. (part 2) */
2250 switch (exitReason)
2251 {
2252 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2253 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2254 /* Already handled above. */
2255 break;
2256
2257 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2258 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2259 break;
2260
2261 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2262 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2263 rc = VINF_EM_RAW_INTERRUPT;
2264 AssertFailed(); /* Can't happen. Yet. */
2265 break;
2266
2267 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2268 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2269 rc = VINF_EM_RAW_INTERRUPT;
2270 AssertFailed(); /* Can't happen afaik. */
2271 break;
2272
2273 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2274 rc = VERR_EM_INTERPRETER;
2275 break;
2276
2277 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2278 /** Check if external interrupts are pending; if so, don't switch back. */
2279 pCtx->rip++; /* skip hlt */
2280 if ( pCtx->eflags.Bits.u1IF
2281 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2282 goto ResumeExecution;
2283
2284 rc = VINF_EM_HALT;
2285 break;
2286
2287 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2288 AssertFailed(); /* can't happen. */
2289 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2290 break;
2291
2292 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2293 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2294 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2295 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2296 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2297 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2298 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2299 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2300 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2301 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2302 /** @todo inject #UD immediately */
2303 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2304 break;
2305
2306 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2307 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2308 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2309 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2310 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2311 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2312 /* already handled above */
2313 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2314 || rc == VINF_EM_RAW_INTERRUPT
2315 || rc == VERR_EM_INTERPRETER
2316 || rc == VINF_EM_RAW_EMULATE_INSTR
2317 || rc == VINF_PGM_SYNC_CR3
2318 || rc == VINF_IOM_HC_IOPORT_READ
2319 || rc == VINF_IOM_HC_IOPORT_WRITE
2320 || rc == VINF_EM_RAW_GUEST_TRAP
2321 || rc == VINF_TRPM_XCPT_DISPATCHED
2322 || rc == VINF_EM_RESCHEDULE_REM,
2323 ("rc = %d\n", rc));
2324 break;
2325
2326 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2327 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2328 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2329 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2330 rc = VERR_EM_INTERPRETER;
2331 break;
2332
2333 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2334 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2335 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2336 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2337 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2338 break;
2339
2340 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2341 Assert(rc == VINF_EM_RAW_INTERRUPT);
2342 break;
2343
2344 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2345 {
2346#ifdef VBOX_STRICT
2347 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2348
2349 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2350 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2351
2352 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2353 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2354
2355 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2356 Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2357
2358 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2359 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2360
2361 VMX_LOG_SELREG(CS, "CS");
2362 VMX_LOG_SELREG(DS, "DS");
2363 VMX_LOG_SELREG(ES, "ES");
2364 VMX_LOG_SELREG(FS, "FS");
2365 VMX_LOG_SELREG(GS, "GS");
2366 VMX_LOG_SELREG(SS, "SS");
2367 VMX_LOG_SELREG(TR, "TR");
2368 VMX_LOG_SELREG(LDTR, "LDTR");
2369
2370 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2371 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2372 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2373 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2374#endif /* VBOX_STRICT */
2375 rc = VERR_VMX_INVALID_GUEST_STATE;
2376 break;
2377 }
2378
2379 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2380 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2381 default:
2382 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
2383 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2384 break;
2385
2386 }
2387end:
2388
2389 /* Signal changes for the recompiler. */
2390 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2391
2392 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2393 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2394 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2395 {
2396 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2397 /* On the next entry we'll only sync the host context. */
2398 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2399 }
2400 else
2401 {
2402 /* On the next entry we'll sync everything. */
2403 /** @todo we can do better than this */
2404 /* Not in the VINF_PGM_CHANGE_MODE though! */
2405 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2406 }
2407
2408 /* translate into a less severe return code */
2409 if (rc == VERR_EM_INTERPRETER)
2410 rc = VINF_EM_RAW_EMULATE_INSTR;
2411 else
2412 /* Try to extract more information about what might have gone wrong here. */
2413 if (rc == VERR_VMX_INVALID_VMCS_PTR)
2414 {
2415 VMXGetActivateVMCS(&pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys);
2416 pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS;
2417 }
2418
2419 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2420
2421 Log2(("X"));
2422 return rc;
2423}
2424
2425
2426/**
2427 * Enters the VT-x session
2428 *
2429 * @returns VBox status code.
2430 * @param pVM The VM to operate on.
2431 * @param pCpu CPU info struct
2432 */
2433HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2434{
2435 Assert(pVM->hwaccm.s.vmx.fSupported);
2436
2437 unsigned cr4 = ASMGetCR4();
2438 if (!(cr4 & X86_CR4_VMXE))
2439 {
2440 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2441 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2442 }
2443
2444 /* Activate the VM Control Structure. */
2445 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2446 if (VBOX_FAILURE(rc))
2447 return rc;
2448
2449 pVM->hwaccm.s.vmx.fResumeVM = false;
2450 return VINF_SUCCESS;
2451}
2452
2453
2454/**
2455 * Leaves the VT-x session
2456 *
2457 * @returns VBox status code.
2458 * @param pVM The VM to operate on.
2459 * @param pCtx CPU context
2460 */
2461HWACCMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx)
2462{
2463 Assert(pVM->hwaccm.s.vmx.fSupported);
2464
2465 /* Save the guest debug state if necessary. */
2466 if (CPUMIsGuestDebugStateActive(pVM))
2467 {
2468 CPUMR0SaveGuestDebugState(pVM, pCtx, true /* save DR6 */);
2469
2470 /* Enable drx move intercepts again. */
2471 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2472 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2473 AssertRC(rc);
2474
2475 /* Resync the debug registers the next time. */
2476 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2477 }
2478 else
2479 Assert(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
2480
2481 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2482 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2483 AssertRC(rc);
2484
2485 return VINF_SUCCESS;
2486}
2487
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette