VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 12732

Last change on this file since 12732 was 12732, checked in by vboxsync, 17 years ago

#GP handler should emulation io instructions in real mode. (VT-x)
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1/* $Id: HWVMXR0.cpp 12732 2008-09-25 13:53:39Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43
44/*******************************************************************************
45* Global Variables *
46*******************************************************************************/
47/* IO operation lookup arrays. */
48static uint32_t aIOSize[4] = {1, 2, 0, 4};
49static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
50
51
52static void VMXR0CheckError(PVM pVM, int rc)
53{
54 if (rc == VERR_VMX_GENERIC)
55 {
56 RTCCUINTREG instrError;
57
58 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
59 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
60 }
61 pVM->hwaccm.s.lLastError = rc;
62}
63
64/**
65 * Sets up and activates VT-x on the current CPU
66 *
67 * @returns VBox status code.
68 * @param pCpu CPU info struct
69 * @param pVM The VM to operate on.
70 * @param pvPageCpu Pointer to the global cpu page
71 * @param pPageCpuPhys Physical address of the global cpu page
72 */
73HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
74{
75 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
76 AssertReturn(pVM, VERR_INVALID_PARAMETER);
77 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
78
79 /* Setup Intel VMX. */
80 Assert(pVM->hwaccm.s.vmx.fSupported);
81
82#ifdef LOG_ENABLED
83 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
84#endif
85 /* Set revision dword at the beginning of the VMXON structure. */
86 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
87
88 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
89 * (which can have very bad consequences!!!)
90 */
91
92 /* Make sure the VMX instructions don't cause #UD faults. */
93 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
94
95 /* Enter VMX Root Mode */
96 int rc = VMXEnable(pPageCpuPhys);
97 if (VBOX_FAILURE(rc))
98 {
99 VMXR0CheckError(pVM, rc);
100 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
101 return VERR_VMX_VMXON_FAILED;
102 }
103 return VINF_SUCCESS;
104}
105
106/**
107 * Deactivates VT-x on the current CPU
108 *
109 * @returns VBox status code.
110 * @param pCpu CPU info struct
111 * @param pvPageCpu Pointer to the global cpu page
112 * @param pPageCpuPhys Physical address of the global cpu page
113 */
114HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
115{
116 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
117 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
118
119 /* Leave VMX Root Mode. */
120 VMXDisable();
121
122 /* And clear the X86_CR4_VMXE bit */
123 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
124
125#ifdef LOG_ENABLED
126 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
127#endif
128 return VINF_SUCCESS;
129}
130
131/**
132 * Does Ring-0 per VM VT-x init.
133 *
134 * @returns VBox status code.
135 * @param pVM The VM to operate on.
136 */
137HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
138{
139 int rc;
140
141#ifdef LOG_ENABLED
142 SUPR0Printf("VMXR0InitVM %x\n", pVM);
143#endif
144 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
145 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
146
147
148 /* Allocate one page for the VM control structure (VMCS). */
149 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
150 AssertRC(rc);
151 if (RT_FAILURE(rc))
152 return rc;
153
154 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
155 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
156 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
157
158 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
159 {
160 /* Allocate one page for the virtual APIC mmio cache. */
161 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
162 AssertRC(rc);
163 if (RT_FAILURE(rc))
164 return rc;
165
166 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
167 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
168 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
169 }
170 else
171 {
172 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
173 pVM->hwaccm.s.vmx.pAPIC = 0;
174 pVM->hwaccm.s.vmx.pAPICPhys = 0;
175 }
176
177 /* Allocate the MSR bitmap if this feature is supported. */
178 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
179 {
180 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
181 AssertRC(rc);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
186 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
187 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
188 }
189
190#ifdef LOG_ENABLED
191 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys);
192#endif
193 return VINF_SUCCESS;
194}
195
196/**
197 * Does Ring-0 per VM VT-x termination.
198 *
199 * @returns VBox status code.
200 * @param pVM The VM to operate on.
201 */
202HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
203{
204 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
205 {
206 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
207 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
208 pVM->hwaccm.s.vmx.pVMCS = 0;
209 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
210 }
211 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
212 {
213 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
214 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
215 pVM->hwaccm.s.vmx.pAPIC = 0;
216 pVM->hwaccm.s.vmx.pAPICPhys = 0;
217 }
218 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
219 {
220 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
221 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
222 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
223 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
224 }
225 return VINF_SUCCESS;
226}
227
228/**
229 * Sets up VT-x for the specified VM
230 *
231 * @returns VBox status code.
232 * @param pVM The VM to operate on.
233 */
234HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
235{
236 int rc = VINF_SUCCESS;
237 uint32_t val;
238
239 AssertReturn(pVM, VERR_INVALID_PARAMETER);
240 Assert(pVM->hwaccm.s.vmx.pVMCS);
241
242 /* Set revision dword at the beginning of the VMCS structure. */
243 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
244
245 /* Clear VM Control Structure. */
246 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
247 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
248 if (VBOX_FAILURE(rc))
249 goto vmx_end;
250
251 /* Activate the VM Control Structure. */
252 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
253 if (VBOX_FAILURE(rc))
254 goto vmx_end;
255
256 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
257 * Set required bits to one and zero according to the MSR capabilities.
258 */
259 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
260 /* External and non-maskable interrupts cause VM-exits. */
261 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
262 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
263
264 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
265 AssertRC(rc);
266
267 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
268 * Set required bits to one and zero according to the MSR capabilities.
269 */
270 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
271 /* Program which event cause VM-exits and which features we want to use. */
272 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
273 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
274 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
275 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
276 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
277 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
278
279 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
280
281#if HC_ARCH_BITS == 64
282 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
283 {
284 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
285 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
286 Assert(pVM->hwaccm.s.vmx.pAPIC);
287 }
288 else
289 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
290 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
291#endif
292
293#ifdef VBOX_WITH_VTX_MSR_BITMAPS
294 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
295 {
296 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
297 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
298 }
299#endif
300
301 /* We will use the secondary control if it's present. */
302 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
303
304 /* Mask away the bits that the CPU doesn't support */
305 /** @todo make sure they don't conflict with the above requirements. */
306 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
307 pVM->hwaccm.s.vmx.proc_ctls = val;
308
309 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
310 AssertRC(rc);
311
312 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
313 {
314 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
315 * Set required bits to one and zero according to the MSR capabilities.
316 */
317 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
318 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
319
320 /* Mask away the bits that the CPU doesn't support */
321 /** @todo make sure they don't conflict with the above requirements. */
322 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
323
324 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
325 AssertRC(rc);
326 }
327
328 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
329 * Set required bits to one and zero according to the MSR capabilities.
330 */
331 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
332 AssertRC(rc);
333
334 /* VMX_VMCS_CTRL_EXIT_CONTROLS
335 * Set required bits to one and zero according to the MSR capabilities.
336 */
337 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
338#if HC_ARCH_BITS == 64
339 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
340#else
341 /* else Must be zero when AMD64 is not available. */
342#endif
343 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
344 /* Don't acknowledge external interrupts on VM-exit. */
345 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
346 AssertRC(rc);
347
348 /* Forward all exception except #NM & #PF to the guest.
349 * We always need to check pagefaults since our shadow page table can be out of sync.
350 * And we always lazily sync the FPU & XMM state.
351 */
352
353 /** @todo Possible optimization:
354 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
355 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
356 * registers ourselves of course.
357 *
358 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
359 */
360 pVM->hwaccm.s.vmx.u32TrapMask = HWACCM_VMX_TRAP_MASK;
361 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
362 AssertRC(rc);
363
364 /* Don't filter page faults; all of them should cause a switch. */
365 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
366 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
367 AssertRC(rc);
368
369 /* Init TSC offset to zero. */
370 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
371#if HC_ARCH_BITS == 32
372 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
373#endif
374 AssertRC(rc);
375
376 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
377#if HC_ARCH_BITS == 32
378 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
379#endif
380 AssertRC(rc);
381
382 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
383#if HC_ARCH_BITS == 32
384 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
385#endif
386 AssertRC(rc);
387
388 /* Set the MSR bitmap address. */
389 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
390 {
391 /* Optional */
392 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
393#if HC_ARCH_BITS == 32
394 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32);
395#endif
396 AssertRC(rc);
397 }
398
399 /* Clear MSR controls. */
400 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
401 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
402 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
403#if HC_ARCH_BITS == 32
404 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
405 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
406 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
407#endif
408 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
409 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
410 AssertRC(rc);
411
412 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
413 {
414 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
415 /* Optional */
416 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
417 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
418#if HC_ARCH_BITS == 32
419 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
420#endif
421 AssertRC(rc);
422 }
423
424 /* Set link pointer to -1. Not currently used. */
425#if HC_ARCH_BITS == 32
426 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
427 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
428#else
429 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
430#endif
431 AssertRC(rc);
432
433 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
434 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
435 AssertRC(rc);
436
437vmx_end:
438 VMXR0CheckError(pVM, rc);
439 return rc;
440}
441
442
443/**
444 * Injects an event (trap or external interrupt)
445 *
446 * @returns VBox status code.
447 * @param pVM The VM to operate on.
448 * @param pCtx CPU Context
449 * @param intInfo VMX interrupt info
450 * @param cbInstr Opcode length of faulting instruction
451 * @param errCode Error code (optional)
452 */
453static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
454{
455 int rc;
456
457#ifdef VBOX_STRICT
458 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
459 if (iGate == 0xE)
460 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
461 else
462 if (iGate < 0x20)
463 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
464 else
465 {
466 Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
467 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
468 Assert(pCtx->eflags.u32 & X86_EFL_IF);
469 }
470#endif
471
472 /* Set event injection state. */
473 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
474 intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
475 );
476
477 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
478 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
479
480 AssertRC(rc);
481 return rc;
482}
483
484
485/**
486 * Checks for pending guest interrupts and injects them
487 *
488 * @returns VBox status code.
489 * @param pVM The VM to operate on.
490 * @param pCtx CPU Context
491 */
492static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
493{
494 int rc;
495
496 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
497 if (pVM->hwaccm.s.Event.fPending)
498 {
499 Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
500 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
501 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
502 AssertRC(rc);
503
504 pVM->hwaccm.s.Event.fPending = false;
505 return VINF_SUCCESS;
506 }
507
508 /* When external interrupts are pending, we should exit the VM when IF is set. */
509 if ( !TRPMHasTrap(pVM)
510 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
511 {
512 if (!(pCtx->eflags.u32 & X86_EFL_IF))
513 {
514 Log2(("Enable irq window exit!\n"));
515 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
516 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
517 AssertRC(rc);
518 }
519 else
520 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
521 {
522 uint8_t u8Interrupt;
523
524 rc = PDMGetInterrupt(pVM, &u8Interrupt);
525 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
526 if (VBOX_SUCCESS(rc))
527 {
528 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
529 AssertRC(rc);
530 }
531 else
532 {
533 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
534 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
535 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
536 /* Just continue */
537 }
538 }
539 else
540 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
541 }
542
543#ifdef VBOX_STRICT
544 if (TRPMHasTrap(pVM))
545 {
546 uint8_t u8Vector;
547 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
548 AssertRC(rc);
549 }
550#endif
551
552 if ( pCtx->eflags.u32 & X86_EFL_IF
553 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
554 && TRPMHasTrap(pVM)
555 )
556 {
557 uint8_t u8Vector;
558 int rc;
559 TRPMEVENT enmType;
560 RTGCUINTPTR intInfo;
561 RTGCUINT errCode;
562
563 /* If a new event is pending, then dispatch it now. */
564 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
565 AssertRC(rc);
566 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
567 Assert(enmType != TRPM_SOFTWARE_INT);
568
569 /* Clear the pending trap. */
570 rc = TRPMResetTrap(pVM);
571 AssertRC(rc);
572
573 intInfo = u8Vector;
574 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
575
576 if (enmType == TRPM_TRAP)
577 {
578 switch (u8Vector) {
579 case 8:
580 case 10:
581 case 11:
582 case 12:
583 case 13:
584 case 14:
585 case 17:
586 /* Valid error codes. */
587 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
588 break;
589 default:
590 break;
591 }
592 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
593 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
594 else
595 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
596 }
597 else
598 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
599
600 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
601 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
602 AssertRC(rc);
603 } /* if (interrupts can be dispatched) */
604
605 return VINF_SUCCESS;
606}
607
608/**
609 * Save the host state
610 *
611 * @returns VBox status code.
612 * @param pVM The VM to operate on.
613 */
614HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
615{
616 int rc = VINF_SUCCESS;
617
618 /*
619 * Host CPU Context
620 */
621 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
622 {
623 RTIDTR idtr;
624 RTGDTR gdtr;
625 RTSEL SelTR;
626 PX86DESCHC pDesc;
627 uintptr_t trBase;
628
629 /* Control registers */
630 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
631 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
632 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
633 AssertRC(rc);
634 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
635 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
636 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
637
638 /* Selector registers. */
639 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
640 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
641 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
642 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
643#if HC_ARCH_BITS == 32
644 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
645 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
646#endif
647 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
648 SelTR = ASMGetTR();
649 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
650 AssertRC(rc);
651 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
652 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
653 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
654 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
655 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
656 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
657 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
658
659 /* GDTR & IDTR */
660 ASMGetGDTR(&gdtr);
661 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
662 ASMGetIDTR(&idtr);
663 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
664 AssertRC(rc);
665 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
666 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
667
668 /* Save the base address of the TR selector. */
669 if (SelTR > gdtr.cbGdt)
670 {
671 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
672 return VERR_VMX_INVALID_HOST_STATE;
673 }
674
675 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
676#if HC_ARCH_BITS == 64
677 trBase = X86DESC64_BASE(*pDesc);
678#else
679 trBase = X86DESC_BASE(*pDesc);
680#endif
681 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
682 AssertRC(rc);
683 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
684
685 /* FS and GS base. */
686#if HC_ARCH_BITS == 64
687 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
688 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
689 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
690 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
691#endif
692 AssertRC(rc);
693
694 /* Sysenter MSRs. */
695 /** @todo expensive!! */
696 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
697 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
698#if HC_ARCH_BITS == 32
699 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
700 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
701 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
702 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
703#else
704 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
705 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
706 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
707 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
708#endif
709 AssertRC(rc);
710
711 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
712 }
713 return rc;
714}
715
716
717/**
718 * Loads the guest state
719 *
720 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
721 *
722 * @returns VBox status code.
723 * @param pVM The VM to operate on.
724 * @param pCtx Guest context
725 */
726HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
727{
728 int rc = VINF_SUCCESS;
729 RTGCUINTPTR val;
730 X86EFLAGS eflags;
731
732 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
733 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
734 {
735 /* VT-x will fail with a guest invalid state otherwise... */
736 if ( CPUMIsGuestInRealModeEx(pCtx)
737 && pCtx->csHid.u64Base == 0xffff0000)
738 {
739 pCtx->csHid.u64Base = 0xf0000;
740 pCtx->cs = 0xf000;
741 }
742
743 VMX_WRITE_SELREG(ES, es);
744 AssertRC(rc);
745
746 VMX_WRITE_SELREG(CS, cs);
747 AssertRC(rc);
748
749 VMX_WRITE_SELREG(SS, ss);
750 AssertRC(rc);
751
752 VMX_WRITE_SELREG(DS, ds);
753 AssertRC(rc);
754
755 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
756 VMX_WRITE_SELREG(FS, fs);
757 AssertRC(rc);
758
759 VMX_WRITE_SELREG(GS, gs);
760 AssertRC(rc);
761 }
762
763 /* Guest CPU context: LDTR. */
764 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
765 {
766 if (pCtx->ldtr == 0)
767 {
768 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
769 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
770 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
771 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
772 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
773 }
774 else
775 {
776 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
777 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
778 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
779 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
780 }
781 AssertRC(rc);
782 }
783 /* Guest CPU context: TR. */
784 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
785 {
786 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
787 if (CPUMIsGuestInRealModeEx(pCtx))
788 {
789 RTGCPHYS GCPhys;
790
791 /* We convert it here every time as pci regions could be reconfigured. */
792 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
793 AssertRC(rc);
794
795 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, 0);
796 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(VBOXTSS));
797 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
798
799 X86DESCATTR attr;
800
801 attr.u = 0;
802 attr.n.u1Present = 1;
803 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
804 val = attr.u;
805 }
806 else
807 {
808 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
809 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
810 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
811
812 val = pCtx->trHid.Attr.u;
813
814 /* The TSS selector must be busy. */
815 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
816 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
817 else
818 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
819 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
820
821 }
822 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
823 AssertRC(rc);
824 }
825 /* Guest CPU context: GDTR. */
826 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
827 {
828 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
829 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
830 AssertRC(rc);
831 }
832 /* Guest CPU context: IDTR. */
833 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
834 {
835 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
836 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
837 AssertRC(rc);
838 }
839
840 /*
841 * Sysenter MSRs (unconditional)
842 */
843 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
844 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
845 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
846 AssertRC(rc);
847
848 /* Control registers */
849 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
850 {
851 val = pCtx->cr0;
852 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
853 Log2(("Guest CR0-shadow %08x\n", val));
854 if (CPUMIsGuestFPUStateActive(pVM) == false)
855 {
856 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
857 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
858 }
859 else
860 {
861 /** @todo check if we support the old style mess correctly. */
862 if (!(val & X86_CR0_NE))
863 {
864 Log(("Forcing X86_CR0_NE!!!\n"));
865
866 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
867 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
868 {
869 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_MF);
870 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
871 AssertRC(rc);
872 pVM->hwaccm.s.fFPUOldStyleOverride = true;
873 }
874 }
875
876 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
877 }
878 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
879 val |= X86_CR0_PE | X86_CR0_PG;
880 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
881 val |= X86_CR0_WP;
882
883 /* Always enable caching. */
884 val &= ~(X86_CR0_CD|X86_CR0_NW);
885
886 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
887 Log2(("Guest CR0 %08x\n", val));
888 /* CR0 flags owned by the host; if the guests attempts to change them, then
889 * the VM will exit.
890 */
891 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
892 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
893 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
894 | X86_CR0_TS
895 | X86_CR0_ET /* Bit not restored during VM-exit! */
896 | X86_CR0_CD /* Bit not restored during VM-exit! */
897 | X86_CR0_NW /* Bit not restored during VM-exit! */
898 | X86_CR0_NE
899 | X86_CR0_MP;
900 pVM->hwaccm.s.vmx.cr0_mask = val;
901
902 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
903 Log2(("Guest CR0-mask %08x\n", val));
904 AssertRC(rc);
905 }
906 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
907 {
908 /* CR4 */
909 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
910 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
911 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
912 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
913 switch(pVM->hwaccm.s.enmShadowMode)
914 {
915 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
916 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
917 case PGMMODE_32_BIT: /* 32-bit paging. */
918 break;
919
920 case PGMMODE_PAE: /* PAE paging. */
921 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
922 /** @todo use normal 32 bits paging */
923 val |= X86_CR4_PAE;
924 break;
925
926 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
927 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
928#ifdef VBOX_ENABLE_64_BITS_GUESTS
929 break;
930#else
931 AssertFailed();
932 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
933#endif
934 default: /* shut up gcc */
935 AssertFailed();
936 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
937 }
938 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
939 if (CPUMIsGuestInRealModeEx(pCtx))
940 val |= X86_CR4_VME;
941
942 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
943 Log2(("Guest CR4 %08x\n", val));
944 /* CR4 flags owned by the host; if the guests attempts to change them, then
945 * the VM will exit.
946 */
947 val = X86_CR4_PAE
948 | X86_CR4_PGE
949 | X86_CR4_PSE
950 | X86_CR4_VMXE;
951 pVM->hwaccm.s.vmx.cr4_mask = val;
952
953 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
954 Log2(("Guest CR4-mask %08x\n", val));
955 AssertRC(rc);
956 }
957
958 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
959 {
960 /* Save our shadow CR3 register. */
961 val = PGMGetHyperCR3(pVM);
962 Assert(val);
963 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
964 AssertRC(rc);
965 }
966
967 /* Debug registers. */
968 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
969 {
970 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
971 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
972
973 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
974 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
975 pCtx->dr[7] |= 0x400; /* must be one */
976
977 /* Resync DR7 */
978 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
979 AssertRC(rc);
980
981 /* Sync the debug state now if any breakpoint is armed. */
982 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
983 && !CPUMIsGuestDebugStateActive(pVM)
984 && !DBGFIsStepping(pVM))
985 {
986 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxArmed);
987
988 /* Disable drx move intercepts. */
989 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
990 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
991 AssertRC(rc);
992
993 /* Save the host and load the guest debug state. */
994 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
995 AssertRC(rc);
996 }
997
998 /* IA32_DEBUGCTL MSR. */
999 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1000 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
1001 AssertRC(rc);
1002
1003 /** @todo do we really ever need this? */
1004 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1005 AssertRC(rc);
1006 }
1007
1008 /* EIP, ESP and EFLAGS */
1009 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
1010 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
1011 AssertRC(rc);
1012
1013 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1014 eflags = pCtx->eflags;
1015 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1016 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1017
1018 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1019 if (CPUMIsGuestInRealModeEx(pCtx))
1020 {
1021 eflags.Bits.u1VM = 1;
1022 eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
1023 eflags.Bits.u2IOPL = 3;
1024 }
1025
1026 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1027 AssertRC(rc);
1028
1029 /* TSC offset. */
1030 uint64_t u64TSCOffset;
1031
1032 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1033 {
1034 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1035#if HC_ARCH_BITS == 64
1036 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1037#else
1038 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
1039 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
1040#endif
1041 AssertRC(rc);
1042
1043 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1044 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1045 AssertRC(rc);
1046 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
1047 }
1048 else
1049 {
1050 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1051 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1052 AssertRC(rc);
1053 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1054 }
1055
1056 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1057 * Set required bits to one and zero according to the MSR capabilities.
1058 */
1059 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1060 /* 64 bits guest mode? */
1061 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1062 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1063 /* else Must be zero when AMD64 is not available. */
1064
1065 /* Mask away the bits that the CPU doesn't support */
1066 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1067 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1068 AssertRC(rc);
1069
1070 /* 64 bits guest mode? */
1071 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1072 {
1073#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
1074 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1075#else
1076 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1077#endif
1078 /* Unconditionally update these as wrmsr might have changed them. */
1079 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1080 AssertRC(rc);
1081 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1082 AssertRC(rc);
1083 }
1084 else
1085 {
1086 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1087 }
1088
1089#ifdef DEBUG
1090 /* Intercept X86_XCPT_DB if stepping is enabled */
1091 if (DBGFIsStepping(pVM))
1092 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_DB);
1093 else
1094 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_DB);
1095
1096 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1097#endif
1098
1099 /* Intercept #GP faults in real mode to handle IO instructions. */
1100 if (CPUMIsGuestInRealModeEx(pCtx))
1101 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_GP);
1102 else
1103 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_GP);
1104
1105 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1106 AssertRC(rc);
1107
1108 /* Done. */
1109 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1110
1111 return rc;
1112}
1113
1114/**
1115 * Runs guest code in a VT-x VM.
1116 *
1117 * @returns VBox status code.
1118 * @param pVM The VM to operate on.
1119 * @param pCtx Guest context
1120 */
1121HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1122{
1123 int rc = VINF_SUCCESS;
1124 RTCCUINTREG val, valShadow;
1125 RTCCUINTREG exitReason, instrError, cbInstr;
1126 RTGCUINTPTR exitQualification;
1127 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1128 RTGCUINTPTR errCode, instrInfo, uInterruptState;
1129 bool fSyncTPR = false;
1130 unsigned cResume = 0;
1131#ifdef VBOX_STRICT
1132 RTCPUID idCpuCheck;
1133#endif
1134
1135 Log2(("\nE"));
1136
1137 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1138
1139#ifdef VBOX_STRICT
1140 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1141 AssertRC(rc);
1142 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1143
1144 /* allowed zero */
1145 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1146 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1147
1148 /* allowed one */
1149 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1150 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1151
1152 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1153 AssertRC(rc);
1154 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1155
1156 /* allowed zero */
1157 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1158 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1159
1160 /* allowed one */
1161 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1162 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1163
1164 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1165 AssertRC(rc);
1166 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1167
1168 /* allowed zero */
1169 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1170 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1171
1172 /* allowed one */
1173 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1174 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1175
1176 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1177 AssertRC(rc);
1178 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1179
1180 /* allowed zero */
1181 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1182 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1183
1184 /* allowed one */
1185 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1186 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1187#endif
1188
1189 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1190 */
1191ResumeExecution:
1192 AssertMsg(pVM->hwaccm.s.idEnteredCpu == RTMpCpuId(),
1193 ("Expected %d, I'm %d; cResume=%d exitReason=%RTreg exitQualification=%RTreg\n",
1194 (int)pVM->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
1195
1196 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1197 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1198 {
1199 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1200 rc = VINF_EM_RAW_INTERRUPT;
1201 goto end;
1202 }
1203
1204 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1205 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1206 {
1207 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1208 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1209 {
1210 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1211 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1212 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1213 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1214 */
1215 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1216 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1217 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1218 AssertRC(rc);
1219 }
1220 }
1221 else
1222 {
1223 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1224 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1225 AssertRC(rc);
1226 }
1227
1228 /* Check for pending actions that force us to go back to ring 3. */
1229 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1230 {
1231 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1232 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1233 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1234 rc = VINF_EM_RAW_TO_R3;
1235 goto end;
1236 }
1237 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1238 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1239 {
1240 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1241 rc = VINF_EM_PENDING_REQUEST;
1242 goto end;
1243 }
1244
1245 /* When external interrupts are pending, we should exit the VM when IF is set. */
1246 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1247 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1248 if (VBOX_FAILURE(rc))
1249 {
1250 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1251 goto end;
1252 }
1253
1254 /** @todo check timers?? */
1255
1256 /* TPR caching using CR8 is only available in 64 bits mode */
1257 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1258 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1259 /**
1260 * @todo reduce overhead
1261 */
1262 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1263 && pVM->hwaccm.s.vmx.pAPIC)
1264 {
1265 /* TPR caching in CR8 */
1266 uint8_t u8TPR;
1267 bool fPending;
1268
1269 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1270 AssertRC(rc);
1271 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1272 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1273
1274 /* Two options here:
1275 * - external interrupt pending, but masked by the TPR value.
1276 * -> a CR8 update that lower the current TPR value should cause an exit
1277 * - no pending interrupts
1278 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1279 */
1280 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1281 AssertRC(rc);
1282
1283 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
1284 fSyncTPR = true;
1285 }
1286 HWACCMDumpRegs(pVM, pCtx);
1287
1288 /*
1289 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1290 * (until the actual world switch)
1291 */
1292#ifdef VBOX_STRICT
1293 idCpuCheck = RTMpCpuId();
1294#endif
1295 /* Save the host state first. */
1296 rc = VMXR0SaveHostState(pVM);
1297 if (rc != VINF_SUCCESS)
1298 {
1299 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1300 goto end;
1301 }
1302 /* Load the guest state */
1303 rc = VMXR0LoadGuestState(pVM, pCtx);
1304 if (rc != VINF_SUCCESS)
1305 {
1306 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1307 goto end;
1308 }
1309
1310 /* Non-register state Guest Context */
1311 /** @todo change me according to cpu state */
1312 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1313 AssertRC(rc);
1314
1315 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1316
1317 /* Manual save and restore:
1318 * - General purpose registers except RIP, RSP
1319 *
1320 * Trashed:
1321 * - CR2 (we don't care)
1322 * - LDTR (reset to 0)
1323 * - DRx (presumably not changed at all)
1324 * - DR7 (reset to 0x400)
1325 * - EFLAGS (reset to RT_BIT(1); not relevant)
1326 *
1327 */
1328
1329 /* All done! Let's start VM execution. */
1330 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1331#ifdef VBOX_STRICT
1332 Assert(idCpuCheck == RTMpCpuId());
1333#endif
1334 TMNotifyStartOfExecution(pVM);
1335 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1336 TMNotifyEndOfExecution(pVM);
1337
1338 /* In case we execute a goto ResumeExecution later on. */
1339 pVM->hwaccm.s.vmx.fResumeVM = true;
1340
1341 /*
1342 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1343 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1344 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1345 */
1346
1347 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1348 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1349
1350 switch (rc)
1351 {
1352 case VINF_SUCCESS:
1353 break;
1354
1355 case VERR_VMX_INVALID_VMXON_PTR:
1356 AssertFailed();
1357 goto end;
1358
1359 case VERR_VMX_UNABLE_TO_START_VM:
1360 case VERR_VMX_UNABLE_TO_RESUME_VM:
1361 {
1362#ifdef VBOX_STRICT
1363 int rc1;
1364
1365 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1366 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1367 AssertRC(rc1);
1368 if (rc1 == VINF_SUCCESS)
1369 {
1370 RTGDTR gdtr;
1371 PX86DESCHC pDesc;
1372
1373 ASMGetGDTR(&gdtr);
1374
1375 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1376 Log(("Current stack %08x\n", &rc1));
1377
1378
1379 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1380 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1381 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1382 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1383 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1384 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1385 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1386 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1387 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1388 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1389
1390 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1391 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1392
1393 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1394 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1395
1396 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1397 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1398
1399 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1400 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1401
1402 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1403 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
1404
1405 if (val < gdtr.cbGdt)
1406 {
1407 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1408 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1409 }
1410
1411 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1412 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1413 if (val < gdtr.cbGdt)
1414 {
1415 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1416 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1417 }
1418
1419 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1420 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1421 if (val < gdtr.cbGdt)
1422 {
1423 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1424 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1425 }
1426
1427 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1428 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1429 if (val < gdtr.cbGdt)
1430 {
1431 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1432 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1433 }
1434
1435 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1436 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1437 if (val < gdtr.cbGdt)
1438 {
1439 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1440 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1441 }
1442
1443 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1444 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1445 if (val < gdtr.cbGdt)
1446 {
1447 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1448 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1449 }
1450
1451 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1452 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1453 if (val < gdtr.cbGdt)
1454 {
1455 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1456 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1457 }
1458
1459 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1460 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1461
1462 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1463 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1464 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1465 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1466
1467 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1468 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1469
1470 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1471 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1472
1473 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1474 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1475
1476 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1477 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1478 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1479 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1480
1481#if HC_ARCH_BITS == 64
1482 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1483 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1484 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1485 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1486 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1487#endif
1488 }
1489#endif /* VBOX_STRICT */
1490 goto end;
1491 }
1492
1493 default:
1494 /* impossible */
1495 AssertFailed();
1496 goto end;
1497 }
1498 /* Success. Query the guest state and figure out what has happened. */
1499
1500 /* Investigate why there was a VM-exit. */
1501 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1502 STAM_COUNTER_INC(&pVM->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1503
1504 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1505 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1506 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1507 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1508 intInfo = val;
1509 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1510 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1511 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1512 instrInfo = val;
1513 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1514 exitQualification = val;
1515 AssertRC(rc);
1516
1517 /* Let's first sync back eip, esp, and eflags. */
1518 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1519 AssertRC(rc);
1520 pCtx->rip = val;
1521 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1522 AssertRC(rc);
1523 pCtx->rsp = val;
1524 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1525 AssertRC(rc);
1526 pCtx->eflags.u32 = val;
1527
1528 /* Take care of instruction fusing (sti, mov ss) */
1529 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1530 uInterruptState = val;
1531 if (uInterruptState != 0)
1532 {
1533 Assert(uInterruptState <= 2); /* only sti & mov ss */
1534 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1535 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1536 }
1537 else
1538 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1539
1540 /* Control registers. */
1541 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1542 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1543 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1544 CPUMSetGuestCR0(pVM, val);
1545
1546 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1547 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1548 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1549 CPUMSetGuestCR4(pVM, val);
1550
1551 CPUMSetGuestCR2(pVM, ASMGetCR2());
1552
1553 /* Sync back DR7 here. */
1554 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1555 pCtx->dr[7] = val;
1556
1557 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1558 VMX_READ_SELREG(ES, es);
1559 VMX_READ_SELREG(SS, ss);
1560 VMX_READ_SELREG(CS, cs);
1561 VMX_READ_SELREG(DS, ds);
1562 VMX_READ_SELREG(FS, fs);
1563 VMX_READ_SELREG(GS, gs);
1564
1565 /*
1566 * System MSRs
1567 */
1568 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1569 pCtx->SysEnter.cs = val;
1570 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1571 pCtx->SysEnter.eip = val;
1572 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1573 pCtx->SysEnter.esp = val;
1574
1575 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1576 VMX_READ_SELREG(LDTR, ldtr);
1577
1578 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1579 pCtx->gdtr.cbGdt = val;
1580 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1581 pCtx->gdtr.pGdt = val;
1582
1583 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1584 pCtx->idtr.cbIdt = val;
1585 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1586 pCtx->idtr.pIdt = val;
1587
1588 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1589 if (CPUMIsGuestInRealModeEx(pCtx))
1590 {
1591 /* Hide our emulation flags */
1592 pCtx->eflags.Bits.u1VM = 0;
1593 pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1594 pCtx->eflags.Bits.u1VIF = 0;
1595 pCtx->eflags.Bits.u2IOPL = 0;
1596
1597 /* Force a TR resync every time in case we switch modes. */
1598 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1599 }
1600 else
1601 {
1602 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1603 VMX_READ_SELREG(TR, tr);
1604 }
1605
1606 /* Note! NOW IT'S SAFE FOR LOGGING! */
1607 Log2(("Raw exit reason %08x\n", exitReason));
1608
1609 /* Check if an injected event was interrupted prematurely. */
1610 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1611 AssertRC(rc);
1612 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1613 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1614 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1615 {
1616 pVM->hwaccm.s.Event.fPending = true;
1617 /* Error code present? */
1618 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1619 {
1620 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1621 AssertRC(rc);
1622 pVM->hwaccm.s.Event.errCode = val;
1623 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1624 }
1625 else
1626 {
1627 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1628 pVM->hwaccm.s.Event.errCode = 0;
1629 }
1630 }
1631
1632#ifdef VBOX_STRICT
1633 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1634 HWACCMDumpRegs(pVM, pCtx);
1635#endif
1636
1637 Log2(("E%d", exitReason));
1638 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1639 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1640 Log2(("Interruption error code %d\n", errCode));
1641 Log2(("IntInfo = %08x\n", intInfo));
1642 Log2(("New EIP=%VGv\n", pCtx->rip));
1643
1644 if (fSyncTPR)
1645 {
1646 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1647 AssertRC(rc);
1648 }
1649
1650 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1651 switch (exitReason)
1652 {
1653 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1654 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1655 {
1656 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1657
1658 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1659 {
1660 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1661 /* External interrupt; leave to allow it to be dispatched again. */
1662 rc = VINF_EM_RAW_INTERRUPT;
1663 break;
1664 }
1665 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1666 {
1667 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1668 /* External interrupt; leave to allow it to be dispatched again. */
1669 rc = VINF_EM_RAW_INTERRUPT;
1670 break;
1671
1672 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1673 AssertFailed(); /* can't come here; fails the first check. */
1674 break;
1675
1676 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1677 Assert(vector == 3 || vector == 4);
1678 /* no break */
1679 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1680 Log2(("Hardware/software interrupt %d\n", vector));
1681 switch (vector)
1682 {
1683 case X86_XCPT_NM:
1684 {
1685 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1686
1687 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1688 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1689 rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1690 if (rc == VINF_SUCCESS)
1691 {
1692 Assert(CPUMIsGuestFPUStateActive(pVM));
1693
1694 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1695
1696 /* Continue execution. */
1697 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1698 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1699
1700 goto ResumeExecution;
1701 }
1702
1703 Log(("Forward #NM fault to the guest\n"));
1704 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1705 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1706 AssertRC(rc);
1707 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1708 goto ResumeExecution;
1709 }
1710
1711 case X86_XCPT_PF: /* Page fault */
1712 {
1713 Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1714 /* Exit qualification contains the linear address of the page fault. */
1715 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1716 TRPMSetErrorCode(pVM, errCode);
1717 TRPMSetFaultAddress(pVM, exitQualification);
1718
1719 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1720 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1721 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1722 if (rc == VINF_SUCCESS)
1723 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1724 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1725 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1726
1727 TRPMResetTrap(pVM);
1728
1729 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1730 goto ResumeExecution;
1731 }
1732 else
1733 if (rc == VINF_EM_RAW_GUEST_TRAP)
1734 { /* A genuine pagefault.
1735 * Forward the trap to the guest by injecting the exception and resuming execution.
1736 */
1737 Log2(("Forward page fault to the guest\n"));
1738 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1739 /* The error code might have been changed. */
1740 errCode = TRPMGetErrorCode(pVM);
1741
1742 TRPMResetTrap(pVM);
1743
1744 /* Now we must update CR2. */
1745 pCtx->cr2 = exitQualification;
1746 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1747 AssertRC(rc);
1748
1749 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1750 goto ResumeExecution;
1751 }
1752#ifdef VBOX_STRICT
1753 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1754 Log2(("PGMTrap0eHandler failed with %d\n", rc));
1755#endif
1756 /* Need to go back to the recompiler to emulate the instruction. */
1757 TRPMResetTrap(pVM);
1758 break;
1759 }
1760
1761 case X86_XCPT_MF: /* Floating point exception. */
1762 {
1763 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1764 if (!(pCtx->cr0 & X86_CR0_NE))
1765 {
1766 /* old style FPU error reporting needs some extra work. */
1767 /** @todo don't fall back to the recompiler, but do it manually. */
1768 rc = VINF_EM_RAW_EMULATE_INSTR;
1769 break;
1770 }
1771 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1772 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1773 AssertRC(rc);
1774
1775 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1776 goto ResumeExecution;
1777 }
1778
1779 case X86_XCPT_DB: /* Debug exception. */
1780 {
1781 uint64_t uDR6;
1782
1783 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
1784 *
1785 * Exit qualification bits:
1786 * 3:0 B0-B3 which breakpoint condition was met
1787 * 12:4 Reserved (0)
1788 * 13 BD - debug register access detected
1789 * 14 BS - single step execution or branch taken
1790 * 63:15 Reserved (0)
1791 */
1792 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDB);
1793
1794 /* Note that we don't support guest and host-initiated debugging at the same time. */
1795 Assert(DBGFIsStepping(pVM));
1796
1797 uDR6 = X86_DR6_INIT_VAL;
1798 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
1799 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
1800 if (rc == VINF_EM_RAW_GUEST_TRAP)
1801 {
1802 /** @todo this isn't working, but we'll never get here normally. */
1803
1804 /* Update DR6 here. */
1805 pCtx->dr[6] = uDR6;
1806
1807 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
1808 pCtx->dr[7] &= ~X86_DR7_GD;
1809
1810 /* Paranoia. */
1811 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1812 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1813 pCtx->dr[7] |= 0x400; /* must be one */
1814
1815 /* Resync DR7 */
1816 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
1817 AssertRC(rc);
1818
1819 Log(("Trap %x (debug) at %VGv exit qualification %VX64\n", vector, pCtx->rip, exitQualification));
1820 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1821 AssertRC(rc);
1822
1823 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1824 goto ResumeExecution;
1825 }
1826 /* Return to ring 3 to deal with the debug exit code. */
1827 break;
1828 }
1829
1830 case X86_XCPT_GP: /* General protection failure exception.*/
1831 {
1832 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1833#ifdef VBOX_STRICT
1834 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
1835 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1836 AssertRC(rc);
1837 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1838 goto ResumeExecution;
1839#else
1840 Assert(CPUMIsGuestInRealModeEx(pCtx));
1841
1842 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %VGv\n", pCtx->rip));
1843 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1844 if (rc == VINF_SUCCESS)
1845 {
1846 /* EIP has been updated already. */
1847
1848 /* Only resume if successful. */
1849 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1850 goto ResumeExecution;
1851 }
1852 AssertMsg(rc == VERR_EM_INTERPRETER);
1853 break;
1854#endif
1855 }
1856
1857#ifdef VBOX_STRICT
1858 case X86_XCPT_DE: /* Divide error. */
1859 case X86_XCPT_UD: /* Unknown opcode exception. */
1860 case X86_XCPT_SS: /* Stack segment exception. */
1861 case X86_XCPT_NP: /* Segment not present exception. */
1862 {
1863 switch(vector)
1864 {
1865 case X86_XCPT_DE:
1866 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1867 break;
1868 case X86_XCPT_UD:
1869 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1870 break;
1871 case X86_XCPT_SS:
1872 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1873 break;
1874 case X86_XCPT_NP:
1875 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1876 break;
1877 }
1878
1879 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
1880 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1881 AssertRC(rc);
1882
1883 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1884 goto ResumeExecution;
1885 }
1886#endif
1887 default:
1888 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1889 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
1890 break;
1891 } /* switch (vector) */
1892
1893 break;
1894
1895 default:
1896 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
1897 AssertFailed();
1898 break;
1899 }
1900
1901 break;
1902 }
1903
1904 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1905 /* Clear VM-exit on IF=1 change. */
1906 Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1907 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1908 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1909 AssertRC(rc);
1910 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1911 goto ResumeExecution; /* we check for pending guest interrupts there */
1912
1913 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
1914 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
1915 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1916 /* Skip instruction and continue directly. */
1917 pCtx->rip += cbInstr;
1918 /* Continue execution.*/
1919 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1920 goto ResumeExecution;
1921
1922 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1923 {
1924 Log2(("VMX: Cpuid %x\n", pCtx->eax));
1925 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1926 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1927 if (rc == VINF_SUCCESS)
1928 {
1929 /* Update EIP and continue execution. */
1930 Assert(cbInstr == 2);
1931 pCtx->rip += cbInstr;
1932 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1933 goto ResumeExecution;
1934 }
1935 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1936 rc = VINF_EM_RAW_EMULATE_INSTR;
1937 break;
1938 }
1939
1940 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1941 {
1942 Log2(("VMX: Rdtsc\n"));
1943 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1944 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1945 if (rc == VINF_SUCCESS)
1946 {
1947 /* Update EIP and continue execution. */
1948 Assert(cbInstr == 2);
1949 pCtx->rip += cbInstr;
1950 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1951 goto ResumeExecution;
1952 }
1953 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1954 rc = VINF_EM_RAW_EMULATE_INSTR;
1955 break;
1956 }
1957
1958 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1959 {
1960 Log2(("VMX: invlpg\n"));
1961 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1962 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1963 if (rc == VINF_SUCCESS)
1964 {
1965 /* Update EIP and continue execution. */
1966 pCtx->rip += cbInstr;
1967 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1968 goto ResumeExecution;
1969 }
1970 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1971 break;
1972 }
1973
1974 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1975 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1976 {
1977 uint32_t cbSize;
1978
1979 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1980 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1981 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1982 if (rc == VINF_SUCCESS)
1983 {
1984 /* EIP has been updated already. */
1985
1986 /* Only resume if successful. */
1987 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1988 goto ResumeExecution;
1989 }
1990 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1991 break;
1992 }
1993
1994 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1995 {
1996 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1997 {
1998 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1999 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
2000 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
2001 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
2002 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
2003 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
2004
2005 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
2006 {
2007 case 0:
2008 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2009 break;
2010 case 2:
2011 break;
2012 case 3:
2013 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2014 break;
2015 case 4:
2016 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2017 break;
2018 case 8:
2019 /* CR8 contains the APIC TPR */
2020 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2021 break;
2022
2023 default:
2024 AssertFailed();
2025 break;
2026 }
2027 /* Check if a sync operation is pending. */
2028 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2029 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2030 {
2031 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2032 AssertRC(rc);
2033 }
2034 break;
2035
2036 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
2037 Log2(("VMX: mov x, crx\n"));
2038 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
2039
2040 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
2041 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2042
2043 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
2044 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
2045 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
2046 break;
2047
2048 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2049 Log2(("VMX: clts\n"));
2050 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
2051 rc = EMInterpretCLTS(pVM);
2052 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2053 break;
2054
2055 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2056 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2057 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
2058 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2059 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2060 break;
2061 }
2062
2063 /* Update EIP if no error occurred. */
2064 if (VBOX_SUCCESS(rc))
2065 pCtx->rip += cbInstr;
2066
2067 if (rc == VINF_SUCCESS)
2068 {
2069 /* Only resume if successful. */
2070 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2071 goto ResumeExecution;
2072 }
2073 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2074 break;
2075 }
2076
2077 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2078 {
2079 if (!DBGFIsStepping(pVM))
2080 {
2081 /* Disable drx move intercepts. */
2082 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2083 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2084 AssertRC(rc);
2085
2086 /* Save the host and load the guest debug state. */
2087 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
2088 AssertRC(rc);
2089
2090#ifdef VBOX_WITH_STATISTICS
2091 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
2092 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2093 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2094 else
2095 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2096#endif
2097
2098 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2099 goto ResumeExecution;
2100 }
2101
2102 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2103 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2104 {
2105 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2106 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2107 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2108 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2109 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2110 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2111 Log2(("DR7=%08x\n", pCtx->dr[7]));
2112 }
2113 else
2114 {
2115 Log2(("VMX: mov x, drx\n"));
2116 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2117 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2118 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2119 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2120 }
2121 /* Update EIP if no error occurred. */
2122 if (VBOX_SUCCESS(rc))
2123 pCtx->rip += cbInstr;
2124
2125 if (rc == VINF_SUCCESS)
2126 {
2127 /* Only resume if successful. */
2128 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2129 goto ResumeExecution;
2130 }
2131 Assert(rc == VERR_EM_INTERPRETER);
2132 break;
2133 }
2134
2135 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2136 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2137 {
2138 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2139 uint32_t uPort;
2140 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2141
2142 /** @todo necessary to make the distinction? */
2143 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2144 {
2145 uPort = pCtx->edx & 0xffff;
2146 }
2147 else
2148 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2149
2150 /* paranoia */
2151 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2152 {
2153 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2154 break;
2155 }
2156
2157 uint32_t cbSize = aIOSize[uIOWidth];
2158
2159 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2160 {
2161 /* ins/outs */
2162 uint32_t prefix = 0;
2163 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
2164 prefix |= PREFIX_REP;
2165
2166 if (fIOWrite)
2167 {
2168 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2169 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
2170 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2171 }
2172 else
2173 {
2174 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2175 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
2176 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2177 }
2178 }
2179 else
2180 {
2181 /* normal in/out */
2182 uint32_t uAndVal = aIOOpAnd[uIOWidth];
2183
2184 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2185
2186 if (fIOWrite)
2187 {
2188 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2189 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2190 }
2191 else
2192 {
2193 uint32_t u32Val = 0;
2194
2195 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2196 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2197 if (IOM_SUCCESS(rc))
2198 {
2199 /* Write back to the EAX register. */
2200 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2201 }
2202 }
2203 }
2204 /*
2205 * Handled the I/O return codes.
2206 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2207 */
2208 if (IOM_SUCCESS(rc))
2209 {
2210 /* Update EIP and continue execution. */
2211 pCtx->rip += cbInstr;
2212 if (RT_LIKELY(rc == VINF_SUCCESS))
2213 {
2214 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2215 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2216 {
2217 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxIOCheck);
2218 for (unsigned i=0;i<4;i++)
2219 {
2220 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2221
2222 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
2223 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2224 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2225 {
2226 uint64_t uDR6;
2227
2228 Assert(CPUMIsGuestDebugStateActive(pVM));
2229
2230 uDR6 = ASMGetDR6();
2231
2232 /* Clear all breakpoint status flags and set the one we just hit. */
2233 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2234 uDR6 |= RT_BIT(i);
2235
2236 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2237 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2238 * the contents have been read.
2239 */
2240 ASMSetDR6(uDR6);
2241
2242 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2243 pCtx->dr[7] &= ~X86_DR7_GD;
2244
2245 /* Paranoia. */
2246 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2247 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2248 pCtx->dr[7] |= 0x400; /* must be one */
2249
2250 /* Resync DR7 */
2251 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2252 AssertRC(rc);
2253
2254 /* Construct inject info. */
2255 intInfo = X86_XCPT_DB;
2256 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2257 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2258
2259 Log(("Inject IO debug trap at %VGv\n", pCtx->rip));
2260 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
2261 AssertRC(rc);
2262
2263 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2264 goto ResumeExecution;
2265 }
2266 }
2267 }
2268
2269 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2270 goto ResumeExecution;
2271 }
2272 break;
2273 }
2274
2275#ifdef VBOX_STRICT
2276 if (rc == VINF_IOM_HC_IOPORT_READ)
2277 Assert(!fIOWrite);
2278 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2279 Assert(fIOWrite);
2280 else
2281 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2282#endif
2283 break;
2284 }
2285
2286 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2287 LogFlow(("VMX_EXIT_TPR\n"));
2288 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2289 goto ResumeExecution;
2290
2291 default:
2292 /* The rest is handled after syncing the entire CPU state. */
2293 break;
2294 }
2295
2296 /* Note: the guest state isn't entirely synced back at this stage. */
2297
2298 /* Investigate why there was a VM-exit. (part 2) */
2299 switch (exitReason)
2300 {
2301 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2302 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2303 /* Already handled above. */
2304 break;
2305
2306 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2307 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2308 break;
2309
2310 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2311 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2312 rc = VINF_EM_RAW_INTERRUPT;
2313 AssertFailed(); /* Can't happen. Yet. */
2314 break;
2315
2316 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2317 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2318 rc = VINF_EM_RAW_INTERRUPT;
2319 AssertFailed(); /* Can't happen afaik. */
2320 break;
2321
2322 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2323 rc = VERR_EM_INTERPRETER;
2324 break;
2325
2326 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2327 /** Check if external interrupts are pending; if so, don't switch back. */
2328 pCtx->rip++; /* skip hlt */
2329 if ( pCtx->eflags.Bits.u1IF
2330 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2331 goto ResumeExecution;
2332
2333 rc = VINF_EM_HALT;
2334 break;
2335
2336 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2337 AssertFailed(); /* can't happen. */
2338 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2339 break;
2340
2341 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2342 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2343 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2344 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2345 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2346 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2347 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2348 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2349 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2350 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2351 /** @todo inject #UD immediately */
2352 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2353 break;
2354
2355 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2356 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2357 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2358 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2359 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2360 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2361 /* already handled above */
2362 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2363 || rc == VINF_EM_RAW_INTERRUPT
2364 || rc == VERR_EM_INTERPRETER
2365 || rc == VINF_EM_RAW_EMULATE_INSTR
2366 || rc == VINF_PGM_SYNC_CR3
2367 || rc == VINF_IOM_HC_IOPORT_READ
2368 || rc == VINF_IOM_HC_IOPORT_WRITE
2369 || rc == VINF_EM_RAW_GUEST_TRAP
2370 || rc == VINF_TRPM_XCPT_DISPATCHED
2371 || rc == VINF_EM_RESCHEDULE_REM,
2372 ("rc = %d\n", rc));
2373 break;
2374
2375 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2376 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2377 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2378 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2379 rc = VERR_EM_INTERPRETER;
2380 break;
2381
2382 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2383 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2384 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2385 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2386 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2387 break;
2388
2389 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2390 Assert(rc == VINF_EM_RAW_INTERRUPT);
2391 break;
2392
2393 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2394 {
2395#ifdef VBOX_STRICT
2396 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2397
2398 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2399 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2400
2401 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2402 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2403
2404 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2405 Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2406
2407 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2408 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2409
2410 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
2411 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
2412
2413 VMX_LOG_SELREG(CS, "CS");
2414 VMX_LOG_SELREG(DS, "DS");
2415 VMX_LOG_SELREG(ES, "ES");
2416 VMX_LOG_SELREG(FS, "FS");
2417 VMX_LOG_SELREG(GS, "GS");
2418 VMX_LOG_SELREG(SS, "SS");
2419 VMX_LOG_SELREG(TR, "TR");
2420 VMX_LOG_SELREG(LDTR, "LDTR");
2421
2422 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2423 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2424 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2425 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2426#endif /* VBOX_STRICT */
2427 rc = VERR_VMX_INVALID_GUEST_STATE;
2428 break;
2429 }
2430
2431 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2432 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2433 default:
2434 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
2435 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2436 break;
2437
2438 }
2439end:
2440
2441 /* Signal changes for the recompiler. */
2442 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2443
2444 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2445 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2446 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2447 {
2448 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2449 /* On the next entry we'll only sync the host context. */
2450 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2451 }
2452 else
2453 {
2454 /* On the next entry we'll sync everything. */
2455 /** @todo we can do better than this */
2456 /* Not in the VINF_PGM_CHANGE_MODE though! */
2457 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2458 }
2459
2460 /* translate into a less severe return code */
2461 if (rc == VERR_EM_INTERPRETER)
2462 rc = VINF_EM_RAW_EMULATE_INSTR;
2463 else
2464 /* Try to extract more information about what might have gone wrong here. */
2465 if (rc == VERR_VMX_INVALID_VMCS_PTR)
2466 {
2467 VMXGetActivateVMCS(&pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys);
2468 pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS;
2469 }
2470
2471 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2472
2473 Log2(("X"));
2474 return rc;
2475}
2476
2477
2478/**
2479 * Enters the VT-x session
2480 *
2481 * @returns VBox status code.
2482 * @param pVM The VM to operate on.
2483 * @param pCpu CPU info struct
2484 */
2485HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2486{
2487 Assert(pVM->hwaccm.s.vmx.fSupported);
2488
2489 unsigned cr4 = ASMGetCR4();
2490 if (!(cr4 & X86_CR4_VMXE))
2491 {
2492 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2493 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2494 }
2495
2496 /* Activate the VM Control Structure. */
2497 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2498 if (VBOX_FAILURE(rc))
2499 return rc;
2500
2501 pVM->hwaccm.s.vmx.fResumeVM = false;
2502 return VINF_SUCCESS;
2503}
2504
2505
2506/**
2507 * Leaves the VT-x session
2508 *
2509 * @returns VBox status code.
2510 * @param pVM The VM to operate on.
2511 * @param pCtx CPU context
2512 */
2513HWACCMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx)
2514{
2515 Assert(pVM->hwaccm.s.vmx.fSupported);
2516
2517 /* Save the guest debug state if necessary. */
2518 if (CPUMIsGuestDebugStateActive(pVM))
2519 {
2520 CPUMR0SaveGuestDebugState(pVM, pCtx, true /* save DR6 */);
2521
2522 /* Enable drx move intercepts again. */
2523 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2524 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2525 AssertRC(rc);
2526
2527 /* Resync the debug registers the next time. */
2528 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2529 }
2530 else
2531 Assert(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
2532
2533 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2534 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2535 AssertRC(rc);
2536
2537 return VINF_SUCCESS;
2538}
2539
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