VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 13037

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1/* $Id: HWVMXR0.cpp 13037 2008-10-07 11:10:32Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43
44/*******************************************************************************
45* Global Variables *
46*******************************************************************************/
47/* IO operation lookup arrays. */
48static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
49static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
50
51
52static void VMXR0CheckError(PVM pVM, int rc)
53{
54 if (rc == VERR_VMX_GENERIC)
55 {
56 RTCCUINTREG instrError;
57
58 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
59 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
60 }
61 pVM->hwaccm.s.lLastError = rc;
62}
63
64/**
65 * Sets up and activates VT-x on the current CPU
66 *
67 * @returns VBox status code.
68 * @param pCpu CPU info struct
69 * @param pVM The VM to operate on.
70 * @param pvPageCpu Pointer to the global cpu page
71 * @param pPageCpuPhys Physical address of the global cpu page
72 */
73VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
74{
75 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
76 AssertReturn(pVM, VERR_INVALID_PARAMETER);
77 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
78
79 /* Setup Intel VMX. */
80 Assert(pVM->hwaccm.s.vmx.fSupported);
81
82#ifdef LOG_ENABLED
83 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
84#endif
85 /* Set revision dword at the beginning of the VMXON structure. */
86 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
87
88 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
89 * (which can have very bad consequences!!!)
90 */
91
92 /* Make sure the VMX instructions don't cause #UD faults. */
93 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
94
95 /* Enter VMX Root Mode */
96 int rc = VMXEnable(pPageCpuPhys);
97 if (VBOX_FAILURE(rc))
98 {
99 VMXR0CheckError(pVM, rc);
100 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
101 return VERR_VMX_VMXON_FAILED;
102 }
103 return VINF_SUCCESS;
104}
105
106/**
107 * Deactivates VT-x on the current CPU
108 *
109 * @returns VBox status code.
110 * @param pCpu CPU info struct
111 * @param pvPageCpu Pointer to the global cpu page
112 * @param pPageCpuPhys Physical address of the global cpu page
113 */
114VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
115{
116 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
117 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
118
119 /* Leave VMX Root Mode. */
120 VMXDisable();
121
122 /* And clear the X86_CR4_VMXE bit */
123 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
124
125#ifdef LOG_ENABLED
126 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
127#endif
128 return VINF_SUCCESS;
129}
130
131/**
132 * Does Ring-0 per VM VT-x init.
133 *
134 * @returns VBox status code.
135 * @param pVM The VM to operate on.
136 */
137VMMR0DECL(int) VMXR0InitVM(PVM pVM)
138{
139 int rc;
140
141#ifdef LOG_ENABLED
142 SUPR0Printf("VMXR0InitVM %x\n", pVM);
143#endif
144 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
145 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
146
147
148 /* Allocate one page for the VM control structure (VMCS). */
149 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
150 AssertRC(rc);
151 if (RT_FAILURE(rc))
152 return rc;
153
154 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
155 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
156 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
157
158 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
159 {
160 /* Allocate one page for the virtual APIC mmio cache. */
161 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
162 AssertRC(rc);
163 if (RT_FAILURE(rc))
164 return rc;
165
166 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
167 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
168 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
169 }
170 else
171 {
172 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
173 pVM->hwaccm.s.vmx.pAPIC = 0;
174 pVM->hwaccm.s.vmx.pAPICPhys = 0;
175 }
176
177 /* Allocate the MSR bitmap if this feature is supported. */
178 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
179 {
180 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
181 AssertRC(rc);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
186 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
187 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
188 }
189
190 /* Current guest paging mode. */
191 pVM->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
192
193#ifdef LOG_ENABLED
194 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys);
195#endif
196 return VINF_SUCCESS;
197}
198
199/**
200 * Does Ring-0 per VM VT-x termination.
201 *
202 * @returns VBox status code.
203 * @param pVM The VM to operate on.
204 */
205VMMR0DECL(int) VMXR0TermVM(PVM pVM)
206{
207 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
208 {
209 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
210 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
211 pVM->hwaccm.s.vmx.pVMCS = 0;
212 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
213 }
214 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
215 {
216 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
217 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
218 pVM->hwaccm.s.vmx.pAPIC = 0;
219 pVM->hwaccm.s.vmx.pAPICPhys = 0;
220 }
221 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
222 {
223 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
224 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
225 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
226 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
227 }
228 return VINF_SUCCESS;
229}
230
231/**
232 * Sets up VT-x for the specified VM
233 *
234 * @returns VBox status code.
235 * @param pVM The VM to operate on.
236 */
237VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
238{
239 int rc = VINF_SUCCESS;
240 uint32_t val;
241
242 AssertReturn(pVM, VERR_INVALID_PARAMETER);
243 Assert(pVM->hwaccm.s.vmx.pVMCS);
244
245 /* Set revision dword at the beginning of the VMCS structure. */
246 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
247
248 /* Clear VM Control Structure. */
249 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
250 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
251 if (VBOX_FAILURE(rc))
252 goto vmx_end;
253
254 /* Activate the VM Control Structure. */
255 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
256 if (VBOX_FAILURE(rc))
257 goto vmx_end;
258
259 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
260 * Set required bits to one and zero according to the MSR capabilities.
261 */
262 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
263 /* External and non-maskable interrupts cause VM-exits. */
264 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
265 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
266
267 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
268 AssertRC(rc);
269
270 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
271 * Set required bits to one and zero according to the MSR capabilities.
272 */
273 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
274 /* Program which event cause VM-exits and which features we want to use. */
275 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
276 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
277 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
278 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
279 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
280
281 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
282 if (!pVM->hwaccm.s.fNestedPaging)
283 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
284 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
285 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
286
287 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
288
289#if HC_ARCH_BITS == 64
290 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
291 {
292 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
293 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
294 Assert(pVM->hwaccm.s.vmx.pAPIC);
295 }
296 else
297 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
298 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
299#endif
300
301#ifdef VBOX_WITH_VTX_MSR_BITMAPS
302 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
303 {
304 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
305 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
306 }
307#endif
308
309 /* We will use the secondary control if it's present. */
310 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
311
312 /* Mask away the bits that the CPU doesn't support */
313 /** @todo make sure they don't conflict with the above requirements. */
314 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
315 pVM->hwaccm.s.vmx.proc_ctls = val;
316
317 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
318 AssertRC(rc);
319
320 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
321 {
322 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
323 * Set required bits to one and zero according to the MSR capabilities.
324 */
325 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
326 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
327
328#ifdef HWACCM_VTX_WITH_EPT
329 if (pVM->hwaccm.s.fNestedPaging)
330 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
331#endif
332 /* Mask away the bits that the CPU doesn't support */
333 /** @todo make sure they don't conflict with the above requirements. */
334 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
335
336 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
337 AssertRC(rc);
338 }
339
340 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
341 * Set required bits to one and zero according to the MSR capabilities.
342 */
343 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
344 AssertRC(rc);
345
346 /* VMX_VMCS_CTRL_EXIT_CONTROLS
347 * Set required bits to one and zero according to the MSR capabilities.
348 */
349 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
350#if HC_ARCH_BITS == 64
351 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
352#else
353 /* else Must be zero when AMD64 is not available. */
354#endif
355 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
356 /* Don't acknowledge external interrupts on VM-exit. */
357 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
358 AssertRC(rc);
359
360 /* Forward all exception except #NM & #PF to the guest.
361 * We always need to check pagefaults since our shadow page table can be out of sync.
362 * And we always lazily sync the FPU & XMM state.
363 */
364
365 /** @todo Possible optimization:
366 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
367 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
368 * registers ourselves of course.
369 *
370 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
371 */
372 pVM->hwaccm.s.vmx.u32TrapMask = HWACCM_VMX_TRAP_MASK;
373#ifndef DEBUG
374 if (pVM->hwaccm.s.fNestedPaging)
375 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
376#endif
377 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
378 AssertRC(rc);
379
380 /* Don't filter page faults; all of them should cause a switch. */
381 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
382 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
383 AssertRC(rc);
384
385 /* Init TSC offset to zero. */
386 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
387#if HC_ARCH_BITS == 32
388 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
389#endif
390 AssertRC(rc);
391
392 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
393#if HC_ARCH_BITS == 32
394 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
395#endif
396 AssertRC(rc);
397
398 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
399#if HC_ARCH_BITS == 32
400 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
401#endif
402 AssertRC(rc);
403
404 /* Set the MSR bitmap address. */
405 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
406 {
407 /* Optional */
408 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
409#if HC_ARCH_BITS == 32
410 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32);
411#endif
412 AssertRC(rc);
413 }
414
415 /* Clear MSR controls. */
416 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
417 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
418 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
419#if HC_ARCH_BITS == 32
420 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
421 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
422 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
423#endif
424 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
425 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
426 AssertRC(rc);
427
428 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
429 {
430 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
431 /* Optional */
432 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
433 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
434#if HC_ARCH_BITS == 32
435 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
436#endif
437 AssertRC(rc);
438 }
439
440 /* Set link pointer to -1. Not currently used. */
441#if HC_ARCH_BITS == 32
442 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
443 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
444#else
445 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
446#endif
447 AssertRC(rc);
448
449 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
450 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
451 AssertRC(rc);
452
453vmx_end:
454 VMXR0CheckError(pVM, rc);
455 return rc;
456}
457
458
459/**
460 * Injects an event (trap or external interrupt)
461 *
462 * @returns VBox status code.
463 * @param pVM The VM to operate on.
464 * @param pCtx CPU Context
465 * @param intInfo VMX interrupt info
466 * @param cbInstr Opcode length of faulting instruction
467 * @param errCode Error code (optional)
468 */
469static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
470{
471 int rc;
472
473#ifdef VBOX_STRICT
474 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
475 if (iGate == 0xE)
476 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
477 else
478 if (iGate < 0x20)
479 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
480 else
481 {
482 LogFlow(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
483 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
484 Assert(pCtx->eflags.u32 & X86_EFL_IF);
485 }
486#endif
487
488#ifdef HWACCM_VMX_EMULATE_REALMODE
489 if (CPUMIsGuestInRealModeEx(pCtx))
490 {
491 /* Injecting events doesn't work right with real mode emulation.
492 * (#GP if we try to inject external hardware interrupts)
493 * Fake an 'int x' instruction. Note that we need to take special precautions when
494 * the inject is interrupted as the normal pending event method seems to be broken in this case.
495 */
496 LogFlow(("Fake 'int %x' inject (real mode)\n", iGate));
497 /* Make sure the return address is set to the current IP. (ugly hack alert) */
498 pCtx->rip--;
499 cbInstr = 1;
500 intInfo = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo) | (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
501
502 pVM->hwaccm.s.vmx.RealMode.Event.intInfo = intInfo;
503 pVM->hwaccm.s.vmx.RealMode.Event.fPending = true;
504 pVM->hwaccm.s.vmx.RealMode.eip = pCtx->eip;
505 }
506#endif /* HWACCM_VMX_EMULATE_REALMODE */
507
508 /* Set event injection state. */
509 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
510
511 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
512 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
513
514 AssertRC(rc);
515 return rc;
516}
517
518
519/**
520 * Checks for pending guest interrupts and injects them
521 *
522 * @returns VBox status code.
523 * @param pVM The VM to operate on.
524 * @param pCtx CPU Context
525 */
526static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
527{
528 int rc;
529
530 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
531 if (pVM->hwaccm.s.Event.fPending)
532 {
533 Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
534 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
535 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
536 AssertRC(rc);
537
538 pVM->hwaccm.s.Event.fPending = false;
539 return VINF_SUCCESS;
540 }
541
542 /* When external interrupts are pending, we should exit the VM when IF is set. */
543 if ( !TRPMHasTrap(pVM)
544 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
545 {
546 if (!(pCtx->eflags.u32 & X86_EFL_IF))
547 {
548 if (!(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
549 {
550 LogFlow(("Enable irq window exit!\n"));
551 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
552 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
553 AssertRC(rc);
554 }
555 /* else nothing to do but wait */
556 }
557 else
558 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
559 {
560 uint8_t u8Interrupt;
561
562 rc = PDMGetInterrupt(pVM, &u8Interrupt);
563 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
564 if (VBOX_SUCCESS(rc))
565 {
566 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
567 AssertRC(rc);
568 }
569 else
570 {
571 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
572 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
573 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
574 /* Just continue */
575 }
576 }
577 else
578 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
579 }
580
581#ifdef VBOX_STRICT
582 if (TRPMHasTrap(pVM))
583 {
584 uint8_t u8Vector;
585 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
586 AssertRC(rc);
587 }
588#endif
589
590 if ( pCtx->eflags.u32 & X86_EFL_IF
591 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
592 && TRPMHasTrap(pVM)
593 )
594 {
595 uint8_t u8Vector;
596 int rc;
597 TRPMEVENT enmType;
598 RTGCUINTPTR intInfo;
599 RTGCUINT errCode;
600
601 /* If a new event is pending, then dispatch it now. */
602 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
603 AssertRC(rc);
604 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
605 Assert(enmType != TRPM_SOFTWARE_INT);
606
607 /* Clear the pending trap. */
608 rc = TRPMResetTrap(pVM);
609 AssertRC(rc);
610
611 intInfo = u8Vector;
612 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
613
614 if (enmType == TRPM_TRAP)
615 {
616 switch (u8Vector) {
617 case 8:
618 case 10:
619 case 11:
620 case 12:
621 case 13:
622 case 14:
623 case 17:
624 /* Valid error codes. */
625 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
626 break;
627 default:
628 break;
629 }
630 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
631 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
632 else
633 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
634 }
635 else
636 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
637
638 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
639 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
640 AssertRC(rc);
641 } /* if (interrupts can be dispatched) */
642
643 return VINF_SUCCESS;
644}
645
646/**
647 * Save the host state
648 *
649 * @returns VBox status code.
650 * @param pVM The VM to operate on.
651 */
652VMMR0DECL(int) VMXR0SaveHostState(PVM pVM)
653{
654 int rc = VINF_SUCCESS;
655
656 /*
657 * Host CPU Context
658 */
659 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
660 {
661 RTIDTR idtr;
662 RTGDTR gdtr;
663 RTSEL SelTR;
664 PX86DESCHC pDesc;
665 uintptr_t trBase;
666
667 /* Control registers */
668 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
669 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
670 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
671 AssertRC(rc);
672 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
673 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
674 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
675
676 /* Selector registers. */
677 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
678 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
679 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
680 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
681#if HC_ARCH_BITS == 32
682 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
683 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
684#endif
685 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
686 SelTR = ASMGetTR();
687 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
688 AssertRC(rc);
689 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
690 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
691 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
692 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
693 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
694 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
695 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
696
697 /* GDTR & IDTR */
698 ASMGetGDTR(&gdtr);
699 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
700 ASMGetIDTR(&idtr);
701 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
702 AssertRC(rc);
703 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
704 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
705
706 /* Save the base address of the TR selector. */
707 if (SelTR > gdtr.cbGdt)
708 {
709 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
710 return VERR_VMX_INVALID_HOST_STATE;
711 }
712
713 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
714#if HC_ARCH_BITS == 64
715 trBase = X86DESC64_BASE(*pDesc);
716#else
717 trBase = X86DESC_BASE(*pDesc);
718#endif
719 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
720 AssertRC(rc);
721 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
722
723 /* FS and GS base. */
724#if HC_ARCH_BITS == 64
725 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
726 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
727 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
728 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
729#endif
730 AssertRC(rc);
731
732 /* Sysenter MSRs. */
733 /** @todo expensive!! */
734 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
735 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
736#if HC_ARCH_BITS == 32
737 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
738 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
739 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
740 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
741#else
742 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
743 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
744 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
745 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
746#endif
747 AssertRC(rc);
748
749 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
750 }
751 return rc;
752}
753
754
755/**
756 * Loads the guest state
757 *
758 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
759 *
760 * @returns VBox status code.
761 * @param pVM The VM to operate on.
762 * @param pCtx Guest context
763 */
764VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
765{
766 int rc = VINF_SUCCESS;
767 RTGCUINTPTR val;
768 X86EFLAGS eflags;
769
770 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
771 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
772 {
773#ifdef HWACCM_VMX_EMULATE_REALMODE
774 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
775 if (pVM->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
776 {
777# define VTX_CORRECT_PROT_SEL(reg) \
778 { \
779 if ( pCtx->reg##Hid.u64Base == (pVM->hwaccm.s.vmx.RealMode.reg##Hid.u64Base & 0xfffff) \
780 && pCtx->reg == ((pVM->hwaccm.s.vmx.RealMode.reg##Hid.u64Base >> 4) & ~X86_SEL_RPL)) \
781 { \
782 pCtx->reg##Hid = pVM->hwaccm.s.vmx.RealMode.reg##Hid; \
783 pCtx->reg = pVM->hwaccm.s.vmx.RealMode.reg; \
784 } \
785 }
786
787 /* Correct weird requirements for switching to protected mode. */
788 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
789 && enmGuestMode >= PGMMODE_PROTECTED)
790 {
791 /* DPL of all hidden selector registers must match the current CPL (0). */
792 pCtx->csHid.Attr.n.u2Dpl = 0;
793 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
794
795 pCtx->dsHid.Attr.n.u2Dpl = 0;
796 pCtx->esHid.Attr.n.u2Dpl = 0;
797 pCtx->fsHid.Attr.n.u2Dpl = 0;
798 pCtx->gsHid.Attr.n.u2Dpl = 0;
799 pCtx->ssHid.Attr.n.u2Dpl = 0;
800
801 /* RPL of all selectors must match the current CPL (0). */
802 pCtx->cs &= ~X86_SEL_RPL;
803 pCtx->ds &= ~X86_SEL_RPL;
804 pCtx->es &= ~X86_SEL_RPL;
805 pCtx->fs &= ~X86_SEL_RPL;
806 pCtx->gs &= ~X86_SEL_RPL;
807 pCtx->ss &= ~X86_SEL_RPL;
808
809 if (pVM->hwaccm.s.vmx.RealMode.fValid)
810 {
811 VTX_CORRECT_PROT_SEL(ds);
812 VTX_CORRECT_PROT_SEL(es);
813 VTX_CORRECT_PROT_SEL(fs);
814 VTX_CORRECT_PROT_SEL(gs);
815 VTX_CORRECT_PROT_SEL(ss);
816 pVM->hwaccm.s.vmx.RealMode.fValid = false;
817 }
818 }
819 else
820 /* Switching from protected mode to real mode. */
821 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode >= PGMMODE_PROTECTED
822 && enmGuestMode == PGMMODE_REAL)
823 {
824 /* Save the original hidden selectors in case we need to restore them later on. */
825 pVM->hwaccm.s.vmx.RealMode.ds = pCtx->ds;
826 pVM->hwaccm.s.vmx.RealMode.dsHid = pCtx->dsHid;
827 pVM->hwaccm.s.vmx.RealMode.es = pCtx->es;
828 pVM->hwaccm.s.vmx.RealMode.esHid = pCtx->esHid;
829 pVM->hwaccm.s.vmx.RealMode.fs = pCtx->fs;
830 pVM->hwaccm.s.vmx.RealMode.fsHid = pCtx->fsHid;
831 pVM->hwaccm.s.vmx.RealMode.gs = pCtx->gs;
832 pVM->hwaccm.s.vmx.RealMode.gsHid = pCtx->gsHid;
833 pVM->hwaccm.s.vmx.RealMode.ss = pCtx->ss;
834 pVM->hwaccm.s.vmx.RealMode.ssHid = pCtx->ssHid;
835 pVM->hwaccm.s.vmx.RealMode.fValid = true;
836
837 /* The selector value & base must be adjusted or else... */
838 pCtx->cs = pCtx->csHid.u64Base >> 4;
839 pCtx->ds = pCtx->dsHid.u64Base >> 4;
840 pCtx->es = pCtx->esHid.u64Base >> 4;
841 pCtx->fs = pCtx->fsHid.u64Base >> 4;
842 pCtx->gs = pCtx->gsHid.u64Base >> 4;
843 pCtx->ss = pCtx->ssHid.u64Base >> 4;
844
845 /* The limit must also be adjusted. */
846 pCtx->csHid.u32Limit &= 0xffff;
847 pCtx->dsHid.u32Limit &= 0xffff;
848 pCtx->esHid.u32Limit &= 0xffff;
849 pCtx->fsHid.u32Limit &= 0xffff;
850 pCtx->gsHid.u32Limit &= 0xffff;
851 pCtx->ssHid.u32Limit &= 0xffff;
852
853 Assert(pCtx->dsHid.u64Base <= 0xfffff);
854 Assert(pCtx->esHid.u64Base <= 0xfffff);
855 Assert(pCtx->fsHid.u64Base <= 0xfffff);
856 Assert(pCtx->gsHid.u64Base <= 0xfffff);
857 }
858 pVM->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
859 }
860 else
861 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
862 if ( CPUMIsGuestInRealModeEx(pCtx)
863 && pCtx->csHid.u64Base == 0xffff0000)
864 {
865 pCtx->csHid.u64Base = 0xf0000;
866 pCtx->cs = 0xf000;
867 }
868#endif /* HWACCM_VMX_EMULATE_REALMODE */
869
870 VMX_WRITE_SELREG(ES, es);
871 AssertRC(rc);
872
873 VMX_WRITE_SELREG(CS, cs);
874 AssertRC(rc);
875
876 VMX_WRITE_SELREG(SS, ss);
877 AssertRC(rc);
878
879 VMX_WRITE_SELREG(DS, ds);
880 AssertRC(rc);
881
882 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
883 VMX_WRITE_SELREG(FS, fs);
884 AssertRC(rc);
885
886 VMX_WRITE_SELREG(GS, gs);
887 AssertRC(rc);
888 }
889
890 /* Guest CPU context: LDTR. */
891 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
892 {
893 if (pCtx->ldtr == 0)
894 {
895 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
896 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
897 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
898 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
899 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
900 }
901 else
902 {
903 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
904 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
905 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
906 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
907 }
908 AssertRC(rc);
909 }
910 /* Guest CPU context: TR. */
911 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
912 {
913#ifdef HWACCM_VMX_EMULATE_REALMODE
914 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
915 if (CPUMIsGuestInRealModeEx(pCtx))
916 {
917 RTGCPHYS GCPhys;
918
919 /* We convert it here every time as pci regions could be reconfigured. */
920 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
921 AssertRC(rc);
922
923 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, 0);
924 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
925 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
926
927 X86DESCATTR attr;
928
929 attr.u = 0;
930 attr.n.u1Present = 1;
931 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
932 val = attr.u;
933 }
934 else
935#endif /* HWACCM_VMX_EMULATE_REALMODE */
936 {
937 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
938 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
939 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
940
941 val = pCtx->trHid.Attr.u;
942
943 /* The TSS selector must be busy. */
944 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
945 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
946 else
947 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
948 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
949
950 }
951 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
952 AssertRC(rc);
953 }
954 /* Guest CPU context: GDTR. */
955 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
956 {
957 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
958 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
959 AssertRC(rc);
960 }
961 /* Guest CPU context: IDTR. */
962 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
963 {
964 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
965 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
966 AssertRC(rc);
967 }
968
969 /*
970 * Sysenter MSRs (unconditional)
971 */
972 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
973 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
974 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
975 AssertRC(rc);
976
977 /* Control registers */
978 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
979 {
980 val = pCtx->cr0;
981 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
982 Log2(("Guest CR0-shadow %08x\n", val));
983 if (CPUMIsGuestFPUStateActive(pVM) == false)
984 {
985 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
986 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
987 }
988 else
989 {
990 /** @todo check if we support the old style mess correctly. */
991 if (!(val & X86_CR0_NE))
992 {
993 Log(("Forcing X86_CR0_NE!!!\n"));
994
995 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
996 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
997 {
998 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_MF);
999 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1000 AssertRC(rc);
1001 pVM->hwaccm.s.fFPUOldStyleOverride = true;
1002 }
1003 }
1004
1005 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1006 }
1007 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1008 val |= X86_CR0_PE | X86_CR0_PG;
1009 if (pVM->hwaccm.s.fNestedPaging)
1010 {
1011 if (!(pCtx->cr0 & X86_CR0_PG))
1012 {
1013 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1014 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1015 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1016 }
1017 else
1018 {
1019 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1020 pVM->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1021 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1022 }
1023 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1024 AssertRC(rc);
1025 }
1026 else
1027 {
1028 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1029 val |= X86_CR0_WP;
1030 }
1031
1032 /* Always enable caching. */
1033 val &= ~(X86_CR0_CD|X86_CR0_NW);
1034
1035 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
1036 Log2(("Guest CR0 %08x\n", val));
1037 /* CR0 flags owned by the host; if the guests attempts to change them, then
1038 * the VM will exit.
1039 */
1040 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1041 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1042 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1043 | X86_CR0_TS
1044 | X86_CR0_ET /* Bit not restored during VM-exit! */
1045 | X86_CR0_CD /* Bit not restored during VM-exit! */
1046 | X86_CR0_NW /* Bit not restored during VM-exit! */
1047 | X86_CR0_NE
1048 | X86_CR0_MP;
1049 pVM->hwaccm.s.vmx.cr0_mask = val;
1050
1051 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1052 Log2(("Guest CR0-mask %08x\n", val));
1053 AssertRC(rc);
1054 }
1055 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1056 {
1057 /* CR4 */
1058 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1059 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1060 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1061 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1062
1063 if (!pVM->hwaccm.s.fNestedPaging)
1064 {
1065 switch(pVM->hwaccm.s.enmShadowMode)
1066 {
1067 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1068 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1069 case PGMMODE_32_BIT: /* 32-bit paging. */
1070 break;
1071
1072 case PGMMODE_PAE: /* PAE paging. */
1073 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1074 /** @todo use normal 32 bits paging */
1075 val |= X86_CR4_PAE;
1076 break;
1077
1078 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1079 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1080#ifdef VBOX_ENABLE_64_BITS_GUESTS
1081 break;
1082#else
1083 AssertFailed();
1084 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1085#endif
1086 default: /* shut up gcc */
1087 AssertFailed();
1088 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1089 }
1090 }
1091
1092#ifdef HWACCM_VMX_EMULATE_REALMODE
1093 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1094 if (CPUMIsGuestInRealModeEx(pCtx))
1095 val |= X86_CR4_VME;
1096#endif /* HWACCM_VMX_EMULATE_REALMODE */
1097
1098 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
1099 Log2(("Guest CR4 %08x\n", val));
1100 /* CR4 flags owned by the host; if the guests attempts to change them, then
1101 * the VM will exit.
1102 */
1103 val = 0
1104#ifdef HWACCM_VMX_EMULATE_REALMODE
1105 | X86_CR4_VME
1106#endif
1107 | X86_CR4_PAE
1108 | X86_CR4_PGE
1109 | X86_CR4_PSE
1110 | X86_CR4_VMXE;
1111 pVM->hwaccm.s.vmx.cr4_mask = val;
1112
1113 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1114 Log2(("Guest CR4-mask %08x\n", val));
1115 AssertRC(rc);
1116 }
1117
1118 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1119 {
1120 val = PGMGetHyperCR3(pVM);
1121 Assert(val);
1122 if (pVM->hwaccm.s.fNestedPaging)
1123 {
1124#if HC_ARCH_BITS == 64
1125 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EPTP_FULL, val);
1126#else
1127 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EPTP_FULL, val);
1128 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EPTP_HIGH, val);
1129#endif
1130 AssertRC(rc);
1131
1132 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1133 val = pCtx->cr3;
1134 }
1135 /* Save our shadow CR3 register. */
1136 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
1137 AssertRC(rc);
1138 }
1139
1140 /* Debug registers. */
1141 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1142 {
1143 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1144 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1145
1146 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1147 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1148 pCtx->dr[7] |= 0x400; /* must be one */
1149
1150 /* Resync DR7 */
1151 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
1152 AssertRC(rc);
1153
1154 /* Sync the debug state now if any breakpoint is armed. */
1155 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1156 && !CPUMIsGuestDebugStateActive(pVM)
1157 && !DBGFIsStepping(pVM))
1158 {
1159 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxArmed);
1160
1161 /* Disable drx move intercepts. */
1162 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1163 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1164 AssertRC(rc);
1165
1166 /* Save the host and load the guest debug state. */
1167 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
1168 AssertRC(rc);
1169 }
1170
1171 /* IA32_DEBUGCTL MSR. */
1172 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1173 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
1174 AssertRC(rc);
1175
1176 /** @todo do we really ever need this? */
1177 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1178 AssertRC(rc);
1179 }
1180
1181 /* EIP, ESP and EFLAGS */
1182 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
1183 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
1184 AssertRC(rc);
1185
1186 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1187 eflags = pCtx->eflags;
1188 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1189 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1190
1191#ifdef HWACCM_VMX_EMULATE_REALMODE
1192 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1193 if (CPUMIsGuestInRealModeEx(pCtx))
1194 {
1195 eflags.Bits.u1VM = 1;
1196 eflags.Bits.u2IOPL = 3;
1197 }
1198#endif /* HWACCM_VMX_EMULATE_REALMODE */
1199 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1200 AssertRC(rc);
1201
1202 /* TSC offset. */
1203 uint64_t u64TSCOffset;
1204
1205 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1206 {
1207 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1208#if HC_ARCH_BITS == 64
1209 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1210#else
1211 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
1212 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
1213#endif
1214 AssertRC(rc);
1215
1216 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1217 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1218 AssertRC(rc);
1219 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
1220 }
1221 else
1222 {
1223 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1224 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1225 AssertRC(rc);
1226 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1227 }
1228
1229 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1230 * Set required bits to one and zero according to the MSR capabilities.
1231 */
1232 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1233 /* 64 bits guest mode? */
1234 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1235 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1236 /* else Must be zero when AMD64 is not available. */
1237
1238 /* Mask away the bits that the CPU doesn't support */
1239 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1240 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1241 AssertRC(rc);
1242
1243 /* 64 bits guest mode? */
1244 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1245 {
1246#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
1247 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1248#else
1249 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1250#endif
1251 /* Unconditionally update these as wrmsr might have changed them. */
1252 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1253 AssertRC(rc);
1254 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1255 AssertRC(rc);
1256 }
1257 else
1258 {
1259 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1260 }
1261
1262#ifdef DEBUG
1263 /* Intercept X86_XCPT_DB if stepping is enabled */
1264 if (DBGFIsStepping(pVM))
1265 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_DB);
1266 else
1267 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_DB);
1268
1269 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1270#endif
1271
1272#ifdef VBOX_STRICT
1273 Assert(pVM->hwaccm.s.vmx.u32TrapMask & RT_BIT(X86_XCPT_GP));
1274#else
1275# ifdef HWACCM_VMX_EMULATE_REALMODE
1276 /* Intercept #GP faults in real mode to handle privileged instructions. */
1277 if (CPUMIsGuestInRealModeEx(pCtx))
1278 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_GP);
1279 else
1280 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_GP);
1281# endif /* HWACCM_VMX_EMULATE_REALMODE */
1282 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1283 AssertRC(rc);
1284#endif
1285
1286 /* Done. */
1287 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1288
1289 return rc;
1290}
1291
1292/**
1293 * Runs guest code in a VT-x VM.
1294 *
1295 * @returns VBox status code.
1296 * @param pVM The VM to operate on.
1297 * @param pCtx Guest context
1298 */
1299VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1300{
1301 int rc = VINF_SUCCESS;
1302 RTCCUINTREG val, valShadow;
1303 RTCCUINTREG exitReason, instrError, cbInstr;
1304 RTGCUINTPTR exitQualification;
1305 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1306 RTGCUINTPTR errCode, instrInfo, uInterruptState;
1307 bool fSyncTPR = false;
1308 PHWACCM_CPUINFO pCpu = 0;
1309 unsigned cResume = 0;
1310#ifdef VBOX_STRICT
1311 RTCPUID idCpuCheck;
1312#endif
1313
1314 Log2(("\nE"));
1315
1316 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1317
1318#ifdef VBOX_STRICT
1319 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1320 AssertRC(rc);
1321 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1322
1323 /* allowed zero */
1324 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1325 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1326
1327 /* allowed one */
1328 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1329 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1330
1331 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1332 AssertRC(rc);
1333 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1334
1335 /* allowed zero */
1336 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1337 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1338
1339 /* allowed one */
1340 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1341 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1342
1343 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1344 AssertRC(rc);
1345 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1346
1347 /* allowed zero */
1348 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1349 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1350
1351 /* allowed one */
1352 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1353 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1354
1355 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1356 AssertRC(rc);
1357 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1358
1359 /* allowed zero */
1360 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1361 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1362
1363 /* allowed one */
1364 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1365 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1366#endif
1367
1368 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1369 */
1370ResumeExecution:
1371 AssertMsg(pVM->hwaccm.s.idEnteredCpu == RTMpCpuId(),
1372 ("Expected %d, I'm %d; cResume=%d exitReason=%RTreg exitQualification=%RTreg\n",
1373 (int)pVM->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
1374
1375 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1376 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1377 {
1378 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1379 rc = VINF_EM_RAW_INTERRUPT;
1380 goto end;
1381 }
1382
1383 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1384 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1385 {
1386 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1387 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1388 {
1389 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1390 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1391 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1392 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1393 */
1394 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1395 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1396 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1397 AssertRC(rc);
1398 }
1399 }
1400 else
1401 {
1402 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1403 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1404 AssertRC(rc);
1405 }
1406
1407 /* Check for pending actions that force us to go back to ring 3. */
1408 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1409 {
1410 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1411 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1412 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1413 rc = VINF_EM_RAW_TO_R3;
1414 goto end;
1415 }
1416 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1417 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1418 {
1419 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1420 rc = VINF_EM_PENDING_REQUEST;
1421 goto end;
1422 }
1423
1424 /* When external interrupts are pending, we should exit the VM when IF is set. */
1425 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1426 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1427 if (VBOX_FAILURE(rc))
1428 {
1429 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1430 goto end;
1431 }
1432
1433 /** @todo check timers?? */
1434
1435 /* TPR caching using CR8 is only available in 64 bits mode */
1436 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1437 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1438 /**
1439 * @todo reduce overhead
1440 */
1441 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1442 && pVM->hwaccm.s.vmx.pAPIC)
1443 {
1444 /* TPR caching in CR8 */
1445 uint8_t u8TPR;
1446 bool fPending;
1447
1448 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1449 AssertRC(rc);
1450 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1451 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1452
1453 /* Two options here:
1454 * - external interrupt pending, but masked by the TPR value.
1455 * -> a CR8 update that lower the current TPR value should cause an exit
1456 * - no pending interrupts
1457 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1458 */
1459 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1460 AssertRC(rc);
1461
1462 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
1463 fSyncTPR = true;
1464 }
1465
1466#ifdef LOG_ENABLED
1467 pCpu = HWACCMR0GetCurrentCpu();
1468 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1469 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1470 {
1471 if (pVM->hwaccm.s.idLastCpu != pCpu->idCpu)
1472 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.idLastCpu, pCpu->idCpu));
1473 else
1474 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1475 }
1476 if (pCpu->fFlushTLB)
1477 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1478#endif
1479
1480 /*
1481 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1482 * (until the actual world switch)
1483 */
1484#ifdef VBOX_STRICT
1485 idCpuCheck = RTMpCpuId();
1486#endif
1487 /* Save the host state first. */
1488 rc = VMXR0SaveHostState(pVM);
1489 if (rc != VINF_SUCCESS)
1490 {
1491 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1492 goto end;
1493 }
1494 /* Load the guest state */
1495 rc = VMXR0LoadGuestState(pVM, pCtx);
1496 if (rc != VINF_SUCCESS)
1497 {
1498 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1499 goto end;
1500 }
1501
1502 /* Deal with tagged TLBs if VPID is supported. */
1503 if (pVM->hwaccm.s.vmx.fVPID)
1504 {
1505 pCpu = HWACCMR0GetCurrentCpu();
1506 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1507 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1508 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1509 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1510 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1511 {
1512 /* Force a TLB flush on VM entry. */
1513 pVM->hwaccm.s.fForceTLBFlush = true;
1514 }
1515 else
1516 Assert(!pCpu->fFlushTLB);
1517
1518 pVM->hwaccm.s.idLastCpu = pCpu->idCpu;
1519
1520 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1521 if (pVM->hwaccm.s.fForceTLBFlush)
1522 {
1523 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1524 || pCpu->fFlushTLB)
1525 {
1526 pCpu->fFlushTLB = false;
1527 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1528 pCpu->cTLBFlushes++;
1529 }
1530 else
1531 {
1532 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
1533 pVM->hwaccm.s.fForceTLBFlush = false;
1534 }
1535
1536 pVM->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1537 pVM->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1538 }
1539 else
1540 {
1541 Assert(!pCpu->fFlushTLB);
1542
1543 if (!pCpu->uCurrentASID || !pVM->hwaccm.s.uCurrentASID)
1544 pVM->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1545 }
1546 AssertMsg(pVM->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1547 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1548 AssertMsg(pVM->hwaccm.s.uCurrentASID >= 1 && pVM->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVM->hwaccm.s.uCurrentASID));
1549
1550 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_VPID, pVM->hwaccm.s.uCurrentASID);
1551 AssertRC(rc);
1552
1553 if (pVM->hwaccm.s.fForceTLBFlush)
1554 {
1555
1556 }
1557
1558#ifdef VBOX_WITH_STATISTICS
1559 if (pVM->hwaccm.s.fForceTLBFlush)
1560 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
1561 else
1562 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
1563#endif
1564
1565 }
1566
1567 /* Non-register state Guest Context */
1568 /** @todo change me according to cpu state */
1569 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1570 AssertRC(rc);
1571
1572 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1573
1574 /* Manual save and restore:
1575 * - General purpose registers except RIP, RSP
1576 *
1577 * Trashed:
1578 * - CR2 (we don't care)
1579 * - LDTR (reset to 0)
1580 * - DRx (presumably not changed at all)
1581 * - DR7 (reset to 0x400)
1582 * - EFLAGS (reset to RT_BIT(1); not relevant)
1583 *
1584 */
1585
1586 /* All done! Let's start VM execution. */
1587 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1588#ifdef VBOX_STRICT
1589 Assert(idCpuCheck == RTMpCpuId());
1590#endif
1591 TMNotifyStartOfExecution(pVM);
1592 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1593 TMNotifyEndOfExecution(pVM);
1594
1595 /* In case we execute a goto ResumeExecution later on. */
1596 pVM->hwaccm.s.vmx.fResumeVM = true;
1597 pVM->hwaccm.s.fForceTLBFlush = false;
1598
1599 /*
1600 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1601 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1602 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1603 */
1604
1605 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1606 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1607
1608 switch (rc)
1609 {
1610 case VINF_SUCCESS:
1611 break;
1612
1613 case VERR_VMX_INVALID_VMXON_PTR:
1614 AssertFailed();
1615 goto end;
1616
1617 case VERR_VMX_UNABLE_TO_START_VM:
1618 case VERR_VMX_UNABLE_TO_RESUME_VM:
1619 {
1620#ifdef VBOX_STRICT
1621 int rc1;
1622
1623 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1624 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1625 AssertRC(rc1);
1626 if (rc1 == VINF_SUCCESS)
1627 {
1628 RTGDTR gdtr;
1629 PX86DESCHC pDesc;
1630
1631 ASMGetGDTR(&gdtr);
1632
1633 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1634 Log(("Current stack %08x\n", &rc1));
1635
1636
1637 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1638 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1639 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1640 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1641 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1642 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1643 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1644 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1645 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1646 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1647
1648 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1649 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1650
1651 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1652 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1653
1654 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1655 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1656
1657 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1658 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1659
1660 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1661 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
1662
1663 if (val < gdtr.cbGdt)
1664 {
1665 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1666 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1667 }
1668
1669 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1670 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1671 if (val < gdtr.cbGdt)
1672 {
1673 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1674 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1675 }
1676
1677 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1678 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1679 if (val < gdtr.cbGdt)
1680 {
1681 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1682 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1683 }
1684
1685 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1686 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1687 if (val < gdtr.cbGdt)
1688 {
1689 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1690 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1691 }
1692
1693 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1694 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1695 if (val < gdtr.cbGdt)
1696 {
1697 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1698 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1699 }
1700
1701 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1702 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1703 if (val < gdtr.cbGdt)
1704 {
1705 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1706 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1707 }
1708
1709 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1710 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1711 if (val < gdtr.cbGdt)
1712 {
1713 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1714 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1715 }
1716
1717 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1718 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1719
1720 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1721 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1722 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1723 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1724
1725 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1726 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1727
1728 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1729 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1730
1731 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1732 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1733
1734 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1735 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1736 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1737 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1738
1739#if HC_ARCH_BITS == 64
1740 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1741 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1742 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1743 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1744 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1745#endif
1746 }
1747#endif /* VBOX_STRICT */
1748 goto end;
1749 }
1750
1751 default:
1752 /* impossible */
1753 AssertFailed();
1754 goto end;
1755 }
1756 /* Success. Query the guest state and figure out what has happened. */
1757
1758 /* Investigate why there was a VM-exit. */
1759 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1760 STAM_COUNTER_INC(&pVM->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1761
1762 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1763 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1764 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1765 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1766 intInfo = val;
1767 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1768 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1769 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1770 instrInfo = val;
1771 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1772 exitQualification = val;
1773 AssertRC(rc);
1774
1775 /* Let's first sync back eip, esp, and eflags. */
1776 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1777 AssertRC(rc);
1778 pCtx->rip = val;
1779 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1780 AssertRC(rc);
1781 pCtx->rsp = val;
1782 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1783 AssertRC(rc);
1784 pCtx->eflags.u32 = val;
1785
1786 /* Take care of instruction fusing (sti, mov ss) */
1787 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1788 uInterruptState = val;
1789 if (uInterruptState != 0)
1790 {
1791 Assert(uInterruptState <= 2); /* only sti & mov ss */
1792 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1793 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1794 }
1795 else
1796 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1797
1798 /* Control registers. */
1799 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1800 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1801 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1802 CPUMSetGuestCR0(pVM, val);
1803
1804 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1805 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1806 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1807 CPUMSetGuestCR4(pVM, val);
1808
1809 /* Can be updated behind our back in the nested paging case. */
1810 CPUMSetGuestCR2(pVM, ASMGetCR2());
1811
1812 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1813 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1814 if (pVM->hwaccm.s.fNestedPaging)
1815 {
1816 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
1817
1818 if (val != pCtx->cr3)
1819 {
1820 CPUMSetGuestCR3(pVM, val);
1821 PGMUpdateCR3(pVM, val);
1822 }
1823 }
1824
1825 /* Sync back DR7 here. */
1826 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1827 pCtx->dr[7] = val;
1828
1829 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1830 VMX_READ_SELREG(ES, es);
1831 VMX_READ_SELREG(SS, ss);
1832 VMX_READ_SELREG(CS, cs);
1833 VMX_READ_SELREG(DS, ds);
1834 VMX_READ_SELREG(FS, fs);
1835 VMX_READ_SELREG(GS, gs);
1836
1837 /*
1838 * System MSRs
1839 */
1840 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1841 pCtx->SysEnter.cs = val;
1842 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1843 pCtx->SysEnter.eip = val;
1844 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1845 pCtx->SysEnter.esp = val;
1846
1847 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1848 VMX_READ_SELREG(LDTR, ldtr);
1849
1850 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1851 pCtx->gdtr.cbGdt = val;
1852 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1853 pCtx->gdtr.pGdt = val;
1854
1855 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1856 pCtx->idtr.cbIdt = val;
1857 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1858 pCtx->idtr.pIdt = val;
1859
1860#ifdef HWACCM_VMX_EMULATE_REALMODE
1861 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1862 if (CPUMIsGuestInRealModeEx(pCtx))
1863 {
1864 /* Hide our emulation flags */
1865 pCtx->eflags.Bits.u1VM = 0;
1866 pCtx->eflags.Bits.u2IOPL = 0;
1867
1868 /* Force a TR resync every time in case we switch modes. */
1869 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1870 }
1871 else
1872#endif /* HWACCM_VMX_EMULATE_REALMODE */
1873 {
1874 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1875 VMX_READ_SELREG(TR, tr);
1876 }
1877
1878 /* Note! NOW IT'S SAFE FOR LOGGING! */
1879 Log2(("Raw exit reason %08x\n", exitReason));
1880
1881 /* Check if an injected event was interrupted prematurely. */
1882 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1883 AssertRC(rc);
1884#ifdef HWACCM_VMX_EMULATE_REALMODE
1885 /* For some reason injected software interrupts are ignored (not signalled as pending) when e.g. a shadow page fault occurs. */
1886 if ( CPUMIsGuestInRealModeEx(pCtx)
1887 && pVM->hwaccm.s.vmx.RealMode.eip == pCtx->eip
1888 && pVM->hwaccm.s.vmx.RealMode.Event.fPending)
1889 {
1890 Assert(!VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo));
1891
1892 Log(("Pending real-mode inject %VX64 at %VGv\n", pVM->hwaccm.s.vmx.RealMode.Event.intInfo, pCtx->rip));
1893
1894 /* We faked an 'int x' instruction and messed with IP, so correct it here. */
1895 pCtx->rip++;
1896 pVM->hwaccm.s.Event.intInfo = pVM->hwaccm.s.vmx.RealMode.Event.intInfo;
1897 pVM->hwaccm.s.Event.fPending = true;
1898 }
1899 else
1900#endif /* HWACCM_VMX_EMULATE_REALMODE */
1901 {
1902 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1903 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1904 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1905 {
1906 pVM->hwaccm.s.Event.fPending = true;
1907 /* Error code present? */
1908 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1909 {
1910 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1911 AssertRC(rc);
1912 pVM->hwaccm.s.Event.errCode = val;
1913 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1914 }
1915 else
1916 {
1917 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1918 pVM->hwaccm.s.Event.errCode = 0;
1919 }
1920 }
1921 }
1922 pVM->hwaccm.s.vmx.RealMode.Event.fPending = false;
1923
1924#ifdef VBOX_STRICT
1925 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1926 HWACCMDumpRegs(pVM, pCtx);
1927#endif
1928
1929 Log2(("E%d", exitReason));
1930 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1931 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1932 Log2(("Interruption error code %d\n", errCode));
1933 Log2(("IntInfo = %08x\n", intInfo));
1934 Log2(("New EIP=%VGv\n", pCtx->rip));
1935
1936 if (fSyncTPR)
1937 {
1938 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1939 AssertRC(rc);
1940 }
1941
1942 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1943 switch (exitReason)
1944 {
1945 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1946 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1947 {
1948 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1949
1950 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1951 {
1952 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1953 /* External interrupt; leave to allow it to be dispatched again. */
1954 rc = VINF_EM_RAW_INTERRUPT;
1955 break;
1956 }
1957 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1958 {
1959 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1960 /* External interrupt; leave to allow it to be dispatched again. */
1961 rc = VINF_EM_RAW_INTERRUPT;
1962 break;
1963
1964 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1965 AssertFailed(); /* can't come here; fails the first check. */
1966 break;
1967
1968 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1969 Assert(vector == 3 || vector == 4);
1970 /* no break */
1971 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1972 Log2(("Hardware/software interrupt %d\n", vector));
1973 switch (vector)
1974 {
1975 case X86_XCPT_NM:
1976 {
1977 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1978
1979 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1980 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1981 rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1982 if (rc == VINF_SUCCESS)
1983 {
1984 Assert(CPUMIsGuestFPUStateActive(pVM));
1985
1986 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1987
1988 /* Continue execution. */
1989 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1990 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1991
1992 goto ResumeExecution;
1993 }
1994
1995 Log(("Forward #NM fault to the guest\n"));
1996 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1997 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1998 AssertRC(rc);
1999 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2000 goto ResumeExecution;
2001 }
2002
2003 case X86_XCPT_PF: /* Page fault */
2004 {
2005#ifdef DEBUG
2006 if (pVM->hwaccm.s.fNestedPaging)
2007 { /* A genuine pagefault.
2008 * Forward the trap to the guest by injecting the exception and resuming execution.
2009 */
2010 Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2011
2012 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
2013 /* The error code might have been changed. */
2014 errCode = TRPMGetErrorCode(pVM);
2015
2016 TRPMResetTrap(pVM);
2017
2018 /* Now we must update CR2. */
2019 pCtx->cr2 = exitQualification;
2020 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2021 AssertRC(rc);
2022
2023 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2024 goto ResumeExecution;
2025 }
2026#endif
2027 Assert(!pVM->hwaccm.s.fNestedPaging);
2028
2029 Log2(("Page fault at %VGv error code %x\n", exitQualification, errCode));
2030 /* Exit qualification contains the linear address of the page fault. */
2031 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2032 TRPMSetErrorCode(pVM, errCode);
2033 TRPMSetFaultAddress(pVM, exitQualification);
2034
2035 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2036 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2037 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
2038 if (rc == VINF_SUCCESS)
2039 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2040 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
2041 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
2042
2043 TRPMResetTrap(pVM);
2044
2045 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2046 goto ResumeExecution;
2047 }
2048 else
2049 if (rc == VINF_EM_RAW_GUEST_TRAP)
2050 { /* A genuine pagefault.
2051 * Forward the trap to the guest by injecting the exception and resuming execution.
2052 */
2053 Log2(("Forward page fault to the guest\n"));
2054
2055 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
2056 /* The error code might have been changed. */
2057 errCode = TRPMGetErrorCode(pVM);
2058
2059 TRPMResetTrap(pVM);
2060
2061 /* Now we must update CR2. */
2062 pCtx->cr2 = exitQualification;
2063 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2064 AssertRC(rc);
2065
2066 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2067 goto ResumeExecution;
2068 }
2069#ifdef VBOX_STRICT
2070 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2071 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2072#endif
2073 /* Need to go back to the recompiler to emulate the instruction. */
2074 TRPMResetTrap(pVM);
2075 break;
2076 }
2077
2078 case X86_XCPT_MF: /* Floating point exception. */
2079 {
2080 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
2081 if (!(pCtx->cr0 & X86_CR0_NE))
2082 {
2083 /* old style FPU error reporting needs some extra work. */
2084 /** @todo don't fall back to the recompiler, but do it manually. */
2085 rc = VINF_EM_RAW_EMULATE_INSTR;
2086 break;
2087 }
2088 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
2089 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2090 AssertRC(rc);
2091
2092 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2093 goto ResumeExecution;
2094 }
2095
2096 case X86_XCPT_DB: /* Debug exception. */
2097 {
2098 uint64_t uDR6;
2099
2100 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2101 *
2102 * Exit qualification bits:
2103 * 3:0 B0-B3 which breakpoint condition was met
2104 * 12:4 Reserved (0)
2105 * 13 BD - debug register access detected
2106 * 14 BS - single step execution or branch taken
2107 * 63:15 Reserved (0)
2108 */
2109 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDB);
2110
2111 /* Note that we don't support guest and host-initiated debugging at the same time. */
2112 Assert(DBGFIsStepping(pVM));
2113
2114 uDR6 = X86_DR6_INIT_VAL;
2115 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2116 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
2117 if (rc == VINF_EM_RAW_GUEST_TRAP)
2118 {
2119 /** @todo this isn't working, but we'll never get here normally. */
2120
2121 /* Update DR6 here. */
2122 pCtx->dr[6] = uDR6;
2123
2124 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2125 pCtx->dr[7] &= ~X86_DR7_GD;
2126
2127 /* Paranoia. */
2128 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2129 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2130 pCtx->dr[7] |= 0x400; /* must be one */
2131
2132 /* Resync DR7 */
2133 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2134 AssertRC(rc);
2135
2136 Log(("Trap %x (debug) at %VGv exit qualification %VX64\n", vector, pCtx->rip, exitQualification));
2137 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2138 AssertRC(rc);
2139
2140 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2141 goto ResumeExecution;
2142 }
2143 /* Return to ring 3 to deal with the debug exit code. */
2144 break;
2145 }
2146
2147 case X86_XCPT_GP: /* General protection failure exception.*/
2148 {
2149 uint32_t cbSize;
2150
2151 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
2152#ifdef VBOX_STRICT
2153 if (!CPUMIsGuestInRealModeEx(pCtx))
2154 {
2155 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
2156 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2157 AssertRC(rc);
2158 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2159 goto ResumeExecution;
2160 }
2161#endif
2162 Assert(CPUMIsGuestInRealModeEx(pCtx));
2163
2164 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %VGv\n", pCtx->rip));
2165 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2166 if (rc == VINF_SUCCESS)
2167 {
2168 /* EIP has been updated already. */
2169
2170 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2171 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2172
2173 /* Only resume if successful. */
2174 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2175 goto ResumeExecution;
2176 }
2177 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Vrc\n", rc));
2178 break;
2179 }
2180
2181#ifdef VBOX_STRICT
2182 case X86_XCPT_DE: /* Divide error. */
2183 case X86_XCPT_UD: /* Unknown opcode exception. */
2184 case X86_XCPT_SS: /* Stack segment exception. */
2185 case X86_XCPT_NP: /* Segment not present exception. */
2186 {
2187 switch(vector)
2188 {
2189 case X86_XCPT_DE:
2190 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
2191 break;
2192 case X86_XCPT_UD:
2193 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
2194 break;
2195 case X86_XCPT_SS:
2196 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
2197 break;
2198 case X86_XCPT_NP:
2199 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
2200 break;
2201 }
2202
2203 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
2204 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2205 AssertRC(rc);
2206
2207 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2208 goto ResumeExecution;
2209 }
2210#endif
2211 default:
2212 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2213 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2214 break;
2215 } /* switch (vector) */
2216
2217 break;
2218
2219 default:
2220 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2221 AssertFailed();
2222 break;
2223 }
2224
2225 break;
2226 }
2227
2228 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2229 {
2230 Log2(("EPT Page fault at %VGv error code %x\n", exitQualification ,errCode));
2231 Assert(pVM->hwaccm.s.fNestedPaging);
2232
2233 /* Exit qualification contains the linear address of the page fault. */
2234 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2235 TRPMSetErrorCode(pVM, errCode);
2236 TRPMSetFaultAddress(pVM, exitQualification );
2237
2238 /* Handle the pagefault trap for the nested shadow table. */
2239 rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), exitQualification );
2240 Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
2241 if (rc == VINF_SUCCESS)
2242 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2243 Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, exitQualification , errCode));
2244 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
2245
2246 TRPMResetTrap(pVM);
2247
2248 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2249 goto ResumeExecution;
2250 }
2251
2252#ifdef VBOX_STRICT
2253 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2254 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2255#endif
2256 /* Need to go back to the recompiler to emulate the instruction. */
2257 TRPMResetTrap(pVM);
2258 break;
2259 }
2260
2261 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2262 /* Clear VM-exit on IF=1 change. */
2263 LogFlow(("VMX_EXIT_IRQ_WINDOW %VGv pending=%d IF=%d\n", pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2264 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2265 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2266 AssertRC(rc);
2267 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
2268 goto ResumeExecution; /* we check for pending guest interrupts there */
2269
2270 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2271 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2272 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
2273 /* Skip instruction and continue directly. */
2274 pCtx->rip += cbInstr;
2275 /* Continue execution.*/
2276 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2277 goto ResumeExecution;
2278
2279 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2280 {
2281 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2282 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
2283 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
2284 if (rc == VINF_SUCCESS)
2285 {
2286 /* Update EIP and continue execution. */
2287 Assert(cbInstr == 2);
2288 pCtx->rip += cbInstr;
2289 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2290 goto ResumeExecution;
2291 }
2292 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
2293 rc = VINF_EM_RAW_EMULATE_INSTR;
2294 break;
2295 }
2296
2297 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2298 {
2299 Log2(("VMX: Rdtsc\n"));
2300 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
2301 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
2302 if (rc == VINF_SUCCESS)
2303 {
2304 /* Update EIP and continue execution. */
2305 Assert(cbInstr == 2);
2306 pCtx->rip += cbInstr;
2307 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2308 goto ResumeExecution;
2309 }
2310 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
2311 rc = VINF_EM_RAW_EMULATE_INSTR;
2312 break;
2313 }
2314
2315 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2316 {
2317 Log2(("VMX: invlpg\n"));
2318 Assert(!pVM->hwaccm.s.fNestedPaging);
2319
2320 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
2321 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
2322 if (rc == VINF_SUCCESS)
2323 {
2324 /* Update EIP and continue execution. */
2325 pCtx->rip += cbInstr;
2326 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2327 goto ResumeExecution;
2328 }
2329 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
2330 break;
2331 }
2332
2333 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2334 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2335 {
2336 uint32_t cbSize;
2337
2338 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2339 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
2340 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2341 if (rc == VINF_SUCCESS)
2342 {
2343 /* EIP has been updated already. */
2344
2345 /* Only resume if successful. */
2346 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2347 goto ResumeExecution;
2348 }
2349 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
2350 break;
2351 }
2352
2353 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2354 {
2355 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
2356 {
2357 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
2358 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
2359 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
2360 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
2361 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
2362 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
2363
2364 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
2365 {
2366 case 0:
2367 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2368 break;
2369 case 2:
2370 break;
2371 case 3:
2372 Assert(!pVM->hwaccm.s.fNestedPaging || !(pCtx->cr0 & X86_CR0_PG));
2373 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2374 break;
2375 case 4:
2376 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2377 break;
2378 case 8:
2379 /* CR8 contains the APIC TPR */
2380 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2381 break;
2382
2383 default:
2384 AssertFailed();
2385 break;
2386 }
2387 /* Check if a sync operation is pending. */
2388 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2389 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2390 {
2391 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2392 AssertRC(rc);
2393 }
2394 break;
2395
2396 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
2397 Log2(("VMX: mov x, crx\n"));
2398 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
2399
2400 Assert(!pVM->hwaccm.s.fNestedPaging || !(pCtx->cr0 & X86_CR0_PG) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
2401
2402 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
2403 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2404
2405 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
2406 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
2407 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
2408 break;
2409
2410 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2411 Log2(("VMX: clts\n"));
2412 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
2413 rc = EMInterpretCLTS(pVM);
2414 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2415 break;
2416
2417 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2418 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2419 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
2420 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2421 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2422 break;
2423 }
2424
2425 /* Update EIP if no error occurred. */
2426 if (VBOX_SUCCESS(rc))
2427 pCtx->rip += cbInstr;
2428
2429 if (rc == VINF_SUCCESS)
2430 {
2431 /* Only resume if successful. */
2432 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2433 goto ResumeExecution;
2434 }
2435 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2436 break;
2437 }
2438
2439 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2440 {
2441 if (!DBGFIsStepping(pVM))
2442 {
2443 /* Disable drx move intercepts. */
2444 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2445 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2446 AssertRC(rc);
2447
2448 /* Save the host and load the guest debug state. */
2449 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
2450 AssertRC(rc);
2451
2452#ifdef VBOX_WITH_STATISTICS
2453 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
2454 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2455 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2456 else
2457 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2458#endif
2459
2460 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2461 goto ResumeExecution;
2462 }
2463
2464 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2465 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2466 {
2467 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2468 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2469 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2470 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2471 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2472 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2473 Log2(("DR7=%08x\n", pCtx->dr[7]));
2474 }
2475 else
2476 {
2477 Log2(("VMX: mov x, drx\n"));
2478 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2479 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2480 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2481 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2482 }
2483 /* Update EIP if no error occurred. */
2484 if (VBOX_SUCCESS(rc))
2485 pCtx->rip += cbInstr;
2486
2487 if (rc == VINF_SUCCESS)
2488 {
2489 /* Only resume if successful. */
2490 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2491 goto ResumeExecution;
2492 }
2493 Assert(rc == VERR_EM_INTERPRETER);
2494 break;
2495 }
2496
2497 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2498 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2499 {
2500 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2501 uint32_t uPort;
2502 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2503
2504 /** @todo necessary to make the distinction? */
2505 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2506 {
2507 uPort = pCtx->edx & 0xffff;
2508 }
2509 else
2510 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2511
2512 /* paranoia */
2513 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2514 {
2515 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2516 break;
2517 }
2518
2519 uint32_t cbSize = g_aIOSize[uIOWidth];
2520
2521 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2522 {
2523 /* ins/outs */
2524 uint32_t prefix = 0;
2525 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
2526 prefix |= PREFIX_REP;
2527
2528 if (fIOWrite)
2529 {
2530 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2531 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
2532 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2533 }
2534 else
2535 {
2536 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2537 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
2538 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2539 }
2540 }
2541 else
2542 {
2543 /* normal in/out */
2544 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
2545
2546 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2547
2548 if (fIOWrite)
2549 {
2550 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2551 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2552 }
2553 else
2554 {
2555 uint32_t u32Val = 0;
2556
2557 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2558 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2559 if (IOM_SUCCESS(rc))
2560 {
2561 /* Write back to the EAX register. */
2562 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2563 }
2564 }
2565 }
2566 /*
2567 * Handled the I/O return codes.
2568 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2569 */
2570 if (IOM_SUCCESS(rc))
2571 {
2572 /* Update EIP and continue execution. */
2573 pCtx->rip += cbInstr;
2574 if (RT_LIKELY(rc == VINF_SUCCESS))
2575 {
2576 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2577 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2578 {
2579 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxIOCheck);
2580 for (unsigned i=0;i<4;i++)
2581 {
2582 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2583
2584 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
2585 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2586 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2587 {
2588 uint64_t uDR6;
2589
2590 Assert(CPUMIsGuestDebugStateActive(pVM));
2591
2592 uDR6 = ASMGetDR6();
2593
2594 /* Clear all breakpoint status flags and set the one we just hit. */
2595 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2596 uDR6 |= RT_BIT(i);
2597
2598 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2599 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2600 * the contents have been read.
2601 */
2602 ASMSetDR6(uDR6);
2603
2604 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2605 pCtx->dr[7] &= ~X86_DR7_GD;
2606
2607 /* Paranoia. */
2608 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2609 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2610 pCtx->dr[7] |= 0x400; /* must be one */
2611
2612 /* Resync DR7 */
2613 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2614 AssertRC(rc);
2615
2616 /* Construct inject info. */
2617 intInfo = X86_XCPT_DB;
2618 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2619 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2620
2621 Log(("Inject IO debug trap at %VGv\n", pCtx->rip));
2622 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
2623 AssertRC(rc);
2624
2625 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2626 goto ResumeExecution;
2627 }
2628 }
2629 }
2630
2631 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2632 goto ResumeExecution;
2633 }
2634 break;
2635 }
2636
2637#ifdef VBOX_STRICT
2638 if (rc == VINF_IOM_HC_IOPORT_READ)
2639 Assert(!fIOWrite);
2640 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2641 Assert(fIOWrite);
2642 else
2643 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2644#endif
2645 break;
2646 }
2647
2648 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2649 LogFlow(("VMX_EXIT_TPR\n"));
2650 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2651 goto ResumeExecution;
2652
2653 default:
2654 /* The rest is handled after syncing the entire CPU state. */
2655 break;
2656 }
2657
2658 /* Note: the guest state isn't entirely synced back at this stage. */
2659
2660 /* Investigate why there was a VM-exit. (part 2) */
2661 switch (exitReason)
2662 {
2663 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2664 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2665 /* Already handled above. */
2666 break;
2667
2668 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2669 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2670 break;
2671
2672 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2673 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2674 rc = VINF_EM_RAW_INTERRUPT;
2675 AssertFailed(); /* Can't happen. Yet. */
2676 break;
2677
2678 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2679 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2680 rc = VINF_EM_RAW_INTERRUPT;
2681 AssertFailed(); /* Can't happen afaik. */
2682 break;
2683
2684 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2685 rc = VERR_EM_INTERPRETER;
2686 break;
2687
2688 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2689 /** Check if external interrupts are pending; if so, don't switch back. */
2690 pCtx->rip++; /* skip hlt */
2691 if ( pCtx->eflags.Bits.u1IF
2692 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2693 goto ResumeExecution;
2694
2695 rc = VINF_EM_HALT;
2696 break;
2697
2698 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2699 AssertFailed(); /* can't happen. */
2700 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2701 break;
2702
2703 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2704 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2705 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2706 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2707 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2708 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2709 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2710 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2711 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2712 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2713 /** @todo inject #UD immediately */
2714 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2715 break;
2716
2717 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2718 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2719 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2720 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2721 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2722 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2723 /* already handled above */
2724 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2725 || rc == VINF_EM_RAW_INTERRUPT
2726 || rc == VERR_EM_INTERPRETER
2727 || rc == VINF_EM_RAW_EMULATE_INSTR
2728 || rc == VINF_PGM_SYNC_CR3
2729 || rc == VINF_IOM_HC_IOPORT_READ
2730 || rc == VINF_IOM_HC_IOPORT_WRITE
2731 || rc == VINF_EM_RAW_GUEST_TRAP
2732 || rc == VINF_TRPM_XCPT_DISPATCHED
2733 || rc == VINF_EM_RESCHEDULE_REM,
2734 ("rc = %d\n", rc));
2735 break;
2736
2737 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2738 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2739 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2740 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2741 rc = VERR_EM_INTERPRETER;
2742 break;
2743
2744 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2745 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2746 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2747 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2748 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2749 break;
2750
2751 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2752 Assert(rc == VINF_EM_RAW_INTERRUPT);
2753 break;
2754
2755 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2756 {
2757#ifdef VBOX_STRICT
2758 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2759
2760 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2761 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2762
2763 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2764 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2765
2766 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2767 Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2768
2769 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2770 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2771
2772 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
2773 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
2774
2775 VMX_LOG_SELREG(CS, "CS");
2776 VMX_LOG_SELREG(DS, "DS");
2777 VMX_LOG_SELREG(ES, "ES");
2778 VMX_LOG_SELREG(FS, "FS");
2779 VMX_LOG_SELREG(GS, "GS");
2780 VMX_LOG_SELREG(SS, "SS");
2781 VMX_LOG_SELREG(TR, "TR");
2782 VMX_LOG_SELREG(LDTR, "LDTR");
2783
2784 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2785 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2786 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2787 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2788#endif /* VBOX_STRICT */
2789 rc = VERR_VMX_INVALID_GUEST_STATE;
2790 break;
2791 }
2792
2793 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2794 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2795 default:
2796 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
2797 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2798 break;
2799
2800 }
2801end:
2802
2803 /* Signal changes for the recompiler. */
2804 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2805
2806 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2807 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2808 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2809 {
2810 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2811 /* On the next entry we'll only sync the host context. */
2812 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2813 }
2814 else
2815 {
2816 /* On the next entry we'll sync everything. */
2817 /** @todo we can do better than this */
2818 /* Not in the VINF_PGM_CHANGE_MODE though! */
2819 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2820 }
2821
2822 /* translate into a less severe return code */
2823 if (rc == VERR_EM_INTERPRETER)
2824 rc = VINF_EM_RAW_EMULATE_INSTR;
2825 else
2826 /* Try to extract more information about what might have gone wrong here. */
2827 if (rc == VERR_VMX_INVALID_VMCS_PTR)
2828 {
2829 VMXGetActivateVMCS(&pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys);
2830 pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS;
2831 }
2832
2833 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2834
2835 Log2(("X"));
2836 return rc;
2837}
2838
2839
2840/**
2841 * Enters the VT-x session
2842 *
2843 * @returns VBox status code.
2844 * @param pVM The VM to operate on.
2845 * @param pCpu CPU info struct
2846 */
2847VMMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2848{
2849 Assert(pVM->hwaccm.s.vmx.fSupported);
2850
2851 unsigned cr4 = ASMGetCR4();
2852 if (!(cr4 & X86_CR4_VMXE))
2853 {
2854 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2855 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2856 }
2857
2858 /* Activate the VM Control Structure. */
2859 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2860 if (VBOX_FAILURE(rc))
2861 return rc;
2862
2863 pVM->hwaccm.s.vmx.fResumeVM = false;
2864 return VINF_SUCCESS;
2865}
2866
2867
2868/**
2869 * Leaves the VT-x session
2870 *
2871 * @returns VBox status code.
2872 * @param pVM The VM to operate on.
2873 * @param pCtx CPU context
2874 */
2875VMMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx)
2876{
2877 Assert(pVM->hwaccm.s.vmx.fSupported);
2878
2879 /* Save the guest debug state if necessary. */
2880 if (CPUMIsGuestDebugStateActive(pVM))
2881 {
2882 CPUMR0SaveGuestDebugState(pVM, pCtx, true /* save DR6 */);
2883
2884 /* Enable drx move intercepts again. */
2885 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2886 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2887 AssertRC(rc);
2888
2889 /* Resync the debug registers the next time. */
2890 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2891 }
2892 else
2893 Assert(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
2894
2895 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2896 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2897 AssertRC(rc);
2898
2899 return VINF_SUCCESS;
2900}
2901
2902/**
2903 * Invalidates a guest page
2904 *
2905 * @returns VBox status code.
2906 * @param pVM The VM to operate on.
2907 * @param GCVirt Page to invalidate
2908 */
2909VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
2910{
2911 bool fFlushPending = pVM->hwaccm.s.fForceTLBFlush;
2912
2913 /* @todo Only relevant if we want to use VPID. */
2914
2915 /* Skip it if a TLB flush is already pending. */
2916 if (!fFlushPending)
2917 {
2918 }
2919 return VINF_SUCCESS;
2920}
2921
2922/**
2923 * Invalidates a guest page by physical address
2924 *
2925 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
2926 *
2927 * @returns VBox status code.
2928 * @param pVM The VM to operate on.
2929 * @param GCPhys Page to invalidate
2930 */
2931VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
2932{
2933 bool fFlushPending = pVM->hwaccm.s.fForceTLBFlush;
2934
2935 Assert(pVM->hwaccm.s.fNestedPaging);
2936
2937 /* Skip it if a TLB flush is already pending. */
2938 if (!fFlushPending)
2939 {
2940 }
2941 return VINF_SUCCESS;
2942}
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