VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 13181

Last change on this file since 13181 was 13181, checked in by vboxsync, 17 years ago

EPT bug fixes
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1/* $Id: HWVMXR0.cpp 13181 2008-10-10 15:48:26Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43/*******************************************************************************
44* Global Variables *
45*******************************************************************************/
46/* IO operation lookup arrays. */
47static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
48static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
49
50/*******************************************************************************
51* Local Functions *
52*******************************************************************************/
53#ifdef VBOX_STRICT
54static void VMXR0ReportWorldSwitchError(PVM pVM, int rc, PCPUMCTX pCtx);
55#else
56#define VMXR0ReportWorldSwitchError(a, b, c) do { } while (0);
57#endif /* VBOX_STRICT */
58static void VMXR0SetupTLBEPT(PVM pVM);
59static void VMXR0SetupTLBVPID(PVM pVM);
60static void VMXR0SetupTLBDummy(PVM pVM);
61static void VMXR0FlushEPT(PVM pVM, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
62static void VMXR0FlushVPID(PVM pVM, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
63
64
65static void VMXR0CheckError(PVM pVM, int rc)
66{
67 if (rc == VERR_VMX_GENERIC)
68 {
69 RTCCUINTREG instrError;
70
71 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
72 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
73 }
74 pVM->hwaccm.s.lLastError = rc;
75}
76
77/**
78 * Sets up and activates VT-x on the current CPU
79 *
80 * @returns VBox status code.
81 * @param pCpu CPU info struct
82 * @param pVM The VM to operate on.
83 * @param pvPageCpu Pointer to the global cpu page
84 * @param pPageCpuPhys Physical address of the global cpu page
85 */
86VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
87{
88 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
89 AssertReturn(pVM, VERR_INVALID_PARAMETER);
90 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
91
92 /* Setup Intel VMX. */
93 Assert(pVM->hwaccm.s.vmx.fSupported);
94
95#ifdef LOG_ENABLED
96 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
97#endif
98 /* Set revision dword at the beginning of the VMXON structure. */
99 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
100
101 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
102 * (which can have very bad consequences!!!)
103 */
104
105 /* Make sure the VMX instructions don't cause #UD faults. */
106 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
107
108 /* Enter VMX Root Mode */
109 int rc = VMXEnable(pPageCpuPhys);
110 if (VBOX_FAILURE(rc))
111 {
112 VMXR0CheckError(pVM, rc);
113 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
114 return VERR_VMX_VMXON_FAILED;
115 }
116 return VINF_SUCCESS;
117}
118
119/**
120 * Deactivates VT-x on the current CPU
121 *
122 * @returns VBox status code.
123 * @param pCpu CPU info struct
124 * @param pvPageCpu Pointer to the global cpu page
125 * @param pPageCpuPhys Physical address of the global cpu page
126 */
127VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
128{
129 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
130 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
131
132 /* Leave VMX Root Mode. */
133 VMXDisable();
134
135 /* And clear the X86_CR4_VMXE bit */
136 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
137
138#ifdef LOG_ENABLED
139 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
140#endif
141 return VINF_SUCCESS;
142}
143
144/**
145 * Does Ring-0 per VM VT-x init.
146 *
147 * @returns VBox status code.
148 * @param pVM The VM to operate on.
149 */
150VMMR0DECL(int) VMXR0InitVM(PVM pVM)
151{
152 int rc;
153
154#ifdef LOG_ENABLED
155 SUPR0Printf("VMXR0InitVM %x\n", pVM);
156#endif
157 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
158 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
159
160
161 /* Allocate one page for the VM control structure (VMCS). */
162 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
163 AssertRC(rc);
164 if (RT_FAILURE(rc))
165 return rc;
166
167 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
168 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
169 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
170
171 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
172 {
173 /* Allocate one page for the virtual APIC mmio cache. */
174 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
175 AssertRC(rc);
176 if (RT_FAILURE(rc))
177 return rc;
178
179 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
180 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
181 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
182 }
183 else
184 {
185 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
186 pVM->hwaccm.s.vmx.pAPIC = 0;
187 pVM->hwaccm.s.vmx.pAPICPhys = 0;
188 }
189
190 /* Allocate the MSR bitmap if this feature is supported. */
191 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
192 {
193 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
194 AssertRC(rc);
195 if (RT_FAILURE(rc))
196 return rc;
197
198 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
199 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
200 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
201 }
202
203 /* Current guest paging mode. */
204 pVM->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
205
206#ifdef LOG_ENABLED
207 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys);
208#endif
209 return VINF_SUCCESS;
210}
211
212/**
213 * Does Ring-0 per VM VT-x termination.
214 *
215 * @returns VBox status code.
216 * @param pVM The VM to operate on.
217 */
218VMMR0DECL(int) VMXR0TermVM(PVM pVM)
219{
220 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
221 {
222 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
223 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
224 pVM->hwaccm.s.vmx.pVMCS = 0;
225 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
226 }
227 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
228 {
229 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
230 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
231 pVM->hwaccm.s.vmx.pAPIC = 0;
232 pVM->hwaccm.s.vmx.pAPICPhys = 0;
233 }
234 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
235 {
236 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
237 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
238 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
239 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
240 }
241 return VINF_SUCCESS;
242}
243
244/**
245 * Sets up VT-x for the specified VM
246 *
247 * @returns VBox status code.
248 * @param pVM The VM to operate on.
249 */
250VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
251{
252 int rc = VINF_SUCCESS;
253 uint32_t val;
254
255 AssertReturn(pVM, VERR_INVALID_PARAMETER);
256 Assert(pVM->hwaccm.s.vmx.pVMCS);
257
258 /* Set revision dword at the beginning of the VMCS structure. */
259 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
260
261 /* Clear VM Control Structure. */
262 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
263 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
264 if (VBOX_FAILURE(rc))
265 goto vmx_end;
266
267 /* Activate the VM Control Structure. */
268 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
269 if (VBOX_FAILURE(rc))
270 goto vmx_end;
271
272 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
273 * Set required bits to one and zero according to the MSR capabilities.
274 */
275 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
276 /* External and non-maskable interrupts cause VM-exits. */
277 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
278 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
279
280 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
281 AssertRC(rc);
282
283 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
284 * Set required bits to one and zero according to the MSR capabilities.
285 */
286 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
287 /* Program which event cause VM-exits and which features we want to use. */
288 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
289 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
290 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
291 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
292 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
293
294 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
295 if (!pVM->hwaccm.s.fNestedPaging)
296 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
297 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
298 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
299
300 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
301
302#if HC_ARCH_BITS == 64
303 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
304 {
305 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
306 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
307 Assert(pVM->hwaccm.s.vmx.pAPIC);
308 }
309 else
310 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
311 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
312#endif
313
314#ifdef VBOX_WITH_VTX_MSR_BITMAPS
315 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
316 {
317 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
318 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
319 }
320#endif
321
322 /* We will use the secondary control if it's present. */
323 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
324
325 /* Mask away the bits that the CPU doesn't support */
326 /** @todo make sure they don't conflict with the above requirements. */
327 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
328 pVM->hwaccm.s.vmx.proc_ctls = val;
329
330 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
331 AssertRC(rc);
332
333 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
334 {
335 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
336 * Set required bits to one and zero according to the MSR capabilities.
337 */
338 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
339 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
340
341#ifdef HWACCM_VTX_WITH_EPT
342 if (pVM->hwaccm.s.fNestedPaging)
343 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
344#endif /* HWACCM_VTX_WITH_EPT */
345#ifdef HWACCM_VTX_WITH_VPID
346 else
347 if (pVM->hwaccm.s.vmx.fVPID)
348 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
349#endif /* HWACCM_VTX_WITH_VPID */
350
351 /* Mask away the bits that the CPU doesn't support */
352 /** @todo make sure they don't conflict with the above requirements. */
353 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
354
355 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
356 AssertRC(rc);
357 }
358
359 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
360 * Set required bits to one and zero according to the MSR capabilities.
361 */
362 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
363 AssertRC(rc);
364
365 /* VMX_VMCS_CTRL_EXIT_CONTROLS
366 * Set required bits to one and zero according to the MSR capabilities.
367 */
368 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
369
370 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
371 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
372#if HC_ARCH_BITS == 64
373 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
374#else
375 /* else Must be zero when AMD64 is not available. */
376#endif
377 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
378 /* Don't acknowledge external interrupts on VM-exit. */
379 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
380 AssertRC(rc);
381
382 /* Forward all exception except #NM & #PF to the guest.
383 * We always need to check pagefaults since our shadow page table can be out of sync.
384 * And we always lazily sync the FPU & XMM state.
385 */
386
387 /** @todo Possible optimization:
388 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
389 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
390 * registers ourselves of course.
391 *
392 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
393 */
394 pVM->hwaccm.s.vmx.u32TrapMask = HWACCM_VMX_TRAP_MASK;
395#ifndef DEBUG
396 if (pVM->hwaccm.s.fNestedPaging)
397 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
398#endif
399 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
400 AssertRC(rc);
401
402 /* Don't filter page faults; all of them should cause a switch. */
403 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
404 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
405 AssertRC(rc);
406
407 /* Init TSC offset to zero. */
408 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
409#if HC_ARCH_BITS == 32
410 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
411#endif
412 AssertRC(rc);
413
414 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
415#if HC_ARCH_BITS == 32
416 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
417#endif
418 AssertRC(rc);
419
420 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
421#if HC_ARCH_BITS == 32
422 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
423#endif
424 AssertRC(rc);
425
426 /* Set the MSR bitmap address. */
427 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
428 {
429 /* Optional */
430 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
431#if HC_ARCH_BITS == 32
432 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32ULL);
433#endif
434 AssertRC(rc);
435 }
436
437 /* Clear MSR controls. */
438 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
439 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
441#if HC_ARCH_BITS == 32
442 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
443 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
444 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
445#endif
446 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
447 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
448 AssertRC(rc);
449
450 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
451 {
452 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
453 /* Optional */
454 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
455 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
456#if HC_ARCH_BITS == 32
457 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32ULL);
458#endif
459 AssertRC(rc);
460 }
461
462 /* Set link pointer to -1. Not currently used. */
463#if HC_ARCH_BITS == 32
464 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
465 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
466#else
467 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
468#endif
469 AssertRC(rc);
470
471 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
472 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
473 AssertRC(rc);
474
475 /* Choose the right TLB setup function. */
476 if (pVM->hwaccm.s.fNestedPaging)
477 {
478 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = VMXR0SetupTLBEPT;
479
480 /* Default values for flushing. */
481 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
482 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
483
484 /* If the capabilities specify we can do more, then make use of it. */
485 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
486 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
487 else
488 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
489 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
490
491 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
492 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
493 }
494#ifdef HWACCM_VTX_WITH_VPID
495 else
496 if (pVM->hwaccm.s.vmx.fVPID)
497 {
498 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = VMXR0SetupTLBVPID;
499
500 /* Default values for flushing. */
501 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
502 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
503
504 /* If the capabilities specify we can do more, then make use of it. */
505 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
506 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
507 else
508 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
509 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
510
511 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
512 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
513 }
514#endif /* HWACCM_VTX_WITH_VPID */
515 else
516 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = VMXR0SetupTLBDummy;
517
518
519vmx_end:
520 VMXR0CheckError(pVM, rc);
521 return rc;
522}
523
524
525/**
526 * Injects an event (trap or external interrupt)
527 *
528 * @returns VBox status code.
529 * @param pVM The VM to operate on.
530 * @param pCtx CPU Context
531 * @param intInfo VMX interrupt info
532 * @param cbInstr Opcode length of faulting instruction
533 * @param errCode Error code (optional)
534 */
535static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
536{
537 int rc;
538
539#ifdef VBOX_STRICT
540 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
541 if (iGate == 0xE)
542 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
543 else
544 if (iGate < 0x20)
545 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
546 else
547 {
548 LogFlow(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
549 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
550 Assert(pCtx->eflags.u32 & X86_EFL_IF);
551 }
552#endif
553
554#ifdef HWACCM_VMX_EMULATE_REALMODE
555 if (CPUMIsGuestInRealModeEx(pCtx))
556 {
557 /* Injecting events doesn't work right with real mode emulation.
558 * (#GP if we try to inject external hardware interrupts)
559 * Fake an 'int x' instruction. Note that we need to take special precautions when
560 * the inject is interrupted as the normal pending event method seems to be broken in this case.
561 */
562 LogFlow(("Fake 'int %x' inject (real mode)\n", iGate));
563 /* Make sure the return address is set to the current IP. (ugly hack alert) */
564 pCtx->rip--;
565 cbInstr = 1;
566 intInfo = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo) | (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
567
568 pVM->hwaccm.s.vmx.RealMode.Event.intInfo = intInfo;
569 pVM->hwaccm.s.vmx.RealMode.Event.fPending = true;
570 pVM->hwaccm.s.vmx.RealMode.eip = pCtx->eip;
571 }
572#endif /* HWACCM_VMX_EMULATE_REALMODE */
573
574 /* Set event injection state. */
575 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
576
577 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
578 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
579
580 AssertRC(rc);
581 return rc;
582}
583
584
585/**
586 * Checks for pending guest interrupts and injects them
587 *
588 * @returns VBox status code.
589 * @param pVM The VM to operate on.
590 * @param pCtx CPU Context
591 */
592static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
593{
594 int rc;
595
596 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
597 if (pVM->hwaccm.s.Event.fPending)
598 {
599 Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
600 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
601 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
602 AssertRC(rc);
603
604 pVM->hwaccm.s.Event.fPending = false;
605 return VINF_SUCCESS;
606 }
607
608 /* When external interrupts are pending, we should exit the VM when IF is set. */
609 if ( !TRPMHasTrap(pVM)
610 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
611 {
612 if (!(pCtx->eflags.u32 & X86_EFL_IF))
613 {
614 if (!(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
615 {
616 LogFlow(("Enable irq window exit!\n"));
617 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
618 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
619 AssertRC(rc);
620 }
621 /* else nothing to do but wait */
622 }
623 else
624 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
625 {
626 uint8_t u8Interrupt;
627
628 rc = PDMGetInterrupt(pVM, &u8Interrupt);
629 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
630 if (VBOX_SUCCESS(rc))
631 {
632 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
633 AssertRC(rc);
634 }
635 else
636 {
637 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
638 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
639 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
640 /* Just continue */
641 }
642 }
643 else
644 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
645 }
646
647#ifdef VBOX_STRICT
648 if (TRPMHasTrap(pVM))
649 {
650 uint8_t u8Vector;
651 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
652 AssertRC(rc);
653 }
654#endif
655
656 if ( pCtx->eflags.u32 & X86_EFL_IF
657 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
658 && TRPMHasTrap(pVM)
659 )
660 {
661 uint8_t u8Vector;
662 int rc;
663 TRPMEVENT enmType;
664 RTGCUINTPTR intInfo;
665 RTGCUINT errCode;
666
667 /* If a new event is pending, then dispatch it now. */
668 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
669 AssertRC(rc);
670 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
671 Assert(enmType != TRPM_SOFTWARE_INT);
672
673 /* Clear the pending trap. */
674 rc = TRPMResetTrap(pVM);
675 AssertRC(rc);
676
677 intInfo = u8Vector;
678 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
679
680 if (enmType == TRPM_TRAP)
681 {
682 switch (u8Vector) {
683 case 8:
684 case 10:
685 case 11:
686 case 12:
687 case 13:
688 case 14:
689 case 17:
690 /* Valid error codes. */
691 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
692 break;
693 default:
694 break;
695 }
696 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
697 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
698 else
699 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
700 }
701 else
702 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
703
704 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
705 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
706 AssertRC(rc);
707 } /* if (interrupts can be dispatched) */
708
709 return VINF_SUCCESS;
710}
711
712/**
713 * Save the host state
714 *
715 * @returns VBox status code.
716 * @param pVM The VM to operate on.
717 */
718VMMR0DECL(int) VMXR0SaveHostState(PVM pVM)
719{
720 int rc = VINF_SUCCESS;
721
722 /*
723 * Host CPU Context
724 */
725 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
726 {
727 RTIDTR idtr;
728 RTGDTR gdtr;
729 RTSEL SelTR;
730 PX86DESCHC pDesc;
731 uintptr_t trBase;
732
733 /* Control registers */
734 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
735 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
736 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
737 AssertRC(rc);
738 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
739 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
740 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
741
742 /* Selector registers. */
743 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
744 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
745 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
746 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
747#if HC_ARCH_BITS == 32
748 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
749 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
750#endif
751 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
752 SelTR = ASMGetTR();
753 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
754 AssertRC(rc);
755 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
756 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
757 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
758 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
759 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
760 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
761 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
762
763 /* GDTR & IDTR */
764 ASMGetGDTR(&gdtr);
765 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
766 ASMGetIDTR(&idtr);
767 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
768 AssertRC(rc);
769 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
770 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
771
772 /* Save the base address of the TR selector. */
773 if (SelTR > gdtr.cbGdt)
774 {
775 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
776 return VERR_VMX_INVALID_HOST_STATE;
777 }
778
779 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
780#if HC_ARCH_BITS == 64
781 trBase = X86DESC64_BASE(*pDesc);
782#else
783 trBase = X86DESC_BASE(*pDesc);
784#endif
785 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
786 AssertRC(rc);
787 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
788
789 /* FS and GS base. */
790#if HC_ARCH_BITS == 64
791 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
792 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
793 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
794 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
795#endif
796 AssertRC(rc);
797
798 /* Sysenter MSRs. */
799 /** @todo expensive!! */
800 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
801 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
802#if HC_ARCH_BITS == 32
803 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
804 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
805 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
806 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
807#else
808 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
809 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
810 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
811 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
812#endif
813 AssertRC(rc);
814
815 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
816 }
817 return rc;
818}
819
820
821/**
822 * Loads the guest state
823 *
824 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
825 *
826 * @returns VBox status code.
827 * @param pVM The VM to operate on.
828 * @param pCtx Guest context
829 */
830VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
831{
832 int rc = VINF_SUCCESS;
833 RTGCUINTPTR val;
834 X86EFLAGS eflags;
835
836 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
837 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
838 {
839#ifdef HWACCM_VMX_EMULATE_REALMODE
840 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
841 if (pVM->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
842 {
843# define VTX_CORRECT_PROT_SEL(reg) \
844 { \
845 if ( pCtx->reg##Hid.u64Base == (pVM->hwaccm.s.vmx.RealMode.reg##Hid.u64Base & 0xfffff) \
846 && pCtx->reg == ((pVM->hwaccm.s.vmx.RealMode.reg##Hid.u64Base >> 4) & ~X86_SEL_RPL)) \
847 { \
848 pCtx->reg##Hid = pVM->hwaccm.s.vmx.RealMode.reg##Hid; \
849 pCtx->reg = pVM->hwaccm.s.vmx.RealMode.reg; \
850 } \
851 }
852
853 /* Correct weird requirements for switching to protected mode. */
854 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
855 && enmGuestMode >= PGMMODE_PROTECTED)
856 {
857 /* DPL of all hidden selector registers must match the current CPL (0). */
858 pCtx->csHid.Attr.n.u2Dpl = 0;
859 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
860
861 pCtx->dsHid.Attr.n.u2Dpl = 0;
862 pCtx->esHid.Attr.n.u2Dpl = 0;
863 pCtx->fsHid.Attr.n.u2Dpl = 0;
864 pCtx->gsHid.Attr.n.u2Dpl = 0;
865 pCtx->ssHid.Attr.n.u2Dpl = 0;
866
867 /* RPL of all selectors must match the current CPL (0). */
868 pCtx->cs &= ~X86_SEL_RPL;
869 pCtx->ds &= ~X86_SEL_RPL;
870 pCtx->es &= ~X86_SEL_RPL;
871 pCtx->fs &= ~X86_SEL_RPL;
872 pCtx->gs &= ~X86_SEL_RPL;
873 pCtx->ss &= ~X86_SEL_RPL;
874
875 if (pVM->hwaccm.s.vmx.RealMode.fValid)
876 {
877 VTX_CORRECT_PROT_SEL(ds);
878 VTX_CORRECT_PROT_SEL(es);
879 VTX_CORRECT_PROT_SEL(fs);
880 VTX_CORRECT_PROT_SEL(gs);
881 VTX_CORRECT_PROT_SEL(ss);
882 pVM->hwaccm.s.vmx.RealMode.fValid = false;
883 }
884 }
885 else
886 /* Switching from protected mode to real mode. */
887 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode >= PGMMODE_PROTECTED
888 && enmGuestMode == PGMMODE_REAL)
889 {
890 /* Save the original hidden selectors in case we need to restore them later on. */
891 pVM->hwaccm.s.vmx.RealMode.ds = pCtx->ds;
892 pVM->hwaccm.s.vmx.RealMode.dsHid = pCtx->dsHid;
893 pVM->hwaccm.s.vmx.RealMode.es = pCtx->es;
894 pVM->hwaccm.s.vmx.RealMode.esHid = pCtx->esHid;
895 pVM->hwaccm.s.vmx.RealMode.fs = pCtx->fs;
896 pVM->hwaccm.s.vmx.RealMode.fsHid = pCtx->fsHid;
897 pVM->hwaccm.s.vmx.RealMode.gs = pCtx->gs;
898 pVM->hwaccm.s.vmx.RealMode.gsHid = pCtx->gsHid;
899 pVM->hwaccm.s.vmx.RealMode.ss = pCtx->ss;
900 pVM->hwaccm.s.vmx.RealMode.ssHid = pCtx->ssHid;
901 pVM->hwaccm.s.vmx.RealMode.fValid = true;
902
903 /* The selector value & base must be adjusted or else... */
904 pCtx->cs = pCtx->csHid.u64Base >> 4;
905 pCtx->ds = pCtx->dsHid.u64Base >> 4;
906 pCtx->es = pCtx->esHid.u64Base >> 4;
907 pCtx->fs = pCtx->fsHid.u64Base >> 4;
908 pCtx->gs = pCtx->gsHid.u64Base >> 4;
909 pCtx->ss = pCtx->ssHid.u64Base >> 4;
910
911 /* The limit must also be adjusted. */
912 pCtx->csHid.u32Limit &= 0xffff;
913 pCtx->dsHid.u32Limit &= 0xffff;
914 pCtx->esHid.u32Limit &= 0xffff;
915 pCtx->fsHid.u32Limit &= 0xffff;
916 pCtx->gsHid.u32Limit &= 0xffff;
917 pCtx->ssHid.u32Limit &= 0xffff;
918
919 Assert(pCtx->csHid.u64Base <= 0xfffff);
920 Assert(pCtx->dsHid.u64Base <= 0xfffff);
921 Assert(pCtx->esHid.u64Base <= 0xfffff);
922 Assert(pCtx->fsHid.u64Base <= 0xfffff);
923 Assert(pCtx->gsHid.u64Base <= 0xfffff);
924 }
925 pVM->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
926 }
927 else
928 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
929 if ( CPUMIsGuestInRealModeEx(pCtx)
930 && pCtx->csHid.u64Base == 0xffff0000)
931 {
932 pCtx->csHid.u64Base = 0xf0000;
933 pCtx->cs = 0xf000;
934 }
935#endif /* HWACCM_VMX_EMULATE_REALMODE */
936
937 VMX_WRITE_SELREG(ES, es);
938 AssertRC(rc);
939
940 VMX_WRITE_SELREG(CS, cs);
941 AssertRC(rc);
942
943 VMX_WRITE_SELREG(SS, ss);
944 AssertRC(rc);
945
946 VMX_WRITE_SELREG(DS, ds);
947 AssertRC(rc);
948
949 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
950 VMX_WRITE_SELREG(FS, fs);
951 AssertRC(rc);
952
953 VMX_WRITE_SELREG(GS, gs);
954 AssertRC(rc);
955 }
956
957 /* Guest CPU context: LDTR. */
958 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
959 {
960 if (pCtx->ldtr == 0)
961 {
962 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
963 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
964 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
965 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
966 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
967 }
968 else
969 {
970 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
971 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
972 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
973 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
974 }
975 AssertRC(rc);
976 }
977 /* Guest CPU context: TR. */
978 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
979 {
980#ifdef HWACCM_VMX_EMULATE_REALMODE
981 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
982 if (CPUMIsGuestInRealModeEx(pCtx))
983 {
984 RTGCPHYS GCPhys;
985
986 /* We convert it here every time as pci regions could be reconfigured. */
987 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
988 AssertRC(rc);
989
990 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, 0);
991 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
992 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
993
994 X86DESCATTR attr;
995
996 attr.u = 0;
997 attr.n.u1Present = 1;
998 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
999 val = attr.u;
1000 }
1001 else
1002#endif /* HWACCM_VMX_EMULATE_REALMODE */
1003 {
1004 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
1005 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1006 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
1007
1008 val = pCtx->trHid.Attr.u;
1009
1010 /* The TSS selector must be busy. */
1011 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1012 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1013 else
1014 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1015 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1016
1017 }
1018 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
1019 AssertRC(rc);
1020 }
1021 /* Guest CPU context: GDTR. */
1022 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1023 {
1024 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1025 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1026 AssertRC(rc);
1027 }
1028 /* Guest CPU context: IDTR. */
1029 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1030 {
1031 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1032 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1033 AssertRC(rc);
1034 }
1035
1036 /*
1037 * Sysenter MSRs (unconditional)
1038 */
1039 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1040 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1041 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1042 AssertRC(rc);
1043
1044 /* Control registers */
1045 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1046 {
1047 val = pCtx->cr0;
1048 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1049 Log2(("Guest CR0-shadow %08x\n", val));
1050 if (CPUMIsGuestFPUStateActive(pVM) == false)
1051 {
1052 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1053 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1054 }
1055 else
1056 {
1057 /** @todo check if we support the old style mess correctly. */
1058 if (!(val & X86_CR0_NE))
1059 {
1060 Log(("Forcing X86_CR0_NE!!!\n"));
1061
1062 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1063 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
1064 {
1065 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_MF);
1066 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1067 AssertRC(rc);
1068 pVM->hwaccm.s.fFPUOldStyleOverride = true;
1069 }
1070 }
1071
1072 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1073 }
1074 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1075 val |= X86_CR0_PE | X86_CR0_PG;
1076 if (pVM->hwaccm.s.fNestedPaging)
1077 {
1078 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1079 {
1080 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1081 pVM->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1082 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1083 }
1084 else
1085 {
1086 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1087 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1088 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1089 }
1090 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1091 AssertRC(rc);
1092 }
1093 else
1094 {
1095 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1096 val |= X86_CR0_WP;
1097 }
1098
1099 /* Always enable caching. */
1100 val &= ~(X86_CR0_CD|X86_CR0_NW);
1101
1102 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
1103 Log2(("Guest CR0 %08x\n", val));
1104 /* CR0 flags owned by the host; if the guests attempts to change them, then
1105 * the VM will exit.
1106 */
1107 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1108 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1109 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1110 | X86_CR0_TS
1111 | X86_CR0_ET /* Bit not restored during VM-exit! */
1112 | X86_CR0_CD /* Bit not restored during VM-exit! */
1113 | X86_CR0_NW /* Bit not restored during VM-exit! */
1114 | X86_CR0_NE
1115 | X86_CR0_MP;
1116 pVM->hwaccm.s.vmx.cr0_mask = val;
1117
1118 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1119 Log2(("Guest CR0-mask %08x\n", val));
1120 AssertRC(rc);
1121 }
1122 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1123 {
1124 /* CR4 */
1125 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1126 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1127 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1128 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1129
1130 if (!pVM->hwaccm.s.fNestedPaging)
1131 {
1132 switch(pVM->hwaccm.s.enmShadowMode)
1133 {
1134 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1135 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1136 case PGMMODE_32_BIT: /* 32-bit paging. */
1137 break;
1138
1139 case PGMMODE_PAE: /* PAE paging. */
1140 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1141 /** @todo use normal 32 bits paging */
1142 val |= X86_CR4_PAE;
1143 break;
1144
1145 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1146 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1147#ifdef VBOX_ENABLE_64_BITS_GUESTS
1148 break;
1149#else
1150 AssertFailed();
1151 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1152#endif
1153 default: /* shut up gcc */
1154 AssertFailed();
1155 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1156 }
1157 }
1158 else
1159 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1160 {
1161 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1162 val |= X86_CR4_PSE;
1163 }
1164
1165#ifdef HWACCM_VMX_EMULATE_REALMODE
1166 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1167 if (CPUMIsGuestInRealModeEx(pCtx))
1168 val |= X86_CR4_VME;
1169#endif /* HWACCM_VMX_EMULATE_REALMODE */
1170
1171 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
1172 Log2(("Guest CR4 %08x\n", val));
1173 /* CR4 flags owned by the host; if the guests attempts to change them, then
1174 * the VM will exit.
1175 */
1176 val = 0
1177#ifdef HWACCM_VMX_EMULATE_REALMODE
1178 | X86_CR4_VME
1179#endif
1180 | X86_CR4_PAE
1181 | X86_CR4_PGE
1182 | X86_CR4_PSE
1183 | X86_CR4_VMXE;
1184 pVM->hwaccm.s.vmx.cr4_mask = val;
1185
1186 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1187 Log2(("Guest CR4-mask %08x\n", val));
1188 AssertRC(rc);
1189 }
1190
1191 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1192 {
1193 if (pVM->hwaccm.s.fNestedPaging)
1194 {
1195 AssertMsg(PGMGetEPTCR3(pVM) == PGMGetHyperCR3(pVM), ("%VHp vs %VHp\n", PGMGetEPTCR3(pVM), PGMGetHyperCR3(pVM)));
1196 pVM->hwaccm.s.vmx.GCPhysEPTP = PGMGetEPTCR3(pVM);
1197
1198 Assert(!(pVM->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1199 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1200 pVM->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1201 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1202
1203 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EPTP_FULL, pVM->hwaccm.s.vmx.GCPhysEPTP);
1204#if HC_ARCH_BITS == 32
1205 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EPTP_HIGH, (uint32_t)(pVM->hwaccm.s.vmx.GCPhysEPTP >> 32ULL));
1206#endif
1207 AssertRC(rc);
1208
1209 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1210 {
1211 RTGCPHYS GCPhys;
1212
1213 /* We convert it here every time as pci regions could be reconfigured. */
1214 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1215 AssertRC(rc);
1216
1217 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1218 * take care of the translation to host physical addresses.
1219 */
1220 val = GCPhys;
1221 }
1222 else
1223 {
1224 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1225 val = pCtx->cr3;
1226 }
1227 }
1228 else
1229 {
1230 val = PGMGetHyperCR3(pVM);
1231 Assert(val);
1232 }
1233
1234 /* Save our shadow CR3 register. */
1235 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
1236 AssertRC(rc);
1237 }
1238
1239 /* Debug registers. */
1240 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1241 {
1242 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1243 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1244
1245 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1246 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1247 pCtx->dr[7] |= 0x400; /* must be one */
1248
1249 /* Resync DR7 */
1250 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
1251 AssertRC(rc);
1252
1253 /* Sync the debug state now if any breakpoint is armed. */
1254 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1255 && !CPUMIsGuestDebugStateActive(pVM)
1256 && !DBGFIsStepping(pVM))
1257 {
1258 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxArmed);
1259
1260 /* Disable drx move intercepts. */
1261 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1262 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1263 AssertRC(rc);
1264
1265 /* Save the host and load the guest debug state. */
1266 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
1267 AssertRC(rc);
1268 }
1269
1270 /* IA32_DEBUGCTL MSR. */
1271 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1272 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
1273 AssertRC(rc);
1274
1275 /** @todo do we really ever need this? */
1276 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1277 AssertRC(rc);
1278 }
1279
1280 /* EIP, ESP and EFLAGS */
1281 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
1282 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
1283 AssertRC(rc);
1284
1285 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1286 eflags = pCtx->eflags;
1287 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1288 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1289
1290#ifdef HWACCM_VMX_EMULATE_REALMODE
1291 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1292 if (CPUMIsGuestInRealModeEx(pCtx))
1293 {
1294 eflags.Bits.u1VM = 1;
1295 eflags.Bits.u2IOPL = 3;
1296 }
1297#endif /* HWACCM_VMX_EMULATE_REALMODE */
1298 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1299 AssertRC(rc);
1300
1301 /* TSC offset. */
1302 uint64_t u64TSCOffset;
1303
1304 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1305 {
1306 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1307 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1308#if HC_ARCH_BITS == 32
1309 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
1310#endif
1311 AssertRC(rc);
1312
1313 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1314 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1315 AssertRC(rc);
1316 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
1317 }
1318 else
1319 {
1320 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1321 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1322 AssertRC(rc);
1323 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1324 }
1325
1326 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1327 * Set required bits to one and zero according to the MSR capabilities.
1328 */
1329 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1330 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1331 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1332
1333 /* 64 bits guest mode? */
1334 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1335 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1336 /* else Must be zero when AMD64 is not available. */
1337
1338 /* Mask away the bits that the CPU doesn't support */
1339 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1340 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1341 AssertRC(rc);
1342
1343 /* 64 bits guest mode? */
1344 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1345 {
1346#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
1347 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1348#else
1349 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1350#endif
1351 /* Unconditionally update these as wrmsr might have changed them. */
1352 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1353 AssertRC(rc);
1354 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1355 AssertRC(rc);
1356 }
1357 else
1358 {
1359 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1360 }
1361
1362#ifdef DEBUG
1363 /* Intercept X86_XCPT_DB if stepping is enabled */
1364 if (DBGFIsStepping(pVM))
1365 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_DB);
1366 else
1367 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_DB);
1368
1369 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1370#endif
1371
1372#ifdef VBOX_STRICT
1373 Assert(pVM->hwaccm.s.vmx.u32TrapMask & RT_BIT(X86_XCPT_GP));
1374#else
1375# ifdef HWACCM_VMX_EMULATE_REALMODE
1376 /* Intercept #GP faults in real mode to handle privileged instructions. */
1377 if (CPUMIsGuestInRealModeEx(pCtx))
1378 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_GP);
1379 else
1380 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_GP);
1381# endif /* HWACCM_VMX_EMULATE_REALMODE */
1382 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1383 AssertRC(rc);
1384#endif
1385
1386 /* Done. */
1387 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1388
1389 return rc;
1390}
1391
1392/**
1393 * Syncs back the guest state
1394 *
1395 * @returns VBox status code.
1396 * @param pVM The VM to operate on.
1397 * @param pCtx Guest context
1398 */
1399DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, CPUMCTX *pCtx)
1400{
1401 RTCCUINTREG val, valShadow;
1402 RTGCUINTPTR uInterruptState;
1403 int rc;
1404
1405 /* Let's first sync back eip, esp, and eflags. */
1406 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1407 AssertRC(rc);
1408 pCtx->rip = val;
1409 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1410 AssertRC(rc);
1411 pCtx->rsp = val;
1412 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1413 AssertRC(rc);
1414 pCtx->eflags.u32 = val;
1415
1416 /* Take care of instruction fusing (sti, mov ss) */
1417 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1418 uInterruptState = val;
1419 if (uInterruptState != 0)
1420 {
1421 Assert(uInterruptState <= 2); /* only sti & mov ss */
1422 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1423 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1424 }
1425 else
1426 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1427
1428 /* Control registers. */
1429 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1430 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1431 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1432 CPUMSetGuestCR0(pVM, val);
1433
1434 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1435 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1436 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1437 CPUMSetGuestCR4(pVM, val);
1438
1439 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1440 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1441 if ( pVM->hwaccm.s.fNestedPaging
1442 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1443 {
1444 /* Can be updated behind our back in the nested paging case. */
1445 CPUMSetGuestCR2(pVM, ASMGetCR2());
1446
1447 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
1448
1449 if (val != pCtx->cr3)
1450 {
1451 CPUMSetGuestCR3(pVM, val);
1452 PGMUpdateCR3(pVM, val);
1453 }
1454 }
1455
1456 /* Sync back DR7 here. */
1457 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1458 pCtx->dr[7] = val;
1459
1460 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1461 VMX_READ_SELREG(ES, es);
1462 VMX_READ_SELREG(SS, ss);
1463 VMX_READ_SELREG(CS, cs);
1464 VMX_READ_SELREG(DS, ds);
1465 VMX_READ_SELREG(FS, fs);
1466 VMX_READ_SELREG(GS, gs);
1467
1468 /*
1469 * System MSRs
1470 */
1471 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1472 pCtx->SysEnter.cs = val;
1473 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1474 pCtx->SysEnter.eip = val;
1475 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1476 pCtx->SysEnter.esp = val;
1477
1478 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1479 VMX_READ_SELREG(LDTR, ldtr);
1480
1481 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1482 pCtx->gdtr.cbGdt = val;
1483 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1484 pCtx->gdtr.pGdt = val;
1485
1486 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1487 pCtx->idtr.cbIdt = val;
1488 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1489 pCtx->idtr.pIdt = val;
1490
1491#ifdef HWACCM_VMX_EMULATE_REALMODE
1492 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1493 if (CPUMIsGuestInRealModeEx(pCtx))
1494 {
1495 /* Hide our emulation flags */
1496 pCtx->eflags.Bits.u1VM = 0;
1497 pCtx->eflags.Bits.u2IOPL = 0;
1498
1499 /* Force a TR resync every time in case we switch modes. */
1500 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1501 }
1502 else
1503#endif /* HWACCM_VMX_EMULATE_REALMODE */
1504 {
1505 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1506 VMX_READ_SELREG(TR, tr);
1507 }
1508 return VINF_SUCCESS;
1509}
1510
1511/**
1512 * Dummy placeholder
1513 *
1514 * @param pVM The VM to operate on.
1515 */
1516static void VMXR0SetupTLBDummy(PVM pVM)
1517{
1518 return;
1519}
1520
1521/**
1522 * Setup the tagged TLB for EPT
1523 *
1524 * @returns VBox status code.
1525 * @param pVM The VM to operate on.
1526 */
1527static void VMXR0SetupTLBEPT(PVM pVM)
1528{
1529 PHWACCM_CPUINFO pCpu;
1530
1531 Assert(pVM->hwaccm.s.fNestedPaging);
1532 Assert(!pVM->hwaccm.s.vmx.fVPID);
1533
1534 /* Deal with tagged TLBs if VPID or EPT is supported. */
1535 pCpu = HWACCMR0GetCurrentCpu();
1536 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1537 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1538 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1539 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1540 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1541 {
1542 /* Force a TLB flush on VM entry. */
1543 pVM->hwaccm.s.fForceTLBFlush = true;
1544 }
1545 else
1546 Assert(!pCpu->fFlushTLB);
1547
1548 pVM->hwaccm.s.idLastCpu = pCpu->idCpu;
1549 pCpu->fFlushTLB = false;
1550
1551 if (pVM->hwaccm.s.fForceTLBFlush)
1552 VMXR0FlushEPT(pVM, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1553
1554#ifdef VBOX_WITH_STATISTICS
1555 if (pVM->hwaccm.s.fForceTLBFlush)
1556 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
1557 else
1558 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
1559#endif
1560}
1561
1562#ifdef HWACCM_VTX_WITH_VPID
1563/**
1564 * Setup the tagged TLB for VPID
1565 *
1566 * @returns VBox status code.
1567 * @param pVM The VM to operate on.
1568 */
1569static void VMXR0SetupTLBVPID(PVM pVM)
1570{
1571 PHWACCM_CPUINFO pCpu;
1572
1573 Assert(pVM->hwaccm.s.vmx.fVPID);
1574 Assert(!pVM->hwaccm.s.fNestedPaging);
1575
1576 /* Deal with tagged TLBs if VPID or EPT is supported. */
1577 pCpu = HWACCMR0GetCurrentCpu();
1578 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1579 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1580 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1581 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1582 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1583 {
1584 /* Force a TLB flush on VM entry. */
1585 pVM->hwaccm.s.fForceTLBFlush = true;
1586 }
1587 else
1588 Assert(!pCpu->fFlushTLB);
1589
1590 pVM->hwaccm.s.idLastCpu = pCpu->idCpu;
1591
1592 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1593 if (pVM->hwaccm.s.fForceTLBFlush)
1594 {
1595 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1596 || pCpu->fFlushTLB)
1597 {
1598 pCpu->fFlushTLB = false;
1599 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1600 pCpu->cTLBFlushes++;
1601 }
1602 else
1603 {
1604 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
1605 pVM->hwaccm.s.fForceTLBFlush = false;
1606 }
1607
1608 pVM->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1609 pVM->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1610 }
1611 else
1612 {
1613 Assert(!pCpu->fFlushTLB);
1614
1615 if (!pCpu->uCurrentASID || !pVM->hwaccm.s.uCurrentASID)
1616 pVM->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1617 }
1618 AssertMsg(pVM->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1619 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1620 AssertMsg(pVM->hwaccm.s.uCurrentASID >= 1 && pVM->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVM->hwaccm.s.uCurrentASID));
1621
1622 int rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_VPID, pVM->hwaccm.s.uCurrentASID);
1623 AssertRC(rc);
1624
1625 if (pVM->hwaccm.s.fForceTLBFlush)
1626 VMXR0FlushVPID(pVM, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1627
1628#ifdef VBOX_WITH_STATISTICS
1629 if (pVM->hwaccm.s.fForceTLBFlush)
1630 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
1631 else
1632 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
1633#endif
1634}
1635#endif /* HWACCM_VTX_WITH_VPID */
1636
1637/**
1638 * Runs guest code in a VT-x VM.
1639 *
1640 * @returns VBox status code.
1641 * @param pVM The VM to operate on.
1642 * @param pCtx Guest context
1643 */
1644VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1645{
1646 int rc = VINF_SUCCESS;
1647 RTCCUINTREG val;
1648 RTCCUINTREG exitReason, instrError, cbInstr;
1649 RTGCUINTPTR exitQualification;
1650 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1651 RTGCUINTPTR errCode, instrInfo;
1652 bool fSyncTPR = false;
1653 PHWACCM_CPUINFO pCpu = 0;
1654 unsigned cResume = 0;
1655#ifdef VBOX_STRICT
1656 RTCPUID idCpuCheck;
1657#endif
1658
1659 Log2(("\nE"));
1660
1661 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1662
1663#ifdef VBOX_STRICT
1664 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1665 AssertRC(rc);
1666 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1667
1668 /* allowed zero */
1669 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1670 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1671
1672 /* allowed one */
1673 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1674 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1675
1676 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1677 AssertRC(rc);
1678 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1679
1680 /* allowed zero */
1681 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1682 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1683
1684 /* allowed one */
1685 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1686 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1687
1688 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1689 AssertRC(rc);
1690 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1691
1692 /* allowed zero */
1693 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1694 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1695
1696 /* allowed one */
1697 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1698 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1699
1700 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1701 AssertRC(rc);
1702 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1703
1704 /* allowed zero */
1705 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1706 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1707
1708 /* allowed one */
1709 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1710 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1711#endif
1712
1713 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1714 */
1715ResumeExecution:
1716 AssertMsg(pVM->hwaccm.s.idEnteredCpu == RTMpCpuId(),
1717 ("Expected %d, I'm %d; cResume=%d exitReason=%RTreg exitQualification=%RTreg\n",
1718 (int)pVM->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
1719
1720 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1721 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1722 {
1723 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1724 rc = VINF_EM_RAW_INTERRUPT;
1725 goto end;
1726 }
1727
1728 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1729 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1730 {
1731 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1732 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1733 {
1734 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1735 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1736 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1737 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1738 */
1739 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1740 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1741 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1742 AssertRC(rc);
1743 }
1744 }
1745 else
1746 {
1747 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1748 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1749 AssertRC(rc);
1750 }
1751
1752 /* Check for pending actions that force us to go back to ring 3. */
1753 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1754 {
1755 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1756 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1757 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1758 rc = VINF_EM_RAW_TO_R3;
1759 goto end;
1760 }
1761 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1762 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1763 {
1764 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1765 rc = VINF_EM_PENDING_REQUEST;
1766 goto end;
1767 }
1768
1769 /* When external interrupts are pending, we should exit the VM when IF is set. */
1770 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1771 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1772 if (VBOX_FAILURE(rc))
1773 {
1774 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1775 goto end;
1776 }
1777
1778 /** @todo check timers?? */
1779
1780 /* TPR caching using CR8 is only available in 64 bits mode */
1781 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1782 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1783 /**
1784 * @todo reduce overhead
1785 */
1786 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1787 && pVM->hwaccm.s.vmx.pAPIC)
1788 {
1789 /* TPR caching in CR8 */
1790 uint8_t u8TPR;
1791 bool fPending;
1792
1793 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1794 AssertRC(rc);
1795 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1796 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1797
1798 /* Two options here:
1799 * - external interrupt pending, but masked by the TPR value.
1800 * -> a CR8 update that lower the current TPR value should cause an exit
1801 * - no pending interrupts
1802 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1803 */
1804 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1805 AssertRC(rc);
1806
1807 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
1808 fSyncTPR = true;
1809 }
1810
1811#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
1812 if ( pVM->hwaccm.s.fNestedPaging
1813# ifdef HWACCM_VTX_WITH_VPID
1814 || pVM->hwaccm.s.vmx.fVPID
1815# endif /* HWACCM_VTX_WITH_VPID */
1816 )
1817 {
1818 pCpu = HWACCMR0GetCurrentCpu();
1819 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1820 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1821 {
1822 if (pVM->hwaccm.s.idLastCpu != pCpu->idCpu)
1823 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.idLastCpu, pCpu->idCpu));
1824 else
1825 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1826 }
1827 if (pCpu->fFlushTLB)
1828 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1829 }
1830#endif
1831
1832 /*
1833 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1834 * (until the actual world switch)
1835 */
1836#ifdef VBOX_STRICT
1837 idCpuCheck = RTMpCpuId();
1838#endif
1839 /* Save the host state first. */
1840 rc = VMXR0SaveHostState(pVM);
1841 if (rc != VINF_SUCCESS)
1842 {
1843 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1844 goto end;
1845 }
1846 /* Load the guest state */
1847 rc = VMXR0LoadGuestState(pVM, pCtx);
1848 if (rc != VINF_SUCCESS)
1849 {
1850 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1851 goto end;
1852 }
1853
1854 /* Deal with tagged TLB setup and invalidation. */
1855 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM);
1856
1857 /* Non-register state Guest Context */
1858 /** @todo change me according to cpu state */
1859 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1860 AssertRC(rc);
1861
1862 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1863
1864 /* Manual save and restore:
1865 * - General purpose registers except RIP, RSP
1866 *
1867 * Trashed:
1868 * - CR2 (we don't care)
1869 * - LDTR (reset to 0)
1870 * - DRx (presumably not changed at all)
1871 * - DR7 (reset to 0x400)
1872 * - EFLAGS (reset to RT_BIT(1); not relevant)
1873 *
1874 */
1875
1876 /* All done! Let's start VM execution. */
1877 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1878#ifdef VBOX_STRICT
1879 Assert(idCpuCheck == RTMpCpuId());
1880#endif
1881 TMNotifyStartOfExecution(pVM);
1882 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1883 TMNotifyEndOfExecution(pVM);
1884
1885 /* In case we execute a goto ResumeExecution later on. */
1886 pVM->hwaccm.s.vmx.fResumeVM = true;
1887 pVM->hwaccm.s.fForceTLBFlush = false;
1888
1889 /*
1890 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1891 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1892 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1893 */
1894
1895 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1896 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1897
1898 if (rc != VINF_SUCCESS)
1899 {
1900 VMXR0ReportWorldSwitchError(pVM, rc, pCtx);
1901 goto end;
1902 }
1903 /* Success. Query the guest state and figure out what has happened. */
1904
1905 /* Investigate why there was a VM-exit. */
1906 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1907 STAM_COUNTER_INC(&pVM->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1908
1909 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1910 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1911 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1912 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1913 intInfo = val;
1914 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1915 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1916 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1917 instrInfo = val;
1918 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1919 exitQualification = val;
1920 AssertRC(rc);
1921
1922 /* Sync back the guest state */
1923 rc = VMXR0SaveGuestState(pVM, pCtx);
1924 AssertRC(rc);
1925
1926 /* Note! NOW IT'S SAFE FOR LOGGING! */
1927 Log2(("Raw exit reason %08x\n", exitReason));
1928
1929 /* Check if an injected event was interrupted prematurely. */
1930 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1931 AssertRC(rc);
1932#ifdef HWACCM_VMX_EMULATE_REALMODE
1933 /* For some reason injected software interrupts are ignored (not signalled as pending) when e.g. a shadow page fault occurs. */
1934 if ( CPUMIsGuestInRealModeEx(pCtx)
1935 && pVM->hwaccm.s.vmx.RealMode.eip == pCtx->eip
1936 && pVM->hwaccm.s.vmx.RealMode.Event.fPending)
1937 {
1938 Assert(!pVM->hwaccm.s.Event.fPending);
1939
1940 Log(("Pending real-mode inject %VX64 at %VGv\n", pVM->hwaccm.s.vmx.RealMode.Event.intInfo, pCtx->rip));
1941
1942 /* We faked an 'int x' instruction and messed with IP, so correct it here. */
1943 pCtx->rip++;
1944 pVM->hwaccm.s.Event.intInfo = pVM->hwaccm.s.vmx.RealMode.Event.intInfo;
1945 pVM->hwaccm.s.Event.fPending = true;
1946 }
1947 else
1948#endif /* HWACCM_VMX_EMULATE_REALMODE */
1949 {
1950 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1951 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1952 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1953 {
1954 pVM->hwaccm.s.Event.fPending = true;
1955 /* Error code present? */
1956 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1957 {
1958 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1959 AssertRC(rc);
1960 pVM->hwaccm.s.Event.errCode = val;
1961 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1962 }
1963 else
1964 {
1965 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1966 pVM->hwaccm.s.Event.errCode = 0;
1967 }
1968 }
1969 }
1970 pVM->hwaccm.s.vmx.RealMode.Event.fPending = false;
1971
1972#ifdef VBOX_STRICT
1973 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1974 HWACCMDumpRegs(pVM, pCtx);
1975#endif
1976
1977 Log2(("E%d", exitReason));
1978 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1979 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1980 Log2(("Interruption error code %d\n", errCode));
1981 Log2(("IntInfo = %08x\n", intInfo));
1982 Log2(("New EIP=%VGv\n", pCtx->rip));
1983
1984 if (fSyncTPR)
1985 {
1986 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1987 AssertRC(rc);
1988 }
1989
1990 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1991 switch (exitReason)
1992 {
1993 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1994 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1995 {
1996 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1997
1998 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1999 {
2000 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2001 /* External interrupt; leave to allow it to be dispatched again. */
2002 rc = VINF_EM_RAW_INTERRUPT;
2003 break;
2004 }
2005 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2006 {
2007 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2008 /* External interrupt; leave to allow it to be dispatched again. */
2009 rc = VINF_EM_RAW_INTERRUPT;
2010 break;
2011
2012 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2013 AssertFailed(); /* can't come here; fails the first check. */
2014 break;
2015
2016 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2017 Assert(vector == 3 || vector == 4);
2018 /* no break */
2019 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2020 Log2(("Hardware/software interrupt %d\n", vector));
2021 switch (vector)
2022 {
2023 case X86_XCPT_NM:
2024 {
2025 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
2026
2027 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2028 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2029 rc = CPUMR0LoadGuestFPU(pVM, pCtx);
2030 if (rc == VINF_SUCCESS)
2031 {
2032 Assert(CPUMIsGuestFPUStateActive(pVM));
2033
2034 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
2035
2036 /* Continue execution. */
2037 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2038 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2039
2040 goto ResumeExecution;
2041 }
2042
2043 Log(("Forward #NM fault to the guest\n"));
2044 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
2045 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2046 AssertRC(rc);
2047 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2048 goto ResumeExecution;
2049 }
2050
2051 case X86_XCPT_PF: /* Page fault */
2052 {
2053#ifdef DEBUG
2054 if (pVM->hwaccm.s.fNestedPaging)
2055 { /* A genuine pagefault.
2056 * Forward the trap to the guest by injecting the exception and resuming execution.
2057 */
2058 Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2059
2060 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
2061
2062 /* Now we must update CR2. */
2063 pCtx->cr2 = exitQualification;
2064 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2065 AssertRC(rc);
2066
2067 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2068 goto ResumeExecution;
2069 }
2070#endif
2071 Assert(!pVM->hwaccm.s.fNestedPaging);
2072
2073 Log2(("Page fault at %VGv error code %x\n", exitQualification, errCode));
2074 /* Exit qualification contains the linear address of the page fault. */
2075 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2076 TRPMSetErrorCode(pVM, errCode);
2077 TRPMSetFaultAddress(pVM, exitQualification);
2078
2079 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2080 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2081 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
2082 if (rc == VINF_SUCCESS)
2083 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2084 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
2085 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
2086
2087 TRPMResetTrap(pVM);
2088
2089 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2090 goto ResumeExecution;
2091 }
2092 else
2093 if (rc == VINF_EM_RAW_GUEST_TRAP)
2094 { /* A genuine pagefault.
2095 * Forward the trap to the guest by injecting the exception and resuming execution.
2096 */
2097 Log2(("Forward page fault to the guest\n"));
2098
2099 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
2100 /* The error code might have been changed. */
2101 errCode = TRPMGetErrorCode(pVM);
2102
2103 TRPMResetTrap(pVM);
2104
2105 /* Now we must update CR2. */
2106 pCtx->cr2 = exitQualification;
2107 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2108 AssertRC(rc);
2109
2110 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2111 goto ResumeExecution;
2112 }
2113#ifdef VBOX_STRICT
2114 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2115 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2116#endif
2117 /* Need to go back to the recompiler to emulate the instruction. */
2118 TRPMResetTrap(pVM);
2119 break;
2120 }
2121
2122 case X86_XCPT_MF: /* Floating point exception. */
2123 {
2124 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
2125 if (!(pCtx->cr0 & X86_CR0_NE))
2126 {
2127 /* old style FPU error reporting needs some extra work. */
2128 /** @todo don't fall back to the recompiler, but do it manually. */
2129 rc = VINF_EM_RAW_EMULATE_INSTR;
2130 break;
2131 }
2132 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
2133 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2134 AssertRC(rc);
2135
2136 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2137 goto ResumeExecution;
2138 }
2139
2140 case X86_XCPT_DB: /* Debug exception. */
2141 {
2142 uint64_t uDR6;
2143
2144 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2145 *
2146 * Exit qualification bits:
2147 * 3:0 B0-B3 which breakpoint condition was met
2148 * 12:4 Reserved (0)
2149 * 13 BD - debug register access detected
2150 * 14 BS - single step execution or branch taken
2151 * 63:15 Reserved (0)
2152 */
2153 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDB);
2154
2155 /* Note that we don't support guest and host-initiated debugging at the same time. */
2156 Assert(DBGFIsStepping(pVM));
2157
2158 uDR6 = X86_DR6_INIT_VAL;
2159 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2160 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
2161 if (rc == VINF_EM_RAW_GUEST_TRAP)
2162 {
2163 /** @todo this isn't working, but we'll never get here normally. */
2164
2165 /* Update DR6 here. */
2166 pCtx->dr[6] = uDR6;
2167
2168 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2169 pCtx->dr[7] &= ~X86_DR7_GD;
2170
2171 /* Paranoia. */
2172 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2173 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2174 pCtx->dr[7] |= 0x400; /* must be one */
2175
2176 /* Resync DR7 */
2177 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2178 AssertRC(rc);
2179
2180 Log(("Trap %x (debug) at %VGv exit qualification %VX64\n", vector, pCtx->rip, exitQualification));
2181 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2182 AssertRC(rc);
2183
2184 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2185 goto ResumeExecution;
2186 }
2187 /* Return to ring 3 to deal with the debug exit code. */
2188 break;
2189 }
2190
2191 case X86_XCPT_GP: /* General protection failure exception.*/
2192 {
2193 uint32_t cbSize;
2194
2195 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
2196#ifdef VBOX_STRICT
2197 if (!CPUMIsGuestInRealModeEx(pCtx))
2198 {
2199 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
2200 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2201 AssertRC(rc);
2202 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2203 goto ResumeExecution;
2204 }
2205#endif
2206 Assert(CPUMIsGuestInRealModeEx(pCtx));
2207
2208 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %VGv\n", pCtx->rip));
2209 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2210 if (rc == VINF_SUCCESS)
2211 {
2212 /* EIP has been updated already. */
2213
2214 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2215 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2216
2217 /* Only resume if successful. */
2218 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2219 goto ResumeExecution;
2220 }
2221 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Vrc\n", rc));
2222 break;
2223 }
2224
2225#ifdef VBOX_STRICT
2226 case X86_XCPT_DE: /* Divide error. */
2227 case X86_XCPT_UD: /* Unknown opcode exception. */
2228 case X86_XCPT_SS: /* Stack segment exception. */
2229 case X86_XCPT_NP: /* Segment not present exception. */
2230 {
2231 switch(vector)
2232 {
2233 case X86_XCPT_DE:
2234 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
2235 break;
2236 case X86_XCPT_UD:
2237 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
2238 break;
2239 case X86_XCPT_SS:
2240 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
2241 break;
2242 case X86_XCPT_NP:
2243 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
2244 break;
2245 }
2246
2247 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
2248 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2249 AssertRC(rc);
2250
2251 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2252 goto ResumeExecution;
2253 }
2254#endif
2255 default:
2256 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2257 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2258 break;
2259 } /* switch (vector) */
2260
2261 break;
2262
2263 default:
2264 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2265 AssertFailed();
2266 break;
2267 }
2268
2269 break;
2270 }
2271
2272 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2273 {
2274 RTGCPHYS GCPhys;
2275
2276 Assert(pVM->hwaccm.s.fNestedPaging);
2277
2278#if HC_ARCH_BITS == 64
2279 rc = VMXReadVMCS(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2280 AssertRC(rc);
2281#else
2282 rc = VMXReadVMCS(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &val);
2283 AssertRC(rc);
2284 GCPhys = val;
2285 rc = VMXReadVMCS(VMX_VMCS_EXIT_PHYS_ADDR_HIGH, &val);
2286 GCPhys |= (val << 32ULL);
2287#endif
2288
2289 Assert(((exitQualification >> 7) & 3) != 2);
2290
2291 /* Determine the kind of violation. */
2292 errCode = 0;
2293 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2294 errCode |= X86_TRAP_PF_ID;
2295
2296 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2297 errCode |= X86_TRAP_PF_RW;
2298
2299 /* If the page is present, then it's a page level protection fault. */
2300 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2301 errCode |= X86_TRAP_PF_P;
2302
2303 Log(("EPT Page fault %x at %VGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2304
2305 /* GCPhys contains the guest physical address of the page fault. */
2306 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2307 TRPMSetErrorCode(pVM, errCode);
2308 TRPMSetFaultAddress(pVM, GCPhys);
2309
2310 /* Handle the pagefault trap for the nested shadow table. */
2311 rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2312 Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
2313 if (rc == VINF_SUCCESS)
2314 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2315 Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, exitQualification , errCode));
2316 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
2317
2318 TRPMResetTrap(pVM);
2319
2320 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2321 goto ResumeExecution;
2322 }
2323
2324#ifdef VBOX_STRICT
2325 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2326 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2327#endif
2328 /* Need to go back to the recompiler to emulate the instruction. */
2329 TRPMResetTrap(pVM);
2330 break;
2331 }
2332
2333 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2334 /* Clear VM-exit on IF=1 change. */
2335 LogFlow(("VMX_EXIT_IRQ_WINDOW %VGv pending=%d IF=%d\n", pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2336 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2337 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2338 AssertRC(rc);
2339 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
2340 goto ResumeExecution; /* we check for pending guest interrupts there */
2341
2342 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2343 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2344 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
2345 /* Skip instruction and continue directly. */
2346 pCtx->rip += cbInstr;
2347 /* Continue execution.*/
2348 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2349 goto ResumeExecution;
2350
2351 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2352 {
2353 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2354 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
2355 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
2356 if (rc == VINF_SUCCESS)
2357 {
2358 /* Update EIP and continue execution. */
2359 Assert(cbInstr == 2);
2360 pCtx->rip += cbInstr;
2361 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2362 goto ResumeExecution;
2363 }
2364 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
2365 rc = VINF_EM_RAW_EMULATE_INSTR;
2366 break;
2367 }
2368
2369 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2370 {
2371 Log2(("VMX: Rdtsc\n"));
2372 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
2373 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
2374 if (rc == VINF_SUCCESS)
2375 {
2376 /* Update EIP and continue execution. */
2377 Assert(cbInstr == 2);
2378 pCtx->rip += cbInstr;
2379 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2380 goto ResumeExecution;
2381 }
2382 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
2383 rc = VINF_EM_RAW_EMULATE_INSTR;
2384 break;
2385 }
2386
2387 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2388 {
2389 Log2(("VMX: invlpg\n"));
2390 Assert(!pVM->hwaccm.s.fNestedPaging);
2391
2392 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
2393 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
2394 if (rc == VINF_SUCCESS)
2395 {
2396 /* Update EIP and continue execution. */
2397 pCtx->rip += cbInstr;
2398 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2399 goto ResumeExecution;
2400 }
2401 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
2402 break;
2403 }
2404
2405 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2406 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2407 {
2408 uint32_t cbSize;
2409
2410 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2411 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
2412 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2413 if (rc == VINF_SUCCESS)
2414 {
2415 /* EIP has been updated already. */
2416
2417 /* Only resume if successful. */
2418 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2419 goto ResumeExecution;
2420 }
2421 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
2422 break;
2423 }
2424
2425 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2426 {
2427 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
2428 {
2429 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
2430 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
2431 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
2432 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
2433 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
2434 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
2435
2436 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
2437 {
2438 case 0:
2439 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
2440 break;
2441 case 2:
2442 break;
2443 case 3:
2444 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
2445 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2446 break;
2447 case 4:
2448 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2449 break;
2450 case 8:
2451 /* CR8 contains the APIC TPR */
2452 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2453 break;
2454
2455 default:
2456 AssertFailed();
2457 break;
2458 }
2459 /* Check if a sync operation is pending. */
2460 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2461 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2462 {
2463 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2464 AssertRC(rc);
2465 }
2466 break;
2467
2468 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
2469 Log2(("VMX: mov x, crx\n"));
2470 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
2471
2472 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
2473
2474 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
2475 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2476
2477 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
2478 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
2479 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
2480 break;
2481
2482 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2483 Log2(("VMX: clts\n"));
2484 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
2485 rc = EMInterpretCLTS(pVM);
2486 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2487 break;
2488
2489 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2490 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2491 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
2492 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2493 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2494 break;
2495 }
2496
2497 /* Update EIP if no error occurred. */
2498 if (VBOX_SUCCESS(rc))
2499 pCtx->rip += cbInstr;
2500
2501 if (rc == VINF_SUCCESS)
2502 {
2503 /* Only resume if successful. */
2504 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2505 goto ResumeExecution;
2506 }
2507 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2508 break;
2509 }
2510
2511 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2512 {
2513 if (!DBGFIsStepping(pVM))
2514 {
2515 /* Disable drx move intercepts. */
2516 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2517 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2518 AssertRC(rc);
2519
2520 /* Save the host and load the guest debug state. */
2521 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
2522 AssertRC(rc);
2523
2524#ifdef VBOX_WITH_STATISTICS
2525 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
2526 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2527 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2528 else
2529 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2530#endif
2531
2532 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2533 goto ResumeExecution;
2534 }
2535
2536 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2537 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2538 {
2539 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2540 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2541 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2542 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2543 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2544 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2545 Log2(("DR7=%08x\n", pCtx->dr[7]));
2546 }
2547 else
2548 {
2549 Log2(("VMX: mov x, drx\n"));
2550 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2551 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2552 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2553 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2554 }
2555 /* Update EIP if no error occurred. */
2556 if (VBOX_SUCCESS(rc))
2557 pCtx->rip += cbInstr;
2558
2559 if (rc == VINF_SUCCESS)
2560 {
2561 /* Only resume if successful. */
2562 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2563 goto ResumeExecution;
2564 }
2565 Assert(rc == VERR_EM_INTERPRETER);
2566 break;
2567 }
2568
2569 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2570 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2571 {
2572 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2573 uint32_t uPort;
2574 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2575
2576 /** @todo necessary to make the distinction? */
2577 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2578 {
2579 uPort = pCtx->edx & 0xffff;
2580 }
2581 else
2582 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2583
2584 /* paranoia */
2585 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2586 {
2587 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2588 break;
2589 }
2590
2591 uint32_t cbSize = g_aIOSize[uIOWidth];
2592
2593 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2594 {
2595 /* ins/outs */
2596 uint32_t prefix = 0;
2597 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
2598 prefix |= PREFIX_REP;
2599
2600 if (fIOWrite)
2601 {
2602 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2603 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
2604 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2605 }
2606 else
2607 {
2608 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2609 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
2610 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2611 }
2612 }
2613 else
2614 {
2615 /* normal in/out */
2616 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
2617
2618 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2619
2620 if (fIOWrite)
2621 {
2622 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2623 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2624 }
2625 else
2626 {
2627 uint32_t u32Val = 0;
2628
2629 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2630 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2631 if (IOM_SUCCESS(rc))
2632 {
2633 /* Write back to the EAX register. */
2634 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2635 }
2636 }
2637 }
2638 /*
2639 * Handled the I/O return codes.
2640 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2641 */
2642 if (IOM_SUCCESS(rc))
2643 {
2644 /* Update EIP and continue execution. */
2645 pCtx->rip += cbInstr;
2646 if (RT_LIKELY(rc == VINF_SUCCESS))
2647 {
2648 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2649 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2650 {
2651 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxIOCheck);
2652 for (unsigned i=0;i<4;i++)
2653 {
2654 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2655
2656 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
2657 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2658 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2659 {
2660 uint64_t uDR6;
2661
2662 Assert(CPUMIsGuestDebugStateActive(pVM));
2663
2664 uDR6 = ASMGetDR6();
2665
2666 /* Clear all breakpoint status flags and set the one we just hit. */
2667 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2668 uDR6 |= (uint64_t)RT_BIT(i);
2669
2670 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2671 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2672 * the contents have been read.
2673 */
2674 ASMSetDR6(uDR6);
2675
2676 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2677 pCtx->dr[7] &= ~X86_DR7_GD;
2678
2679 /* Paranoia. */
2680 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2681 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2682 pCtx->dr[7] |= 0x400; /* must be one */
2683
2684 /* Resync DR7 */
2685 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2686 AssertRC(rc);
2687
2688 /* Construct inject info. */
2689 intInfo = X86_XCPT_DB;
2690 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2691 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2692
2693 Log(("Inject IO debug trap at %VGv\n", pCtx->rip));
2694 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
2695 AssertRC(rc);
2696
2697 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2698 goto ResumeExecution;
2699 }
2700 }
2701 }
2702
2703 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2704 goto ResumeExecution;
2705 }
2706 break;
2707 }
2708
2709#ifdef VBOX_STRICT
2710 if (rc == VINF_IOM_HC_IOPORT_READ)
2711 Assert(!fIOWrite);
2712 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2713 Assert(fIOWrite);
2714 else
2715 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2716#endif
2717 break;
2718 }
2719
2720 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2721 LogFlow(("VMX_EXIT_TPR\n"));
2722 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2723 goto ResumeExecution;
2724
2725 default:
2726 /* The rest is handled after syncing the entire CPU state. */
2727 break;
2728 }
2729
2730 /* Note: the guest state isn't entirely synced back at this stage. */
2731
2732 /* Investigate why there was a VM-exit. (part 2) */
2733 switch (exitReason)
2734 {
2735 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2736 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2737 case VMX_EXIT_EPT_VIOLATION:
2738 /* Already handled above. */
2739 break;
2740
2741 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2742 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2743 break;
2744
2745 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2746 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2747 rc = VINF_EM_RAW_INTERRUPT;
2748 AssertFailed(); /* Can't happen. Yet. */
2749 break;
2750
2751 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2752 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2753 rc = VINF_EM_RAW_INTERRUPT;
2754 AssertFailed(); /* Can't happen afaik. */
2755 break;
2756
2757 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2758 rc = VERR_EM_INTERPRETER;
2759 break;
2760
2761 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2762 /** Check if external interrupts are pending; if so, don't switch back. */
2763 pCtx->rip++; /* skip hlt */
2764 if ( pCtx->eflags.Bits.u1IF
2765 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2766 goto ResumeExecution;
2767
2768 rc = VINF_EM_HALT;
2769 break;
2770
2771 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2772 AssertFailed(); /* can't happen. */
2773 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2774 break;
2775
2776 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2777 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2778 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2779 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2780 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2781 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2782 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2783 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2784 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2785 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2786 /** @todo inject #UD immediately */
2787 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2788 break;
2789
2790 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2791 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2792 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2793 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2794 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2795 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2796 /* already handled above */
2797 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2798 || rc == VINF_EM_RAW_INTERRUPT
2799 || rc == VERR_EM_INTERPRETER
2800 || rc == VINF_EM_RAW_EMULATE_INSTR
2801 || rc == VINF_PGM_SYNC_CR3
2802 || rc == VINF_IOM_HC_IOPORT_READ
2803 || rc == VINF_IOM_HC_IOPORT_WRITE
2804 || rc == VINF_EM_RAW_GUEST_TRAP
2805 || rc == VINF_TRPM_XCPT_DISPATCHED
2806 || rc == VINF_EM_RESCHEDULE_REM,
2807 ("rc = %d\n", rc));
2808 break;
2809
2810 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2811 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2812 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2813 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2814 rc = VERR_EM_INTERPRETER;
2815 break;
2816
2817 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2818 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2819 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2820 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2821 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2822 break;
2823
2824 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2825 Assert(rc == VINF_EM_RAW_INTERRUPT);
2826 break;
2827
2828 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2829 {
2830#ifdef VBOX_STRICT
2831 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2832
2833 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2834 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2835
2836 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2837 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2838
2839 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2840 Log(("VMX_VMCS_GUEST_CR3 %VGp\n", val));
2841
2842 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2843 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2844
2845 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
2846 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
2847
2848 VMX_LOG_SELREG(CS, "CS");
2849 VMX_LOG_SELREG(DS, "DS");
2850 VMX_LOG_SELREG(ES, "ES");
2851 VMX_LOG_SELREG(FS, "FS");
2852 VMX_LOG_SELREG(GS, "GS");
2853 VMX_LOG_SELREG(SS, "SS");
2854 VMX_LOG_SELREG(TR, "TR");
2855 VMX_LOG_SELREG(LDTR, "LDTR");
2856
2857 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2858 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2859 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2860 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2861#endif /* VBOX_STRICT */
2862 rc = VERR_VMX_INVALID_GUEST_STATE;
2863 break;
2864 }
2865
2866 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2867 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2868 default:
2869 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
2870 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2871 break;
2872
2873 }
2874end:
2875
2876 /* Signal changes for the recompiler. */
2877 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2878
2879 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2880 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2881 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2882 {
2883 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2884 /* On the next entry we'll only sync the host context. */
2885 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2886 }
2887 else
2888 {
2889 /* On the next entry we'll sync everything. */
2890 /** @todo we can do better than this */
2891 /* Not in the VINF_PGM_CHANGE_MODE though! */
2892 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2893 }
2894
2895 /* translate into a less severe return code */
2896 if (rc == VERR_EM_INTERPRETER)
2897 rc = VINF_EM_RAW_EMULATE_INSTR;
2898 else
2899 /* Try to extract more information about what might have gone wrong here. */
2900 if (rc == VERR_VMX_INVALID_VMCS_PTR)
2901 {
2902 VMXGetActivateVMCS(&pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys);
2903 pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS;
2904 }
2905
2906 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2907
2908 Log2(("X"));
2909 return rc;
2910}
2911
2912
2913/**
2914 * Enters the VT-x session
2915 *
2916 * @returns VBox status code.
2917 * @param pVM The VM to operate on.
2918 * @param pCpu CPU info struct
2919 */
2920VMMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2921{
2922 Assert(pVM->hwaccm.s.vmx.fSupported);
2923
2924 unsigned cr4 = ASMGetCR4();
2925 if (!(cr4 & X86_CR4_VMXE))
2926 {
2927 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2928 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2929 }
2930
2931 /* Activate the VM Control Structure. */
2932 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2933 if (VBOX_FAILURE(rc))
2934 return rc;
2935
2936 pVM->hwaccm.s.vmx.fResumeVM = false;
2937 return VINF_SUCCESS;
2938}
2939
2940
2941/**
2942 * Leaves the VT-x session
2943 *
2944 * @returns VBox status code.
2945 * @param pVM The VM to operate on.
2946 * @param pCtx CPU context
2947 */
2948VMMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx)
2949{
2950 Assert(pVM->hwaccm.s.vmx.fSupported);
2951
2952 /* Save the guest debug state if necessary. */
2953 if (CPUMIsGuestDebugStateActive(pVM))
2954 {
2955 CPUMR0SaveGuestDebugState(pVM, pCtx, true /* save DR6 */);
2956
2957 /* Enable drx move intercepts again. */
2958 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2959 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2960 AssertRC(rc);
2961
2962 /* Resync the debug registers the next time. */
2963 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2964 }
2965 else
2966 Assert(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
2967
2968 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2969 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2970 AssertRC(rc);
2971
2972 return VINF_SUCCESS;
2973}
2974
2975/**
2976 * Flush the TLB (EPT)
2977 *
2978 * @returns VBox status code.
2979 * @param pVM The VM to operate on.
2980 * @param enmFlush Type of flush
2981 * @param GCPhys Physical address of the page to flush
2982 */
2983static void VMXR0FlushEPT(PVM pVM, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
2984{
2985 uint64_t descriptor[2];
2986
2987 LogFlow(("VMXR0FlushEPT %d %VGv\n", enmFlush, GCPhys));
2988 Assert(pVM->hwaccm.s.fNestedPaging);
2989 descriptor[0] = pVM->hwaccm.s.vmx.GCPhysEPTP;
2990 descriptor[1] = GCPhys;
2991 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
2992 AssertRC(rc);
2993}
2994
2995#ifdef HWACCM_VTX_WITH_VPID
2996/**
2997 * Flush the TLB (EPT)
2998 *
2999 * @returns VBox status code.
3000 * @param pVM The VM to operate on.
3001 * @param enmFlush Type of flush
3002 * @param GCPtr Virtual address of the page to flush
3003 */
3004static void VMXR0FlushVPID(PVM pVM, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3005{
3006 uint64_t descriptor[2];
3007
3008 Assert(pVM->hwaccm.s.vmx.fVPID);
3009 descriptor[0] = pVM->hwaccm.s.uCurrentASID;
3010 descriptor[1] = GCPtr;
3011 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3012 AssertRC(rc);
3013}
3014#endif /* HWACCM_VTX_WITH_VPID */
3015
3016/**
3017 * Invalidates a guest page
3018 *
3019 * @returns VBox status code.
3020 * @param pVM The VM to operate on.
3021 * @param GCVirt Page to invalidate
3022 */
3023VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
3024{
3025 bool fFlushPending = pVM->hwaccm.s.fForceTLBFlush;
3026
3027 /* @todo Only relevant if we want to use VPID. */
3028 Assert(!pVM->hwaccm.s.fNestedPaging);
3029
3030#ifdef HWACCM_VTX_WITH_VPID
3031 /* Skip it if a TLB flush is already pending. */
3032 if ( !fFlushPending
3033 && pVM->hwaccm.s.vmx.fVPID)
3034 VMXR0FlushVPID(pVM, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3035#endif /* HWACCM_VTX_WITH_VPID */
3036
3037 return VINF_SUCCESS;
3038}
3039
3040/**
3041 * Invalidates a guest page by physical address
3042 *
3043 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3044 *
3045 * @returns VBox status code.
3046 * @param pVM The VM to operate on.
3047 * @param GCPhys Page to invalidate
3048 */
3049VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
3050{
3051 bool fFlushPending = pVM->hwaccm.s.fForceTLBFlush;
3052
3053 Assert(pVM->hwaccm.s.fNestedPaging);
3054
3055 /* Skip it if a TLB flush is already pending. */
3056 if (!fFlushPending)
3057 VMXR0FlushEPT(pVM, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3058
3059 return VINF_SUCCESS;
3060}
3061
3062#ifdef VBOX_STRICT
3063/**
3064 * Report world switch error and dump some useful debug info
3065 *
3066 * @param pVM The VM to operate on.
3067 * @param rc Return code
3068 * @param pCtx Current CPU context (not updated)
3069 */
3070static void VMXR0ReportWorldSwitchError(PVM pVM, int rc, PCPUMCTX pCtx)
3071{
3072 switch (rc)
3073 {
3074 case VERR_VMX_INVALID_VMXON_PTR:
3075 AssertFailed();
3076 break;
3077
3078 case VERR_VMX_UNABLE_TO_START_VM:
3079 case VERR_VMX_UNABLE_TO_RESUME_VM:
3080 {
3081 int rc;
3082 RTCCUINTREG exitReason, instrError, val;
3083
3084 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
3085 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
3086 AssertRC(rc);
3087 if (rc == VINF_SUCCESS)
3088 {
3089 RTGDTR gdtr;
3090 PX86DESCHC pDesc;
3091
3092 ASMGetGDTR(&gdtr);
3093
3094 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3095 Log(("Current stack %08x\n", &rc));
3096
3097
3098 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
3099 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
3100 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3101 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3102 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3103 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3104 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3105 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3106 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3107 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3108
3109 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3110 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3111
3112 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3113 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
3114
3115 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3116 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3117
3118 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
3119 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3120
3121 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3122 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3123
3124 if (val < gdtr.cbGdt)
3125 {
3126 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3127 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3128 }
3129
3130 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
3131 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3132 if (val < gdtr.cbGdt)
3133 {
3134 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3135 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3136 }
3137
3138 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
3139 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3140 if (val < gdtr.cbGdt)
3141 {
3142 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3143 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3144 }
3145
3146 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
3147 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
3148 if (val < gdtr.cbGdt)
3149 {
3150 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3151 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3152 }
3153
3154 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
3155 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
3156 if (val < gdtr.cbGdt)
3157 {
3158 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3159 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3160 }
3161
3162 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
3163 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
3164 if (val < gdtr.cbGdt)
3165 {
3166 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3167 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3168 }
3169
3170 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
3171 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
3172 if (val < gdtr.cbGdt)
3173 {
3174 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3175 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3176 }
3177
3178 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3179 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
3180
3181 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3182 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
3183 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3184 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
3185
3186 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
3187 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3188
3189 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3190 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
3191
3192 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3193 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
3194
3195 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3196 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
3197 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3198 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
3199
3200#if HC_ARCH_BITS == 64
3201 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
3202 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
3203 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3204 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3205 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3206#endif
3207 }
3208 break;
3209 }
3210
3211 default:
3212 /* impossible */
3213 AssertFailed();
3214 break;
3215 }
3216}
3217#endif /* VBOX_STRICT */
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