VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 13200

Last change on this file since 13200 was 13200, checked in by vboxsync, 16 years ago

VMXR0InvalidatePage calls still occur in EPT mode.
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1/* $Id: HWVMXR0.cpp 13200 2008-10-13 09:27:44Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43/*******************************************************************************
44* Global Variables *
45*******************************************************************************/
46/* IO operation lookup arrays. */
47static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
48static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
49
50/*******************************************************************************
51* Local Functions *
52*******************************************************************************/
53#ifdef VBOX_STRICT
54static void VMXR0ReportWorldSwitchError(PVM pVM, int rc, PCPUMCTX pCtx);
55#else
56#define VMXR0ReportWorldSwitchError(a, b, c) do { } while (0);
57#endif /* VBOX_STRICT */
58static void vmxR0SetupTLBEPT(PVM pVM);
59static void vmxR0SetupTLBVPID(PVM pVM);
60static void vmxR0SetupTLBDummy(PVM pVM);
61static void vmxR0FlushEPT(PVM pVM, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
62static void vmxR0FlushVPID(PVM pVM, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
63
64
65static void VMXR0CheckError(PVM pVM, int rc)
66{
67 if (rc == VERR_VMX_GENERIC)
68 {
69 RTCCUINTREG instrError;
70
71 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
72 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
73 }
74 pVM->hwaccm.s.lLastError = rc;
75}
76
77/**
78 * Sets up and activates VT-x on the current CPU
79 *
80 * @returns VBox status code.
81 * @param pCpu CPU info struct
82 * @param pVM The VM to operate on.
83 * @param pvPageCpu Pointer to the global cpu page
84 * @param pPageCpuPhys Physical address of the global cpu page
85 */
86VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
87{
88 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
89 AssertReturn(pVM, VERR_INVALID_PARAMETER);
90 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
91
92 /* Setup Intel VMX. */
93 Assert(pVM->hwaccm.s.vmx.fSupported);
94
95#ifdef LOG_ENABLED
96 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
97#endif
98 /* Set revision dword at the beginning of the VMXON structure. */
99 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
100
101 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
102 * (which can have very bad consequences!!!)
103 */
104
105 /* Make sure the VMX instructions don't cause #UD faults. */
106 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
107
108 /* Enter VMX Root Mode */
109 int rc = VMXEnable(pPageCpuPhys);
110 if (VBOX_FAILURE(rc))
111 {
112 VMXR0CheckError(pVM, rc);
113 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
114 return VERR_VMX_VMXON_FAILED;
115 }
116 return VINF_SUCCESS;
117}
118
119/**
120 * Deactivates VT-x on the current CPU
121 *
122 * @returns VBox status code.
123 * @param pCpu CPU info struct
124 * @param pvPageCpu Pointer to the global cpu page
125 * @param pPageCpuPhys Physical address of the global cpu page
126 */
127VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
128{
129 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
130 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
131
132 /* Leave VMX Root Mode. */
133 VMXDisable();
134
135 /* And clear the X86_CR4_VMXE bit */
136 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
137
138#ifdef LOG_ENABLED
139 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
140#endif
141 return VINF_SUCCESS;
142}
143
144/**
145 * Does Ring-0 per VM VT-x init.
146 *
147 * @returns VBox status code.
148 * @param pVM The VM to operate on.
149 */
150VMMR0DECL(int) VMXR0InitVM(PVM pVM)
151{
152 int rc;
153
154#ifdef LOG_ENABLED
155 SUPR0Printf("VMXR0InitVM %x\n", pVM);
156#endif
157 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
158 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
159
160
161 /* Allocate one page for the VM control structure (VMCS). */
162 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
163 AssertRC(rc);
164 if (RT_FAILURE(rc))
165 return rc;
166
167 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
168 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
169 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
170
171 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
172 {
173 /* Allocate one page for the virtual APIC mmio cache. */
174 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
175 AssertRC(rc);
176 if (RT_FAILURE(rc))
177 return rc;
178
179 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
180 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
181 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
182 }
183 else
184 {
185 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
186 pVM->hwaccm.s.vmx.pAPIC = 0;
187 pVM->hwaccm.s.vmx.pAPICPhys = 0;
188 }
189
190 /* Allocate the MSR bitmap if this feature is supported. */
191 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
192 {
193 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
194 AssertRC(rc);
195 if (RT_FAILURE(rc))
196 return rc;
197
198 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
199 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
200 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
201 }
202
203 /* Current guest paging mode. */
204 pVM->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
205
206#ifdef LOG_ENABLED
207 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys);
208#endif
209 return VINF_SUCCESS;
210}
211
212/**
213 * Does Ring-0 per VM VT-x termination.
214 *
215 * @returns VBox status code.
216 * @param pVM The VM to operate on.
217 */
218VMMR0DECL(int) VMXR0TermVM(PVM pVM)
219{
220 if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
221 {
222 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
223 pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
224 pVM->hwaccm.s.vmx.pVMCS = 0;
225 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
226 }
227 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
228 {
229 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
230 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
231 pVM->hwaccm.s.vmx.pAPIC = 0;
232 pVM->hwaccm.s.vmx.pAPICPhys = 0;
233 }
234 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
235 {
236 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
237 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
238 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
239 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
240 }
241 return VINF_SUCCESS;
242}
243
244/**
245 * Sets up VT-x for the specified VM
246 *
247 * @returns VBox status code.
248 * @param pVM The VM to operate on.
249 */
250VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
251{
252 int rc = VINF_SUCCESS;
253 uint32_t val;
254
255 AssertReturn(pVM, VERR_INVALID_PARAMETER);
256 Assert(pVM->hwaccm.s.vmx.pVMCS);
257
258 /* Set revision dword at the beginning of the VMCS structure. */
259 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
260
261 /* Clear VM Control Structure. */
262 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
263 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
264 if (VBOX_FAILURE(rc))
265 goto vmx_end;
266
267 /* Activate the VM Control Structure. */
268 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
269 if (VBOX_FAILURE(rc))
270 goto vmx_end;
271
272 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
273 * Set required bits to one and zero according to the MSR capabilities.
274 */
275 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
276 /* External and non-maskable interrupts cause VM-exits. */
277 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
278 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
279
280 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
281 AssertRC(rc);
282
283 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
284 * Set required bits to one and zero according to the MSR capabilities.
285 */
286 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
287 /* Program which event cause VM-exits and which features we want to use. */
288 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
289 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
290 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
291 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
292 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
293
294 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
295 if (!pVM->hwaccm.s.fNestedPaging)
296 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
297 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
298 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
299
300 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
301
302#if HC_ARCH_BITS == 64
303 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
304 {
305 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
306 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
307 Assert(pVM->hwaccm.s.vmx.pAPIC);
308 }
309 else
310 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
311 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
312#endif
313
314#ifdef VBOX_WITH_VTX_MSR_BITMAPS
315 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
316 {
317 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
318 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
319 }
320#endif
321
322 /* We will use the secondary control if it's present. */
323 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
324
325 /* Mask away the bits that the CPU doesn't support */
326 /** @todo make sure they don't conflict with the above requirements. */
327 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
328 pVM->hwaccm.s.vmx.proc_ctls = val;
329
330 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
331 AssertRC(rc);
332
333 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
334 {
335 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
336 * Set required bits to one and zero according to the MSR capabilities.
337 */
338 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
339 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
340
341#ifdef HWACCM_VTX_WITH_EPT
342 if (pVM->hwaccm.s.fNestedPaging)
343 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
344#endif /* HWACCM_VTX_WITH_EPT */
345#ifdef HWACCM_VTX_WITH_VPID
346 else
347 if (pVM->hwaccm.s.vmx.fVPID)
348 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
349#endif /* HWACCM_VTX_WITH_VPID */
350
351 /* Mask away the bits that the CPU doesn't support */
352 /** @todo make sure they don't conflict with the above requirements. */
353 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
354
355 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
356 AssertRC(rc);
357 }
358
359 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
360 * Set required bits to one and zero according to the MSR capabilities.
361 */
362 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
363 AssertRC(rc);
364
365 /* VMX_VMCS_CTRL_EXIT_CONTROLS
366 * Set required bits to one and zero according to the MSR capabilities.
367 */
368 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
369
370 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
371 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
372#if HC_ARCH_BITS == 64
373 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
374#else
375 /* else Must be zero when AMD64 is not available. */
376#endif
377 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
378 /* Don't acknowledge external interrupts on VM-exit. */
379 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
380 AssertRC(rc);
381
382 /* Forward all exception except #NM & #PF to the guest.
383 * We always need to check pagefaults since our shadow page table can be out of sync.
384 * And we always lazily sync the FPU & XMM state.
385 */
386
387 /** @todo Possible optimization:
388 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
389 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
390 * registers ourselves of course.
391 *
392 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
393 */
394 pVM->hwaccm.s.vmx.u32TrapMask = HWACCM_VMX_TRAP_MASK;
395#ifndef DEBUG
396 if (pVM->hwaccm.s.fNestedPaging)
397 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
398#endif
399 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
400 AssertRC(rc);
401
402 /* Don't filter page faults; all of them should cause a switch. */
403 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
404 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
405 AssertRC(rc);
406
407 /* Init TSC offset to zero. */
408 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
409#if HC_ARCH_BITS == 32
410 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
411#endif
412 AssertRC(rc);
413
414 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
415#if HC_ARCH_BITS == 32
416 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
417#endif
418 AssertRC(rc);
419
420 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
421#if HC_ARCH_BITS == 32
422 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
423#endif
424 AssertRC(rc);
425
426 /* Set the MSR bitmap address. */
427 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
428 {
429 /* Optional */
430 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
431#if HC_ARCH_BITS == 32
432 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, pVM->hwaccm.s.vmx.pMSRBitmapPhys >> 32ULL);
433#endif
434 AssertRC(rc);
435 }
436
437 /* Clear MSR controls. */
438 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
439 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
441#if HC_ARCH_BITS == 32
442 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
443 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
444 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
445#endif
446 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
447 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
448 AssertRC(rc);
449
450 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
451 {
452 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
453 /* Optional */
454 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
455 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
456#if HC_ARCH_BITS == 32
457 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32ULL);
458#endif
459 AssertRC(rc);
460 }
461
462 /* Set link pointer to -1. Not currently used. */
463#if HC_ARCH_BITS == 32
464 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
465 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
466#else
467 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
468#endif
469 AssertRC(rc);
470
471 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
472 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
473 AssertRC(rc);
474
475 /* Choose the right TLB setup function. */
476 if (pVM->hwaccm.s.fNestedPaging)
477 {
478 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
479
480 /* Default values for flushing. */
481 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
482 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
483
484 /* If the capabilities specify we can do more, then make use of it. */
485 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
486 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
487 else
488 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
489 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
490
491 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
492 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
493 }
494#ifdef HWACCM_VTX_WITH_VPID
495 else
496 if (pVM->hwaccm.s.vmx.fVPID)
497 {
498 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
499
500 /* Default values for flushing. */
501 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
502 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
503
504 /* If the capabilities specify we can do more, then make use of it. */
505 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
506 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
507 else
508 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
509 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
510
511 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
512 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
513 }
514#endif /* HWACCM_VTX_WITH_VPID */
515 else
516 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
517
518
519vmx_end:
520 VMXR0CheckError(pVM, rc);
521 return rc;
522}
523
524
525/**
526 * Injects an event (trap or external interrupt)
527 *
528 * @returns VBox status code.
529 * @param pVM The VM to operate on.
530 * @param pCtx CPU Context
531 * @param intInfo VMX interrupt info
532 * @param cbInstr Opcode length of faulting instruction
533 * @param errCode Error code (optional)
534 */
535static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
536{
537 int rc;
538
539#ifdef VBOX_STRICT
540 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
541 if (iGate == 0xE)
542 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
543 else
544 if (iGate < 0x20)
545 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
546 else
547 {
548 LogFlow(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
549 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
550 Assert(pCtx->eflags.u32 & X86_EFL_IF);
551 }
552#endif
553
554#ifdef HWACCM_VMX_EMULATE_REALMODE
555 if (CPUMIsGuestInRealModeEx(pCtx))
556 {
557 /* Injecting events doesn't work right with real mode emulation.
558 * (#GP if we try to inject external hardware interrupts)
559 * Fake an 'int x' instruction. Note that we need to take special precautions when
560 * the inject is interrupted as the normal pending event method seems to be broken in this case.
561 */
562 LogFlow(("Fake 'int %x' inject (real mode)\n", iGate));
563 /* Make sure the return address is set to the current IP. (ugly hack alert) */
564 pCtx->rip--;
565 cbInstr = 1;
566 intInfo = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo) | (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
567
568 pVM->hwaccm.s.vmx.RealMode.Event.intInfo = intInfo;
569 pVM->hwaccm.s.vmx.RealMode.Event.fPending = true;
570 pVM->hwaccm.s.vmx.RealMode.eip = pCtx->eip;
571 }
572#endif /* HWACCM_VMX_EMULATE_REALMODE */
573
574 /* Set event injection state. */
575 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
576
577 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
578 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
579
580 AssertRC(rc);
581 return rc;
582}
583
584
585/**
586 * Checks for pending guest interrupts and injects them
587 *
588 * @returns VBox status code.
589 * @param pVM The VM to operate on.
590 * @param pCtx CPU Context
591 */
592static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
593{
594 int rc;
595
596 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
597 if (pVM->hwaccm.s.Event.fPending)
598 {
599 Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
600 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
601 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
602 AssertRC(rc);
603
604 pVM->hwaccm.s.Event.fPending = false;
605 return VINF_SUCCESS;
606 }
607
608 /* When external interrupts are pending, we should exit the VM when IF is set. */
609 if ( !TRPMHasTrap(pVM)
610 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
611 {
612 if (!(pCtx->eflags.u32 & X86_EFL_IF))
613 {
614 if (!(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
615 {
616 LogFlow(("Enable irq window exit!\n"));
617 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
618 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
619 AssertRC(rc);
620 }
621 /* else nothing to do but wait */
622 }
623 else
624 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
625 {
626 uint8_t u8Interrupt;
627
628 rc = PDMGetInterrupt(pVM, &u8Interrupt);
629 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc cs:eip=%04X:%VGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, pCtx->rip));
630 if (VBOX_SUCCESS(rc))
631 {
632 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
633 AssertRC(rc);
634 }
635 else
636 {
637 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
638 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
639 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
640 /* Just continue */
641 }
642 }
643 else
644 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
645 }
646
647#ifdef VBOX_STRICT
648 if (TRPMHasTrap(pVM))
649 {
650 uint8_t u8Vector;
651 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
652 AssertRC(rc);
653 }
654#endif
655
656 if ( pCtx->eflags.u32 & X86_EFL_IF
657 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
658 && TRPMHasTrap(pVM)
659 )
660 {
661 uint8_t u8Vector;
662 int rc;
663 TRPMEVENT enmType;
664 RTGCUINTPTR intInfo;
665 RTGCUINT errCode;
666
667 /* If a new event is pending, then dispatch it now. */
668 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
669 AssertRC(rc);
670 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
671 Assert(enmType != TRPM_SOFTWARE_INT);
672
673 /* Clear the pending trap. */
674 rc = TRPMResetTrap(pVM);
675 AssertRC(rc);
676
677 intInfo = u8Vector;
678 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
679
680 if (enmType == TRPM_TRAP)
681 {
682 switch (u8Vector) {
683 case 8:
684 case 10:
685 case 11:
686 case 12:
687 case 13:
688 case 14:
689 case 17:
690 /* Valid error codes. */
691 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
692 break;
693 default:
694 break;
695 }
696 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
697 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
698 else
699 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
700 }
701 else
702 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
703
704 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
705 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
706 AssertRC(rc);
707 } /* if (interrupts can be dispatched) */
708
709 return VINF_SUCCESS;
710}
711
712/**
713 * Save the host state
714 *
715 * @returns VBox status code.
716 * @param pVM The VM to operate on.
717 */
718VMMR0DECL(int) VMXR0SaveHostState(PVM pVM)
719{
720 int rc = VINF_SUCCESS;
721
722 /*
723 * Host CPU Context
724 */
725 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
726 {
727 RTIDTR idtr;
728 RTGDTR gdtr;
729 RTSEL SelTR;
730 PX86DESCHC pDesc;
731 uintptr_t trBase;
732
733 /* Control registers */
734 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
735 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
736 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
737 AssertRC(rc);
738 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
739 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
740 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
741
742 /* Selector registers. */
743 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
744 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
745 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
746 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
747#if HC_ARCH_BITS == 32
748 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
749 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
750#endif
751 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
752 SelTR = ASMGetTR();
753 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
754 AssertRC(rc);
755 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
756 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
757 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
758 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
759 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
760 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
761 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
762
763 /* GDTR & IDTR */
764 ASMGetGDTR(&gdtr);
765 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
766 ASMGetIDTR(&idtr);
767 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
768 AssertRC(rc);
769 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
770 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
771
772 /* Save the base address of the TR selector. */
773 if (SelTR > gdtr.cbGdt)
774 {
775 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
776 return VERR_VMX_INVALID_HOST_STATE;
777 }
778
779 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
780#if HC_ARCH_BITS == 64
781 trBase = X86DESC64_BASE(*pDesc);
782#else
783 trBase = X86DESC_BASE(*pDesc);
784#endif
785 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
786 AssertRC(rc);
787 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
788
789 /* FS and GS base. */
790#if HC_ARCH_BITS == 64
791 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
792 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
793 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
794 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
795#endif
796 AssertRC(rc);
797
798 /* Sysenter MSRs. */
799 /** @todo expensive!! */
800 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
801 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
802#if HC_ARCH_BITS == 32
803 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
804 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
805 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
806 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
807#else
808 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
809 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
810 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
811 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
812#endif
813 AssertRC(rc);
814
815 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
816 }
817 return rc;
818}
819
820/**
821 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
822 *
823 * @param pVM The VM to operate on.
824 * @param pCtx Guest context
825 */
826static void vmxR0PrefetchPAEPdptrs(PVM pVM, PCPUMCTX pCtx)
827{
828 if (CPUMIsGuestInPAEModeEx(pCtx))
829 {
830 X86PDPE Pdpe;
831
832 for (unsigned i=0;i<4;i++)
833 {
834 Pdpe = PGMGstGetPaePDPtr(pVM, i);
835 int rc = VMXWriteVMCS(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
836#if HC_ARCH_BITS == 32
837 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_PDPTR0_FULL + i*2 + 1, Pdpe.u >> 32ULL);
838#endif
839 AssertRC(rc);
840 }
841 }
842}
843
844/**
845 * Loads the guest state
846 *
847 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
848 *
849 * @returns VBox status code.
850 * @param pVM The VM to operate on.
851 * @param pCtx Guest context
852 */
853VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
854{
855 int rc = VINF_SUCCESS;
856 RTGCUINTPTR val;
857 X86EFLAGS eflags;
858
859 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
860 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
861 {
862#ifdef HWACCM_VMX_EMULATE_REALMODE
863 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
864 if (pVM->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
865 {
866# define VTX_CORRECT_PROT_SEL(reg) \
867 { \
868 if ( pCtx->reg##Hid.u64Base == (pVM->hwaccm.s.vmx.RealMode.reg##Hid.u64Base & 0xfffff) \
869 && pCtx->reg == ((pVM->hwaccm.s.vmx.RealMode.reg##Hid.u64Base >> 4) & ~X86_SEL_RPL)) \
870 { \
871 pCtx->reg##Hid = pVM->hwaccm.s.vmx.RealMode.reg##Hid; \
872 pCtx->reg = pVM->hwaccm.s.vmx.RealMode.reg; \
873 } \
874 }
875
876 /* Correct weird requirements for switching to protected mode. */
877 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
878 && enmGuestMode >= PGMMODE_PROTECTED)
879 {
880 /* DPL of all hidden selector registers must match the current CPL (0). */
881 pCtx->csHid.Attr.n.u2Dpl = 0;
882 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
883
884 pCtx->dsHid.Attr.n.u2Dpl = 0;
885 pCtx->esHid.Attr.n.u2Dpl = 0;
886 pCtx->fsHid.Attr.n.u2Dpl = 0;
887 pCtx->gsHid.Attr.n.u2Dpl = 0;
888 pCtx->ssHid.Attr.n.u2Dpl = 0;
889
890 /* RPL of all selectors must match the current CPL (0). */
891 pCtx->cs &= ~X86_SEL_RPL;
892 pCtx->ds &= ~X86_SEL_RPL;
893 pCtx->es &= ~X86_SEL_RPL;
894 pCtx->fs &= ~X86_SEL_RPL;
895 pCtx->gs &= ~X86_SEL_RPL;
896 pCtx->ss &= ~X86_SEL_RPL;
897
898 if (pVM->hwaccm.s.vmx.RealMode.fValid)
899 {
900 VTX_CORRECT_PROT_SEL(ds);
901 VTX_CORRECT_PROT_SEL(es);
902 VTX_CORRECT_PROT_SEL(fs);
903 VTX_CORRECT_PROT_SEL(gs);
904 VTX_CORRECT_PROT_SEL(ss);
905 pVM->hwaccm.s.vmx.RealMode.fValid = false;
906 }
907 }
908 else
909 /* Switching from protected mode to real mode. */
910 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode >= PGMMODE_PROTECTED
911 && enmGuestMode == PGMMODE_REAL)
912 {
913 /* Save the original hidden selectors in case we need to restore them later on. */
914 pVM->hwaccm.s.vmx.RealMode.ds = pCtx->ds;
915 pVM->hwaccm.s.vmx.RealMode.dsHid = pCtx->dsHid;
916 pVM->hwaccm.s.vmx.RealMode.es = pCtx->es;
917 pVM->hwaccm.s.vmx.RealMode.esHid = pCtx->esHid;
918 pVM->hwaccm.s.vmx.RealMode.fs = pCtx->fs;
919 pVM->hwaccm.s.vmx.RealMode.fsHid = pCtx->fsHid;
920 pVM->hwaccm.s.vmx.RealMode.gs = pCtx->gs;
921 pVM->hwaccm.s.vmx.RealMode.gsHid = pCtx->gsHid;
922 pVM->hwaccm.s.vmx.RealMode.ss = pCtx->ss;
923 pVM->hwaccm.s.vmx.RealMode.ssHid = pCtx->ssHid;
924 pVM->hwaccm.s.vmx.RealMode.fValid = true;
925
926 /* The selector value & base must be adjusted or else... */
927 pCtx->cs = pCtx->csHid.u64Base >> 4;
928 pCtx->ds = pCtx->dsHid.u64Base >> 4;
929 pCtx->es = pCtx->esHid.u64Base >> 4;
930 pCtx->fs = pCtx->fsHid.u64Base >> 4;
931 pCtx->gs = pCtx->gsHid.u64Base >> 4;
932 pCtx->ss = pCtx->ssHid.u64Base >> 4;
933
934 /* The limit must also be adjusted. */
935 pCtx->csHid.u32Limit &= 0xffff;
936 pCtx->dsHid.u32Limit &= 0xffff;
937 pCtx->esHid.u32Limit &= 0xffff;
938 pCtx->fsHid.u32Limit &= 0xffff;
939 pCtx->gsHid.u32Limit &= 0xffff;
940 pCtx->ssHid.u32Limit &= 0xffff;
941
942 Assert(pCtx->csHid.u64Base <= 0xfffff);
943 Assert(pCtx->dsHid.u64Base <= 0xfffff);
944 Assert(pCtx->esHid.u64Base <= 0xfffff);
945 Assert(pCtx->fsHid.u64Base <= 0xfffff);
946 Assert(pCtx->gsHid.u64Base <= 0xfffff);
947 }
948 pVM->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
949 }
950 else
951 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
952 if ( CPUMIsGuestInRealModeEx(pCtx)
953 && pCtx->csHid.u64Base == 0xffff0000)
954 {
955 pCtx->csHid.u64Base = 0xf0000;
956 pCtx->cs = 0xf000;
957 }
958#endif /* HWACCM_VMX_EMULATE_REALMODE */
959
960 VMX_WRITE_SELREG(ES, es);
961 AssertRC(rc);
962
963 VMX_WRITE_SELREG(CS, cs);
964 AssertRC(rc);
965
966 VMX_WRITE_SELREG(SS, ss);
967 AssertRC(rc);
968
969 VMX_WRITE_SELREG(DS, ds);
970 AssertRC(rc);
971
972 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
973 VMX_WRITE_SELREG(FS, fs);
974 AssertRC(rc);
975
976 VMX_WRITE_SELREG(GS, gs);
977 AssertRC(rc);
978 }
979
980 /* Guest CPU context: LDTR. */
981 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
982 {
983 if (pCtx->ldtr == 0)
984 {
985 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
986 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
987 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
988 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
989 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
990 }
991 else
992 {
993 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
994 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
995 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
996 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
997 }
998 AssertRC(rc);
999 }
1000 /* Guest CPU context: TR. */
1001 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1002 {
1003#ifdef HWACCM_VMX_EMULATE_REALMODE
1004 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1005 if (CPUMIsGuestInRealModeEx(pCtx))
1006 {
1007 RTGCPHYS GCPhys;
1008
1009 /* We convert it here every time as pci regions could be reconfigured. */
1010 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1011 AssertRC(rc);
1012
1013 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, 0);
1014 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1015 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1016
1017 X86DESCATTR attr;
1018
1019 attr.u = 0;
1020 attr.n.u1Present = 1;
1021 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1022 val = attr.u;
1023 }
1024 else
1025#endif /* HWACCM_VMX_EMULATE_REALMODE */
1026 {
1027 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
1028 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1029 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
1030
1031 val = pCtx->trHid.Attr.u;
1032
1033 /* The TSS selector must be busy. */
1034 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1035 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1036 else
1037 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1038 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1039
1040 }
1041 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
1042 AssertRC(rc);
1043 }
1044 /* Guest CPU context: GDTR. */
1045 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1046 {
1047 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1048 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1049 AssertRC(rc);
1050 }
1051 /* Guest CPU context: IDTR. */
1052 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1053 {
1054 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1055 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1056 AssertRC(rc);
1057 }
1058
1059 /*
1060 * Sysenter MSRs (unconditional)
1061 */
1062 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1063 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1064 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1065 AssertRC(rc);
1066
1067 /* Control registers */
1068 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1069 {
1070 val = pCtx->cr0;
1071 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1072 Log2(("Guest CR0-shadow %08x\n", val));
1073 if (CPUMIsGuestFPUStateActive(pVM) == false)
1074 {
1075 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1076 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1077 }
1078 else
1079 {
1080 /** @todo check if we support the old style mess correctly. */
1081 if (!(val & X86_CR0_NE))
1082 {
1083 Log(("Forcing X86_CR0_NE!!!\n"));
1084
1085 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1086 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
1087 {
1088 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_MF);
1089 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1090 AssertRC(rc);
1091 pVM->hwaccm.s.fFPUOldStyleOverride = true;
1092 }
1093 }
1094
1095 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1096 }
1097 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1098 val |= X86_CR0_PE | X86_CR0_PG;
1099 if (pVM->hwaccm.s.fNestedPaging)
1100 {
1101 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1102 {
1103 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1104 pVM->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1105 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1106 }
1107 else
1108 {
1109 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1110 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1111 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1112 }
1113 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1114 AssertRC(rc);
1115 }
1116 else
1117 {
1118 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1119 val |= X86_CR0_WP;
1120 }
1121
1122 /* Always enable caching. */
1123 val &= ~(X86_CR0_CD|X86_CR0_NW);
1124
1125 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
1126 Log2(("Guest CR0 %08x\n", val));
1127 /* CR0 flags owned by the host; if the guests attempts to change them, then
1128 * the VM will exit.
1129 */
1130 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1131 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1132 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1133 | X86_CR0_TS
1134 | X86_CR0_ET /* Bit not restored during VM-exit! */
1135 | X86_CR0_CD /* Bit not restored during VM-exit! */
1136 | X86_CR0_NW /* Bit not restored during VM-exit! */
1137 | X86_CR0_NE
1138 | X86_CR0_MP;
1139 pVM->hwaccm.s.vmx.cr0_mask = val;
1140
1141 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1142 Log2(("Guest CR0-mask %08x\n", val));
1143 AssertRC(rc);
1144 }
1145 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1146 {
1147 /* CR4 */
1148 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1149 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1150 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1151 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1152
1153 if (!pVM->hwaccm.s.fNestedPaging)
1154 {
1155 switch(pVM->hwaccm.s.enmShadowMode)
1156 {
1157 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1158 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1159 case PGMMODE_32_BIT: /* 32-bit paging. */
1160 break;
1161
1162 case PGMMODE_PAE: /* PAE paging. */
1163 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1164 /** @todo use normal 32 bits paging */
1165 val |= X86_CR4_PAE;
1166 break;
1167
1168 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1169 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1170#ifdef VBOX_ENABLE_64_BITS_GUESTS
1171 break;
1172#else
1173 AssertFailed();
1174 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1175#endif
1176 default: /* shut up gcc */
1177 AssertFailed();
1178 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1179 }
1180 }
1181 else
1182 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1183 {
1184 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1185 val |= X86_CR4_PSE;
1186 /* Our identity mapping is a 32 bits page directory. */
1187 val &= ~X86_CR4_PAE;
1188 }
1189
1190#ifdef HWACCM_VMX_EMULATE_REALMODE
1191 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1192 if (CPUMIsGuestInRealModeEx(pCtx))
1193 val |= X86_CR4_VME;
1194#endif /* HWACCM_VMX_EMULATE_REALMODE */
1195
1196 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
1197 Log2(("Guest CR4 %08x\n", val));
1198 /* CR4 flags owned by the host; if the guests attempts to change them, then
1199 * the VM will exit.
1200 */
1201 val = 0
1202#ifdef HWACCM_VMX_EMULATE_REALMODE
1203 | X86_CR4_VME
1204#endif
1205 | X86_CR4_PAE
1206 | X86_CR4_PGE
1207 | X86_CR4_PSE
1208 | X86_CR4_VMXE;
1209 pVM->hwaccm.s.vmx.cr4_mask = val;
1210
1211 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1212 Log2(("Guest CR4-mask %08x\n", val));
1213 AssertRC(rc);
1214 }
1215
1216 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1217 {
1218 if (pVM->hwaccm.s.fNestedPaging)
1219 {
1220 AssertMsg(PGMGetEPTCR3(pVM) == PGMGetHyperCR3(pVM), ("%VHp vs %VHp\n", PGMGetEPTCR3(pVM), PGMGetHyperCR3(pVM)));
1221 pVM->hwaccm.s.vmx.GCPhysEPTP = PGMGetEPTCR3(pVM);
1222
1223 Assert(!(pVM->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1224 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1225 pVM->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1226 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1227
1228 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EPTP_FULL, pVM->hwaccm.s.vmx.GCPhysEPTP);
1229#if HC_ARCH_BITS == 32
1230 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EPTP_HIGH, (uint32_t)(pVM->hwaccm.s.vmx.GCPhysEPTP >> 32ULL));
1231#endif
1232 AssertRC(rc);
1233
1234 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1235 {
1236 RTGCPHYS GCPhys;
1237
1238 /* We convert it here every time as pci regions could be reconfigured. */
1239 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1240 AssertRC(rc);
1241
1242 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1243 * take care of the translation to host physical addresses.
1244 */
1245 val = GCPhys;
1246 }
1247 else
1248 {
1249 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1250 val = pCtx->cr3;
1251 /* Prefetch the four PDPT entries in PAE mode. */
1252 vmxR0PrefetchPAEPdptrs(pVM, pCtx);
1253 }
1254 }
1255 else
1256 {
1257 val = PGMGetHyperCR3(pVM);
1258 Assert(val);
1259 }
1260
1261 /* Save our shadow CR3 register. */
1262 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
1263 AssertRC(rc);
1264 }
1265
1266 /* Debug registers. */
1267 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1268 {
1269 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1270 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1271
1272 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1273 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1274 pCtx->dr[7] |= 0x400; /* must be one */
1275
1276 /* Resync DR7 */
1277 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
1278 AssertRC(rc);
1279
1280 /* Sync the debug state now if any breakpoint is armed. */
1281 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1282 && !CPUMIsGuestDebugStateActive(pVM)
1283 && !DBGFIsStepping(pVM))
1284 {
1285 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxArmed);
1286
1287 /* Disable drx move intercepts. */
1288 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1289 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1290 AssertRC(rc);
1291
1292 /* Save the host and load the guest debug state. */
1293 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
1294 AssertRC(rc);
1295 }
1296
1297 /* IA32_DEBUGCTL MSR. */
1298 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1299 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
1300 AssertRC(rc);
1301
1302 /** @todo do we really ever need this? */
1303 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1304 AssertRC(rc);
1305 }
1306
1307 /* EIP, ESP and EFLAGS */
1308 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
1309 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
1310 AssertRC(rc);
1311
1312 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1313 eflags = pCtx->eflags;
1314 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1315 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1316
1317#ifdef HWACCM_VMX_EMULATE_REALMODE
1318 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1319 if (CPUMIsGuestInRealModeEx(pCtx))
1320 {
1321 eflags.Bits.u1VM = 1;
1322 eflags.Bits.u2IOPL = 3;
1323 }
1324#endif /* HWACCM_VMX_EMULATE_REALMODE */
1325 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1326 AssertRC(rc);
1327
1328 /* TSC offset. */
1329 uint64_t u64TSCOffset;
1330
1331 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1332 {
1333 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1334 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1335#if HC_ARCH_BITS == 32
1336 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
1337#endif
1338 AssertRC(rc);
1339
1340 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1341 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1342 AssertRC(rc);
1343 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
1344 }
1345 else
1346 {
1347 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1348 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1349 AssertRC(rc);
1350 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
1351 }
1352
1353 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1354 * Set required bits to one and zero according to the MSR capabilities.
1355 */
1356 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1357 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1358 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1359
1360 /* 64 bits guest mode? */
1361 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1362 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1363 /* else Must be zero when AMD64 is not available. */
1364
1365 /* Mask away the bits that the CPU doesn't support */
1366 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1367 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1368 AssertRC(rc);
1369
1370 /* 64 bits guest mode? */
1371 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1372 {
1373#if !defined(VBOX_WITH_64_BITS_GUESTS) || HC_ARCH_BITS != 64
1374 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1375#else
1376 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1377#endif
1378 /* Unconditionally update these as wrmsr might have changed them. */
1379 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1380 AssertRC(rc);
1381 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1382 AssertRC(rc);
1383 }
1384 else
1385 {
1386 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1387 }
1388
1389#ifdef DEBUG
1390 /* Intercept X86_XCPT_DB if stepping is enabled */
1391 if (DBGFIsStepping(pVM))
1392 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_DB);
1393 else
1394 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_DB);
1395
1396 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1397#endif
1398
1399#ifdef VBOX_STRICT
1400 Assert(pVM->hwaccm.s.vmx.u32TrapMask & RT_BIT(X86_XCPT_GP));
1401#else
1402# ifdef HWACCM_VMX_EMULATE_REALMODE
1403 /* Intercept #GP faults in real mode to handle privileged instructions. */
1404 if (CPUMIsGuestInRealModeEx(pCtx))
1405 pVM->hwaccm.s.vmx.u32TrapMask |= RT_BIT(X86_XCPT_GP);
1406 else
1407 pVM->hwaccm.s.vmx.u32TrapMask &= ~RT_BIT(X86_XCPT_GP);
1408# endif /* HWACCM_VMX_EMULATE_REALMODE */
1409 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
1410 AssertRC(rc);
1411#endif
1412
1413 /* Done. */
1414 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1415
1416 return rc;
1417}
1418
1419/**
1420 * Syncs back the guest state
1421 *
1422 * @returns VBox status code.
1423 * @param pVM The VM to operate on.
1424 * @param pCtx Guest context
1425 */
1426DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, CPUMCTX *pCtx)
1427{
1428 RTCCUINTREG val, valShadow;
1429 RTGCUINTPTR uInterruptState;
1430 int rc;
1431
1432 /* Let's first sync back eip, esp, and eflags. */
1433 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1434 AssertRC(rc);
1435 pCtx->rip = val;
1436 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1437 AssertRC(rc);
1438 pCtx->rsp = val;
1439 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1440 AssertRC(rc);
1441 pCtx->eflags.u32 = val;
1442
1443 /* Take care of instruction fusing (sti, mov ss) */
1444 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1445 uInterruptState = val;
1446 if (uInterruptState != 0)
1447 {
1448 Assert(uInterruptState <= 2); /* only sti & mov ss */
1449 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1450 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1451 }
1452 else
1453 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1454
1455 /* Control registers. */
1456 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1457 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1458 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1459 CPUMSetGuestCR0(pVM, val);
1460
1461 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1462 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1463 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1464 CPUMSetGuestCR4(pVM, val);
1465
1466 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1467 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1468 if ( pVM->hwaccm.s.fNestedPaging
1469 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1470 {
1471 /* Can be updated behind our back in the nested paging case. */
1472 CPUMSetGuestCR2(pVM, ASMGetCR2());
1473
1474 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
1475
1476 if (val != pCtx->cr3)
1477 {
1478 CPUMSetGuestCR3(pVM, val);
1479 PGMUpdateCR3(pVM, val);
1480 }
1481 /* Prefetch the four PDPT entries in PAE mode. */
1482 vmxR0PrefetchPAEPdptrs(pVM, pCtx);
1483 }
1484
1485 /* Sync back DR7 here. */
1486 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1487 pCtx->dr[7] = val;
1488
1489 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1490 VMX_READ_SELREG(ES, es);
1491 VMX_READ_SELREG(SS, ss);
1492 VMX_READ_SELREG(CS, cs);
1493 VMX_READ_SELREG(DS, ds);
1494 VMX_READ_SELREG(FS, fs);
1495 VMX_READ_SELREG(GS, gs);
1496
1497 /*
1498 * System MSRs
1499 */
1500 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1501 pCtx->SysEnter.cs = val;
1502 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1503 pCtx->SysEnter.eip = val;
1504 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1505 pCtx->SysEnter.esp = val;
1506
1507 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1508 VMX_READ_SELREG(LDTR, ldtr);
1509
1510 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1511 pCtx->gdtr.cbGdt = val;
1512 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1513 pCtx->gdtr.pGdt = val;
1514
1515 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1516 pCtx->idtr.cbIdt = val;
1517 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1518 pCtx->idtr.pIdt = val;
1519
1520#ifdef HWACCM_VMX_EMULATE_REALMODE
1521 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1522 if (CPUMIsGuestInRealModeEx(pCtx))
1523 {
1524 /* Hide our emulation flags */
1525 pCtx->eflags.Bits.u1VM = 0;
1526 pCtx->eflags.Bits.u2IOPL = 0;
1527
1528 /* Force a TR resync every time in case we switch modes. */
1529 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1530 }
1531 else
1532#endif /* HWACCM_VMX_EMULATE_REALMODE */
1533 {
1534 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1535 VMX_READ_SELREG(TR, tr);
1536 }
1537 return VINF_SUCCESS;
1538}
1539
1540/**
1541 * Dummy placeholder
1542 *
1543 * @param pVM The VM to operate on.
1544 */
1545static void vmxR0SetupTLBDummy(PVM pVM)
1546{
1547 return;
1548}
1549
1550/**
1551 * Setup the tagged TLB for EPT
1552 *
1553 * @returns VBox status code.
1554 * @param pVM The VM to operate on.
1555 */
1556static void vmxR0SetupTLBEPT(PVM pVM)
1557{
1558 PHWACCM_CPUINFO pCpu;
1559
1560 Assert(pVM->hwaccm.s.fNestedPaging);
1561 Assert(!pVM->hwaccm.s.vmx.fVPID);
1562
1563 /* Deal with tagged TLBs if VPID or EPT is supported. */
1564 pCpu = HWACCMR0GetCurrentCpu();
1565 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1566 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1567 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1568 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1569 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1570 {
1571 /* Force a TLB flush on VM entry. */
1572 pVM->hwaccm.s.fForceTLBFlush = true;
1573 }
1574 else
1575 Assert(!pCpu->fFlushTLB);
1576
1577 pVM->hwaccm.s.idLastCpu = pCpu->idCpu;
1578 pCpu->fFlushTLB = false;
1579
1580 if (pVM->hwaccm.s.fForceTLBFlush)
1581 vmxR0FlushEPT(pVM, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1582
1583#ifdef VBOX_WITH_STATISTICS
1584 if (pVM->hwaccm.s.fForceTLBFlush)
1585 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
1586 else
1587 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
1588#endif
1589}
1590
1591#ifdef HWACCM_VTX_WITH_VPID
1592/**
1593 * Setup the tagged TLB for VPID
1594 *
1595 * @returns VBox status code.
1596 * @param pVM The VM to operate on.
1597 */
1598static void vmxR0SetupTLBVPID(PVM pVM)
1599{
1600 PHWACCM_CPUINFO pCpu;
1601
1602 Assert(pVM->hwaccm.s.vmx.fVPID);
1603 Assert(!pVM->hwaccm.s.fNestedPaging);
1604
1605 /* Deal with tagged TLBs if VPID or EPT is supported. */
1606 pCpu = HWACCMR0GetCurrentCpu();
1607 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1608 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1609 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1610 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1611 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1612 {
1613 /* Force a TLB flush on VM entry. */
1614 pVM->hwaccm.s.fForceTLBFlush = true;
1615 }
1616 else
1617 Assert(!pCpu->fFlushTLB);
1618
1619 pVM->hwaccm.s.idLastCpu = pCpu->idCpu;
1620
1621 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1622 if (pVM->hwaccm.s.fForceTLBFlush)
1623 {
1624 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1625 || pCpu->fFlushTLB)
1626 {
1627 pCpu->fFlushTLB = false;
1628 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1629 pCpu->cTLBFlushes++;
1630 }
1631 else
1632 {
1633 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
1634 pVM->hwaccm.s.fForceTLBFlush = false;
1635 }
1636
1637 pVM->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1638 pVM->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1639 }
1640 else
1641 {
1642 Assert(!pCpu->fFlushTLB);
1643
1644 if (!pCpu->uCurrentASID || !pVM->hwaccm.s.uCurrentASID)
1645 pVM->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1646 }
1647 AssertMsg(pVM->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1648 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1649 AssertMsg(pVM->hwaccm.s.uCurrentASID >= 1 && pVM->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVM->hwaccm.s.uCurrentASID));
1650
1651 int rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_VPID, pVM->hwaccm.s.uCurrentASID);
1652 AssertRC(rc);
1653
1654 if (pVM->hwaccm.s.fForceTLBFlush)
1655 vmxR0FlushVPID(pVM, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1656
1657#ifdef VBOX_WITH_STATISTICS
1658 if (pVM->hwaccm.s.fForceTLBFlush)
1659 STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
1660 else
1661 STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
1662#endif
1663}
1664#endif /* HWACCM_VTX_WITH_VPID */
1665
1666/**
1667 * Runs guest code in a VT-x VM.
1668 *
1669 * @returns VBox status code.
1670 * @param pVM The VM to operate on.
1671 * @param pCtx Guest context
1672 */
1673VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1674{
1675 int rc = VINF_SUCCESS;
1676 RTCCUINTREG val;
1677 RTCCUINTREG exitReason, instrError, cbInstr;
1678 RTGCUINTPTR exitQualification;
1679 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1680 RTGCUINTPTR errCode, instrInfo;
1681 bool fSyncTPR = false;
1682 PHWACCM_CPUINFO pCpu = 0;
1683 unsigned cResume = 0;
1684#ifdef VBOX_STRICT
1685 RTCPUID idCpuCheck;
1686#endif
1687
1688 Log2(("\nE"));
1689
1690 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1691
1692#ifdef VBOX_STRICT
1693 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1694 AssertRC(rc);
1695 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1696
1697 /* allowed zero */
1698 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1699 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1700
1701 /* allowed one */
1702 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1703 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1704
1705 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1706 AssertRC(rc);
1707 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1708
1709 /* allowed zero */
1710 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1711 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1712
1713 /* allowed one */
1714 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1715 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1716
1717 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1718 AssertRC(rc);
1719 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1720
1721 /* allowed zero */
1722 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1723 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1724
1725 /* allowed one */
1726 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1727 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1728
1729 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1730 AssertRC(rc);
1731 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1732
1733 /* allowed zero */
1734 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1735 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1736
1737 /* allowed one */
1738 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1739 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1740#endif
1741
1742 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1743 */
1744ResumeExecution:
1745 AssertMsg(pVM->hwaccm.s.idEnteredCpu == RTMpCpuId(),
1746 ("Expected %d, I'm %d; cResume=%d exitReason=%RTreg exitQualification=%RTreg\n",
1747 (int)pVM->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
1748
1749 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1750 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1751 {
1752 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1753 rc = VINF_EM_RAW_INTERRUPT;
1754 goto end;
1755 }
1756
1757 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1758 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1759 {
1760 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1761 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1762 {
1763 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1764 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1765 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1766 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1767 */
1768 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1769 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1770 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1771 AssertRC(rc);
1772 }
1773 }
1774 else
1775 {
1776 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1777 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1778 AssertRC(rc);
1779 }
1780
1781 /* Check for pending actions that force us to go back to ring 3. */
1782 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1783 {
1784 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1785 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1786 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1787 rc = VINF_EM_RAW_TO_R3;
1788 goto end;
1789 }
1790 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1791 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1792 {
1793 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1794 rc = VINF_EM_PENDING_REQUEST;
1795 goto end;
1796 }
1797
1798 /* When external interrupts are pending, we should exit the VM when IF is set. */
1799 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1800 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1801 if (VBOX_FAILURE(rc))
1802 {
1803 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1804 goto end;
1805 }
1806
1807 /** @todo check timers?? */
1808
1809 /* TPR caching using CR8 is only available in 64 bits mode */
1810 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1811 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1812 /**
1813 * @todo reduce overhead
1814 */
1815 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1816 && pVM->hwaccm.s.vmx.pAPIC)
1817 {
1818 /* TPR caching in CR8 */
1819 uint8_t u8TPR;
1820 bool fPending;
1821
1822 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1823 AssertRC(rc);
1824 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
1825 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1826
1827 /* Two options here:
1828 * - external interrupt pending, but masked by the TPR value.
1829 * -> a CR8 update that lower the current TPR value should cause an exit
1830 * - no pending interrupts
1831 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1832 */
1833 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1834 AssertRC(rc);
1835
1836 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
1837 fSyncTPR = true;
1838 }
1839
1840#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
1841 if ( pVM->hwaccm.s.fNestedPaging
1842# ifdef HWACCM_VTX_WITH_VPID
1843 || pVM->hwaccm.s.vmx.fVPID
1844# endif /* HWACCM_VTX_WITH_VPID */
1845 )
1846 {
1847 pCpu = HWACCMR0GetCurrentCpu();
1848 if ( pVM->hwaccm.s.idLastCpu != pCpu->idCpu
1849 || pVM->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1850 {
1851 if (pVM->hwaccm.s.idLastCpu != pCpu->idCpu)
1852 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.idLastCpu, pCpu->idCpu));
1853 else
1854 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1855 }
1856 if (pCpu->fFlushTLB)
1857 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1858 }
1859#endif
1860
1861 /*
1862 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1863 * (until the actual world switch)
1864 */
1865#ifdef VBOX_STRICT
1866 idCpuCheck = RTMpCpuId();
1867#endif
1868 /* Save the host state first. */
1869 rc = VMXR0SaveHostState(pVM);
1870 if (rc != VINF_SUCCESS)
1871 {
1872 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1873 goto end;
1874 }
1875 /* Load the guest state */
1876 rc = VMXR0LoadGuestState(pVM, pCtx);
1877 if (rc != VINF_SUCCESS)
1878 {
1879 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1880 goto end;
1881 }
1882
1883 /* Deal with tagged TLB setup and invalidation. */
1884 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM);
1885
1886 /* Non-register state Guest Context */
1887 /** @todo change me according to cpu state */
1888 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1889 AssertRC(rc);
1890
1891 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1892
1893 /* Manual save and restore:
1894 * - General purpose registers except RIP, RSP
1895 *
1896 * Trashed:
1897 * - CR2 (we don't care)
1898 * - LDTR (reset to 0)
1899 * - DRx (presumably not changed at all)
1900 * - DR7 (reset to 0x400)
1901 * - EFLAGS (reset to RT_BIT(1); not relevant)
1902 *
1903 */
1904
1905 /* All done! Let's start VM execution. */
1906 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1907#ifdef VBOX_STRICT
1908 Assert(idCpuCheck == RTMpCpuId());
1909#endif
1910 TMNotifyStartOfExecution(pVM);
1911 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1912 TMNotifyEndOfExecution(pVM);
1913
1914 /* In case we execute a goto ResumeExecution later on. */
1915 pVM->hwaccm.s.vmx.fResumeVM = true;
1916 pVM->hwaccm.s.fForceTLBFlush = false;
1917
1918 /*
1919 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1920 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1921 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1922 */
1923
1924 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1925 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1926
1927 if (rc != VINF_SUCCESS)
1928 {
1929 VMXR0ReportWorldSwitchError(pVM, rc, pCtx);
1930 goto end;
1931 }
1932 /* Success. Query the guest state and figure out what has happened. */
1933
1934 /* Investigate why there was a VM-exit. */
1935 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1936 STAM_COUNTER_INC(&pVM->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1937
1938 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1939 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1940 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1941 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1942 intInfo = val;
1943 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1944 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1945 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1946 instrInfo = val;
1947 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1948 exitQualification = val;
1949 AssertRC(rc);
1950
1951 /* Sync back the guest state */
1952 rc = VMXR0SaveGuestState(pVM, pCtx);
1953 AssertRC(rc);
1954
1955 /* Note! NOW IT'S SAFE FOR LOGGING! */
1956 Log2(("Raw exit reason %08x\n", exitReason));
1957
1958 /* Check if an injected event was interrupted prematurely. */
1959 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1960 AssertRC(rc);
1961#ifdef HWACCM_VMX_EMULATE_REALMODE
1962 /* For some reason injected software interrupts are ignored (not signalled as pending) when e.g. a shadow page fault occurs. */
1963 if ( CPUMIsGuestInRealModeEx(pCtx)
1964 && pVM->hwaccm.s.vmx.RealMode.eip == pCtx->eip
1965 && pVM->hwaccm.s.vmx.RealMode.Event.fPending)
1966 {
1967 Assert(!pVM->hwaccm.s.Event.fPending);
1968
1969 Log(("Pending real-mode inject %VX64 at %VGv\n", pVM->hwaccm.s.vmx.RealMode.Event.intInfo, pCtx->rip));
1970
1971 /* We faked an 'int x' instruction and messed with IP, so correct it here. */
1972 pCtx->rip++;
1973 pVM->hwaccm.s.Event.intInfo = pVM->hwaccm.s.vmx.RealMode.Event.intInfo;
1974 pVM->hwaccm.s.Event.fPending = true;
1975 }
1976 else
1977#endif /* HWACCM_VMX_EMULATE_REALMODE */
1978 {
1979 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1980 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1981 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1982 {
1983 pVM->hwaccm.s.Event.fPending = true;
1984 /* Error code present? */
1985 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1986 {
1987 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1988 AssertRC(rc);
1989 pVM->hwaccm.s.Event.errCode = val;
1990 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1991 }
1992 else
1993 {
1994 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1995 pVM->hwaccm.s.Event.errCode = 0;
1996 }
1997 }
1998 }
1999 pVM->hwaccm.s.vmx.RealMode.Event.fPending = false;
2000
2001#ifdef VBOX_STRICT
2002 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2003 HWACCMDumpRegs(pVM, pCtx);
2004#endif
2005
2006 Log2(("E%d", exitReason));
2007 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
2008 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
2009 Log2(("Interruption error code %d\n", errCode));
2010 Log2(("IntInfo = %08x\n", intInfo));
2011 Log2(("New EIP=%VGv\n", pCtx->rip));
2012
2013 if (fSyncTPR)
2014 {
2015 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
2016 AssertRC(rc);
2017 }
2018
2019 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2020 switch (exitReason)
2021 {
2022 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2023 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2024 {
2025 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2026
2027 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2028 {
2029 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2030 /* External interrupt; leave to allow it to be dispatched again. */
2031 rc = VINF_EM_RAW_INTERRUPT;
2032 break;
2033 }
2034 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2035 {
2036 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2037 /* External interrupt; leave to allow it to be dispatched again. */
2038 rc = VINF_EM_RAW_INTERRUPT;
2039 break;
2040
2041 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2042 AssertFailed(); /* can't come here; fails the first check. */
2043 break;
2044
2045 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2046 Assert(vector == 3 || vector == 4);
2047 /* no break */
2048 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2049 Log2(("Hardware/software interrupt %d\n", vector));
2050 switch (vector)
2051 {
2052 case X86_XCPT_NM:
2053 {
2054 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
2055
2056 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2057 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2058 rc = CPUMR0LoadGuestFPU(pVM, pCtx);
2059 if (rc == VINF_SUCCESS)
2060 {
2061 Assert(CPUMIsGuestFPUStateActive(pVM));
2062
2063 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
2064
2065 /* Continue execution. */
2066 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2067 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2068
2069 goto ResumeExecution;
2070 }
2071
2072 Log(("Forward #NM fault to the guest\n"));
2073 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
2074 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2075 AssertRC(rc);
2076 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2077 goto ResumeExecution;
2078 }
2079
2080 case X86_XCPT_PF: /* Page fault */
2081 {
2082#ifdef DEBUG
2083 if (pVM->hwaccm.s.fNestedPaging)
2084 { /* A genuine pagefault.
2085 * Forward the trap to the guest by injecting the exception and resuming execution.
2086 */
2087 Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2088
2089 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2090
2091 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
2092
2093 /* Now we must update CR2. */
2094 pCtx->cr2 = exitQualification;
2095 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2096 AssertRC(rc);
2097
2098 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2099 goto ResumeExecution;
2100 }
2101#endif
2102 Assert(!pVM->hwaccm.s.fNestedPaging);
2103
2104 Log2(("Page fault at %VGv error code %x\n", exitQualification, errCode));
2105 /* Exit qualification contains the linear address of the page fault. */
2106 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2107 TRPMSetErrorCode(pVM, errCode);
2108 TRPMSetFaultAddress(pVM, exitQualification);
2109
2110 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2111 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2112 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
2113 if (rc == VINF_SUCCESS)
2114 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2115 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
2116 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
2117
2118 TRPMResetTrap(pVM);
2119
2120 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2121 goto ResumeExecution;
2122 }
2123 else
2124 if (rc == VINF_EM_RAW_GUEST_TRAP)
2125 { /* A genuine pagefault.
2126 * Forward the trap to the guest by injecting the exception and resuming execution.
2127 */
2128 Log2(("Forward page fault to the guest\n"));
2129
2130 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
2131 /* The error code might have been changed. */
2132 errCode = TRPMGetErrorCode(pVM);
2133
2134 TRPMResetTrap(pVM);
2135
2136 /* Now we must update CR2. */
2137 pCtx->cr2 = exitQualification;
2138 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2139 AssertRC(rc);
2140
2141 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2142 goto ResumeExecution;
2143 }
2144#ifdef VBOX_STRICT
2145 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2146 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2147#endif
2148 /* Need to go back to the recompiler to emulate the instruction. */
2149 TRPMResetTrap(pVM);
2150 break;
2151 }
2152
2153 case X86_XCPT_MF: /* Floating point exception. */
2154 {
2155 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
2156 if (!(pCtx->cr0 & X86_CR0_NE))
2157 {
2158 /* old style FPU error reporting needs some extra work. */
2159 /** @todo don't fall back to the recompiler, but do it manually. */
2160 rc = VINF_EM_RAW_EMULATE_INSTR;
2161 break;
2162 }
2163 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
2164 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2165 AssertRC(rc);
2166
2167 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2168 goto ResumeExecution;
2169 }
2170
2171 case X86_XCPT_DB: /* Debug exception. */
2172 {
2173 uint64_t uDR6;
2174
2175 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2176 *
2177 * Exit qualification bits:
2178 * 3:0 B0-B3 which breakpoint condition was met
2179 * 12:4 Reserved (0)
2180 * 13 BD - debug register access detected
2181 * 14 BS - single step execution or branch taken
2182 * 63:15 Reserved (0)
2183 */
2184 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDB);
2185
2186 /* Note that we don't support guest and host-initiated debugging at the same time. */
2187 Assert(DBGFIsStepping(pVM));
2188
2189 uDR6 = X86_DR6_INIT_VAL;
2190 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2191 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
2192 if (rc == VINF_EM_RAW_GUEST_TRAP)
2193 {
2194 /** @todo this isn't working, but we'll never get here normally. */
2195
2196 /* Update DR6 here. */
2197 pCtx->dr[6] = uDR6;
2198
2199 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2200 pCtx->dr[7] &= ~X86_DR7_GD;
2201
2202 /* Paranoia. */
2203 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2204 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2205 pCtx->dr[7] |= 0x400; /* must be one */
2206
2207 /* Resync DR7 */
2208 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2209 AssertRC(rc);
2210
2211 Log(("Trap %x (debug) at %VGv exit qualification %VX64\n", vector, pCtx->rip, exitQualification));
2212 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2213 AssertRC(rc);
2214
2215 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2216 goto ResumeExecution;
2217 }
2218 /* Return to ring 3 to deal with the debug exit code. */
2219 break;
2220 }
2221
2222 case X86_XCPT_GP: /* General protection failure exception.*/
2223 {
2224 uint32_t cbSize;
2225
2226 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
2227#ifdef VBOX_STRICT
2228 if (!CPUMIsGuestInRealModeEx(pCtx))
2229 {
2230 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
2231 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2232 AssertRC(rc);
2233 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2234 goto ResumeExecution;
2235 }
2236#endif
2237 Assert(CPUMIsGuestInRealModeEx(pCtx));
2238
2239 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %VGv\n", pCtx->rip));
2240 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2241 if (rc == VINF_SUCCESS)
2242 {
2243 /* EIP has been updated already. */
2244
2245 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2246 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2247
2248 /* Only resume if successful. */
2249 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2250 goto ResumeExecution;
2251 }
2252 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Vrc\n", rc));
2253 break;
2254 }
2255
2256#ifdef VBOX_STRICT
2257 case X86_XCPT_DE: /* Divide error. */
2258 case X86_XCPT_UD: /* Unknown opcode exception. */
2259 case X86_XCPT_SS: /* Stack segment exception. */
2260 case X86_XCPT_NP: /* Segment not present exception. */
2261 {
2262 switch(vector)
2263 {
2264 case X86_XCPT_DE:
2265 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
2266 break;
2267 case X86_XCPT_UD:
2268 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
2269 break;
2270 case X86_XCPT_SS:
2271 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
2272 break;
2273 case X86_XCPT_NP:
2274 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
2275 break;
2276 }
2277
2278 Log(("Trap %x at %VGv error code %x\n", vector, pCtx->rip, errCode));
2279 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2280 AssertRC(rc);
2281
2282 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2283 goto ResumeExecution;
2284 }
2285#endif
2286 default:
2287 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2288 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2289 break;
2290 } /* switch (vector) */
2291
2292 break;
2293
2294 default:
2295 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2296 AssertFailed();
2297 break;
2298 }
2299
2300 break;
2301 }
2302
2303 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2304 {
2305 RTGCPHYS GCPhys;
2306
2307 Assert(pVM->hwaccm.s.fNestedPaging);
2308
2309#if HC_ARCH_BITS == 64
2310 rc = VMXReadVMCS(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2311 AssertRC(rc);
2312#else
2313 uint32_t val_hi;
2314 rc = VMXReadVMCS(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &val);
2315 AssertRC(rc);
2316 rc = VMXReadVMCS(VMX_VMCS_EXIT_PHYS_ADDR_HIGH, &val_hi);
2317 AssertRC(rc);
2318 GCPhys = RT_MAKE_U64(val, val_hi);
2319#endif
2320
2321 Assert(((exitQualification >> 7) & 3) != 2);
2322
2323 /* Determine the kind of violation. */
2324 errCode = 0;
2325 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2326 errCode |= X86_TRAP_PF_ID;
2327
2328 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2329 errCode |= X86_TRAP_PF_RW;
2330
2331 /* If the page is present, then it's a page level protection fault. */
2332 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2333 errCode |= X86_TRAP_PF_P;
2334
2335 Log(("EPT Page fault %x at %VGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2336
2337 /* GCPhys contains the guest physical address of the page fault. */
2338 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2339 TRPMSetErrorCode(pVM, errCode);
2340 TRPMSetFaultAddress(pVM, GCPhys);
2341
2342 /* Handle the pagefault trap for the nested shadow table. */
2343 rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2344 Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
2345 if (rc == VINF_SUCCESS)
2346 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2347 Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, exitQualification , errCode));
2348 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
2349
2350 TRPMResetTrap(pVM);
2351
2352 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2353 goto ResumeExecution;
2354 }
2355
2356#ifdef VBOX_STRICT
2357 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2358 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2359#endif
2360 /* Need to go back to the recompiler to emulate the instruction. */
2361 TRPMResetTrap(pVM);
2362 break;
2363 }
2364
2365 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2366 /* Clear VM-exit on IF=1 change. */
2367 LogFlow(("VMX_EXIT_IRQ_WINDOW %VGv pending=%d IF=%d\n", pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2368 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2369 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2370 AssertRC(rc);
2371 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
2372 goto ResumeExecution; /* we check for pending guest interrupts there */
2373
2374 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2375 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2376 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
2377 /* Skip instruction and continue directly. */
2378 pCtx->rip += cbInstr;
2379 /* Continue execution.*/
2380 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2381 goto ResumeExecution;
2382
2383 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2384 {
2385 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2386 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
2387 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
2388 if (rc == VINF_SUCCESS)
2389 {
2390 /* Update EIP and continue execution. */
2391 Assert(cbInstr == 2);
2392 pCtx->rip += cbInstr;
2393 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2394 goto ResumeExecution;
2395 }
2396 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
2397 rc = VINF_EM_RAW_EMULATE_INSTR;
2398 break;
2399 }
2400
2401 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2402 {
2403 Log2(("VMX: Rdtsc\n"));
2404 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
2405 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
2406 if (rc == VINF_SUCCESS)
2407 {
2408 /* Update EIP and continue execution. */
2409 Assert(cbInstr == 2);
2410 pCtx->rip += cbInstr;
2411 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2412 goto ResumeExecution;
2413 }
2414 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
2415 rc = VINF_EM_RAW_EMULATE_INSTR;
2416 break;
2417 }
2418
2419 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2420 {
2421 Log2(("VMX: invlpg\n"));
2422 Assert(!pVM->hwaccm.s.fNestedPaging);
2423
2424 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
2425 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
2426 if (rc == VINF_SUCCESS)
2427 {
2428 /* Update EIP and continue execution. */
2429 pCtx->rip += cbInstr;
2430 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2431 goto ResumeExecution;
2432 }
2433 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
2434 break;
2435 }
2436
2437 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2438 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2439 {
2440 uint32_t cbSize;
2441
2442 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2443 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
2444 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2445 if (rc == VINF_SUCCESS)
2446 {
2447 /* EIP has been updated already. */
2448
2449 /* Only resume if successful. */
2450 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2451 goto ResumeExecution;
2452 }
2453 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
2454 break;
2455 }
2456
2457 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2458 {
2459 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
2460 {
2461 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
2462 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
2463 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
2464 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
2465 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
2466 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
2467
2468 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
2469 {
2470 case 0:
2471 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
2472 break;
2473 case 2:
2474 break;
2475 case 3:
2476 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
2477 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2478 break;
2479 case 4:
2480 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2481 break;
2482 case 8:
2483 /* CR8 contains the APIC TPR */
2484 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2485 break;
2486
2487 default:
2488 AssertFailed();
2489 break;
2490 }
2491 /* Check if a sync operation is pending. */
2492 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2493 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2494 {
2495 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2496 AssertRC(rc);
2497 }
2498 break;
2499
2500 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
2501 Log2(("VMX: mov x, crx\n"));
2502 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
2503
2504 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
2505
2506 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
2507 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2508
2509 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
2510 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
2511 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
2512 break;
2513
2514 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2515 Log2(("VMX: clts\n"));
2516 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
2517 rc = EMInterpretCLTS(pVM);
2518 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2519 break;
2520
2521 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2522 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2523 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
2524 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2525 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2526 break;
2527 }
2528
2529 /* Update EIP if no error occurred. */
2530 if (VBOX_SUCCESS(rc))
2531 pCtx->rip += cbInstr;
2532
2533 if (rc == VINF_SUCCESS)
2534 {
2535 /* Only resume if successful. */
2536 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2537 goto ResumeExecution;
2538 }
2539 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2540 break;
2541 }
2542
2543 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2544 {
2545 if (!DBGFIsStepping(pVM))
2546 {
2547 /* Disable drx move intercepts. */
2548 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2549 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2550 AssertRC(rc);
2551
2552 /* Save the host and load the guest debug state. */
2553 rc = CPUMR0LoadGuestDebugState(pVM, pCtx, true /* include DR6 */);
2554 AssertRC(rc);
2555
2556#ifdef VBOX_WITH_STATISTICS
2557 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
2558 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2559 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2560 else
2561 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2562#endif
2563
2564 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2565 goto ResumeExecution;
2566 }
2567
2568 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2569 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2570 {
2571 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2572 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
2573 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2574 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2575 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2576 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2577 Log2(("DR7=%08x\n", pCtx->dr[7]));
2578 }
2579 else
2580 {
2581 Log2(("VMX: mov x, drx\n"));
2582 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
2583 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2584 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2585 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2586 }
2587 /* Update EIP if no error occurred. */
2588 if (VBOX_SUCCESS(rc))
2589 pCtx->rip += cbInstr;
2590
2591 if (rc == VINF_SUCCESS)
2592 {
2593 /* Only resume if successful. */
2594 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2595 goto ResumeExecution;
2596 }
2597 Assert(rc == VERR_EM_INTERPRETER);
2598 break;
2599 }
2600
2601 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2602 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2603 {
2604 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2605 uint32_t uPort;
2606 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2607
2608 /** @todo necessary to make the distinction? */
2609 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2610 {
2611 uPort = pCtx->edx & 0xffff;
2612 }
2613 else
2614 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2615
2616 /* paranoia */
2617 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2618 {
2619 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2620 break;
2621 }
2622
2623 uint32_t cbSize = g_aIOSize[uIOWidth];
2624
2625 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2626 {
2627 /* ins/outs */
2628 uint32_t prefix = 0;
2629 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
2630 prefix |= PREFIX_REP;
2631
2632 if (fIOWrite)
2633 {
2634 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2635 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
2636 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2637 }
2638 else
2639 {
2640 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
2641 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
2642 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
2643 }
2644 }
2645 else
2646 {
2647 /* normal in/out */
2648 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
2649
2650 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2651
2652 if (fIOWrite)
2653 {
2654 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
2655 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2656 }
2657 else
2658 {
2659 uint32_t u32Val = 0;
2660
2661 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
2662 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2663 if (IOM_SUCCESS(rc))
2664 {
2665 /* Write back to the EAX register. */
2666 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2667 }
2668 }
2669 }
2670 /*
2671 * Handled the I/O return codes.
2672 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2673 */
2674 if (IOM_SUCCESS(rc))
2675 {
2676 /* Update EIP and continue execution. */
2677 pCtx->rip += cbInstr;
2678 if (RT_LIKELY(rc == VINF_SUCCESS))
2679 {
2680 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2681 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2682 {
2683 STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxIOCheck);
2684 for (unsigned i=0;i<4;i++)
2685 {
2686 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2687
2688 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
2689 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2690 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2691 {
2692 uint64_t uDR6;
2693
2694 Assert(CPUMIsGuestDebugStateActive(pVM));
2695
2696 uDR6 = ASMGetDR6();
2697
2698 /* Clear all breakpoint status flags and set the one we just hit. */
2699 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2700 uDR6 |= (uint64_t)RT_BIT(i);
2701
2702 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2703 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2704 * the contents have been read.
2705 */
2706 ASMSetDR6(uDR6);
2707
2708 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2709 pCtx->dr[7] &= ~X86_DR7_GD;
2710
2711 /* Paranoia. */
2712 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2713 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2714 pCtx->dr[7] |= 0x400; /* must be one */
2715
2716 /* Resync DR7 */
2717 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
2718 AssertRC(rc);
2719
2720 /* Construct inject info. */
2721 intInfo = X86_XCPT_DB;
2722 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2723 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2724
2725 Log(("Inject IO debug trap at %VGv\n", pCtx->rip));
2726 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
2727 AssertRC(rc);
2728
2729 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2730 goto ResumeExecution;
2731 }
2732 }
2733 }
2734
2735 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2736 goto ResumeExecution;
2737 }
2738 break;
2739 }
2740
2741#ifdef VBOX_STRICT
2742 if (rc == VINF_IOM_HC_IOPORT_READ)
2743 Assert(!fIOWrite);
2744 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2745 Assert(fIOWrite);
2746 else
2747 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2748#endif
2749 break;
2750 }
2751
2752 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2753 LogFlow(("VMX_EXIT_TPR\n"));
2754 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2755 goto ResumeExecution;
2756
2757 default:
2758 /* The rest is handled after syncing the entire CPU state. */
2759 break;
2760 }
2761
2762 /* Note: the guest state isn't entirely synced back at this stage. */
2763
2764 /* Investigate why there was a VM-exit. (part 2) */
2765 switch (exitReason)
2766 {
2767 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2768 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2769 case VMX_EXIT_EPT_VIOLATION:
2770 /* Already handled above. */
2771 break;
2772
2773 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2774 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2775 break;
2776
2777 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2778 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2779 rc = VINF_EM_RAW_INTERRUPT;
2780 AssertFailed(); /* Can't happen. Yet. */
2781 break;
2782
2783 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2784 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2785 rc = VINF_EM_RAW_INTERRUPT;
2786 AssertFailed(); /* Can't happen afaik. */
2787 break;
2788
2789 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2790 rc = VERR_EM_INTERPRETER;
2791 break;
2792
2793 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2794 /** Check if external interrupts are pending; if so, don't switch back. */
2795 pCtx->rip++; /* skip hlt */
2796 if ( pCtx->eflags.Bits.u1IF
2797 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
2798 goto ResumeExecution;
2799
2800 rc = VINF_EM_HALT;
2801 break;
2802
2803 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2804 AssertFailed(); /* can't happen. */
2805 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2806 break;
2807
2808 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2809 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2810 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2811 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2812 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2813 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2814 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2815 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2816 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2817 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2818 /** @todo inject #UD immediately */
2819 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2820 break;
2821
2822 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2823 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2824 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2825 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2826 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2827 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2828 /* already handled above */
2829 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2830 || rc == VINF_EM_RAW_INTERRUPT
2831 || rc == VERR_EM_INTERPRETER
2832 || rc == VINF_EM_RAW_EMULATE_INSTR
2833 || rc == VINF_PGM_SYNC_CR3
2834 || rc == VINF_IOM_HC_IOPORT_READ
2835 || rc == VINF_IOM_HC_IOPORT_WRITE
2836 || rc == VINF_EM_RAW_GUEST_TRAP
2837 || rc == VINF_TRPM_XCPT_DISPATCHED
2838 || rc == VINF_EM_RESCHEDULE_REM,
2839 ("rc = %d\n", rc));
2840 break;
2841
2842 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2843 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2844 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2845 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2846 rc = VERR_EM_INTERPRETER;
2847 break;
2848
2849 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2850 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2851 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2852 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2853 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2854 break;
2855
2856 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2857 Assert(rc == VINF_EM_RAW_INTERRUPT);
2858 break;
2859
2860 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2861 {
2862#ifdef VBOX_STRICT
2863 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2864
2865 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2866 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2867
2868 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2869 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2870
2871 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2872 Log(("VMX_VMCS_GUEST_CR3 %VGp\n", val));
2873
2874 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2875 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2876
2877 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
2878 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
2879
2880 VMX_LOG_SELREG(CS, "CS");
2881 VMX_LOG_SELREG(DS, "DS");
2882 VMX_LOG_SELREG(ES, "ES");
2883 VMX_LOG_SELREG(FS, "FS");
2884 VMX_LOG_SELREG(GS, "GS");
2885 VMX_LOG_SELREG(SS, "SS");
2886 VMX_LOG_SELREG(TR, "TR");
2887 VMX_LOG_SELREG(LDTR, "LDTR");
2888
2889 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2890 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2891 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2892 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2893#endif /* VBOX_STRICT */
2894 rc = VERR_VMX_INVALID_GUEST_STATE;
2895 break;
2896 }
2897
2898 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2899 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2900 default:
2901 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
2902 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2903 break;
2904
2905 }
2906end:
2907
2908 /* Signal changes for the recompiler. */
2909 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2910
2911 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2912 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2913 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2914 {
2915 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2916 /* On the next entry we'll only sync the host context. */
2917 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2918 }
2919 else
2920 {
2921 /* On the next entry we'll sync everything. */
2922 /** @todo we can do better than this */
2923 /* Not in the VINF_PGM_CHANGE_MODE though! */
2924 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2925 }
2926
2927 /* translate into a less severe return code */
2928 if (rc == VERR_EM_INTERPRETER)
2929 rc = VINF_EM_RAW_EMULATE_INSTR;
2930 else
2931 /* Try to extract more information about what might have gone wrong here. */
2932 if (rc == VERR_VMX_INVALID_VMCS_PTR)
2933 {
2934 VMXGetActivateVMCS(&pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys);
2935 pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS;
2936 }
2937
2938 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2939
2940 Log2(("X"));
2941 return rc;
2942}
2943
2944
2945/**
2946 * Enters the VT-x session
2947 *
2948 * @returns VBox status code.
2949 * @param pVM The VM to operate on.
2950 * @param pCpu CPU info struct
2951 */
2952VMMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2953{
2954 Assert(pVM->hwaccm.s.vmx.fSupported);
2955
2956 unsigned cr4 = ASMGetCR4();
2957 if (!(cr4 & X86_CR4_VMXE))
2958 {
2959 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2960 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2961 }
2962
2963 /* Activate the VM Control Structure. */
2964 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2965 if (VBOX_FAILURE(rc))
2966 return rc;
2967
2968 pVM->hwaccm.s.vmx.fResumeVM = false;
2969 return VINF_SUCCESS;
2970}
2971
2972
2973/**
2974 * Leaves the VT-x session
2975 *
2976 * @returns VBox status code.
2977 * @param pVM The VM to operate on.
2978 * @param pCtx CPU context
2979 */
2980VMMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx)
2981{
2982 Assert(pVM->hwaccm.s.vmx.fSupported);
2983
2984 /* Save the guest debug state if necessary. */
2985 if (CPUMIsGuestDebugStateActive(pVM))
2986 {
2987 CPUMR0SaveGuestDebugState(pVM, pCtx, true /* save DR6 */);
2988
2989 /* Enable drx move intercepts again. */
2990 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2991 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
2992 AssertRC(rc);
2993
2994 /* Resync the debug registers the next time. */
2995 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2996 }
2997 else
2998 Assert(pVM->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
2999
3000 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3001 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
3002 AssertRC(rc);
3003
3004 return VINF_SUCCESS;
3005}
3006
3007/**
3008 * Flush the TLB (EPT)
3009 *
3010 * @returns VBox status code.
3011 * @param pVM The VM to operate on.
3012 * @param enmFlush Type of flush
3013 * @param GCPhys Physical address of the page to flush
3014 */
3015static void vmxR0FlushEPT(PVM pVM, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3016{
3017 uint64_t descriptor[2];
3018
3019 LogFlow(("vmxR0FlushEPT %d %VGv\n", enmFlush, GCPhys));
3020 Assert(pVM->hwaccm.s.fNestedPaging);
3021 descriptor[0] = pVM->hwaccm.s.vmx.GCPhysEPTP;
3022 descriptor[1] = GCPhys;
3023 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3024 AssertRC(rc);
3025}
3026
3027#ifdef HWACCM_VTX_WITH_VPID
3028/**
3029 * Flush the TLB (EPT)
3030 *
3031 * @returns VBox status code.
3032 * @param pVM The VM to operate on.
3033 * @param enmFlush Type of flush
3034 * @param GCPtr Virtual address of the page to flush
3035 */
3036static void vmxR0FlushVPID(PVM pVM, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3037{
3038 uint64_t descriptor[2];
3039
3040 Assert(pVM->hwaccm.s.vmx.fVPID);
3041 descriptor[0] = pVM->hwaccm.s.uCurrentASID;
3042 descriptor[1] = GCPtr;
3043 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3044 AssertRC(rc);
3045}
3046#endif /* HWACCM_VTX_WITH_VPID */
3047
3048/**
3049 * Invalidates a guest page
3050 *
3051 * @returns VBox status code.
3052 * @param pVM The VM to operate on.
3053 * @param GCVirt Page to invalidate
3054 */
3055VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
3056{
3057 bool fFlushPending = pVM->hwaccm.s.fForceTLBFlush;
3058
3059 /* Only relevant if we want to use VPID.
3060 * In the nested paging case we still see such calls, but
3061 * can safely ignore them. (e.g. after cr3 updates)
3062 */
3063#ifdef HWACCM_VTX_WITH_VPID
3064 /* Skip it if a TLB flush is already pending. */
3065 if ( !fFlushPending
3066 && pVM->hwaccm.s.vmx.fVPID)
3067 vmxR0FlushVPID(pVM, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3068#endif /* HWACCM_VTX_WITH_VPID */
3069
3070 return VINF_SUCCESS;
3071}
3072
3073/**
3074 * Invalidates a guest page by physical address
3075 *
3076 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3077 *
3078 * @returns VBox status code.
3079 * @param pVM The VM to operate on.
3080 * @param GCPhys Page to invalidate
3081 */
3082VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
3083{
3084 bool fFlushPending = pVM->hwaccm.s.fForceTLBFlush;
3085
3086 Assert(pVM->hwaccm.s.fNestedPaging);
3087
3088 /* Skip it if a TLB flush is already pending. */
3089 if (!fFlushPending)
3090 vmxR0FlushEPT(pVM, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3091
3092 return VINF_SUCCESS;
3093}
3094
3095#ifdef VBOX_STRICT
3096/**
3097 * Report world switch error and dump some useful debug info
3098 *
3099 * @param pVM The VM to operate on.
3100 * @param rc Return code
3101 * @param pCtx Current CPU context (not updated)
3102 */
3103static void VMXR0ReportWorldSwitchError(PVM pVM, int rc, PCPUMCTX pCtx)
3104{
3105 switch (rc)
3106 {
3107 case VERR_VMX_INVALID_VMXON_PTR:
3108 AssertFailed();
3109 break;
3110
3111 case VERR_VMX_UNABLE_TO_START_VM:
3112 case VERR_VMX_UNABLE_TO_RESUME_VM:
3113 {
3114 int rc;
3115 RTCCUINTREG exitReason, instrError, val;
3116
3117 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
3118 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
3119 AssertRC(rc);
3120 if (rc == VINF_SUCCESS)
3121 {
3122 RTGDTR gdtr;
3123 PX86DESCHC pDesc;
3124
3125 ASMGetGDTR(&gdtr);
3126
3127 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3128 Log(("Current stack %08x\n", &rc));
3129
3130
3131 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
3132 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
3133 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3134 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3135 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3136 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3137 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3138 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3139 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3140 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3141
3142 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3143 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3144
3145 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3146 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
3147
3148 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3149 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3150
3151 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
3152 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3153
3154 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3155 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3156
3157 if (val < gdtr.cbGdt)
3158 {
3159 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3160 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3161 }
3162
3163 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
3164 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3165 if (val < gdtr.cbGdt)
3166 {
3167 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3168 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3169 }
3170
3171 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
3172 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3173 if (val < gdtr.cbGdt)
3174 {
3175 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3176 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3177 }
3178
3179 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
3180 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
3181 if (val < gdtr.cbGdt)
3182 {
3183 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3184 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3185 }
3186
3187 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
3188 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
3189 if (val < gdtr.cbGdt)
3190 {
3191 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3192 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3193 }
3194
3195 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
3196 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
3197 if (val < gdtr.cbGdt)
3198 {
3199 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3200 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3201 }
3202
3203 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
3204 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
3205 if (val < gdtr.cbGdt)
3206 {
3207 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3208 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3209 }
3210
3211 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3212 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
3213
3214 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3215 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
3216 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3217 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
3218
3219 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
3220 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3221
3222 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3223 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
3224
3225 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3226 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
3227
3228 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3229 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
3230 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3231 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
3232
3233#if HC_ARCH_BITS == 64
3234 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
3235 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
3236 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3237 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3238 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3239#endif
3240 }
3241 break;
3242 }
3243
3244 default:
3245 /* impossible */
3246 AssertFailed();
3247 break;
3248 }
3249}
3250#endif /* VBOX_STRICT */
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