VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 15981

Last change on this file since 15981 was 15981, checked in by vboxsync, 16 years ago

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1/* $Id: HWVMXR0.cpp 15981 2009-01-16 09:10:53Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43/*******************************************************************************
44* Defined Constants And Macros *
45*******************************************************************************/
46#if defined(RT_ARCH_AMD64)
47# define VMX_IS_64BIT_HOST_MODE() (true)
48#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
49# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
50#else
51# define VMX_IS_64BIT_HOST_MODE() (false)
52#endif
53
54/*******************************************************************************
55* Global Variables *
56*******************************************************************************/
57/* IO operation lookup arrays. */
58static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
59static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
60
61#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
62/** See HWACCMR0A.asm. */
63extern "C" uint32_t g_fVMXIs64bitHost;
64#endif
65
66/*******************************************************************************
67* Local Functions *
68*******************************************************************************/
69static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
70static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
71static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
72static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
73static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
74static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
75static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
76#ifdef VBOX_STRICT
77static bool vmxR0IsValidReadField(uint32_t idxField);
78static bool vmxR0IsValidWriteField(uint32_t idxField);
79#endif
80
81static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
82{
83 if (rc == VERR_VMX_GENERIC)
84 {
85 RTCCUINTREG instrError;
86
87 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
88 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
89 }
90 pVM->hwaccm.s.lLastError = rc;
91}
92
93/**
94 * Sets up and activates VT-x on the current CPU
95 *
96 * @returns VBox status code.
97 * @param pCpu CPU info struct
98 * @param pVM The VM to operate on. (can be NULL after a resume!!)
99 * @param pvPageCpu Pointer to the global cpu page
100 * @param pPageCpuPhys Physical address of the global cpu page
101 */
102VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
103{
104 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
105 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
106
107#ifdef LOG_ENABLED
108 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
109#endif
110 if (pVM)
111 {
112 /* Set revision dword at the beginning of the VMXON structure. */
113 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
114 }
115
116 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
117 * (which can have very bad consequences!!!)
118 */
119
120 /* Make sure the VMX instructions don't cause #UD faults. */
121 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
122
123 /* Enter VMX Root Mode */
124 int rc = VMXEnable(pPageCpuPhys);
125 if (RT_FAILURE(rc))
126 {
127 if (pVM)
128 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
129 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
130 return VERR_VMX_VMXON_FAILED;
131 }
132 return VINF_SUCCESS;
133}
134
135/**
136 * Deactivates VT-x on the current CPU
137 *
138 * @returns VBox status code.
139 * @param pCpu CPU info struct
140 * @param pvPageCpu Pointer to the global cpu page
141 * @param pPageCpuPhys Physical address of the global cpu page
142 */
143VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
144{
145 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
146 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
147
148 /* Leave VMX Root Mode. */
149 VMXDisable();
150
151 /* And clear the X86_CR4_VMXE bit */
152 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
153
154#ifdef LOG_ENABLED
155 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
156#endif
157 return VINF_SUCCESS;
158}
159
160/**
161 * Does Ring-0 per VM VT-x init.
162 *
163 * @returns VBox status code.
164 * @param pVM The VM to operate on.
165 */
166VMMR0DECL(int) VMXR0InitVM(PVM pVM)
167{
168 int rc;
169
170#ifdef LOG_ENABLED
171 SUPR0Printf("VMXR0InitVM %x\n", pVM);
172#endif
173
174 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
175
176 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
177 {
178 /* Allocate one page for the virtual APIC mmio cache. */
179 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
180 AssertRC(rc);
181 if (RT_FAILURE(rc))
182 return rc;
183
184 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
185 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
186 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
187 }
188 else
189 {
190 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
191 pVM->hwaccm.s.vmx.pAPIC = 0;
192 pVM->hwaccm.s.vmx.pAPICPhys = 0;
193 }
194
195 /* Allocate the MSR bitmap if this feature is supported. */
196 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
197 {
198 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
199 AssertRC(rc);
200 if (RT_FAILURE(rc))
201 return rc;
202
203 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
204 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
205 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
206 }
207
208#ifdef VBOX_WITH_CRASHDUMP_MAGIC
209 {
210 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
211 AssertRC(rc);
212 if (RT_FAILURE(rc))
213 return rc;
214
215 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
216 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
217
218 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
219 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
220 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
221 }
222#endif
223
224 /* Allocate VMCBs for all guest CPUs. */
225 for (unsigned i=0;i<pVM->cCPUs;i++)
226 {
227 PVMCPU pVCpu = &pVM->aCpus[i];
228
229 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
230
231 /* Allocate one page for the VM control structure (VMCS). */
232 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
233 AssertRC(rc);
234 if (RT_FAILURE(rc))
235 return rc;
236
237 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
238 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
239 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
240
241 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
242 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
243
244 /* Current guest paging mode. */
245 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
246
247#ifdef LOG_ENABLED
248 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
249#endif
250 }
251
252 return VINF_SUCCESS;
253}
254
255/**
256 * Does Ring-0 per VM VT-x termination.
257 *
258 * @returns VBox status code.
259 * @param pVM The VM to operate on.
260 */
261VMMR0DECL(int) VMXR0TermVM(PVM pVM)
262{
263 for (unsigned i=0;i<pVM->cCPUs;i++)
264 {
265 if (pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
266 {
267 RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, false);
268 pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
269 pVM->aCpus[i].hwaccm.s.vmx.pVMCS = 0;
270 pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys = 0;
271 }
272 }
273 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
274 {
275 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
276 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
277 pVM->hwaccm.s.vmx.pAPIC = 0;
278 pVM->hwaccm.s.vmx.pAPICPhys = 0;
279 }
280 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
281 {
282 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
283 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
284 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
285 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
286 }
287#ifdef VBOX_WITH_CRASHDUMP_MAGIC
288 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
289 {
290 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
291 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
292 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
293 pVM->hwaccm.s.vmx.pScratch = 0;
294 pVM->hwaccm.s.vmx.pScratchPhys = 0;
295 }
296#endif
297 return VINF_SUCCESS;
298}
299
300/**
301 * Sets up VT-x for the specified VM
302 *
303 * @returns VBox status code.
304 * @param pVM The VM to operate on.
305 */
306VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
307{
308 int rc = VINF_SUCCESS;
309 uint32_t val;
310
311 AssertReturn(pVM, VERR_INVALID_PARAMETER);
312
313 for (unsigned i=0;i<pVM->cCPUs;i++)
314 {
315 PVMCPU pVCpu = &pVM->aCpus[i];
316
317 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
318
319 /* Set revision dword at the beginning of the VMCS structure. */
320 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
321
322 /* Clear VM Control Structure. */
323 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
324 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
325 if (RT_FAILURE(rc))
326 goto vmx_end;
327
328 /* Activate the VM Control Structure. */
329 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
330 if (RT_FAILURE(rc))
331 goto vmx_end;
332
333 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
334 * Set required bits to one and zero according to the MSR capabilities.
335 */
336 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
337 /* External and non-maskable interrupts cause VM-exits. */
338 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
339 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
340
341 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
342 AssertRC(rc);
343
344 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
345 * Set required bits to one and zero according to the MSR capabilities.
346 */
347 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
348 /* Program which event cause VM-exits and which features we want to use. */
349 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
350 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
351 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
352 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
353 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
354 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
355
356 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
357 if (!pVM->hwaccm.s.fNestedPaging)
358 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
359 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
360 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
361
362 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
363 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
364 {
365 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
366 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
367 Assert(pVM->hwaccm.s.vmx.pAPIC);
368 }
369 else
370 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
371 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
372
373#ifdef VBOX_WITH_VTX_MSR_BITMAPS
374 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
375 {
376 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
377 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
378 }
379#endif
380
381 /* We will use the secondary control if it's present. */
382 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
383
384 /* Mask away the bits that the CPU doesn't support */
385 /** @todo make sure they don't conflict with the above requirements. */
386 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
387 pVCpu->hwaccm.s.vmx.proc_ctls = val;
388
389 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
390 AssertRC(rc);
391
392 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
393 {
394 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
395 * Set required bits to one and zero according to the MSR capabilities.
396 */
397 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
398 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
399
400#ifdef HWACCM_VTX_WITH_EPT
401 if (pVM->hwaccm.s.fNestedPaging)
402 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
403#endif /* HWACCM_VTX_WITH_EPT */
404#ifdef HWACCM_VTX_WITH_VPID
405 else
406 if (pVM->hwaccm.s.vmx.fVPID)
407 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
408#endif /* HWACCM_VTX_WITH_VPID */
409
410 /* Mask away the bits that the CPU doesn't support */
411 /** @todo make sure they don't conflict with the above requirements. */
412 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
413
414 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
415 AssertRC(rc);
416 }
417
418 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
419 * Set required bits to one and zero according to the MSR capabilities.
420 */
421 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
422 AssertRC(rc);
423
424 /* Forward all exception except #NM & #PF to the guest.
425 * We always need to check pagefaults since our shadow page table can be out of sync.
426 * And we always lazily sync the FPU & XMM state.
427 */
428
429 /** @todo Possible optimization:
430 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
431 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
432 * registers ourselves of course.
433 *
434 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
435 */
436
437 /* Don't filter page faults; all of them should cause a switch. */
438 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
439 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
440 AssertRC(rc);
441
442 /* Init TSC offset to zero. */
443 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
444 AssertRC(rc);
445
446 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
447 AssertRC(rc);
448
449 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
450 AssertRC(rc);
451
452 /* Set the MSR bitmap address. */
453 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
454 {
455 /* Optional */
456 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
457 AssertRC(rc);
458 }
459
460 /* Clear MSR controls. */
461 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
462 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
463 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
464 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
465 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
466 AssertRC(rc);
467
468 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
469 {
470 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
471 /* Optional */
472 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
473 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
474 AssertRC(rc);
475 }
476
477 /* Set link pointer to -1. Not currently used. */
478 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
479 AssertRC(rc);
480
481 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
482 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
483 AssertRC(rc);
484
485 /* Configure the VMCS read cache. */
486 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
487
488 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
489 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
490 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
491 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
492 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
493 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
494 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
495 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
496 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
497 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
498 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
499 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
500 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
501 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
502 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
503 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
504
505 VMX_SETUP_SELREG(ES, pCache);
506 VMX_SETUP_SELREG(SS, pCache);
507 VMX_SETUP_SELREG(CS, pCache);
508 VMX_SETUP_SELREG(DS, pCache);
509 VMX_SETUP_SELREG(FS, pCache);
510 VMX_SETUP_SELREG(GS, pCache);
511 VMX_SETUP_SELREG(LDTR, pCache);
512 VMX_SETUP_SELREG(TR, pCache);
513
514 /* Status code VMCS reads. */
515 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
516 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
517 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
518 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
524
525 if (pVM->hwaccm.s.fNestedPaging)
526 {
527 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
529 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
530 }
531 else
532 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
533 } /* for each VMCPU */
534
535 /* Choose the right TLB setup function. */
536 if (pVM->hwaccm.s.fNestedPaging)
537 {
538 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
539
540 /* Default values for flushing. */
541 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
542 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
543
544 /* If the capabilities specify we can do more, then make use of it. */
545 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
546 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
547 else
548 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
549 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
550
551 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
552 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
553 }
554#ifdef HWACCM_VTX_WITH_VPID
555 else
556 if (pVM->hwaccm.s.vmx.fVPID)
557 {
558 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
559
560 /* Default values for flushing. */
561 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
562 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
563
564 /* If the capabilities specify we can do more, then make use of it. */
565 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
566 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
567 else
568 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
569 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
570
571 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
572 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
573 }
574#endif /* HWACCM_VTX_WITH_VPID */
575 else
576 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
577
578vmx_end:
579 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
580 return rc;
581}
582
583
584/**
585 * Injects an event (trap or external interrupt)
586 *
587 * @returns VBox status code.
588 * @param pVM The VM to operate on.
589 * @param pVCpu The VMCPU to operate on.
590 * @param pCtx CPU Context
591 * @param intInfo VMX interrupt info
592 * @param cbInstr Opcode length of faulting instruction
593 * @param errCode Error code (optional)
594 */
595static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
596{
597 int rc;
598 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
599
600#ifdef VBOX_STRICT
601 if (iGate == 0xE)
602 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
603 else
604 if (iGate < 0x20)
605 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
606 else
607 {
608 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
609 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
610 Assert(pCtx->eflags.u32 & X86_EFL_IF);
611 }
612#endif
613
614#ifdef HWACCM_VMX_EMULATE_REALMODE
615 if (CPUMIsGuestInRealModeEx(pCtx))
616 {
617 RTGCPHYS GCPhysHandler;
618 uint16_t offset, ip;
619 RTSEL sel;
620
621 /* Injecting events doesn't work right with real mode emulation.
622 * (#GP if we try to inject external hardware interrupts)
623 * Inject the interrupt or trap directly instead.
624 */
625 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
626
627 /* Check if the interrupt handler is present. */
628 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
629 {
630 Log(("IDT cbIdt violation\n"));
631 if (iGate != X86_XCPT_DF)
632 {
633 RTGCUINTPTR intInfo;
634
635 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
636 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
637 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
638 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
639
640 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
641 }
642 Log(("Triple fault -> reset the VM!\n"));
643 return VINF_EM_RESET;
644 }
645 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
646 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
647 || iGate == 4)
648 {
649 ip = pCtx->ip + cbInstr;
650 }
651 else
652 ip = pCtx->ip;
653
654 /* Read the selector:offset pair of the interrupt handler. */
655 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
656 PGMPhysRead(pVM, GCPhysHandler, &offset, sizeof(offset));
657 PGMPhysRead(pVM, GCPhysHandler + 2, &sel, sizeof(sel));
658
659 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
660
661 /* Construct the stack frame. */
662 /** @todo should check stack limit. */
663 pCtx->sp -= 2;
664 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
665 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t));
666 pCtx->sp -= 2;
667 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
668 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t));
669 pCtx->sp -= 2;
670 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
671 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip));
672
673 /* Update the CPU state for executing the handler. */
674 pCtx->rip = offset;
675 pCtx->cs = sel;
676 pCtx->csHid.u64Base = sel << 4;
677 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
678
679 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
680 return VINF_SUCCESS;
681 }
682#endif /* HWACCM_VMX_EMULATE_REALMODE */
683
684 /* Set event injection state. */
685 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
686
687 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
688 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
689
690 AssertRC(rc);
691 return rc;
692}
693
694
695/**
696 * Checks for pending guest interrupts and injects them
697 *
698 * @returns VBox status code.
699 * @param pVM The VM to operate on.
700 * @param pVCpu The VMCPU to operate on.
701 * @param pCtx CPU Context
702 */
703static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
704{
705 int rc;
706
707 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
708 if (pVCpu->hwaccm.s.Event.fPending)
709 {
710 Log(("Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
711 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
712 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
713 AssertRC(rc);
714
715 pVCpu->hwaccm.s.Event.fPending = false;
716 return VINF_SUCCESS;
717 }
718
719 if (pVM->hwaccm.s.fInjectNMI)
720 {
721 RTGCUINTPTR intInfo;
722
723 intInfo = X86_XCPT_NMI;
724 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
725 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
726
727 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
728 AssertRC(rc);
729
730 pVM->hwaccm.s.fInjectNMI = false;
731 return VINF_SUCCESS;
732 }
733
734 /* When external interrupts are pending, we should exit the VM when IF is set. */
735 if ( !TRPMHasTrap(pVM)
736 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
737 {
738 if (!(pCtx->eflags.u32 & X86_EFL_IF))
739 {
740 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
741 {
742 LogFlow(("Enable irq window exit!\n"));
743 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
744 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
745 AssertRC(rc);
746 }
747 /* else nothing to do but wait */
748 }
749 else
750 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
751 {
752 uint8_t u8Interrupt;
753
754 rc = PDMGetInterrupt(pVM, &u8Interrupt);
755 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
756 if (RT_SUCCESS(rc))
757 {
758 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
759 AssertRC(rc);
760 }
761 else
762 {
763 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
764 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
765 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
766 /* Just continue */
767 }
768 }
769 else
770 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
771 }
772
773#ifdef VBOX_STRICT
774 if (TRPMHasTrap(pVM))
775 {
776 uint8_t u8Vector;
777 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
778 AssertRC(rc);
779 }
780#endif
781
782 if ( pCtx->eflags.u32 & X86_EFL_IF
783 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
784 && TRPMHasTrap(pVM)
785 )
786 {
787 uint8_t u8Vector;
788 int rc;
789 TRPMEVENT enmType;
790 RTGCUINTPTR intInfo;
791 RTGCUINT errCode;
792
793 /* If a new event is pending, then dispatch it now. */
794 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
795 AssertRC(rc);
796 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
797 Assert(enmType != TRPM_SOFTWARE_INT);
798
799 /* Clear the pending trap. */
800 rc = TRPMResetTrap(pVM);
801 AssertRC(rc);
802
803 intInfo = u8Vector;
804 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
805
806 if (enmType == TRPM_TRAP)
807 {
808 switch (u8Vector) {
809 case 8:
810 case 10:
811 case 11:
812 case 12:
813 case 13:
814 case 14:
815 case 17:
816 /* Valid error codes. */
817 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
818 break;
819 default:
820 break;
821 }
822 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
823 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
824 else
825 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
826 }
827 else
828 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
829
830 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
831 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
832 AssertRC(rc);
833 } /* if (interrupts can be dispatched) */
834
835 return VINF_SUCCESS;
836}
837
838/**
839 * Save the host state
840 *
841 * @returns VBox status code.
842 * @param pVM The VM to operate on.
843 * @param pVCpu The VMCPU to operate on.
844 */
845VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
846{
847 int rc = VINF_SUCCESS;
848
849 /*
850 * Host CPU Context
851 */
852 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
853 {
854 RTIDTR idtr;
855 RTGDTR gdtr;
856 RTSEL SelTR;
857 PX86DESCHC pDesc;
858 uintptr_t trBase;
859 RTSEL cs;
860 RTSEL ss;
861 uint64_t cr3;
862
863 /* Control registers */
864 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
865#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
866 if (VMX_IS_64BIT_HOST_MODE())
867 {
868 cr3 = hwaccmR0Get64bitCR3();
869 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
870 }
871 else
872#endif
873 {
874 cr3 = ASMGetCR3();
875 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
876 }
877 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
878 AssertRC(rc);
879 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
880 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
881 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
882
883 /* Selector registers. */
884#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
885 if (VMX_IS_64BIT_HOST_MODE())
886 {
887 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
888 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
889 }
890 else
891 {
892 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
893 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
894 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
895 }
896#else
897 cs = ASMGetCS();
898 ss = ASMGetSS();
899#endif
900 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
901 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
902 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
903 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
904 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
905 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
906#if HC_ARCH_BITS == 32
907 if (!VMX_IS_64BIT_HOST_MODE())
908 {
909 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
910 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
911 }
912#endif
913 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
914 SelTR = ASMGetTR();
915 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
916 AssertRC(rc);
917 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
918 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
919 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
920 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
921 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
922 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
923 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
924
925 /* GDTR & IDTR */
926#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
927 if (VMX_IS_64BIT_HOST_MODE())
928 {
929 X86XDTR64 gdtr64, idtr64;
930 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
931 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
932 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
933 AssertRC(rc);
934 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
935 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
936 gdtr.cbGdt = gdtr64.cb;
937 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
938 }
939 else
940#endif
941 {
942 ASMGetGDTR(&gdtr);
943 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
944 ASMGetIDTR(&idtr);
945 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
946 AssertRC(rc);
947 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
948 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
949 }
950
951
952 /* Save the base address of the TR selector. */
953 if (SelTR > gdtr.cbGdt)
954 {
955 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
956 return VERR_VMX_INVALID_HOST_STATE;
957 }
958
959#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
960 if (VMX_IS_64BIT_HOST_MODE())
961 {
962 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
963 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
964 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
965 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
966 AssertRC(rc);
967 }
968 else
969#endif
970 {
971 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
972#if HC_ARCH_BITS == 64
973 trBase = X86DESC64_BASE(*pDesc);
974#else
975 trBase = X86DESC_BASE(*pDesc);
976#endif
977 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
978 AssertRC(rc);
979 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
980 }
981
982 /* FS and GS base. */
983#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
984 if (VMX_IS_64BIT_HOST_MODE())
985 {
986 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
987 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
988 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
989 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
990 }
991#endif
992 AssertRC(rc);
993
994 /* Sysenter MSRs. */
995 /** @todo expensive!! */
996 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
997 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
998#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
999 if (VMX_IS_64BIT_HOST_MODE())
1000 {
1001 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1002 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1003 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1004 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1005 }
1006 else
1007 {
1008 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1009 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1010 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1011 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1012 }
1013#elif HC_ARCH_BITS == 32
1014 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1015 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1016 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1017 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1018#else
1019 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1020 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1021 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1022 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1023#endif
1024 AssertRC(rc);
1025
1026#if 0 /* @todo deal with 32/64 */
1027 /* Restore the host EFER - on CPUs that support it. */
1028 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1029 {
1030 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1031 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1032 AssertRC(rc);
1033 }
1034#endif
1035 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1036 }
1037 return rc;
1038}
1039
1040/**
1041 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1042 *
1043 * @param pVM The VM to operate on.
1044 * @param pVCpu The VMCPU to operate on.
1045 * @param pCtx Guest context
1046 */
1047static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1048{
1049 if (CPUMIsGuestInPAEModeEx(pCtx))
1050 {
1051 X86PDPE Pdpe;
1052
1053 for (unsigned i=0;i<4;i++)
1054 {
1055 Pdpe = PGMGstGetPaePDPtr(pVM, i);
1056 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1057 AssertRC(rc);
1058 }
1059 }
1060}
1061
1062/**
1063 * Update the exception bitmap according to the current CPU state
1064 *
1065 * @param pVM The VM to operate on.
1066 * @param pVCpu The VMCPU to operate on.
1067 * @param pCtx Guest context
1068 */
1069static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1070{
1071 uint32_t u32TrapMask;
1072 Assert(pCtx);
1073
1074 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1075#ifndef DEBUG
1076 if (pVM->hwaccm.s.fNestedPaging)
1077 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1078#endif
1079
1080 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1081 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1082 && !(pCtx->cr0 & X86_CR0_NE)
1083 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1084 {
1085 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1086 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1087 }
1088
1089#ifdef DEBUG
1090 /* Intercept X86_XCPT_DB if stepping is enabled */
1091 if (DBGFIsStepping(pVM))
1092 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1093#endif
1094
1095#ifdef VBOX_STRICT
1096 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1097#endif
1098
1099# ifdef HWACCM_VMX_EMULATE_REALMODE
1100 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1101 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1102 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1103# endif /* HWACCM_VMX_EMULATE_REALMODE */
1104
1105 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1106 AssertRC(rc);
1107}
1108
1109/**
1110 * Loads the guest state
1111 *
1112 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1113 *
1114 * @returns VBox status code.
1115 * @param pVM The VM to operate on.
1116 * @param pVCpu The VMCPU to operate on.
1117 * @param pCtx Guest context
1118 */
1119VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1120{
1121 int rc = VINF_SUCCESS;
1122 RTGCUINTPTR val;
1123 X86EFLAGS eflags;
1124
1125 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1126 * Set required bits to one and zero according to the MSR capabilities.
1127 */
1128 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1129 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1130 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1131#if 0 /* @todo deal with 32/64 */
1132 /* Required for the EFER write below, not supported on all CPUs. */
1133 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1134#endif
1135 /* 64 bits guest mode? */
1136 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1137 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1138 /* else Must be zero when AMD64 is not available. */
1139
1140 /* Mask away the bits that the CPU doesn't support */
1141 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1142 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1143 AssertRC(rc);
1144
1145 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1146 * Set required bits to one and zero according to the MSR capabilities.
1147 */
1148 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1149
1150 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1151#if 0 /* @todo deal with 32/64 */
1152 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1153#else
1154 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1155#endif
1156
1157#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1158 if (VMX_IS_64BIT_HOST_MODE())
1159 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1160 /* else: Must be zero when AMD64 is not available. */
1161#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1162 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1163 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1164 else
1165 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1166#endif
1167 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1168 /* Don't acknowledge external interrupts on VM-exit. */
1169 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1170 AssertRC(rc);
1171
1172 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1173 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1174 {
1175#ifdef HWACCM_VMX_EMULATE_REALMODE
1176 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1177 {
1178 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1179 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1180 {
1181 /* Correct weird requirements for switching to protected mode. */
1182 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1183 && enmGuestMode >= PGMMODE_PROTECTED)
1184 {
1185 /* DPL of all hidden selector registers must match the current CPL (0). */
1186 pCtx->csHid.Attr.n.u2Dpl = 0;
1187 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1188
1189 pCtx->dsHid.Attr.n.u2Dpl = 0;
1190 pCtx->esHid.Attr.n.u2Dpl = 0;
1191 pCtx->fsHid.Attr.n.u2Dpl = 0;
1192 pCtx->gsHid.Attr.n.u2Dpl = 0;
1193 pCtx->ssHid.Attr.n.u2Dpl = 0;
1194
1195 /* The limit must correspond to the granularity bit. */
1196 if (!pCtx->csHid.Attr.n.u1Granularity)
1197 pCtx->csHid.u32Limit &= 0xffff;
1198 if (!pCtx->dsHid.Attr.n.u1Granularity)
1199 pCtx->dsHid.u32Limit &= 0xffff;
1200 if (!pCtx->esHid.Attr.n.u1Granularity)
1201 pCtx->esHid.u32Limit &= 0xffff;
1202 if (!pCtx->fsHid.Attr.n.u1Granularity)
1203 pCtx->fsHid.u32Limit &= 0xffff;
1204 if (!pCtx->gsHid.Attr.n.u1Granularity)
1205 pCtx->gsHid.u32Limit &= 0xffff;
1206 if (!pCtx->ssHid.Attr.n.u1Granularity)
1207 pCtx->ssHid.u32Limit &= 0xffff;
1208 }
1209 else
1210 /* Switching from protected mode to real mode. */
1211 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1212 && enmGuestMode == PGMMODE_REAL)
1213 {
1214 /* The limit must also be set to 0xffff. */
1215 pCtx->csHid.u32Limit = 0xffff;
1216 pCtx->dsHid.u32Limit = 0xffff;
1217 pCtx->esHid.u32Limit = 0xffff;
1218 pCtx->fsHid.u32Limit = 0xffff;
1219 pCtx->gsHid.u32Limit = 0xffff;
1220 pCtx->ssHid.u32Limit = 0xffff;
1221
1222 Assert(pCtx->csHid.u64Base <= 0xfffff);
1223 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1224 Assert(pCtx->esHid.u64Base <= 0xfffff);
1225 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1226 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1227 }
1228 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1229 }
1230 else
1231 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1232 if ( CPUMIsGuestInRealModeEx(pCtx)
1233 && pCtx->csHid.u64Base == 0xffff0000)
1234 {
1235 pCtx->csHid.u64Base = 0xf0000;
1236 pCtx->cs = 0xf000;
1237 }
1238 }
1239#endif /* HWACCM_VMX_EMULATE_REALMODE */
1240
1241 VMX_WRITE_SELREG(ES, es);
1242 AssertRC(rc);
1243
1244 VMX_WRITE_SELREG(CS, cs);
1245 AssertRC(rc);
1246
1247 VMX_WRITE_SELREG(SS, ss);
1248 AssertRC(rc);
1249
1250 VMX_WRITE_SELREG(DS, ds);
1251 AssertRC(rc);
1252
1253 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1254 VMX_WRITE_SELREG(FS, fs);
1255 AssertRC(rc);
1256
1257 VMX_WRITE_SELREG(GS, gs);
1258 AssertRC(rc);
1259 }
1260
1261 /* Guest CPU context: LDTR. */
1262 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1263 {
1264 if (pCtx->ldtr == 0)
1265 {
1266 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1267 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1268 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1269 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1270 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1271 }
1272 else
1273 {
1274 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1275 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1276 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1277 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1278 }
1279 AssertRC(rc);
1280 }
1281 /* Guest CPU context: TR. */
1282 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1283 {
1284#ifdef HWACCM_VMX_EMULATE_REALMODE
1285 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1286 if (CPUMIsGuestInRealModeEx(pCtx))
1287 {
1288 RTGCPHYS GCPhys;
1289
1290 /* We convert it here every time as pci regions could be reconfigured. */
1291 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1292 AssertRC(rc);
1293
1294 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1295 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1296 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1297
1298 X86DESCATTR attr;
1299
1300 attr.u = 0;
1301 attr.n.u1Present = 1;
1302 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1303 val = attr.u;
1304 }
1305 else
1306#endif /* HWACCM_VMX_EMULATE_REALMODE */
1307 {
1308 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1309 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1310 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1311
1312 val = pCtx->trHid.Attr.u;
1313
1314 /* The TSS selector must be busy. */
1315 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1316 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1317 else
1318 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1319 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1320
1321 }
1322 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1323 AssertRC(rc);
1324 }
1325 /* Guest CPU context: GDTR. */
1326 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1327 {
1328 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1329 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1330 AssertRC(rc);
1331 }
1332 /* Guest CPU context: IDTR. */
1333 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1334 {
1335 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1336 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1337 AssertRC(rc);
1338 }
1339
1340 /*
1341 * Sysenter MSRs (unconditional)
1342 */
1343 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1344 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1345 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1346 AssertRC(rc);
1347
1348 /* Control registers */
1349 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1350 {
1351 val = pCtx->cr0;
1352 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1353 Log2(("Guest CR0-shadow %08x\n", val));
1354 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1355 {
1356 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1357 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1358 }
1359 else
1360 {
1361 /** @todo check if we support the old style mess correctly. */
1362 if (!(val & X86_CR0_NE))
1363 Log(("Forcing X86_CR0_NE!!!\n"));
1364
1365 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1366 }
1367 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1368 val |= X86_CR0_PE | X86_CR0_PG;
1369 if (pVM->hwaccm.s.fNestedPaging)
1370 {
1371 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1372 {
1373 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1374 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1375 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1376 }
1377 else
1378 {
1379 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1380 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1381 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1382 }
1383 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1384 AssertRC(rc);
1385 }
1386 else
1387 {
1388 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1389 val |= X86_CR0_WP;
1390 }
1391
1392 /* Always enable caching. */
1393 val &= ~(X86_CR0_CD|X86_CR0_NW);
1394
1395 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1396 Log2(("Guest CR0 %08x\n", val));
1397 /* CR0 flags owned by the host; if the guests attempts to change them, then
1398 * the VM will exit.
1399 */
1400 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1401 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1402 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1403 | X86_CR0_TS
1404 | X86_CR0_ET /* Bit not restored during VM-exit! */
1405 | X86_CR0_CD /* Bit not restored during VM-exit! */
1406 | X86_CR0_NW /* Bit not restored during VM-exit! */
1407 | X86_CR0_NE
1408 | X86_CR0_MP;
1409 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1410
1411 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1412 Log2(("Guest CR0-mask %08x\n", val));
1413 AssertRC(rc);
1414 }
1415 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1416 {
1417 /* CR4 */
1418 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1419 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1420 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1421 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1422
1423 if (!pVM->hwaccm.s.fNestedPaging)
1424 {
1425 switch(pVCpu->hwaccm.s.enmShadowMode)
1426 {
1427 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1428 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1429 case PGMMODE_32_BIT: /* 32-bit paging. */
1430 val &= ~X86_CR4_PAE;
1431 break;
1432
1433 case PGMMODE_PAE: /* PAE paging. */
1434 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1435 /** @todo use normal 32 bits paging */
1436 val |= X86_CR4_PAE;
1437 break;
1438
1439 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1440 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1441#ifdef VBOX_ENABLE_64_BITS_GUESTS
1442 break;
1443#else
1444 AssertFailed();
1445 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1446#endif
1447 default: /* shut up gcc */
1448 AssertFailed();
1449 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1450 }
1451 }
1452 else
1453 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1454 {
1455 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1456 val |= X86_CR4_PSE;
1457 /* Our identity mapping is a 32 bits page directory. */
1458 val &= ~X86_CR4_PAE;
1459 }
1460
1461#ifdef HWACCM_VMX_EMULATE_REALMODE
1462 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1463 if (CPUMIsGuestInRealModeEx(pCtx))
1464 val |= X86_CR4_VME;
1465#endif /* HWACCM_VMX_EMULATE_REALMODE */
1466
1467 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1468 Log2(("Guest CR4 %08x\n", val));
1469 /* CR4 flags owned by the host; if the guests attempts to change them, then
1470 * the VM will exit.
1471 */
1472 val = 0
1473#ifdef HWACCM_VMX_EMULATE_REALMODE
1474 | (pVM->hwaccm.s.vmx.pRealModeTSS ? X86_CR4_VME : 0)
1475#endif
1476 | X86_CR4_PAE
1477 | X86_CR4_PGE
1478 | X86_CR4_PSE
1479 | X86_CR4_VMXE;
1480 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1481
1482 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1483 Log2(("Guest CR4-mask %08x\n", val));
1484 AssertRC(rc);
1485 }
1486
1487 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1488 {
1489 if (pVM->hwaccm.s.fNestedPaging)
1490 {
1491 AssertMsg( PGMGetEPTCR3(pVM) == PGMGetHyperCR3(pVM)
1492 || VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
1493 ("%RHp vs %RHp\n", PGMGetEPTCR3(pVM), PGMGetHyperCR3(pVM)));
1494 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetEPTCR3(pVM);
1495
1496 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1497 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1498 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1499 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1500
1501 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1502 AssertRC(rc);
1503
1504 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1505 {
1506 RTGCPHYS GCPhys;
1507
1508 /* We convert it here every time as pci regions could be reconfigured. */
1509 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1510 AssertRC(rc);
1511
1512 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1513 * take care of the translation to host physical addresses.
1514 */
1515 val = GCPhys;
1516 }
1517 else
1518 {
1519 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1520 val = pCtx->cr3;
1521 /* Prefetch the four PDPT entries in PAE mode. */
1522 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1523 }
1524 }
1525 else
1526 {
1527 val = PGMGetHyperCR3(pVM);
1528 Assert(val || VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
1529 }
1530
1531 /* Save our shadow CR3 register. */
1532 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1533 AssertRC(rc);
1534 }
1535
1536 /* Debug registers. */
1537 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1538 {
1539 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1540 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1541
1542 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1543 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1544 pCtx->dr[7] |= 0x400; /* must be one */
1545
1546 /* Resync DR7 */
1547 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1548 AssertRC(rc);
1549
1550 /* Sync the debug state now if any breakpoint is armed. */
1551 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1552 && !CPUMIsGuestDebugStateActive(pVM)
1553 && !DBGFIsStepping(pVM))
1554 {
1555 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1556
1557 /* Disable drx move intercepts. */
1558 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1559 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1560 AssertRC(rc);
1561
1562 /* Save the host and load the guest debug state. */
1563 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1564 AssertRC(rc);
1565 }
1566
1567 /* IA32_DEBUGCTL MSR. */
1568 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1569 AssertRC(rc);
1570
1571 /** @todo do we really ever need this? */
1572 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1573 AssertRC(rc);
1574 }
1575
1576 /* EIP, ESP and EFLAGS */
1577 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1578 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1579 AssertRC(rc);
1580
1581 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1582 eflags = pCtx->eflags;
1583 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1584 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1585
1586#ifdef HWACCM_VMX_EMULATE_REALMODE
1587 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1588 if (CPUMIsGuestInRealModeEx(pCtx))
1589 {
1590 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1591
1592 eflags.Bits.u1VM = 1;
1593 eflags.Bits.u2IOPL = 3;
1594 }
1595#endif /* HWACCM_VMX_EMULATE_REALMODE */
1596 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1597 AssertRC(rc);
1598
1599 /* TSC offset. */
1600 uint64_t u64TSCOffset;
1601
1602 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1603 {
1604 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1605 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1606 AssertRC(rc);
1607
1608 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1609 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1610 AssertRC(rc);
1611 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1612 }
1613 else
1614 {
1615 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1616 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1617 AssertRC(rc);
1618 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1619 }
1620
1621 /* 64 bits guest mode? */
1622 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1623 {
1624#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1625 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1626#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1627 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1628#else
1629# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1630 if (!pVM->hwaccm.s.fAllow64BitGuests)
1631 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1632# endif
1633 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1634#endif
1635 /* Unconditionally update these as wrmsr might have changed them. */
1636 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1637 AssertRC(rc);
1638 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1639 AssertRC(rc);
1640 }
1641 else
1642 {
1643 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1644 }
1645
1646#if 0 /* @todo deal with 32/64 */
1647 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1648 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1649 {
1650 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1651 AssertRC(rc);
1652 }
1653#endif
1654
1655 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1656
1657 /* Done. */
1658 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1659
1660 return rc;
1661}
1662
1663/**
1664 * Syncs back the guest state
1665 *
1666 * @returns VBox status code.
1667 * @param pVM The VM to operate on.
1668 * @param pVCpu The VMCPU to operate on.
1669 * @param pCtx Guest context
1670 */
1671DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1672{
1673 RTGCUINTREG val, valShadow;
1674 RTGCUINTPTR uInterruptState;
1675 int rc;
1676
1677 /* Let's first sync back eip, esp, and eflags. */
1678 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1679 AssertRC(rc);
1680 pCtx->rip = val;
1681 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1682 AssertRC(rc);
1683 pCtx->rsp = val;
1684 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1685 AssertRC(rc);
1686 pCtx->eflags.u32 = val;
1687
1688 /* Take care of instruction fusing (sti, mov ss) */
1689 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1690 uInterruptState = val;
1691 if (uInterruptState != 0)
1692 {
1693 Assert(uInterruptState <= 2); /* only sti & mov ss */
1694 Log(("uInterruptState %x eip=%RGv\n", uInterruptState, pCtx->rip));
1695 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1696 }
1697 else
1698 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1699
1700 /* Control registers. */
1701 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1702 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1703 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1704 CPUMSetGuestCR0(pVM, val);
1705
1706 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1707 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1708 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1709 CPUMSetGuestCR4(pVM, val);
1710
1711 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1712 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1713 if ( pVM->hwaccm.s.fNestedPaging
1714 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1715 {
1716 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1717
1718 /* Can be updated behind our back in the nested paging case. */
1719 CPUMSetGuestCR2(pVM, pCache->cr2);
1720
1721 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1722
1723 if (val != pCtx->cr3)
1724 {
1725 CPUMSetGuestCR3(pVM, val);
1726 PGMUpdateCR3(pVM, val);
1727 }
1728 /* Prefetch the four PDPT entries in PAE mode. */
1729 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1730 }
1731
1732 /* Sync back DR7 here. */
1733 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1734 pCtx->dr[7] = val;
1735
1736 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1737 VMX_READ_SELREG(ES, es);
1738 VMX_READ_SELREG(SS, ss);
1739 VMX_READ_SELREG(CS, cs);
1740 VMX_READ_SELREG(DS, ds);
1741 VMX_READ_SELREG(FS, fs);
1742 VMX_READ_SELREG(GS, gs);
1743
1744 /*
1745 * System MSRs
1746 */
1747 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1748 pCtx->SysEnter.cs = val;
1749 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1750 pCtx->SysEnter.eip = val;
1751 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1752 pCtx->SysEnter.esp = val;
1753
1754 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1755 VMX_READ_SELREG(LDTR, ldtr);
1756
1757 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1758 pCtx->gdtr.cbGdt = val;
1759 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1760 pCtx->gdtr.pGdt = val;
1761
1762 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1763 pCtx->idtr.cbIdt = val;
1764 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1765 pCtx->idtr.pIdt = val;
1766
1767#ifdef HWACCM_VMX_EMULATE_REALMODE
1768 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1769 if (CPUMIsGuestInRealModeEx(pCtx))
1770 {
1771 /* Hide our emulation flags */
1772 pCtx->eflags.Bits.u1VM = 0;
1773 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1774
1775 /* Force a TR resync every time in case we switch modes. */
1776 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1777 }
1778 else
1779#endif /* HWACCM_VMX_EMULATE_REALMODE */
1780 {
1781 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1782 VMX_READ_SELREG(TR, tr);
1783 }
1784 return VINF_SUCCESS;
1785}
1786
1787/**
1788 * Dummy placeholder
1789 *
1790 * @param pVM The VM to operate on.
1791 * @param pVCpu The VMCPU to operate on.
1792 */
1793static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1794{
1795 NOREF(pVM);
1796 NOREF(pVCpu);
1797 return;
1798}
1799
1800/**
1801 * Setup the tagged TLB for EPT
1802 *
1803 * @returns VBox status code.
1804 * @param pVM The VM to operate on.
1805 * @param pVCpu The VMCPU to operate on.
1806 */
1807static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1808{
1809 PHWACCM_CPUINFO pCpu;
1810
1811 Assert(pVM->hwaccm.s.fNestedPaging);
1812 Assert(!pVM->hwaccm.s.vmx.fVPID);
1813
1814 /* Deal with tagged TLBs if VPID or EPT is supported. */
1815 pCpu = HWACCMR0GetCurrentCpu();
1816 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1817 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1818 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1819 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1820 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1821 {
1822 /* Force a TLB flush on VM entry. */
1823 pVCpu->hwaccm.s.fForceTLBFlush = true;
1824 }
1825 else
1826 Assert(!pCpu->fFlushTLB);
1827
1828 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1829 pCpu->fFlushTLB = false;
1830
1831 if (pVCpu->hwaccm.s.fForceTLBFlush)
1832 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1833
1834#ifdef VBOX_WITH_STATISTICS
1835 if (pVCpu->hwaccm.s.fForceTLBFlush)
1836 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1837 else
1838 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1839#endif
1840}
1841
1842#ifdef HWACCM_VTX_WITH_VPID
1843/**
1844 * Setup the tagged TLB for VPID
1845 *
1846 * @returns VBox status code.
1847 * @param pVM The VM to operate on.
1848 * @param pVCpu The VMCPU to operate on.
1849 */
1850static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1851{
1852 PHWACCM_CPUINFO pCpu;
1853
1854 Assert(pVM->hwaccm.s.vmx.fVPID);
1855 Assert(!pVM->hwaccm.s.fNestedPaging);
1856
1857 /* Deal with tagged TLBs if VPID or EPT is supported. */
1858 pCpu = HWACCMR0GetCurrentCpu();
1859 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1860 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1861 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1862 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1863 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1864 {
1865 /* Force a TLB flush on VM entry. */
1866 pVCpu->hwaccm.s.fForceTLBFlush = true;
1867 }
1868 else
1869 Assert(!pCpu->fFlushTLB);
1870
1871 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1872
1873 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1874 if (pVCpu->hwaccm.s.fForceTLBFlush)
1875 {
1876 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1877 || pCpu->fFlushTLB)
1878 {
1879 pCpu->fFlushTLB = false;
1880 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1881 pCpu->cTLBFlushes++;
1882 }
1883 else
1884 {
1885 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1886 pVCpu->hwaccm.s.fForceTLBFlush = false;
1887 }
1888
1889 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1890 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1891 }
1892 else
1893 {
1894 Assert(!pCpu->fFlushTLB);
1895
1896 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1897 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1898 }
1899 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1900 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1901 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1902
1903 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1904 AssertRC(rc);
1905
1906 if (pVCpu->hwaccm.s.fForceTLBFlush)
1907 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1908
1909#ifdef VBOX_WITH_STATISTICS
1910 if (pVCpu->hwaccm.s.fForceTLBFlush)
1911 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1912 else
1913 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1914#endif
1915}
1916#endif /* HWACCM_VTX_WITH_VPID */
1917
1918/**
1919 * Runs guest code in a VT-x VM.
1920 *
1921 * @returns VBox status code.
1922 * @param pVM The VM to operate on.
1923 * @param pVCpu The VMCPU to operate on.
1924 * @param pCtx Guest context
1925 */
1926VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1927{
1928 int rc = VINF_SUCCESS;
1929 RTGCUINTREG val;
1930 RTGCUINTREG exitReason, instrError, cbInstr;
1931 RTGCUINTPTR exitQualification;
1932 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1933 RTGCUINTPTR errCode, instrInfo;
1934 bool fSyncTPR = false;
1935 PHWACCM_CPUINFO pCpu = 0;
1936 unsigned cResume = 0;
1937#ifdef VBOX_STRICT
1938 RTCPUID idCpuCheck;
1939#endif
1940#ifdef VBOX_WITH_STATISTICS
1941 bool fStatEntryStarted = true;
1942 bool fStatExit2Started = false;
1943#endif
1944
1945 Log2(("\nE"));
1946
1947 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
1948
1949#ifdef VBOX_STRICT
1950 {
1951 RTCCUINTREG val;
1952
1953 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1954 AssertRC(rc);
1955 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1956
1957 /* allowed zero */
1958 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1959 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1960
1961 /* allowed one */
1962 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1963 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1964
1965 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1966 AssertRC(rc);
1967 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1968
1969 /* Must be set according to the MSR, but can be cleared in case of EPT. */
1970 if (pVM->hwaccm.s.fNestedPaging)
1971 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
1972 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1973 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1974
1975 /* allowed zero */
1976 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1977 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1978
1979 /* allowed one */
1980 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1981 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1982
1983 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1984 AssertRC(rc);
1985 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1986
1987 /* allowed zero */
1988 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1989 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1990
1991 /* allowed one */
1992 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1993 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1994
1995 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1996 AssertRC(rc);
1997 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1998
1999 /* allowed zero */
2000 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2001 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2002
2003 /* allowed one */
2004 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2005 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2006 }
2007#endif
2008
2009#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2010 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2011#endif
2012
2013 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2014 */
2015ResumeExecution:
2016 STAM_STATS({
2017 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2018 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2019 });
2020 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2021 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2022 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2023 Assert(!HWACCMR0SuspendPending());
2024
2025 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2026 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
2027 {
2028 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2029 rc = VINF_EM_RAW_INTERRUPT;
2030 goto end;
2031 }
2032
2033 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2034 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
2035 {
2036 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
2037 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
2038 {
2039 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2040 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2041 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2042 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2043 */
2044 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
2045 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2046 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2047 AssertRC(rc);
2048 }
2049 }
2050 else
2051 {
2052 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2053 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2054 AssertRC(rc);
2055 }
2056
2057 /* Check for pending actions that force us to go back to ring 3. */
2058 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
2059 {
2060 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
2061 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2062 rc = VINF_EM_RAW_TO_R3;
2063 goto end;
2064 }
2065 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2066 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
2067 {
2068 rc = VINF_EM_PENDING_REQUEST;
2069 goto end;
2070 }
2071
2072 /* When external interrupts are pending, we should exit the VM when IF is set. */
2073 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2074 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2075 if (RT_FAILURE(rc))
2076 goto end;
2077
2078 /** @todo check timers?? */
2079
2080 /* TPR caching using CR8 is only available in 64 bits mode */
2081 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2082 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2083 /**
2084 * @todo reduce overhead
2085 */
2086 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
2087 && pVM->hwaccm.s.vmx.pAPIC)
2088 {
2089 /* TPR caching in CR8 */
2090 uint8_t u8TPR;
2091 bool fPending;
2092
2093 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
2094 AssertRC(rc);
2095 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2096 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
2097
2098 /* Two options here:
2099 * - external interrupt pending, but masked by the TPR value.
2100 * -> a CR8 update that lower the current TPR value should cause an exit
2101 * - no pending interrupts
2102 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2103 */
2104 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
2105 AssertRC(rc);
2106
2107 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
2108 fSyncTPR = true;
2109 }
2110
2111#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2112 if ( pVM->hwaccm.s.fNestedPaging
2113# ifdef HWACCM_VTX_WITH_VPID
2114 || pVM->hwaccm.s.vmx.fVPID
2115# endif /* HWACCM_VTX_WITH_VPID */
2116 )
2117 {
2118 pCpu = HWACCMR0GetCurrentCpu();
2119 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2120 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2121 {
2122 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2123 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2124 else
2125 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2126 }
2127 if (pCpu->fFlushTLB)
2128 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2129 else
2130 if (pVCpu->hwaccm.s.fForceTLBFlush)
2131 LogFlow(("Manual TLB flush\n"));
2132 }
2133#endif
2134#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2135 PGMDynMapFlushAutoSet(pVCpu);
2136#endif
2137
2138 /*
2139 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2140 * (until the actual world switch)
2141 */
2142#ifdef VBOX_STRICT
2143 idCpuCheck = RTMpCpuId();
2144#endif
2145#ifdef LOG_LOGGING
2146 VMMR0LogFlushDisable(pVCpu);
2147#endif
2148 /* Save the host state first. */
2149 rc = VMXR0SaveHostState(pVM, pVCpu);
2150 if (rc != VINF_SUCCESS)
2151 goto end;
2152 /* Load the guest state */
2153 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2154 if (rc != VINF_SUCCESS)
2155 goto end;
2156
2157 /* Deal with tagged TLB setup and invalidation. */
2158 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2159
2160 /* Non-register state Guest Context */
2161 /** @todo change me according to cpu state */
2162 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2163 AssertRC(rc);
2164
2165 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2166
2167 /* Manual save and restore:
2168 * - General purpose registers except RIP, RSP
2169 *
2170 * Trashed:
2171 * - CR2 (we don't care)
2172 * - LDTR (reset to 0)
2173 * - DRx (presumably not changed at all)
2174 * - DR7 (reset to 0x400)
2175 * - EFLAGS (reset to RT_BIT(1); not relevant)
2176 *
2177 */
2178
2179
2180 /* All done! Let's start VM execution. */
2181 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2182#ifdef VBOX_STRICT
2183 Assert(idCpuCheck == RTMpCpuId());
2184#endif
2185
2186#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2187 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2188 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2189#endif
2190
2191 TMNotifyStartOfExecution(pVM);
2192 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2193 TMNotifyEndOfExecution(pVM);
2194
2195 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2196
2197 /* In case we execute a goto ResumeExecution later on. */
2198 pVCpu->hwaccm.s.fResumeVM = true;
2199 pVCpu->hwaccm.s.fForceTLBFlush = false;
2200
2201 /*
2202 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2203 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2204 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2205 */
2206 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2207 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2208
2209 if (rc != VINF_SUCCESS)
2210 {
2211 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2212 goto end;
2213 }
2214
2215 /* Success. Query the guest state and figure out what has happened. */
2216
2217 /* Investigate why there was a VM-exit. */
2218 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2219 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2220
2221 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2222 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2223 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2224 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2225 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2226 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2227 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2228 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2229 AssertRC(rc);
2230
2231 /* Sync back the guest state */
2232 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2233 AssertRC(rc);
2234
2235 /* Note! NOW IT'S SAFE FOR LOGGING! */
2236#ifdef LOG_LOGGING
2237 VMMR0LogFlushEnable(pVCpu);
2238#endif
2239 Log2(("Raw exit reason %08x\n", exitReason));
2240
2241 /* Check if an injected event was interrupted prematurely. */
2242 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2243 AssertRC(rc);
2244 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2245 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2246 /* Ignore 'int xx' as they'll be restarted anyway. */
2247 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2248 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2249 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2250 {
2251 pVCpu->hwaccm.s.Event.fPending = true;
2252 /* Error code present? */
2253 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2254 {
2255 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2256 AssertRC(rc);
2257 pVCpu->hwaccm.s.Event.errCode = val;
2258 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2259 }
2260 else
2261 {
2262 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2263 pVCpu->hwaccm.s.Event.errCode = 0;
2264 }
2265 }
2266#ifdef VBOX_STRICT
2267 else
2268 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2269 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2270 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2271 {
2272 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2273 }
2274
2275 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2276 HWACCMDumpRegs(pVM, pCtx);
2277#endif
2278
2279 Log2(("E%d", exitReason));
2280 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2281 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2282 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2283 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2284 Log2(("New EIP=%RGv\n", (RTGCPTR)pCtx->rip));
2285
2286 if (fSyncTPR)
2287 {
2288 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
2289 AssertRC(rc);
2290 }
2291
2292 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2293 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2294
2295 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2296 switch (exitReason)
2297 {
2298 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2299 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2300 {
2301 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2302
2303 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2304 {
2305 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2306 /* External interrupt; leave to allow it to be dispatched again. */
2307 rc = VINF_EM_RAW_INTERRUPT;
2308 break;
2309 }
2310 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2311 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2312 {
2313 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2314 /* External interrupt; leave to allow it to be dispatched again. */
2315 rc = VINF_EM_RAW_INTERRUPT;
2316 break;
2317
2318 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2319 AssertFailed(); /* can't come here; fails the first check. */
2320 break;
2321
2322 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2323 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2324 Assert(vector == 1 || vector == 3 || vector == 4);
2325 /* no break */
2326 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2327 Log2(("Hardware/software interrupt %d\n", vector));
2328 switch (vector)
2329 {
2330 case X86_XCPT_NM:
2331 {
2332 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2333
2334 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2335 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2336 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2337 if (rc == VINF_SUCCESS)
2338 {
2339 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2340
2341 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2342
2343 /* Continue execution. */
2344 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2345
2346 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2347 goto ResumeExecution;
2348 }
2349
2350 Log(("Forward #NM fault to the guest\n"));
2351 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2352 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2353 AssertRC(rc);
2354 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2355 goto ResumeExecution;
2356 }
2357
2358 case X86_XCPT_PF: /* Page fault */
2359 {
2360#ifdef DEBUG
2361 if (pVM->hwaccm.s.fNestedPaging)
2362 { /* A genuine pagefault.
2363 * Forward the trap to the guest by injecting the exception and resuming execution.
2364 */
2365 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2366
2367 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2368
2369 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2370
2371 /* Now we must update CR2. */
2372 pCtx->cr2 = exitQualification;
2373 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2374 AssertRC(rc);
2375
2376 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2377 goto ResumeExecution;
2378 }
2379#endif
2380 Assert(!pVM->hwaccm.s.fNestedPaging);
2381
2382 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2383 /* Exit qualification contains the linear address of the page fault. */
2384 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2385 TRPMSetErrorCode(pVM, errCode);
2386 TRPMSetFaultAddress(pVM, exitQualification);
2387
2388 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2389 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2390 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2391 if (rc == VINF_SUCCESS)
2392 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2393 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2394 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2395
2396 TRPMResetTrap(pVM);
2397
2398 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2399 goto ResumeExecution;
2400 }
2401 else
2402 if (rc == VINF_EM_RAW_GUEST_TRAP)
2403 { /* A genuine pagefault.
2404 * Forward the trap to the guest by injecting the exception and resuming execution.
2405 */
2406 Log2(("Forward page fault to the guest\n"));
2407
2408 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2409 /* The error code might have been changed. */
2410 errCode = TRPMGetErrorCode(pVM);
2411
2412 TRPMResetTrap(pVM);
2413
2414 /* Now we must update CR2. */
2415 pCtx->cr2 = exitQualification;
2416 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2417 AssertRC(rc);
2418
2419 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2420 goto ResumeExecution;
2421 }
2422#ifdef VBOX_STRICT
2423 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2424 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2425#endif
2426 /* Need to go back to the recompiler to emulate the instruction. */
2427 TRPMResetTrap(pVM);
2428 break;
2429 }
2430
2431 case X86_XCPT_MF: /* Floating point exception. */
2432 {
2433 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2434 if (!(pCtx->cr0 & X86_CR0_NE))
2435 {
2436 /* old style FPU error reporting needs some extra work. */
2437 /** @todo don't fall back to the recompiler, but do it manually. */
2438 rc = VINF_EM_RAW_EMULATE_INSTR;
2439 break;
2440 }
2441 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2442 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2443 AssertRC(rc);
2444
2445 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2446 goto ResumeExecution;
2447 }
2448
2449 case X86_XCPT_DB: /* Debug exception. */
2450 {
2451 uint64_t uDR6;
2452
2453 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2454 *
2455 * Exit qualification bits:
2456 * 3:0 B0-B3 which breakpoint condition was met
2457 * 12:4 Reserved (0)
2458 * 13 BD - debug register access detected
2459 * 14 BS - single step execution or branch taken
2460 * 63:15 Reserved (0)
2461 */
2462 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2463
2464 /* Note that we don't support guest and host-initiated debugging at the same time. */
2465 Assert(DBGFIsStepping(pVM) || CPUMIsGuestInRealModeEx(pCtx));
2466
2467 uDR6 = X86_DR6_INIT_VAL;
2468 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2469 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
2470 if (rc == VINF_EM_RAW_GUEST_TRAP)
2471 {
2472 /** @todo this isn't working, but we'll never get here normally. */
2473
2474 /* Update DR6 here. */
2475 pCtx->dr[6] = uDR6;
2476
2477 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2478 pCtx->dr[7] &= ~X86_DR7_GD;
2479
2480 /* Paranoia. */
2481 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2482 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2483 pCtx->dr[7] |= 0x400; /* must be one */
2484
2485 /* Resync DR7 */
2486 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2487 AssertRC(rc);
2488
2489 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2490 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2491 AssertRC(rc);
2492
2493 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2494 goto ResumeExecution;
2495 }
2496 /* Return to ring 3 to deal with the debug exit code. */
2497 break;
2498 }
2499
2500 case X86_XCPT_GP: /* General protection failure exception.*/
2501 {
2502 uint32_t cbSize;
2503
2504 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2505#ifdef VBOX_STRICT
2506 if (!CPUMIsGuestInRealModeEx(pCtx))
2507 {
2508 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2509 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2510 AssertRC(rc);
2511 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2512 goto ResumeExecution;
2513 }
2514#endif
2515 Assert(CPUMIsGuestInRealModeEx(pCtx));
2516
2517 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2518 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2519 if (rc == VINF_SUCCESS)
2520 {
2521 /* EIP has been updated already. */
2522
2523 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2524 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2525
2526 /* Only resume if successful. */
2527 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2528 goto ResumeExecution;
2529 }
2530 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2531 break;
2532 }
2533
2534#ifdef VBOX_STRICT
2535 case X86_XCPT_DE: /* Divide error. */
2536 case X86_XCPT_UD: /* Unknown opcode exception. */
2537 case X86_XCPT_SS: /* Stack segment exception. */
2538 case X86_XCPT_NP: /* Segment not present exception. */
2539 {
2540 switch(vector)
2541 {
2542 case X86_XCPT_DE:
2543 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2544 break;
2545 case X86_XCPT_UD:
2546 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2547 break;
2548 case X86_XCPT_SS:
2549 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2550 break;
2551 case X86_XCPT_NP:
2552 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2553 break;
2554 }
2555
2556 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2557 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2558 AssertRC(rc);
2559
2560 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2561 goto ResumeExecution;
2562 }
2563#endif
2564 default:
2565#ifdef HWACCM_VMX_EMULATE_REALMODE
2566 if (CPUMIsGuestInRealModeEx(pCtx))
2567 {
2568 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2569 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2570 AssertRC(rc);
2571
2572 /* Go back to ring 3 in case of a triple fault. */
2573 if ( vector == X86_XCPT_DF
2574 && rc == VINF_EM_RESET)
2575 break;
2576
2577 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2578 goto ResumeExecution;
2579 }
2580#endif
2581 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2582 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2583 break;
2584 } /* switch (vector) */
2585
2586 break;
2587
2588 default:
2589 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2590 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2591 break;
2592 }
2593
2594 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2595 break;
2596 }
2597
2598 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2599 {
2600 RTGCPHYS GCPhys;
2601
2602 Assert(pVM->hwaccm.s.fNestedPaging);
2603
2604 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2605 AssertRC(rc);
2606 Assert(((exitQualification >> 7) & 3) != 2);
2607
2608 /* Determine the kind of violation. */
2609 errCode = 0;
2610 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2611 errCode |= X86_TRAP_PF_ID;
2612
2613 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2614 errCode |= X86_TRAP_PF_RW;
2615
2616 /* If the page is present, then it's a page level protection fault. */
2617 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2618 errCode |= X86_TRAP_PF_P;
2619
2620 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2621
2622 /* GCPhys contains the guest physical address of the page fault. */
2623 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2624 TRPMSetErrorCode(pVM, errCode);
2625 TRPMSetFaultAddress(pVM, GCPhys);
2626
2627 /* Handle the pagefault trap for the nested shadow table. */
2628 rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2629 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2630 if (rc == VINF_SUCCESS)
2631 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2632 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
2633 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
2634
2635 TRPMResetTrap(pVM);
2636
2637 goto ResumeExecution;
2638 }
2639
2640#ifdef VBOX_STRICT
2641 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2642 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2643#endif
2644 /* Need to go back to the recompiler to emulate the instruction. */
2645 TRPMResetTrap(pVM);
2646 break;
2647 }
2648
2649 case VMX_EXIT_EPT_MISCONFIG:
2650 {
2651 RTGCPHYS GCPhys;
2652
2653 Assert(pVM->hwaccm.s.fNestedPaging);
2654
2655 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2656 AssertRC(rc);
2657
2658 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
2659 break;
2660 }
2661
2662 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2663 /* Clear VM-exit on IF=1 change. */
2664 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2665 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2666 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2667 AssertRC(rc);
2668 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
2669 goto ResumeExecution; /* we check for pending guest interrupts there */
2670
2671 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2672 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2673 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
2674 /* Skip instruction and continue directly. */
2675 pCtx->rip += cbInstr;
2676 /* Continue execution.*/
2677 goto ResumeExecution;
2678
2679 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2680 {
2681 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2682 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
2683 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
2684 if (rc == VINF_SUCCESS)
2685 {
2686 /* Update EIP and continue execution. */
2687 Assert(cbInstr == 2);
2688 pCtx->rip += cbInstr;
2689 goto ResumeExecution;
2690 }
2691 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
2692 rc = VINF_EM_RAW_EMULATE_INSTR;
2693 break;
2694 }
2695
2696 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2697 {
2698 Log2(("VMX: Rdtsc\n"));
2699 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2700 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
2701 if (rc == VINF_SUCCESS)
2702 {
2703 /* Update EIP and continue execution. */
2704 Assert(cbInstr == 2);
2705 pCtx->rip += cbInstr;
2706 goto ResumeExecution;
2707 }
2708 AssertMsgFailed(("EMU: rdtsc failed with %Rrc\n", rc));
2709 rc = VINF_EM_RAW_EMULATE_INSTR;
2710 break;
2711 }
2712
2713 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2714 {
2715 Log2(("VMX: invlpg\n"));
2716 Assert(!pVM->hwaccm.s.fNestedPaging);
2717
2718 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2719 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
2720 if (rc == VINF_SUCCESS)
2721 {
2722 /* Update EIP and continue execution. */
2723 pCtx->rip += cbInstr;
2724 goto ResumeExecution;
2725 }
2726 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
2727 break;
2728 }
2729
2730 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2731 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2732 {
2733 uint32_t cbSize;
2734
2735 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2736 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
2737 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2738 if (rc == VINF_SUCCESS)
2739 {
2740 /* EIP has been updated already. */
2741
2742 /* Only resume if successful. */
2743 goto ResumeExecution;
2744 }
2745 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
2746 break;
2747 }
2748
2749 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2750 {
2751 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2752
2753 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
2754 {
2755 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
2756 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
2757 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
2758 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
2759 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
2760 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
2761
2762 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
2763 {
2764 case 0:
2765 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
2766 break;
2767 case 2:
2768 break;
2769 case 3:
2770 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
2771 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2772 break;
2773 case 4:
2774 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2775 break;
2776 case 8:
2777 /* CR8 contains the APIC TPR */
2778 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2779 break;
2780
2781 default:
2782 AssertFailed();
2783 break;
2784 }
2785 /* Check if a sync operation is pending. */
2786 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2787 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2788 {
2789 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2790 AssertRC(rc);
2791 }
2792 break;
2793
2794 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
2795 Log2(("VMX: mov x, crx\n"));
2796 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
2797
2798 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
2799
2800 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
2801 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2802
2803 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
2804 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
2805 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
2806 break;
2807
2808 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2809 Log2(("VMX: clts\n"));
2810 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
2811 rc = EMInterpretCLTS(pVM);
2812 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2813 break;
2814
2815 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2816 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2817 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
2818 rc = EMInterpretLMSW(pVM, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2819 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2820 break;
2821 }
2822
2823 /* Update EIP if no error occurred. */
2824 if (RT_SUCCESS(rc))
2825 pCtx->rip += cbInstr;
2826
2827 if (rc == VINF_SUCCESS)
2828 {
2829 /* Only resume if successful. */
2830 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2831 goto ResumeExecution;
2832 }
2833 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2834 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2835 break;
2836 }
2837
2838 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2839 {
2840 if (!DBGFIsStepping(pVM))
2841 {
2842 /* Disable drx move intercepts. */
2843 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2844 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2845 AssertRC(rc);
2846
2847 /* Save the host and load the guest debug state. */
2848 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
2849 AssertRC(rc);
2850
2851#ifdef VBOX_WITH_STATISTICS
2852 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2853 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2854 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2855 else
2856 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2857#endif
2858
2859 goto ResumeExecution;
2860 }
2861
2862 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2863 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2864 {
2865 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2866 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2867 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2868 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2869 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2870 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2871 Log2(("DR7=%08x\n", pCtx->dr[7]));
2872 }
2873 else
2874 {
2875 Log2(("VMX: mov x, drx\n"));
2876 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2877 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2878 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2879 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2880 }
2881 /* Update EIP if no error occurred. */
2882 if (RT_SUCCESS(rc))
2883 pCtx->rip += cbInstr;
2884
2885 if (rc == VINF_SUCCESS)
2886 {
2887 /* Only resume if successful. */
2888 goto ResumeExecution;
2889 }
2890 Assert(rc == VERR_EM_INTERPRETER);
2891 break;
2892 }
2893
2894 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2895 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2896 {
2897 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
2898 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2899 uint32_t uPort;
2900 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2901
2902 /** @todo necessary to make the distinction? */
2903 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2904 {
2905 uPort = pCtx->edx & 0xffff;
2906 }
2907 else
2908 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2909
2910 /* paranoia */
2911 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2912 {
2913 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2914 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
2915 break;
2916 }
2917
2918 uint32_t cbSize = g_aIOSize[uIOWidth];
2919
2920 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2921 {
2922 /* ins/outs */
2923 DISCPUSTATE Cpu;
2924
2925 /* Disassemble manually to deal with segment prefixes. */
2926 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
2927 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
2928 rc = EMInterpretDisasOne(pVM, CPUMCTX2CORE(pCtx), &Cpu, NULL);
2929 if (rc == VINF_SUCCESS)
2930 {
2931 if (fIOWrite)
2932 {
2933 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
2934 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2935 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
2936 }
2937 else
2938 {
2939 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
2940 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2941 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
2942 }
2943 }
2944 else
2945 rc = VINF_EM_RAW_EMULATE_INSTR;
2946 }
2947 else
2948 {
2949 /* normal in/out */
2950 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
2951
2952 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2953
2954 if (fIOWrite)
2955 {
2956 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2957 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2958 }
2959 else
2960 {
2961 uint32_t u32Val = 0;
2962
2963 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2964 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2965 if (IOM_SUCCESS(rc))
2966 {
2967 /* Write back to the EAX register. */
2968 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2969 }
2970 }
2971 }
2972 /*
2973 * Handled the I/O return codes.
2974 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2975 */
2976 if (IOM_SUCCESS(rc))
2977 {
2978 /* Update EIP and continue execution. */
2979 pCtx->rip += cbInstr;
2980 if (RT_LIKELY(rc == VINF_SUCCESS))
2981 {
2982 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2983 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2984 {
2985 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2986 for (unsigned i=0;i<4;i++)
2987 {
2988 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2989
2990 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
2991 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2992 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2993 {
2994 uint64_t uDR6;
2995
2996 Assert(CPUMIsGuestDebugStateActive(pVM));
2997
2998 uDR6 = ASMGetDR6();
2999
3000 /* Clear all breakpoint status flags and set the one we just hit. */
3001 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3002 uDR6 |= (uint64_t)RT_BIT(i);
3003
3004 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3005 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3006 * the contents have been read.
3007 */
3008 ASMSetDR6(uDR6);
3009
3010 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3011 pCtx->dr[7] &= ~X86_DR7_GD;
3012
3013 /* Paranoia. */
3014 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3015 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3016 pCtx->dr[7] |= 0x400; /* must be one */
3017
3018 /* Resync DR7 */
3019 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3020 AssertRC(rc);
3021
3022 /* Construct inject info. */
3023 intInfo = X86_XCPT_DB;
3024 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3025 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3026
3027 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3028 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3029 AssertRC(rc);
3030
3031 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3032 goto ResumeExecution;
3033 }
3034 }
3035 }
3036
3037 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3038 goto ResumeExecution;
3039 }
3040 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3041 break;
3042 }
3043
3044#ifdef VBOX_STRICT
3045 if (rc == VINF_IOM_HC_IOPORT_READ)
3046 Assert(!fIOWrite);
3047 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3048 Assert(fIOWrite);
3049 else
3050 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3051#endif
3052 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3053 break;
3054 }
3055
3056 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3057 LogFlow(("VMX_EXIT_TPR\n"));
3058 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3059 goto ResumeExecution;
3060
3061 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3062 goto ResumeExecution;
3063
3064 default:
3065 /* The rest is handled after syncing the entire CPU state. */
3066 break;
3067 }
3068
3069 /* Note: the guest state isn't entirely synced back at this stage. */
3070
3071 /* Investigate why there was a VM-exit. (part 2) */
3072 switch (exitReason)
3073 {
3074 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3075 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3076 case VMX_EXIT_EPT_VIOLATION:
3077 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3078 /* Already handled above. */
3079 break;
3080
3081 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3082 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3083 break;
3084
3085 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3086 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3087 rc = VINF_EM_RAW_INTERRUPT;
3088 AssertFailed(); /* Can't happen. Yet. */
3089 break;
3090
3091 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3092 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3093 rc = VINF_EM_RAW_INTERRUPT;
3094 AssertFailed(); /* Can't happen afaik. */
3095 break;
3096
3097 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3098 rc = VERR_EM_INTERPRETER;
3099 break;
3100
3101 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3102 /** Check if external interrupts are pending; if so, don't switch back. */
3103 pCtx->rip++; /* skip hlt */
3104 if ( pCtx->eflags.Bits.u1IF
3105 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
3106 goto ResumeExecution;
3107
3108 rc = VINF_EM_HALT;
3109 break;
3110
3111 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3112 AssertFailed(); /* can't happen. */
3113 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3114 break;
3115
3116 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3117 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3118 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3119 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3120 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3121 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3122 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3123 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3124 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3125 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3126 /** @todo inject #UD immediately */
3127 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3128 break;
3129
3130 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3131 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3132 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3133 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3134 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3135 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3136 /* already handled above */
3137 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3138 || rc == VINF_EM_RAW_INTERRUPT
3139 || rc == VERR_EM_INTERPRETER
3140 || rc == VINF_EM_RAW_EMULATE_INSTR
3141 || rc == VINF_PGM_SYNC_CR3
3142 || rc == VINF_IOM_HC_IOPORT_READ
3143 || rc == VINF_IOM_HC_IOPORT_WRITE
3144 || rc == VINF_EM_RAW_GUEST_TRAP
3145 || rc == VINF_TRPM_XCPT_DISPATCHED
3146 || rc == VINF_EM_RESCHEDULE_REM,
3147 ("rc = %d\n", rc));
3148 break;
3149
3150 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3151 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3152 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3153 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3154 rc = VERR_EM_INTERPRETER;
3155 break;
3156
3157 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3158 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3159 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3160 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3161 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3162 break;
3163
3164 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3165 Assert(rc == VINF_EM_RAW_INTERRUPT);
3166 break;
3167
3168 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3169 {
3170#ifdef VBOX_STRICT
3171 RTCCUINTREG val = 0;
3172
3173 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3174
3175 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3176 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3177
3178 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3179 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3180
3181 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3182 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3183
3184 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3185 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3186
3187 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3188 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3189
3190 VMX_LOG_SELREG(CS, "CS");
3191 VMX_LOG_SELREG(DS, "DS");
3192 VMX_LOG_SELREG(ES, "ES");
3193 VMX_LOG_SELREG(FS, "FS");
3194 VMX_LOG_SELREG(GS, "GS");
3195 VMX_LOG_SELREG(SS, "SS");
3196 VMX_LOG_SELREG(TR, "TR");
3197 VMX_LOG_SELREG(LDTR, "LDTR");
3198
3199 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3200 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3201 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3202 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3203#endif /* VBOX_STRICT */
3204 rc = VERR_VMX_INVALID_GUEST_STATE;
3205 break;
3206 }
3207
3208 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3209 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3210 default:
3211 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3212 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3213 break;
3214
3215 }
3216end:
3217
3218 /* Signal changes for the recompiler. */
3219 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3220
3221 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3222 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3223 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3224 {
3225 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3226 /* On the next entry we'll only sync the host context. */
3227 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3228 }
3229 else
3230 {
3231 /* On the next entry we'll sync everything. */
3232 /** @todo we can do better than this */
3233 /* Not in the VINF_PGM_CHANGE_MODE though! */
3234 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3235 }
3236
3237 /* translate into a less severe return code */
3238 if (rc == VERR_EM_INTERPRETER)
3239 rc = VINF_EM_RAW_EMULATE_INSTR;
3240 else
3241 /* Try to extract more information about what might have gone wrong here. */
3242 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3243 {
3244 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3245 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3246 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3247 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3248 }
3249
3250 STAM_STATS({
3251 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3252 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3253 });
3254 Log2(("X"));
3255 return rc;
3256}
3257
3258
3259/**
3260 * Enters the VT-x session
3261 *
3262 * @returns VBox status code.
3263 * @param pVM The VM to operate on.
3264 * @param pVCpu The VMCPU to operate on.
3265 * @param pCpu CPU info struct
3266 */
3267VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3268{
3269 Assert(pVM->hwaccm.s.vmx.fSupported);
3270
3271 unsigned cr4 = ASMGetCR4();
3272 if (!(cr4 & X86_CR4_VMXE))
3273 {
3274 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3275 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3276 }
3277
3278 /* Activate the VM Control Structure. */
3279 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3280 if (RT_FAILURE(rc))
3281 return rc;
3282
3283 pVCpu->hwaccm.s.fResumeVM = false;
3284 return VINF_SUCCESS;
3285}
3286
3287
3288/**
3289 * Leaves the VT-x session
3290 *
3291 * @returns VBox status code.
3292 * @param pVM The VM to operate on.
3293 * @param pVCpu The VMCPU to operate on.
3294 * @param pCtx CPU context
3295 */
3296VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3297{
3298 Assert(pVM->hwaccm.s.vmx.fSupported);
3299
3300 /* Save the guest debug state if necessary. */
3301 if (CPUMIsGuestDebugStateActive(pVM))
3302 {
3303 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3304
3305 /* Enable drx move intercepts again. */
3306 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3307 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3308 AssertRC(rc);
3309
3310 /* Resync the debug registers the next time. */
3311 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3312 }
3313 else
3314 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3315
3316 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3317 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3318 AssertRC(rc);
3319
3320 return VINF_SUCCESS;
3321}
3322
3323/**
3324 * Flush the TLB (EPT)
3325 *
3326 * @returns VBox status code.
3327 * @param pVM The VM to operate on.
3328 * @param pVCpu The VM CPU to operate on.
3329 * @param enmFlush Type of flush
3330 * @param GCPhys Physical address of the page to flush
3331 */
3332static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3333{
3334 uint64_t descriptor[2];
3335
3336 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3337 Assert(pVM->hwaccm.s.fNestedPaging);
3338 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3339 descriptor[1] = GCPhys;
3340 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3341 AssertRC(rc);
3342}
3343
3344#ifdef HWACCM_VTX_WITH_VPID
3345/**
3346 * Flush the TLB (EPT)
3347 *
3348 * @returns VBox status code.
3349 * @param pVM The VM to operate on.
3350 * @param pVCpu The VM CPU to operate on.
3351 * @param enmFlush Type of flush
3352 * @param GCPtr Virtual address of the page to flush
3353 */
3354static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3355{
3356#if HC_ARCH_BITS == 32
3357 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3358 if ( CPUMIsGuestInLongMode(pVM)
3359 && !VMX_IS_64BIT_HOST_MODE())
3360 {
3361 pVCpu->hwaccm.s.fForceTLBFlush = true;
3362 }
3363 else
3364#endif
3365 {
3366 uint64_t descriptor[2];
3367
3368 Assert(pVM->hwaccm.s.vmx.fVPID);
3369 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3370 descriptor[1] = GCPtr;
3371 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3372 AssertRC(rc);
3373 }
3374}
3375#endif /* HWACCM_VTX_WITH_VPID */
3376
3377/**
3378 * Invalidates a guest page
3379 *
3380 * @returns VBox status code.
3381 * @param pVM The VM to operate on.
3382 * @param pVCpu The VM CPU to operate on.
3383 * @param GCVirt Page to invalidate
3384 */
3385VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3386{
3387 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3388
3389 LogFlow(("VMXR0InvalidatePage %RGv\n", GCVirt));
3390
3391 /* Only relevant if we want to use VPID.
3392 * In the nested paging case we still see such calls, but
3393 * can safely ignore them. (e.g. after cr3 updates)
3394 */
3395#ifdef HWACCM_VTX_WITH_VPID
3396 /* Skip it if a TLB flush is already pending. */
3397 if ( !fFlushPending
3398 && pVM->hwaccm.s.vmx.fVPID)
3399 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3400#endif /* HWACCM_VTX_WITH_VPID */
3401
3402 return VINF_SUCCESS;
3403}
3404
3405/**
3406 * Invalidates a guest page by physical address
3407 *
3408 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3409 *
3410 * @returns VBox status code.
3411 * @param pVM The VM to operate on.
3412 * @param pVCpu The VM CPU to operate on.
3413 * @param GCPhys Page to invalidate
3414 */
3415VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3416{
3417 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3418
3419 Assert(pVM->hwaccm.s.fNestedPaging);
3420
3421 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3422
3423 /* Skip it if a TLB flush is already pending. */
3424 if (!fFlushPending)
3425 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3426
3427 return VINF_SUCCESS;
3428}
3429
3430/**
3431 * Report world switch error and dump some useful debug info
3432 *
3433 * @param pVM The VM to operate on.
3434 * @param pVCpu The VMCPU to operate on.
3435 * @param rc Return code
3436 * @param pCtx Current CPU context (not updated)
3437 */
3438static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3439{
3440 switch (rc)
3441 {
3442 case VERR_VMX_INVALID_VMXON_PTR:
3443 AssertFailed();
3444 break;
3445
3446 case VERR_VMX_UNABLE_TO_START_VM:
3447 case VERR_VMX_UNABLE_TO_RESUME_VM:
3448 {
3449 int rc;
3450 RTCCUINTREG exitReason, instrError;
3451
3452 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3453 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3454 AssertRC(rc);
3455 if (rc == VINF_SUCCESS)
3456 {
3457 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3458 Log(("Current stack %08x\n", &rc));
3459
3460 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3461 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3462
3463#ifdef VBOX_STRICT
3464 RTGDTR gdtr;
3465 PX86DESCHC pDesc;
3466 RTCCUINTREG val;
3467
3468 ASMGetGDTR(&gdtr);
3469
3470 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3471 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3472 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3473 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3474 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3475 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3476 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3477 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3478 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3479 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3480
3481 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3482 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3483
3484 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3485 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3486
3487 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3488 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3489
3490 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3491 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3492
3493 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3494 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3495
3496 if (val < gdtr.cbGdt)
3497 {
3498 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3499 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3500 }
3501
3502 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3503 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3504 if (val < gdtr.cbGdt)
3505 {
3506 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3507 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3508 }
3509
3510 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
3511 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3512 if (val < gdtr.cbGdt)
3513 {
3514 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3515 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3516 }
3517
3518 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
3519 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
3520 if (val < gdtr.cbGdt)
3521 {
3522 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3523 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3524 }
3525
3526 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
3527 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
3528 if (val < gdtr.cbGdt)
3529 {
3530 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3531 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3532 }
3533
3534 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
3535 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
3536 if (val < gdtr.cbGdt)
3537 {
3538 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3539 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3540 }
3541
3542 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
3543 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
3544 if (val < gdtr.cbGdt)
3545 {
3546 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3547 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3548 }
3549
3550 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3551 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
3552
3553 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3554 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
3555 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3556 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
3557
3558 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
3559 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3560
3561 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3562 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
3563
3564 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3565 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
3566
3567 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3568 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
3569 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3570 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
3571
3572# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3573 if (VMX_IS_64BIT_HOST_MODE())
3574 {
3575 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
3576 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
3577 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3578 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3579 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3580 }
3581# endif
3582#endif /* VBOX_STRICT */
3583 }
3584 break;
3585 }
3586
3587 default:
3588 /* impossible */
3589 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
3590 break;
3591 }
3592}
3593
3594#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3595/**
3596 * Prepares for and executes VMLAUNCH (64 bits guest mode)
3597 *
3598 * @returns VBox status code
3599 * @param fResume vmlauch/vmresume
3600 * @param pCtx Guest context
3601 * @param pCache VMCS cache
3602 * @param pVM The VM to operate on.
3603 * @param pVCpu The VMCPU to operate on.
3604 */
3605DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
3606{
3607 uint32_t aParam[6];
3608 PHWACCM_CPUINFO pCpu;
3609 RTHCPHYS pPageCpuPhys;
3610 int rc;
3611
3612 pCpu = HWACCMR0GetCurrentCpu();
3613 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3614
3615#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3616 pCache->uPos = 1;
3617 pCache->interPD = PGMGetInterPaeCR3(pVM);
3618 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
3619#endif
3620
3621#ifdef DEBUG
3622 pCache->TestIn.pPageCpuPhys = 0;
3623 pCache->TestIn.pVMCSPhys = 0;
3624 pCache->TestIn.pCache = 0;
3625 pCache->TestOut.pVMCSPhys = 0;
3626 pCache->TestOut.pCache = 0;
3627 pCache->TestOut.pCtx = 0;
3628 pCache->TestOut.eflags = 0;
3629#endif
3630
3631 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
3632 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
3633 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
3634 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
3635 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
3636 aParam[5] = 0;
3637
3638#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3639 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
3640 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
3641#endif
3642 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
3643
3644#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3645 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
3646 Assert(pCtx->dr[4] == 10);
3647 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
3648#endif
3649
3650#ifdef DEBUG
3651 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
3652 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
3653 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
3654 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
3655 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
3656 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
3657 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
3658#endif
3659 return rc;
3660}
3661
3662/**
3663 * Executes the specified handler in 64 mode
3664 *
3665 * @returns VBox status code.
3666 * @param pVM The VM to operate on.
3667 * @param pVCpu The VMCPU to operate on.
3668 * @param pCtx Guest context
3669 * @param pfnHandler RC handler
3670 * @param cbParam Number of parameters
3671 * @param paParam Array of 32 bits parameters
3672 */
3673VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
3674{
3675 int rc, rc2;
3676 PHWACCM_CPUINFO pCpu;
3677 RTHCPHYS pPageCpuPhys;
3678
3679 /* @todo This code is not guest SMP safe (hyper context) */
3680 AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
3681 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
3682 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
3683 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
3684
3685#ifdef VBOX_STRICT
3686 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
3687 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
3688
3689 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
3690 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
3691#endif
3692
3693 pCpu = HWACCMR0GetCurrentCpu();
3694 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3695
3696 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3697 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3698
3699 /* Leave VMX Root Mode. */
3700 VMXDisable();
3701
3702 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3703
3704 CPUMSetHyperESP(pVM, VMMGetStackRC(pVM));
3705 CPUMSetHyperEIP(pVM, pfnHandler);
3706 for (int i=(int)cbParam-1;i>=0;i--)
3707 CPUMPushHyper(pVM, paParam[i]);
3708
3709 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3710 /* Call switcher. */
3711 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
3712 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3713
3714 /* Make sure the VMX instructions don't cause #UD faults. */
3715 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
3716
3717 /* Enter VMX Root Mode */
3718 rc2 = VMXEnable(pPageCpuPhys);
3719 if (RT_FAILURE(rc2))
3720 {
3721 if (pVM)
3722 VMXR0CheckError(pVM, pVCpu, rc2);
3723 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3724 return VERR_VMX_VMXON_FAILED;
3725 }
3726
3727 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3728 AssertRCReturn(rc2, rc2);
3729#ifdef RT_OS_WINDOWS
3730 Assert(ASMGetFlags() & X86_EFL_IF);
3731#else
3732 Assert(!(ASMGetFlags() & X86_EFL_IF));
3733#endif
3734 return rc;
3735}
3736
3737#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
3738
3739
3740#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3741/**
3742 * Executes VMWRITE
3743 *
3744 * @returns VBox status code
3745 * @param pVCpu The VMCPU to operate on.
3746 * @param idxField VMCS index
3747 * @param u64Val 16, 32 or 64 bits value
3748 */
3749VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
3750{
3751 int rc;
3752
3753 switch (idxField)
3754 {
3755 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
3756 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
3757 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
3758 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
3759 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
3760 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
3761 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
3762 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
3763 case VMX_VMCS_GUEST_LINK_PTR_FULL:
3764 case VMX_VMCS_GUEST_PDPTR0_FULL:
3765 case VMX_VMCS_GUEST_PDPTR1_FULL:
3766 case VMX_VMCS_GUEST_PDPTR2_FULL:
3767 case VMX_VMCS_GUEST_PDPTR3_FULL:
3768 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
3769 case VMX_VMCS_GUEST_EFER_FULL:
3770 case VMX_VMCS_CTRL_EPTP_FULL:
3771 /* These fields consist of two parts, which are both writable in 32 bits mode. */
3772 rc = VMXWriteVMCS32(idxField, u64Val);
3773 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
3774 AssertRC(rc);
3775 return rc;
3776
3777 case VMX_VMCS64_GUEST_LDTR_BASE:
3778 case VMX_VMCS64_GUEST_TR_BASE:
3779 case VMX_VMCS64_GUEST_GDTR_BASE:
3780 case VMX_VMCS64_GUEST_IDTR_BASE:
3781 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3782 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3783 case VMX_VMCS64_GUEST_CR0:
3784 case VMX_VMCS64_GUEST_CR4:
3785 case VMX_VMCS64_GUEST_CR3:
3786 case VMX_VMCS64_GUEST_DR7:
3787 case VMX_VMCS64_GUEST_RIP:
3788 case VMX_VMCS64_GUEST_RSP:
3789 case VMX_VMCS64_GUEST_CS_BASE:
3790 case VMX_VMCS64_GUEST_DS_BASE:
3791 case VMX_VMCS64_GUEST_ES_BASE:
3792 case VMX_VMCS64_GUEST_FS_BASE:
3793 case VMX_VMCS64_GUEST_GS_BASE:
3794 case VMX_VMCS64_GUEST_SS_BASE:
3795 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
3796 if (u64Val >> 32ULL)
3797 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
3798 else
3799 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
3800
3801 return rc;
3802
3803 default:
3804 AssertMsgFailed(("Unexpected field %x\n", idxField));
3805 return VERR_INVALID_PARAMETER;
3806 }
3807}
3808
3809/**
3810 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
3811 *
3812 * @param pVCpu The VMCPU to operate on.
3813 * @param idxField VMCS field
3814 * @param u64Val Value
3815 */
3816VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
3817{
3818 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
3819
3820 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
3821
3822 /* Make sure there are no duplicates. */
3823 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
3824 {
3825 if (pCache->Write.aField[i] == idxField)
3826 {
3827 pCache->Write.aFieldVal[i] = u64Val;
3828 return VINF_SUCCESS;
3829 }
3830 }
3831
3832 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
3833 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
3834 pCache->Write.cValidEntries++;
3835 return VINF_SUCCESS;
3836}
3837
3838#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3839
3840#ifdef VBOX_STRICT
3841static bool vmxR0IsValidReadField(uint32_t idxField)
3842{
3843 switch(idxField)
3844 {
3845 case VMX_VMCS64_GUEST_RIP:
3846 case VMX_VMCS64_GUEST_RSP:
3847 case VMX_VMCS_GUEST_RFLAGS:
3848 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
3849 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
3850 case VMX_VMCS64_GUEST_CR0:
3851 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
3852 case VMX_VMCS64_GUEST_CR4:
3853 case VMX_VMCS64_GUEST_DR7:
3854 case VMX_VMCS32_GUEST_SYSENTER_CS:
3855 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3856 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3857 case VMX_VMCS32_GUEST_GDTR_LIMIT:
3858 case VMX_VMCS64_GUEST_GDTR_BASE:
3859 case VMX_VMCS32_GUEST_IDTR_LIMIT:
3860 case VMX_VMCS64_GUEST_IDTR_BASE:
3861 case VMX_VMCS16_GUEST_FIELD_CS:
3862 case VMX_VMCS32_GUEST_CS_LIMIT:
3863 case VMX_VMCS64_GUEST_CS_BASE:
3864 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
3865 case VMX_VMCS16_GUEST_FIELD_DS:
3866 case VMX_VMCS32_GUEST_DS_LIMIT:
3867 case VMX_VMCS64_GUEST_DS_BASE:
3868 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
3869 case VMX_VMCS16_GUEST_FIELD_ES:
3870 case VMX_VMCS32_GUEST_ES_LIMIT:
3871 case VMX_VMCS64_GUEST_ES_BASE:
3872 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
3873 case VMX_VMCS16_GUEST_FIELD_FS:
3874 case VMX_VMCS32_GUEST_FS_LIMIT:
3875 case VMX_VMCS64_GUEST_FS_BASE:
3876 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
3877 case VMX_VMCS16_GUEST_FIELD_GS:
3878 case VMX_VMCS32_GUEST_GS_LIMIT:
3879 case VMX_VMCS64_GUEST_GS_BASE:
3880 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
3881 case VMX_VMCS16_GUEST_FIELD_SS:
3882 case VMX_VMCS32_GUEST_SS_LIMIT:
3883 case VMX_VMCS64_GUEST_SS_BASE:
3884 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
3885 case VMX_VMCS16_GUEST_FIELD_LDTR:
3886 case VMX_VMCS32_GUEST_LDTR_LIMIT:
3887 case VMX_VMCS64_GUEST_LDTR_BASE:
3888 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
3889 case VMX_VMCS16_GUEST_FIELD_TR:
3890 case VMX_VMCS32_GUEST_TR_LIMIT:
3891 case VMX_VMCS64_GUEST_TR_BASE:
3892 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
3893 case VMX_VMCS32_RO_EXIT_REASON:
3894 case VMX_VMCS32_RO_VM_INSTR_ERROR:
3895 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
3896 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
3897 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
3898 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
3899 case VMX_VMCS_RO_EXIT_QUALIFICATION:
3900 case VMX_VMCS32_RO_IDT_INFO:
3901 case VMX_VMCS32_RO_IDT_ERRCODE:
3902 case VMX_VMCS64_GUEST_CR3:
3903 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
3904 return true;
3905 }
3906 return false;
3907}
3908
3909static bool vmxR0IsValidWriteField(uint32_t idxField)
3910{
3911 switch(idxField)
3912 {
3913 case VMX_VMCS64_GUEST_LDTR_BASE:
3914 case VMX_VMCS64_GUEST_TR_BASE:
3915 case VMX_VMCS64_GUEST_GDTR_BASE:
3916 case VMX_VMCS64_GUEST_IDTR_BASE:
3917 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3918 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3919 case VMX_VMCS64_GUEST_CR0:
3920 case VMX_VMCS64_GUEST_CR4:
3921 case VMX_VMCS64_GUEST_CR3:
3922 case VMX_VMCS64_GUEST_DR7:
3923 case VMX_VMCS64_GUEST_RIP:
3924 case VMX_VMCS64_GUEST_RSP:
3925 case VMX_VMCS64_GUEST_CS_BASE:
3926 case VMX_VMCS64_GUEST_DS_BASE:
3927 case VMX_VMCS64_GUEST_ES_BASE:
3928 case VMX_VMCS64_GUEST_FS_BASE:
3929 case VMX_VMCS64_GUEST_GS_BASE:
3930 case VMX_VMCS64_GUEST_SS_BASE:
3931 return true;
3932 }
3933 return false;
3934}
3935
3936#endif
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