VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 16524

Last change on this file since 16524 was 16110, checked in by vboxsync, 16 years ago

HWCMXR0: debugger (dbgf) breakpoints; DEBUG build only for the time being. Corrected a log statment.
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1/* $Id: HWVMXR0.cpp 16110 2009-01-21 01:37:45Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/param.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/string.h>
42#include "HWVMXR0.h"
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47#if defined(RT_ARCH_AMD64)
48# define VMX_IS_64BIT_HOST_MODE() (true)
49#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
50# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
51#else
52# define VMX_IS_64BIT_HOST_MODE() (false)
53#endif
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58/* IO operation lookup arrays. */
59static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
60static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
61
62#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
63/** See HWACCMR0A.asm. */
64extern "C" uint32_t g_fVMXIs64bitHost;
65#endif
66
67/*******************************************************************************
68* Local Functions *
69*******************************************************************************/
70static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
71static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
72static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
73static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
74static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
75static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
76static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
77#ifdef VBOX_STRICT
78static bool vmxR0IsValidReadField(uint32_t idxField);
79static bool vmxR0IsValidWriteField(uint32_t idxField);
80#endif
81
82static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
83{
84 if (rc == VERR_VMX_GENERIC)
85 {
86 RTCCUINTREG instrError;
87
88 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
89 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
90 }
91 pVM->hwaccm.s.lLastError = rc;
92}
93
94/**
95 * Sets up and activates VT-x on the current CPU
96 *
97 * @returns VBox status code.
98 * @param pCpu CPU info struct
99 * @param pVM The VM to operate on. (can be NULL after a resume!!)
100 * @param pvPageCpu Pointer to the global cpu page
101 * @param pPageCpuPhys Physical address of the global cpu page
102 */
103VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
104{
105 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
106 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
107
108#ifdef LOG_ENABLED
109 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
110#endif
111 if (pVM)
112 {
113 /* Set revision dword at the beginning of the VMXON structure. */
114 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
115 }
116
117 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
118 * (which can have very bad consequences!!!)
119 */
120
121 /* Make sure the VMX instructions don't cause #UD faults. */
122 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
123
124 /* Enter VMX Root Mode */
125 int rc = VMXEnable(pPageCpuPhys);
126 if (RT_FAILURE(rc))
127 {
128 if (pVM)
129 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
130 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
131 return VERR_VMX_VMXON_FAILED;
132 }
133 return VINF_SUCCESS;
134}
135
136/**
137 * Deactivates VT-x on the current CPU
138 *
139 * @returns VBox status code.
140 * @param pCpu CPU info struct
141 * @param pvPageCpu Pointer to the global cpu page
142 * @param pPageCpuPhys Physical address of the global cpu page
143 */
144VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
145{
146 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
147 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
148
149 /* Leave VMX Root Mode. */
150 VMXDisable();
151
152 /* And clear the X86_CR4_VMXE bit */
153 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
154
155#ifdef LOG_ENABLED
156 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
157#endif
158 return VINF_SUCCESS;
159}
160
161/**
162 * Does Ring-0 per VM VT-x init.
163 *
164 * @returns VBox status code.
165 * @param pVM The VM to operate on.
166 */
167VMMR0DECL(int) VMXR0InitVM(PVM pVM)
168{
169 int rc;
170
171#ifdef LOG_ENABLED
172 SUPR0Printf("VMXR0InitVM %x\n", pVM);
173#endif
174
175 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
176
177 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
178 {
179 /* Allocate one page for the virtual APIC mmio cache. */
180 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
181 AssertRC(rc);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
186 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
187 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
188 }
189 else
190 {
191 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
192 pVM->hwaccm.s.vmx.pAPIC = 0;
193 pVM->hwaccm.s.vmx.pAPICPhys = 0;
194 }
195
196 /* Allocate the MSR bitmap if this feature is supported. */
197 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
198 {
199 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
200 AssertRC(rc);
201 if (RT_FAILURE(rc))
202 return rc;
203
204 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
205 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
206 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
207 }
208
209#ifdef VBOX_WITH_CRASHDUMP_MAGIC
210 {
211 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
212 AssertRC(rc);
213 if (RT_FAILURE(rc))
214 return rc;
215
216 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
217 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
218
219 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
220 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
221 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
222 }
223#endif
224
225 /* Allocate VMCBs for all guest CPUs. */
226 for (unsigned i=0;i<pVM->cCPUs;i++)
227 {
228 PVMCPU pVCpu = &pVM->aCpus[i];
229
230 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
231
232 /* Allocate one page for the VM control structure (VMCS). */
233 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
234 AssertRC(rc);
235 if (RT_FAILURE(rc))
236 return rc;
237
238 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
239 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
240 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
241
242 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
243 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
244
245 /* Current guest paging mode. */
246 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
247
248#ifdef LOG_ENABLED
249 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
250#endif
251 }
252
253 return VINF_SUCCESS;
254}
255
256/**
257 * Does Ring-0 per VM VT-x termination.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262VMMR0DECL(int) VMXR0TermVM(PVM pVM)
263{
264 for (unsigned i=0;i<pVM->cCPUs;i++)
265 {
266 if (pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
267 {
268 RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, false);
269 pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
270 pVM->aCpus[i].hwaccm.s.vmx.pVMCS = 0;
271 pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys = 0;
272 }
273 }
274 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
275 {
276 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
277 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
278 pVM->hwaccm.s.vmx.pAPIC = 0;
279 pVM->hwaccm.s.vmx.pAPICPhys = 0;
280 }
281 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
282 {
283 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
284 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
285 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
286 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
287 }
288#ifdef VBOX_WITH_CRASHDUMP_MAGIC
289 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
290 {
291 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
292 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
293 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
294 pVM->hwaccm.s.vmx.pScratch = 0;
295 pVM->hwaccm.s.vmx.pScratchPhys = 0;
296 }
297#endif
298 return VINF_SUCCESS;
299}
300
301/**
302 * Sets up VT-x for the specified VM
303 *
304 * @returns VBox status code.
305 * @param pVM The VM to operate on.
306 */
307VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
308{
309 int rc = VINF_SUCCESS;
310 uint32_t val;
311
312 AssertReturn(pVM, VERR_INVALID_PARAMETER);
313
314 for (unsigned i=0;i<pVM->cCPUs;i++)
315 {
316 PVMCPU pVCpu = &pVM->aCpus[i];
317
318 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
319
320 /* Set revision dword at the beginning of the VMCS structure. */
321 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
322
323 /* Clear VM Control Structure. */
324 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
325 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
326 if (RT_FAILURE(rc))
327 goto vmx_end;
328
329 /* Activate the VM Control Structure. */
330 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
331 if (RT_FAILURE(rc))
332 goto vmx_end;
333
334 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
335 * Set required bits to one and zero according to the MSR capabilities.
336 */
337 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
338 /* External and non-maskable interrupts cause VM-exits. */
339 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
340 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
341
342 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
343 AssertRC(rc);
344
345 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
346 * Set required bits to one and zero according to the MSR capabilities.
347 */
348 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
349 /* Program which event cause VM-exits and which features we want to use. */
350 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
351 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
352 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
353 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
354 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
355 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
356
357 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
358 if (!pVM->hwaccm.s.fNestedPaging)
359 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
360 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
361 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
362
363 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
364 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
365 {
366 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
367 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
368 Assert(pVM->hwaccm.s.vmx.pAPIC);
369 }
370 else
371 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
372 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
373
374#ifdef VBOX_WITH_VTX_MSR_BITMAPS
375 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
376 {
377 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
378 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
379 }
380#endif
381
382 /* We will use the secondary control if it's present. */
383 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
384
385 /* Mask away the bits that the CPU doesn't support */
386 /** @todo make sure they don't conflict with the above requirements. */
387 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
388 pVCpu->hwaccm.s.vmx.proc_ctls = val;
389
390 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
391 AssertRC(rc);
392
393 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
394 {
395 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
396 * Set required bits to one and zero according to the MSR capabilities.
397 */
398 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
399 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
400
401#ifdef HWACCM_VTX_WITH_EPT
402 if (pVM->hwaccm.s.fNestedPaging)
403 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
404#endif /* HWACCM_VTX_WITH_EPT */
405#ifdef HWACCM_VTX_WITH_VPID
406 else
407 if (pVM->hwaccm.s.vmx.fVPID)
408 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
409#endif /* HWACCM_VTX_WITH_VPID */
410
411 /* Mask away the bits that the CPU doesn't support */
412 /** @todo make sure they don't conflict with the above requirements. */
413 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
414
415 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
416 AssertRC(rc);
417 }
418
419 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
420 * Set required bits to one and zero according to the MSR capabilities.
421 */
422 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
423 AssertRC(rc);
424
425 /* Forward all exception except #NM & #PF to the guest.
426 * We always need to check pagefaults since our shadow page table can be out of sync.
427 * And we always lazily sync the FPU & XMM state.
428 */
429
430 /** @todo Possible optimization:
431 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
432 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
433 * registers ourselves of course.
434 *
435 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
436 */
437
438 /* Don't filter page faults; all of them should cause a switch. */
439 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
441 AssertRC(rc);
442
443 /* Init TSC offset to zero. */
444 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
445 AssertRC(rc);
446
447 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
448 AssertRC(rc);
449
450 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
451 AssertRC(rc);
452
453 /* Set the MSR bitmap address. */
454 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
455 {
456 /* Optional */
457 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
458 AssertRC(rc);
459 }
460
461 /* Clear MSR controls. */
462 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
463 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
464 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
465 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
467 AssertRC(rc);
468
469 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
470 {
471 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
472 /* Optional */
473 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
474 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
475 AssertRC(rc);
476 }
477
478 /* Set link pointer to -1. Not currently used. */
479 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
480 AssertRC(rc);
481
482 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
483 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
484 AssertRC(rc);
485
486 /* Configure the VMCS read cache. */
487 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
488
489 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
490 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
491 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
492 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
493 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
494 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
495 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
496 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
497 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
498 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
499 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
500 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
501 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
502 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
503 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
504 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
505
506 VMX_SETUP_SELREG(ES, pCache);
507 VMX_SETUP_SELREG(SS, pCache);
508 VMX_SETUP_SELREG(CS, pCache);
509 VMX_SETUP_SELREG(DS, pCache);
510 VMX_SETUP_SELREG(FS, pCache);
511 VMX_SETUP_SELREG(GS, pCache);
512 VMX_SETUP_SELREG(LDTR, pCache);
513 VMX_SETUP_SELREG(TR, pCache);
514
515 /* Status code VMCS reads. */
516 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
517 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
518 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
525
526 if (pVM->hwaccm.s.fNestedPaging)
527 {
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
530 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
531 }
532 else
533 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
534 } /* for each VMCPU */
535
536 /* Choose the right TLB setup function. */
537 if (pVM->hwaccm.s.fNestedPaging)
538 {
539 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
540
541 /* Default values for flushing. */
542 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
543 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
544
545 /* If the capabilities specify we can do more, then make use of it. */
546 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
547 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
548 else
549 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
550 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
551
552 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
553 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
554 }
555#ifdef HWACCM_VTX_WITH_VPID
556 else
557 if (pVM->hwaccm.s.vmx.fVPID)
558 {
559 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
560
561 /* Default values for flushing. */
562 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
563 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
564
565 /* If the capabilities specify we can do more, then make use of it. */
566 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
567 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
568 else
569 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
570 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
571
572 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
574 }
575#endif /* HWACCM_VTX_WITH_VPID */
576 else
577 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
578
579vmx_end:
580 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
581 return rc;
582}
583
584
585/**
586 * Injects an event (trap or external interrupt)
587 *
588 * @returns VBox status code.
589 * @param pVM The VM to operate on.
590 * @param pVCpu The VMCPU to operate on.
591 * @param pCtx CPU Context
592 * @param intInfo VMX interrupt info
593 * @param cbInstr Opcode length of faulting instruction
594 * @param errCode Error code (optional)
595 */
596static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
597{
598 int rc;
599 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
600
601#ifdef VBOX_STRICT
602 if (iGate == 0xE)
603 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
604 else
605 if (iGate < 0x20)
606 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
607 else
608 {
609 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
610 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
611 Assert(pCtx->eflags.u32 & X86_EFL_IF);
612 }
613#endif
614
615#ifdef HWACCM_VMX_EMULATE_REALMODE
616 if (CPUMIsGuestInRealModeEx(pCtx))
617 {
618 RTGCPHYS GCPhysHandler;
619 uint16_t offset, ip;
620 RTSEL sel;
621
622 /* Injecting events doesn't work right with real mode emulation.
623 * (#GP if we try to inject external hardware interrupts)
624 * Inject the interrupt or trap directly instead.
625 */
626 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
627
628 /* Check if the interrupt handler is present. */
629 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
630 {
631 Log(("IDT cbIdt violation\n"));
632 if (iGate != X86_XCPT_DF)
633 {
634 RTGCUINTPTR intInfo;
635
636 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
637 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
638 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
639 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
640
641 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
642 }
643 Log(("Triple fault -> reset the VM!\n"));
644 return VINF_EM_RESET;
645 }
646 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
647 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
648 || iGate == 4)
649 {
650 ip = pCtx->ip + cbInstr;
651 }
652 else
653 ip = pCtx->ip;
654
655 /* Read the selector:offset pair of the interrupt handler. */
656 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
657 PGMPhysRead(pVM, GCPhysHandler, &offset, sizeof(offset));
658 PGMPhysRead(pVM, GCPhysHandler + 2, &sel, sizeof(sel));
659
660 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
661
662 /* Construct the stack frame. */
663 /** @todo should check stack limit. */
664 pCtx->sp -= 2;
665 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
666 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t));
667 pCtx->sp -= 2;
668 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
669 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t));
670 pCtx->sp -= 2;
671 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
672 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip));
673
674 /* Update the CPU state for executing the handler. */
675 pCtx->rip = offset;
676 pCtx->cs = sel;
677 pCtx->csHid.u64Base = sel << 4;
678 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
679
680 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
681 return VINF_SUCCESS;
682 }
683#endif /* HWACCM_VMX_EMULATE_REALMODE */
684
685 /* Set event injection state. */
686 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
687
688 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
689 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
690
691 AssertRC(rc);
692 return rc;
693}
694
695
696/**
697 * Checks for pending guest interrupts and injects them
698 *
699 * @returns VBox status code.
700 * @param pVM The VM to operate on.
701 * @param pVCpu The VMCPU to operate on.
702 * @param pCtx CPU Context
703 */
704static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
705{
706 int rc;
707
708 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
709 if (pVCpu->hwaccm.s.Event.fPending)
710 {
711 Log(("Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
712 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
713 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
714 AssertRC(rc);
715
716 pVCpu->hwaccm.s.Event.fPending = false;
717 return VINF_SUCCESS;
718 }
719
720 if (pVM->hwaccm.s.fInjectNMI)
721 {
722 RTGCUINTPTR intInfo;
723
724 intInfo = X86_XCPT_NMI;
725 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
726 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
727
728 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
729 AssertRC(rc);
730
731 pVM->hwaccm.s.fInjectNMI = false;
732 return VINF_SUCCESS;
733 }
734
735 /* When external interrupts are pending, we should exit the VM when IF is set. */
736 if ( !TRPMHasTrap(pVM)
737 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
738 {
739 if (!(pCtx->eflags.u32 & X86_EFL_IF))
740 {
741 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
742 {
743 LogFlow(("Enable irq window exit!\n"));
744 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
745 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
746 AssertRC(rc);
747 }
748 /* else nothing to do but wait */
749 }
750 else
751 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
752 {
753 uint8_t u8Interrupt;
754
755 rc = PDMGetInterrupt(pVM, &u8Interrupt);
756 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
757 if (RT_SUCCESS(rc))
758 {
759 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
760 AssertRC(rc);
761 }
762 else
763 {
764 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
765 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
766 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
767 /* Just continue */
768 }
769 }
770 else
771 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
772 }
773
774#ifdef VBOX_STRICT
775 if (TRPMHasTrap(pVM))
776 {
777 uint8_t u8Vector;
778 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
779 AssertRC(rc);
780 }
781#endif
782
783 if ( pCtx->eflags.u32 & X86_EFL_IF
784 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
785 && TRPMHasTrap(pVM)
786 )
787 {
788 uint8_t u8Vector;
789 int rc;
790 TRPMEVENT enmType;
791 RTGCUINTPTR intInfo;
792 RTGCUINT errCode;
793
794 /* If a new event is pending, then dispatch it now. */
795 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
796 AssertRC(rc);
797 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
798 Assert(enmType != TRPM_SOFTWARE_INT);
799
800 /* Clear the pending trap. */
801 rc = TRPMResetTrap(pVM);
802 AssertRC(rc);
803
804 intInfo = u8Vector;
805 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
806
807 if (enmType == TRPM_TRAP)
808 {
809 switch (u8Vector) {
810 case 8:
811 case 10:
812 case 11:
813 case 12:
814 case 13:
815 case 14:
816 case 17:
817 /* Valid error codes. */
818 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
819 break;
820 default:
821 break;
822 }
823 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
824 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
825 else
826 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
827 }
828 else
829 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
830
831 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
832 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
833 AssertRC(rc);
834 } /* if (interrupts can be dispatched) */
835
836 return VINF_SUCCESS;
837}
838
839/**
840 * Save the host state
841 *
842 * @returns VBox status code.
843 * @param pVM The VM to operate on.
844 * @param pVCpu The VMCPU to operate on.
845 */
846VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
847{
848 int rc = VINF_SUCCESS;
849
850 /*
851 * Host CPU Context
852 */
853 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
854 {
855 RTIDTR idtr;
856 RTGDTR gdtr;
857 RTSEL SelTR;
858 PX86DESCHC pDesc;
859 uintptr_t trBase;
860 RTSEL cs;
861 RTSEL ss;
862 uint64_t cr3;
863
864 /* Control registers */
865 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
866#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
867 if (VMX_IS_64BIT_HOST_MODE())
868 {
869 cr3 = hwaccmR0Get64bitCR3();
870 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
871 }
872 else
873#endif
874 {
875 cr3 = ASMGetCR3();
876 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
877 }
878 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
879 AssertRC(rc);
880 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
881 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
882 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
883
884 /* Selector registers. */
885#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
886 if (VMX_IS_64BIT_HOST_MODE())
887 {
888 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
889 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
890 }
891 else
892 {
893 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
894 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
895 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
896 }
897#else
898 cs = ASMGetCS();
899 ss = ASMGetSS();
900#endif
901 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
902 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
903 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
904 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
905 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
906 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
907#if HC_ARCH_BITS == 32
908 if (!VMX_IS_64BIT_HOST_MODE())
909 {
910 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
911 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
912 }
913#endif
914 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
915 SelTR = ASMGetTR();
916 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
917 AssertRC(rc);
918 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
919 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
920 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
921 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
922 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
923 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
924 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
925
926 /* GDTR & IDTR */
927#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
928 if (VMX_IS_64BIT_HOST_MODE())
929 {
930 X86XDTR64 gdtr64, idtr64;
931 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
932 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
933 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
934 AssertRC(rc);
935 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
936 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
937 gdtr.cbGdt = gdtr64.cb;
938 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
939 }
940 else
941#endif
942 {
943 ASMGetGDTR(&gdtr);
944 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
945 ASMGetIDTR(&idtr);
946 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
947 AssertRC(rc);
948 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
949 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
950 }
951
952
953 /* Save the base address of the TR selector. */
954 if (SelTR > gdtr.cbGdt)
955 {
956 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
957 return VERR_VMX_INVALID_HOST_STATE;
958 }
959
960#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
961 if (VMX_IS_64BIT_HOST_MODE())
962 {
963 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
964 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
965 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
966 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
967 AssertRC(rc);
968 }
969 else
970#endif
971 {
972 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
973#if HC_ARCH_BITS == 64
974 trBase = X86DESC64_BASE(*pDesc);
975#else
976 trBase = X86DESC_BASE(*pDesc);
977#endif
978 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
979 AssertRC(rc);
980 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
981 }
982
983 /* FS and GS base. */
984#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
985 if (VMX_IS_64BIT_HOST_MODE())
986 {
987 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
988 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
989 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
990 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
991 }
992#endif
993 AssertRC(rc);
994
995 /* Sysenter MSRs. */
996 /** @todo expensive!! */
997 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
998 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
999#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1000 if (VMX_IS_64BIT_HOST_MODE())
1001 {
1002 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1003 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1004 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1005 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1006 }
1007 else
1008 {
1009 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1010 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1011 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1012 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1013 }
1014#elif HC_ARCH_BITS == 32
1015 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1016 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1017 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1018 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1019#else
1020 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1021 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1022 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1023 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1024#endif
1025 AssertRC(rc);
1026
1027#if 0 /* @todo deal with 32/64 */
1028 /* Restore the host EFER - on CPUs that support it. */
1029 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1030 {
1031 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1032 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1033 AssertRC(rc);
1034 }
1035#endif
1036 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1037 }
1038 return rc;
1039}
1040
1041/**
1042 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1043 *
1044 * @param pVM The VM to operate on.
1045 * @param pVCpu The VMCPU to operate on.
1046 * @param pCtx Guest context
1047 */
1048static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1049{
1050 if (CPUMIsGuestInPAEModeEx(pCtx))
1051 {
1052 X86PDPE Pdpe;
1053
1054 for (unsigned i=0;i<4;i++)
1055 {
1056 Pdpe = PGMGstGetPaePDPtr(pVM, i);
1057 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1058 AssertRC(rc);
1059 }
1060 }
1061}
1062
1063/**
1064 * Update the exception bitmap according to the current CPU state
1065 *
1066 * @param pVM The VM to operate on.
1067 * @param pVCpu The VMCPU to operate on.
1068 * @param pCtx Guest context
1069 */
1070static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1071{
1072 uint32_t u32TrapMask;
1073 Assert(pCtx);
1074
1075 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1076#ifndef DEBUG
1077 if (pVM->hwaccm.s.fNestedPaging)
1078 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1079#endif
1080
1081 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1082 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1083 && !(pCtx->cr0 & X86_CR0_NE)
1084 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1085 {
1086 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1087 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1088 }
1089
1090#ifdef DEBUG /* till after branching, enable it by default then. */
1091 /* Intercept X86_XCPT_DB if stepping is enabled */
1092 if (DBGFIsStepping(pVM))
1093 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1094 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1095 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1096#endif
1097
1098#ifdef VBOX_STRICT
1099 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1100#endif
1101
1102# ifdef HWACCM_VMX_EMULATE_REALMODE
1103 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1104 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1105 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1106# endif /* HWACCM_VMX_EMULATE_REALMODE */
1107
1108 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1109 AssertRC(rc);
1110}
1111
1112/**
1113 * Loads the guest state
1114 *
1115 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1116 *
1117 * @returns VBox status code.
1118 * @param pVM The VM to operate on.
1119 * @param pVCpu The VMCPU to operate on.
1120 * @param pCtx Guest context
1121 */
1122VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1123{
1124 int rc = VINF_SUCCESS;
1125 RTGCUINTPTR val;
1126 X86EFLAGS eflags;
1127
1128 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1129 * Set required bits to one and zero according to the MSR capabilities.
1130 */
1131 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1132 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1133 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1134#if 0 /* @todo deal with 32/64 */
1135 /* Required for the EFER write below, not supported on all CPUs. */
1136 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1137#endif
1138 /* 64 bits guest mode? */
1139 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1140 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1141 /* else Must be zero when AMD64 is not available. */
1142
1143 /* Mask away the bits that the CPU doesn't support */
1144 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1145 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1146 AssertRC(rc);
1147
1148 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1149 * Set required bits to one and zero according to the MSR capabilities.
1150 */
1151 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1152
1153 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1154#if 0 /* @todo deal with 32/64 */
1155 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1156#else
1157 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1158#endif
1159
1160#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1161 if (VMX_IS_64BIT_HOST_MODE())
1162 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1163 /* else: Must be zero when AMD64 is not available. */
1164#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1165 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1166 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1167 else
1168 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1169#endif
1170 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1171 /* Don't acknowledge external interrupts on VM-exit. */
1172 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1173 AssertRC(rc);
1174
1175 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1176 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1177 {
1178#ifdef HWACCM_VMX_EMULATE_REALMODE
1179 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1180 {
1181 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1182 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1183 {
1184 /* Correct weird requirements for switching to protected mode. */
1185 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1186 && enmGuestMode >= PGMMODE_PROTECTED)
1187 {
1188 /* Flush the recompiler code cache as it's not unlikely
1189 * the guest will rewrite code it will later execute in real
1190 * mode (OpenBSD 4.0 is one such example)
1191 */
1192 REMFlushTBs(pVM);
1193
1194 /* DPL of all hidden selector registers must match the current CPL (0). */
1195 pCtx->csHid.Attr.n.u2Dpl = 0;
1196 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1197
1198 pCtx->dsHid.Attr.n.u2Dpl = 0;
1199 pCtx->esHid.Attr.n.u2Dpl = 0;
1200 pCtx->fsHid.Attr.n.u2Dpl = 0;
1201 pCtx->gsHid.Attr.n.u2Dpl = 0;
1202 pCtx->ssHid.Attr.n.u2Dpl = 0;
1203
1204 /* The limit must correspond to the granularity bit. */
1205 if (!pCtx->csHid.Attr.n.u1Granularity)
1206 pCtx->csHid.u32Limit &= 0xffff;
1207 if (!pCtx->dsHid.Attr.n.u1Granularity)
1208 pCtx->dsHid.u32Limit &= 0xffff;
1209 if (!pCtx->esHid.Attr.n.u1Granularity)
1210 pCtx->esHid.u32Limit &= 0xffff;
1211 if (!pCtx->fsHid.Attr.n.u1Granularity)
1212 pCtx->fsHid.u32Limit &= 0xffff;
1213 if (!pCtx->gsHid.Attr.n.u1Granularity)
1214 pCtx->gsHid.u32Limit &= 0xffff;
1215 if (!pCtx->ssHid.Attr.n.u1Granularity)
1216 pCtx->ssHid.u32Limit &= 0xffff;
1217 }
1218 else
1219 /* Switching from protected mode to real mode. */
1220 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1221 && enmGuestMode == PGMMODE_REAL)
1222 {
1223 /* The limit must also be set to 0xffff. */
1224 pCtx->csHid.u32Limit = 0xffff;
1225 pCtx->dsHid.u32Limit = 0xffff;
1226 pCtx->esHid.u32Limit = 0xffff;
1227 pCtx->fsHid.u32Limit = 0xffff;
1228 pCtx->gsHid.u32Limit = 0xffff;
1229 pCtx->ssHid.u32Limit = 0xffff;
1230
1231 Assert(pCtx->csHid.u64Base <= 0xfffff);
1232 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1233 Assert(pCtx->esHid.u64Base <= 0xfffff);
1234 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1235 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1236 }
1237 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1238 }
1239 else
1240 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1241 if ( CPUMIsGuestInRealModeEx(pCtx)
1242 && pCtx->csHid.u64Base == 0xffff0000)
1243 {
1244 pCtx->csHid.u64Base = 0xf0000;
1245 pCtx->cs = 0xf000;
1246 }
1247 }
1248#endif /* HWACCM_VMX_EMULATE_REALMODE */
1249
1250 VMX_WRITE_SELREG(ES, es);
1251 AssertRC(rc);
1252
1253 VMX_WRITE_SELREG(CS, cs);
1254 AssertRC(rc);
1255
1256 VMX_WRITE_SELREG(SS, ss);
1257 AssertRC(rc);
1258
1259 VMX_WRITE_SELREG(DS, ds);
1260 AssertRC(rc);
1261
1262 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1263 VMX_WRITE_SELREG(FS, fs);
1264 AssertRC(rc);
1265
1266 VMX_WRITE_SELREG(GS, gs);
1267 AssertRC(rc);
1268 }
1269
1270 /* Guest CPU context: LDTR. */
1271 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1272 {
1273 if (pCtx->ldtr == 0)
1274 {
1275 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1276 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1277 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1278 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1279 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1280 }
1281 else
1282 {
1283 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1284 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1285 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1286 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1287 }
1288 AssertRC(rc);
1289 }
1290 /* Guest CPU context: TR. */
1291 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1292 {
1293#ifdef HWACCM_VMX_EMULATE_REALMODE
1294 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1295 if (CPUMIsGuestInRealModeEx(pCtx))
1296 {
1297 RTGCPHYS GCPhys;
1298
1299 /* We convert it here every time as pci regions could be reconfigured. */
1300 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1301 AssertRC(rc);
1302
1303 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1304 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1305 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1306
1307 X86DESCATTR attr;
1308
1309 attr.u = 0;
1310 attr.n.u1Present = 1;
1311 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1312 val = attr.u;
1313 }
1314 else
1315#endif /* HWACCM_VMX_EMULATE_REALMODE */
1316 {
1317 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1318 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1319 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1320
1321 val = pCtx->trHid.Attr.u;
1322
1323 /* The TSS selector must be busy. */
1324 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1325 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1326 else
1327 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1328 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1329
1330 }
1331 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1332 AssertRC(rc);
1333 }
1334 /* Guest CPU context: GDTR. */
1335 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1336 {
1337 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1338 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1339 AssertRC(rc);
1340 }
1341 /* Guest CPU context: IDTR. */
1342 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1343 {
1344 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1345 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1346 AssertRC(rc);
1347 }
1348
1349 /*
1350 * Sysenter MSRs (unconditional)
1351 */
1352 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1353 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1354 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1355 AssertRC(rc);
1356
1357 /* Control registers */
1358 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1359 {
1360 val = pCtx->cr0;
1361 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1362 Log2(("Guest CR0-shadow %08x\n", val));
1363 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1364 {
1365 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1366 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1367 }
1368 else
1369 {
1370 /** @todo check if we support the old style mess correctly. */
1371 if (!(val & X86_CR0_NE))
1372 Log(("Forcing X86_CR0_NE!!!\n"));
1373
1374 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1375 }
1376 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1377 val |= X86_CR0_PE | X86_CR0_PG;
1378 if (pVM->hwaccm.s.fNestedPaging)
1379 {
1380 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1381 {
1382 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1383 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1384 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1385 }
1386 else
1387 {
1388 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1389 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1390 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1391 }
1392 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1393 AssertRC(rc);
1394 }
1395 else
1396 {
1397 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1398 val |= X86_CR0_WP;
1399 }
1400
1401 /* Always enable caching. */
1402 val &= ~(X86_CR0_CD|X86_CR0_NW);
1403
1404 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1405 Log2(("Guest CR0 %08x\n", val));
1406 /* CR0 flags owned by the host; if the guests attempts to change them, then
1407 * the VM will exit.
1408 */
1409 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1410 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1411 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1412 | X86_CR0_TS
1413 | X86_CR0_ET /* Bit not restored during VM-exit! */
1414 | X86_CR0_CD /* Bit not restored during VM-exit! */
1415 | X86_CR0_NW /* Bit not restored during VM-exit! */
1416 | X86_CR0_NE
1417 | X86_CR0_MP;
1418 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1419
1420 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1421 Log2(("Guest CR0-mask %08x\n", val));
1422 AssertRC(rc);
1423 }
1424 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1425 {
1426 /* CR4 */
1427 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1428 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1429 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1430 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1431
1432 if (!pVM->hwaccm.s.fNestedPaging)
1433 {
1434 switch(pVCpu->hwaccm.s.enmShadowMode)
1435 {
1436 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1437 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1438 case PGMMODE_32_BIT: /* 32-bit paging. */
1439 val &= ~X86_CR4_PAE;
1440 break;
1441
1442 case PGMMODE_PAE: /* PAE paging. */
1443 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1444 /** @todo use normal 32 bits paging */
1445 val |= X86_CR4_PAE;
1446 break;
1447
1448 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1449 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1450#ifdef VBOX_ENABLE_64_BITS_GUESTS
1451 break;
1452#else
1453 AssertFailed();
1454 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1455#endif
1456 default: /* shut up gcc */
1457 AssertFailed();
1458 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1459 }
1460 }
1461 else
1462 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1463 {
1464 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1465 val |= X86_CR4_PSE;
1466 /* Our identity mapping is a 32 bits page directory. */
1467 val &= ~X86_CR4_PAE;
1468 }
1469
1470#ifdef HWACCM_VMX_EMULATE_REALMODE
1471 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1472 if (CPUMIsGuestInRealModeEx(pCtx))
1473 val |= X86_CR4_VME;
1474#endif /* HWACCM_VMX_EMULATE_REALMODE */
1475
1476 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1477 Log2(("Guest CR4 %08x\n", val));
1478 /* CR4 flags owned by the host; if the guests attempts to change them, then
1479 * the VM will exit.
1480 */
1481 val = 0
1482#ifdef HWACCM_VMX_EMULATE_REALMODE
1483 | (pVM->hwaccm.s.vmx.pRealModeTSS ? X86_CR4_VME : 0)
1484#endif
1485 | X86_CR4_PAE
1486 | X86_CR4_PGE
1487 | X86_CR4_PSE
1488 | X86_CR4_VMXE;
1489 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1490
1491 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1492 Log2(("Guest CR4-mask %08x\n", val));
1493 AssertRC(rc);
1494 }
1495
1496 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1497 {
1498 if (pVM->hwaccm.s.fNestedPaging)
1499 {
1500 AssertMsg( PGMGetEPTCR3(pVM) == PGMGetHyperCR3(pVM)
1501 || VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
1502 ("%RHp vs %RHp\n", PGMGetEPTCR3(pVM), PGMGetHyperCR3(pVM)));
1503 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetEPTCR3(pVM);
1504
1505 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1506 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1507 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1508 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1509
1510 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1511 AssertRC(rc);
1512
1513 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1514 {
1515 RTGCPHYS GCPhys;
1516
1517 /* We convert it here every time as pci regions could be reconfigured. */
1518 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1519 AssertRC(rc);
1520
1521 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1522 * take care of the translation to host physical addresses.
1523 */
1524 val = GCPhys;
1525 }
1526 else
1527 {
1528 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1529 val = pCtx->cr3;
1530 /* Prefetch the four PDPT entries in PAE mode. */
1531 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1532 }
1533 }
1534 else
1535 {
1536 val = PGMGetHyperCR3(pVM);
1537 Assert(val || VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
1538 }
1539
1540 /* Save our shadow CR3 register. */
1541 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1542 AssertRC(rc);
1543 }
1544
1545 /* Debug registers. */
1546 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1547 {
1548 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1549 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1550
1551 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1552 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1553 pCtx->dr[7] |= 0x400; /* must be one */
1554
1555 /* Resync DR7 */
1556 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1557 AssertRC(rc);
1558
1559 /* Sync the debug state now if any breakpoint is armed. */
1560 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1561 && !CPUMIsGuestDebugStateActive(pVM)
1562 && !DBGFIsStepping(pVM))
1563 {
1564 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1565
1566 /* Disable drx move intercepts. */
1567 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1568 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1569 AssertRC(rc);
1570
1571 /* Save the host and load the guest debug state. */
1572 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1573 AssertRC(rc);
1574 }
1575
1576 /* IA32_DEBUGCTL MSR. */
1577 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1578 AssertRC(rc);
1579
1580 /** @todo do we really ever need this? */
1581 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1582 AssertRC(rc);
1583 }
1584
1585 /* EIP, ESP and EFLAGS */
1586 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1587 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1588 AssertRC(rc);
1589
1590 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1591 eflags = pCtx->eflags;
1592 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1593 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1594
1595#ifdef HWACCM_VMX_EMULATE_REALMODE
1596 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1597 if (CPUMIsGuestInRealModeEx(pCtx))
1598 {
1599 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1600
1601 eflags.Bits.u1VM = 1;
1602 eflags.Bits.u2IOPL = 3;
1603 }
1604#endif /* HWACCM_VMX_EMULATE_REALMODE */
1605 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1606 AssertRC(rc);
1607
1608 /* TSC offset. */
1609 uint64_t u64TSCOffset;
1610
1611 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1612 {
1613 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1614 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1615 AssertRC(rc);
1616
1617 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1618 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1619 AssertRC(rc);
1620 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1621 }
1622 else
1623 {
1624 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1625 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1626 AssertRC(rc);
1627 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1628 }
1629
1630 /* 64 bits guest mode? */
1631 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1632 {
1633#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1634 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1635#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1636 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1637#else
1638# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1639 if (!pVM->hwaccm.s.fAllow64BitGuests)
1640 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1641# endif
1642 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1643#endif
1644 /* Unconditionally update these as wrmsr might have changed them. */
1645 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1646 AssertRC(rc);
1647 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1648 AssertRC(rc);
1649 }
1650 else
1651 {
1652 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1653 }
1654
1655#if 0 /* @todo deal with 32/64 */
1656 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1657 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1658 {
1659 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1660 AssertRC(rc);
1661 }
1662#endif
1663
1664 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1665
1666 /* Done. */
1667 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1668
1669 return rc;
1670}
1671
1672/**
1673 * Syncs back the guest state
1674 *
1675 * @returns VBox status code.
1676 * @param pVM The VM to operate on.
1677 * @param pVCpu The VMCPU to operate on.
1678 * @param pCtx Guest context
1679 */
1680DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1681{
1682 RTGCUINTREG val, valShadow;
1683 RTGCUINTPTR uInterruptState;
1684 int rc;
1685
1686 /* Let's first sync back eip, esp, and eflags. */
1687 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1688 AssertRC(rc);
1689 pCtx->rip = val;
1690 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1691 AssertRC(rc);
1692 pCtx->rsp = val;
1693 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1694 AssertRC(rc);
1695 pCtx->eflags.u32 = val;
1696
1697 /* Take care of instruction fusing (sti, mov ss) */
1698 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1699 uInterruptState = val;
1700 if (uInterruptState != 0)
1701 {
1702 Assert(uInterruptState <= 2); /* only sti & mov ss */
1703 Log(("uInterruptState %x eip=%RGv\n", uInterruptState, pCtx->rip));
1704 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1705 }
1706 else
1707 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1708
1709 /* Control registers. */
1710 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1711 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1712 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1713 CPUMSetGuestCR0(pVM, val);
1714
1715 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1716 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1717 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1718 CPUMSetGuestCR4(pVM, val);
1719
1720 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1721 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1722 if ( pVM->hwaccm.s.fNestedPaging
1723 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1724 {
1725 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1726
1727 /* Can be updated behind our back in the nested paging case. */
1728 CPUMSetGuestCR2(pVM, pCache->cr2);
1729
1730 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1731
1732 if (val != pCtx->cr3)
1733 {
1734 CPUMSetGuestCR3(pVM, val);
1735 PGMUpdateCR3(pVM, val);
1736 }
1737 /* Prefetch the four PDPT entries in PAE mode. */
1738 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1739 }
1740
1741 /* Sync back DR7 here. */
1742 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1743 pCtx->dr[7] = val;
1744
1745 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1746 VMX_READ_SELREG(ES, es);
1747 VMX_READ_SELREG(SS, ss);
1748 VMX_READ_SELREG(CS, cs);
1749 VMX_READ_SELREG(DS, ds);
1750 VMX_READ_SELREG(FS, fs);
1751 VMX_READ_SELREG(GS, gs);
1752
1753 /*
1754 * System MSRs
1755 */
1756 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1757 pCtx->SysEnter.cs = val;
1758 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1759 pCtx->SysEnter.eip = val;
1760 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1761 pCtx->SysEnter.esp = val;
1762
1763 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1764 VMX_READ_SELREG(LDTR, ldtr);
1765
1766 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1767 pCtx->gdtr.cbGdt = val;
1768 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1769 pCtx->gdtr.pGdt = val;
1770
1771 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1772 pCtx->idtr.cbIdt = val;
1773 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1774 pCtx->idtr.pIdt = val;
1775
1776#ifdef HWACCM_VMX_EMULATE_REALMODE
1777 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1778 if (CPUMIsGuestInRealModeEx(pCtx))
1779 {
1780 /* Hide our emulation flags */
1781 pCtx->eflags.Bits.u1VM = 0;
1782 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1783
1784 /* Force a TR resync every time in case we switch modes. */
1785 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1786 }
1787 else
1788#endif /* HWACCM_VMX_EMULATE_REALMODE */
1789 {
1790 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1791 VMX_READ_SELREG(TR, tr);
1792 }
1793 return VINF_SUCCESS;
1794}
1795
1796/**
1797 * Dummy placeholder
1798 *
1799 * @param pVM The VM to operate on.
1800 * @param pVCpu The VMCPU to operate on.
1801 */
1802static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1803{
1804 NOREF(pVM);
1805 NOREF(pVCpu);
1806 return;
1807}
1808
1809/**
1810 * Setup the tagged TLB for EPT
1811 *
1812 * @returns VBox status code.
1813 * @param pVM The VM to operate on.
1814 * @param pVCpu The VMCPU to operate on.
1815 */
1816static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1817{
1818 PHWACCM_CPUINFO pCpu;
1819
1820 Assert(pVM->hwaccm.s.fNestedPaging);
1821 Assert(!pVM->hwaccm.s.vmx.fVPID);
1822
1823 /* Deal with tagged TLBs if VPID or EPT is supported. */
1824 pCpu = HWACCMR0GetCurrentCpu();
1825 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1826 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1827 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1828 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1829 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1830 {
1831 /* Force a TLB flush on VM entry. */
1832 pVCpu->hwaccm.s.fForceTLBFlush = true;
1833 }
1834 else
1835 Assert(!pCpu->fFlushTLB);
1836
1837 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1838 pCpu->fFlushTLB = false;
1839
1840 if (pVCpu->hwaccm.s.fForceTLBFlush)
1841 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1842
1843#ifdef VBOX_WITH_STATISTICS
1844 if (pVCpu->hwaccm.s.fForceTLBFlush)
1845 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1846 else
1847 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1848#endif
1849}
1850
1851#ifdef HWACCM_VTX_WITH_VPID
1852/**
1853 * Setup the tagged TLB for VPID
1854 *
1855 * @returns VBox status code.
1856 * @param pVM The VM to operate on.
1857 * @param pVCpu The VMCPU to operate on.
1858 */
1859static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1860{
1861 PHWACCM_CPUINFO pCpu;
1862
1863 Assert(pVM->hwaccm.s.vmx.fVPID);
1864 Assert(!pVM->hwaccm.s.fNestedPaging);
1865
1866 /* Deal with tagged TLBs if VPID or EPT is supported. */
1867 pCpu = HWACCMR0GetCurrentCpu();
1868 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1869 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1870 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1871 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1872 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1873 {
1874 /* Force a TLB flush on VM entry. */
1875 pVCpu->hwaccm.s.fForceTLBFlush = true;
1876 }
1877 else
1878 Assert(!pCpu->fFlushTLB);
1879
1880 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1881
1882 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1883 if (pVCpu->hwaccm.s.fForceTLBFlush)
1884 {
1885 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1886 || pCpu->fFlushTLB)
1887 {
1888 pCpu->fFlushTLB = false;
1889 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1890 pCpu->cTLBFlushes++;
1891 }
1892 else
1893 {
1894 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1895 pVCpu->hwaccm.s.fForceTLBFlush = false;
1896 }
1897
1898 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1899 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1900 }
1901 else
1902 {
1903 Assert(!pCpu->fFlushTLB);
1904
1905 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1906 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1907 }
1908 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1909 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1910 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1911
1912 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1913 AssertRC(rc);
1914
1915 if (pVCpu->hwaccm.s.fForceTLBFlush)
1916 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1917
1918#ifdef VBOX_WITH_STATISTICS
1919 if (pVCpu->hwaccm.s.fForceTLBFlush)
1920 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1921 else
1922 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1923#endif
1924}
1925#endif /* HWACCM_VTX_WITH_VPID */
1926
1927/**
1928 * Runs guest code in a VT-x VM.
1929 *
1930 * @returns VBox status code.
1931 * @param pVM The VM to operate on.
1932 * @param pVCpu The VMCPU to operate on.
1933 * @param pCtx Guest context
1934 */
1935VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1936{
1937 int rc = VINF_SUCCESS;
1938 RTGCUINTREG val;
1939 RTGCUINTREG exitReason, instrError, cbInstr;
1940 RTGCUINTPTR exitQualification;
1941 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1942 RTGCUINTPTR errCode, instrInfo;
1943 bool fSyncTPR = false;
1944 PHWACCM_CPUINFO pCpu = 0;
1945 unsigned cResume = 0;
1946#ifdef VBOX_STRICT
1947 RTCPUID idCpuCheck;
1948#endif
1949#ifdef VBOX_WITH_STATISTICS
1950 bool fStatEntryStarted = true;
1951 bool fStatExit2Started = false;
1952#endif
1953
1954 Log2(("\nE"));
1955
1956 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
1957
1958#ifdef VBOX_STRICT
1959 {
1960 RTCCUINTREG val;
1961
1962 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1963 AssertRC(rc);
1964 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1965
1966 /* allowed zero */
1967 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1968 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1969
1970 /* allowed one */
1971 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1972 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1973
1974 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1975 AssertRC(rc);
1976 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1977
1978 /* Must be set according to the MSR, but can be cleared in case of EPT. */
1979 if (pVM->hwaccm.s.fNestedPaging)
1980 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
1981 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1982 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1983
1984 /* allowed zero */
1985 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1986 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1987
1988 /* allowed one */
1989 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1990 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1991
1992 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1993 AssertRC(rc);
1994 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1995
1996 /* allowed zero */
1997 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1998 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1999
2000 /* allowed one */
2001 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2002 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2003
2004 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2005 AssertRC(rc);
2006 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2007
2008 /* allowed zero */
2009 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2010 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2011
2012 /* allowed one */
2013 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2014 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2015 }
2016#endif
2017
2018#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2019 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2020#endif
2021
2022 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2023 */
2024ResumeExecution:
2025 STAM_STATS({
2026 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2027 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2028 });
2029 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2030 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2031 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2032 Assert(!HWACCMR0SuspendPending());
2033
2034 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2035 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
2036 {
2037 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2038 rc = VINF_EM_RAW_INTERRUPT;
2039 goto end;
2040 }
2041
2042 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2043 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
2044 {
2045 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
2046 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
2047 {
2048 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2049 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2050 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2051 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2052 */
2053 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
2054 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2055 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2056 AssertRC(rc);
2057 }
2058 }
2059 else
2060 {
2061 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2062 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2063 AssertRC(rc);
2064 }
2065
2066 /* Check for pending actions that force us to go back to ring 3. */
2067 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
2068 {
2069 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
2070 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2071 rc = VINF_EM_RAW_TO_R3;
2072 goto end;
2073 }
2074 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2075 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
2076 {
2077 rc = VINF_EM_PENDING_REQUEST;
2078 goto end;
2079 }
2080
2081 /* When external interrupts are pending, we should exit the VM when IF is set. */
2082 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2083 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2084 if (RT_FAILURE(rc))
2085 goto end;
2086
2087 /** @todo check timers?? */
2088
2089 /* TPR caching using CR8 is only available in 64 bits mode */
2090 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2091 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2092 /**
2093 * @todo reduce overhead
2094 */
2095 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
2096 && pVM->hwaccm.s.vmx.pAPIC)
2097 {
2098 /* TPR caching in CR8 */
2099 uint8_t u8TPR;
2100 bool fPending;
2101
2102 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
2103 AssertRC(rc);
2104 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2105 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
2106
2107 /* Two options here:
2108 * - external interrupt pending, but masked by the TPR value.
2109 * -> a CR8 update that lower the current TPR value should cause an exit
2110 * - no pending interrupts
2111 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2112 */
2113 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
2114 AssertRC(rc);
2115
2116 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
2117 fSyncTPR = true;
2118 }
2119
2120#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2121 if ( pVM->hwaccm.s.fNestedPaging
2122# ifdef HWACCM_VTX_WITH_VPID
2123 || pVM->hwaccm.s.vmx.fVPID
2124# endif /* HWACCM_VTX_WITH_VPID */
2125 )
2126 {
2127 pCpu = HWACCMR0GetCurrentCpu();
2128 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2129 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2130 {
2131 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2132 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2133 else
2134 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2135 }
2136 if (pCpu->fFlushTLB)
2137 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2138 else
2139 if (pVCpu->hwaccm.s.fForceTLBFlush)
2140 LogFlow(("Manual TLB flush\n"));
2141 }
2142#endif
2143#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2144 PGMDynMapFlushAutoSet(pVCpu);
2145#endif
2146
2147 /*
2148 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2149 * (until the actual world switch)
2150 */
2151#ifdef VBOX_STRICT
2152 idCpuCheck = RTMpCpuId();
2153#endif
2154#ifdef LOG_LOGGING
2155 VMMR0LogFlushDisable(pVCpu);
2156#endif
2157 /* Save the host state first. */
2158 rc = VMXR0SaveHostState(pVM, pVCpu);
2159 if (rc != VINF_SUCCESS)
2160 goto end;
2161 /* Load the guest state */
2162 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2163 if (rc != VINF_SUCCESS)
2164 goto end;
2165
2166 /* Deal with tagged TLB setup and invalidation. */
2167 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2168
2169 /* Non-register state Guest Context */
2170 /** @todo change me according to cpu state */
2171 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2172 AssertRC(rc);
2173
2174 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2175
2176 /* Manual save and restore:
2177 * - General purpose registers except RIP, RSP
2178 *
2179 * Trashed:
2180 * - CR2 (we don't care)
2181 * - LDTR (reset to 0)
2182 * - DRx (presumably not changed at all)
2183 * - DR7 (reset to 0x400)
2184 * - EFLAGS (reset to RT_BIT(1); not relevant)
2185 *
2186 */
2187
2188
2189 /* All done! Let's start VM execution. */
2190 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2191#ifdef VBOX_STRICT
2192 Assert(idCpuCheck == RTMpCpuId());
2193#endif
2194
2195#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2196 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2197 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2198#endif
2199
2200 TMNotifyStartOfExecution(pVM);
2201 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2202 TMNotifyEndOfExecution(pVM);
2203
2204 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2205
2206 /* In case we execute a goto ResumeExecution later on. */
2207 pVCpu->hwaccm.s.fResumeVM = true;
2208 pVCpu->hwaccm.s.fForceTLBFlush = false;
2209
2210 /*
2211 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2212 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2213 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2214 */
2215 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2216 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2217
2218 if (rc != VINF_SUCCESS)
2219 {
2220 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2221 goto end;
2222 }
2223
2224 /* Success. Query the guest state and figure out what has happened. */
2225
2226 /* Investigate why there was a VM-exit. */
2227 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2228 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2229
2230 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2231 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2232 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2233 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2234 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2235 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2236 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2237 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2238 AssertRC(rc);
2239
2240 /* Sync back the guest state */
2241 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2242 AssertRC(rc);
2243
2244 /* Note! NOW IT'S SAFE FOR LOGGING! */
2245#ifdef LOG_LOGGING
2246 VMMR0LogFlushEnable(pVCpu);
2247#endif
2248 Log2(("Raw exit reason %08x\n", exitReason));
2249
2250 /* Check if an injected event was interrupted prematurely. */
2251 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2252 AssertRC(rc);
2253 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2254 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2255 /* Ignore 'int xx' as they'll be restarted anyway. */
2256 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2257 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2258 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2259 {
2260 pVCpu->hwaccm.s.Event.fPending = true;
2261 /* Error code present? */
2262 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2263 {
2264 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2265 AssertRC(rc);
2266 pVCpu->hwaccm.s.Event.errCode = val;
2267 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2268 }
2269 else
2270 {
2271 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2272 pVCpu->hwaccm.s.Event.errCode = 0;
2273 }
2274 }
2275#ifdef VBOX_STRICT
2276 else
2277 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2278 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2279 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2280 {
2281 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2282 }
2283
2284 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2285 HWACCMDumpRegs(pVM, pCtx);
2286#endif
2287
2288 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2289 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2290 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2291 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2292 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2293
2294 if (fSyncTPR)
2295 {
2296 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
2297 AssertRC(rc);
2298 }
2299
2300 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2301 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2302
2303 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2304 switch (exitReason)
2305 {
2306 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2307 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2308 {
2309 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2310
2311 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2312 {
2313 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2314 /* External interrupt; leave to allow it to be dispatched again. */
2315 rc = VINF_EM_RAW_INTERRUPT;
2316 break;
2317 }
2318 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2319 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2320 {
2321 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2322 /* External interrupt; leave to allow it to be dispatched again. */
2323 rc = VINF_EM_RAW_INTERRUPT;
2324 break;
2325
2326 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2327 AssertFailed(); /* can't come here; fails the first check. */
2328 break;
2329
2330 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2331 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2332 Assert(vector == 1 || vector == 3 || vector == 4);
2333 /* no break */
2334 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2335 Log2(("Hardware/software interrupt %d\n", vector));
2336 switch (vector)
2337 {
2338 case X86_XCPT_NM:
2339 {
2340 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2341
2342 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2343 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2344 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2345 if (rc == VINF_SUCCESS)
2346 {
2347 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2348
2349 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2350
2351 /* Continue execution. */
2352 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2353
2354 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2355 goto ResumeExecution;
2356 }
2357
2358 Log(("Forward #NM fault to the guest\n"));
2359 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2360 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2361 AssertRC(rc);
2362 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2363 goto ResumeExecution;
2364 }
2365
2366 case X86_XCPT_PF: /* Page fault */
2367 {
2368#ifdef DEBUG
2369 if (pVM->hwaccm.s.fNestedPaging)
2370 { /* A genuine pagefault.
2371 * Forward the trap to the guest by injecting the exception and resuming execution.
2372 */
2373 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2374
2375 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2376
2377 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2378
2379 /* Now we must update CR2. */
2380 pCtx->cr2 = exitQualification;
2381 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2382 AssertRC(rc);
2383
2384 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2385 goto ResumeExecution;
2386 }
2387#endif
2388 Assert(!pVM->hwaccm.s.fNestedPaging);
2389
2390 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2391 /* Exit qualification contains the linear address of the page fault. */
2392 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2393 TRPMSetErrorCode(pVM, errCode);
2394 TRPMSetFaultAddress(pVM, exitQualification);
2395
2396 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2397 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2398 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2399 if (rc == VINF_SUCCESS)
2400 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2401 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2402 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2403
2404 TRPMResetTrap(pVM);
2405
2406 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2407 goto ResumeExecution;
2408 }
2409 else
2410 if (rc == VINF_EM_RAW_GUEST_TRAP)
2411 { /* A genuine pagefault.
2412 * Forward the trap to the guest by injecting the exception and resuming execution.
2413 */
2414 Log2(("Forward page fault to the guest\n"));
2415
2416 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2417 /* The error code might have been changed. */
2418 errCode = TRPMGetErrorCode(pVM);
2419
2420 TRPMResetTrap(pVM);
2421
2422 /* Now we must update CR2. */
2423 pCtx->cr2 = exitQualification;
2424 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2425 AssertRC(rc);
2426
2427 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2428 goto ResumeExecution;
2429 }
2430#ifdef VBOX_STRICT
2431 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2432 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2433#endif
2434 /* Need to go back to the recompiler to emulate the instruction. */
2435 TRPMResetTrap(pVM);
2436 break;
2437 }
2438
2439 case X86_XCPT_MF: /* Floating point exception. */
2440 {
2441 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2442 if (!(pCtx->cr0 & X86_CR0_NE))
2443 {
2444 /* old style FPU error reporting needs some extra work. */
2445 /** @todo don't fall back to the recompiler, but do it manually. */
2446 rc = VINF_EM_RAW_EMULATE_INSTR;
2447 break;
2448 }
2449 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2450 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2451 AssertRC(rc);
2452
2453 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2454 goto ResumeExecution;
2455 }
2456
2457 case X86_XCPT_DB: /* Debug exception. */
2458 {
2459 uint64_t uDR6;
2460
2461 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2462 *
2463 * Exit qualification bits:
2464 * 3:0 B0-B3 which breakpoint condition was met
2465 * 12:4 Reserved (0)
2466 * 13 BD - debug register access detected
2467 * 14 BS - single step execution or branch taken
2468 * 63:15 Reserved (0)
2469 */
2470 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2471
2472 /* Note that we don't support guest and host-initiated debugging at the same time. */
2473 Assert(DBGFIsStepping(pVM) || CPUMIsGuestInRealModeEx(pCtx));
2474
2475 uDR6 = X86_DR6_INIT_VAL;
2476 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2477 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
2478 if (rc == VINF_EM_RAW_GUEST_TRAP)
2479 {
2480 /** @todo this isn't working, but we'll never get here normally. */
2481
2482 /* Update DR6 here. */
2483 pCtx->dr[6] = uDR6;
2484
2485 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2486 pCtx->dr[7] &= ~X86_DR7_GD;
2487
2488 /* Paranoia. */
2489 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2490 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2491 pCtx->dr[7] |= 0x400; /* must be one */
2492
2493 /* Resync DR7 */
2494 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2495 AssertRC(rc);
2496
2497 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2498 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2499 AssertRC(rc);
2500
2501 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2502 goto ResumeExecution;
2503 }
2504 /* Return to ring 3 to deal with the debug exit code. */
2505 break;
2506 }
2507
2508#ifdef DEBUG /* till after branching, enable by default after that. */
2509 case X86_XCPT_BP: /* Breakpoint. */
2510 {
2511 rc = DBGFR0Trap03Handler(pVM, CPUMCTX2CORE(pCtx));
2512 if (rc == VINF_EM_RAW_GUEST_TRAP)
2513 {
2514 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2515 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2516 AssertRC(rc);
2517 goto ResumeExecution;
2518 }
2519 if (rc == VINF_SUCCESS)
2520 goto ResumeExecution;
2521 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2522 break;
2523 }
2524#endif
2525
2526 case X86_XCPT_GP: /* General protection failure exception.*/
2527 {
2528 uint32_t cbSize;
2529
2530 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2531#ifdef VBOX_STRICT
2532 if (!CPUMIsGuestInRealModeEx(pCtx))
2533 {
2534 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2535 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2536 AssertRC(rc);
2537 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2538 goto ResumeExecution;
2539 }
2540#endif
2541 Assert(CPUMIsGuestInRealModeEx(pCtx));
2542
2543 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2544 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2545 if (rc == VINF_SUCCESS)
2546 {
2547 /* EIP has been updated already. */
2548
2549 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2550 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2551
2552 /* Only resume if successful. */
2553 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2554 goto ResumeExecution;
2555 }
2556 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2557 break;
2558 }
2559
2560#ifdef VBOX_STRICT
2561 case X86_XCPT_DE: /* Divide error. */
2562 case X86_XCPT_UD: /* Unknown opcode exception. */
2563 case X86_XCPT_SS: /* Stack segment exception. */
2564 case X86_XCPT_NP: /* Segment not present exception. */
2565 {
2566 switch(vector)
2567 {
2568 case X86_XCPT_DE:
2569 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2570 break;
2571 case X86_XCPT_UD:
2572 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2573 break;
2574 case X86_XCPT_SS:
2575 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2576 break;
2577 case X86_XCPT_NP:
2578 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2579 break;
2580 }
2581
2582 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2583 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2584 AssertRC(rc);
2585
2586 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2587 goto ResumeExecution;
2588 }
2589#endif
2590 default:
2591#ifdef HWACCM_VMX_EMULATE_REALMODE
2592 if (CPUMIsGuestInRealModeEx(pCtx))
2593 {
2594 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2595 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2596 AssertRC(rc);
2597
2598 /* Go back to ring 3 in case of a triple fault. */
2599 if ( vector == X86_XCPT_DF
2600 && rc == VINF_EM_RESET)
2601 break;
2602
2603 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2604 goto ResumeExecution;
2605 }
2606#endif
2607 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2608 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2609 break;
2610 } /* switch (vector) */
2611
2612 break;
2613
2614 default:
2615 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2616 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2617 break;
2618 }
2619
2620 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2621 break;
2622 }
2623
2624 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2625 {
2626 RTGCPHYS GCPhys;
2627
2628 Assert(pVM->hwaccm.s.fNestedPaging);
2629
2630 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2631 AssertRC(rc);
2632 Assert(((exitQualification >> 7) & 3) != 2);
2633
2634 /* Determine the kind of violation. */
2635 errCode = 0;
2636 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2637 errCode |= X86_TRAP_PF_ID;
2638
2639 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2640 errCode |= X86_TRAP_PF_RW;
2641
2642 /* If the page is present, then it's a page level protection fault. */
2643 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2644 errCode |= X86_TRAP_PF_P;
2645
2646 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2647
2648 /* GCPhys contains the guest physical address of the page fault. */
2649 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2650 TRPMSetErrorCode(pVM, errCode);
2651 TRPMSetFaultAddress(pVM, GCPhys);
2652
2653 /* Handle the pagefault trap for the nested shadow table. */
2654 rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2655 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2656 if (rc == VINF_SUCCESS)
2657 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2658 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
2659 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
2660
2661 TRPMResetTrap(pVM);
2662
2663 goto ResumeExecution;
2664 }
2665
2666#ifdef VBOX_STRICT
2667 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2668 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2669#endif
2670 /* Need to go back to the recompiler to emulate the instruction. */
2671 TRPMResetTrap(pVM);
2672 break;
2673 }
2674
2675 case VMX_EXIT_EPT_MISCONFIG:
2676 {
2677 RTGCPHYS GCPhys;
2678
2679 Assert(pVM->hwaccm.s.fNestedPaging);
2680
2681 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2682 AssertRC(rc);
2683
2684 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
2685 break;
2686 }
2687
2688 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2689 /* Clear VM-exit on IF=1 change. */
2690 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2691 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2692 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2693 AssertRC(rc);
2694 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
2695 goto ResumeExecution; /* we check for pending guest interrupts there */
2696
2697 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2698 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2699 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
2700 /* Skip instruction and continue directly. */
2701 pCtx->rip += cbInstr;
2702 /* Continue execution.*/
2703 goto ResumeExecution;
2704
2705 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2706 {
2707 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2708 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
2709 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
2710 if (rc == VINF_SUCCESS)
2711 {
2712 /* Update EIP and continue execution. */
2713 Assert(cbInstr == 2);
2714 pCtx->rip += cbInstr;
2715 goto ResumeExecution;
2716 }
2717 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
2718 rc = VINF_EM_RAW_EMULATE_INSTR;
2719 break;
2720 }
2721
2722 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2723 {
2724 Log2(("VMX: Rdtsc\n"));
2725 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2726 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
2727 if (rc == VINF_SUCCESS)
2728 {
2729 /* Update EIP and continue execution. */
2730 Assert(cbInstr == 2);
2731 pCtx->rip += cbInstr;
2732 goto ResumeExecution;
2733 }
2734 AssertMsgFailed(("EMU: rdtsc failed with %Rrc\n", rc));
2735 rc = VINF_EM_RAW_EMULATE_INSTR;
2736 break;
2737 }
2738
2739 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2740 {
2741 Log2(("VMX: invlpg\n"));
2742 Assert(!pVM->hwaccm.s.fNestedPaging);
2743
2744 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2745 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
2746 if (rc == VINF_SUCCESS)
2747 {
2748 /* Update EIP and continue execution. */
2749 pCtx->rip += cbInstr;
2750 goto ResumeExecution;
2751 }
2752 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
2753 break;
2754 }
2755
2756 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2757 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2758 {
2759 uint32_t cbSize;
2760
2761 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2762 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
2763 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2764 if (rc == VINF_SUCCESS)
2765 {
2766 /* EIP has been updated already. */
2767
2768 /* Only resume if successful. */
2769 goto ResumeExecution;
2770 }
2771 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
2772 break;
2773 }
2774
2775 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2776 {
2777 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2778
2779 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
2780 {
2781 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
2782 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
2783 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
2784 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
2785 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
2786 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
2787
2788 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
2789 {
2790 case 0:
2791 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
2792 break;
2793 case 2:
2794 break;
2795 case 3:
2796 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
2797 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2798 break;
2799 case 4:
2800 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2801 break;
2802 case 8:
2803 /* CR8 contains the APIC TPR */
2804 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2805 break;
2806
2807 default:
2808 AssertFailed();
2809 break;
2810 }
2811 /* Check if a sync operation is pending. */
2812 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2813 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2814 {
2815 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2816 AssertRC(rc);
2817 }
2818 break;
2819
2820 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
2821 Log2(("VMX: mov x, crx\n"));
2822 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
2823
2824 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
2825
2826 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
2827 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2828
2829 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
2830 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
2831 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
2832 break;
2833
2834 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2835 Log2(("VMX: clts\n"));
2836 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
2837 rc = EMInterpretCLTS(pVM);
2838 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2839 break;
2840
2841 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2842 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2843 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
2844 rc = EMInterpretLMSW(pVM, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2845 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2846 break;
2847 }
2848
2849 /* Update EIP if no error occurred. */
2850 if (RT_SUCCESS(rc))
2851 pCtx->rip += cbInstr;
2852
2853 if (rc == VINF_SUCCESS)
2854 {
2855 /* Only resume if successful. */
2856 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2857 goto ResumeExecution;
2858 }
2859 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2860 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2861 break;
2862 }
2863
2864 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2865 {
2866 if (!DBGFIsStepping(pVM))
2867 {
2868 /* Disable drx move intercepts. */
2869 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2870 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2871 AssertRC(rc);
2872
2873 /* Save the host and load the guest debug state. */
2874 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
2875 AssertRC(rc);
2876
2877#ifdef VBOX_WITH_STATISTICS
2878 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2879 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2880 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2881 else
2882 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2883#endif
2884
2885 goto ResumeExecution;
2886 }
2887
2888 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2889 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2890 {
2891 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2892 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2893 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2894 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2895 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2896 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2897 Log2(("DR7=%08x\n", pCtx->dr[7]));
2898 }
2899 else
2900 {
2901 Log2(("VMX: mov x, drx\n"));
2902 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2903 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2904 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2905 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2906 }
2907 /* Update EIP if no error occurred. */
2908 if (RT_SUCCESS(rc))
2909 pCtx->rip += cbInstr;
2910
2911 if (rc == VINF_SUCCESS)
2912 {
2913 /* Only resume if successful. */
2914 goto ResumeExecution;
2915 }
2916 Assert(rc == VERR_EM_INTERPRETER);
2917 break;
2918 }
2919
2920 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2921 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2922 {
2923 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
2924 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2925 uint32_t uPort;
2926 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2927
2928 /** @todo necessary to make the distinction? */
2929 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2930 {
2931 uPort = pCtx->edx & 0xffff;
2932 }
2933 else
2934 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2935
2936 /* paranoia */
2937 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2938 {
2939 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2940 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
2941 break;
2942 }
2943
2944 uint32_t cbSize = g_aIOSize[uIOWidth];
2945
2946 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2947 {
2948 /* ins/outs */
2949 DISCPUSTATE Cpu;
2950
2951 /* Disassemble manually to deal with segment prefixes. */
2952 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
2953 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
2954 rc = EMInterpretDisasOne(pVM, CPUMCTX2CORE(pCtx), &Cpu, NULL);
2955 if (rc == VINF_SUCCESS)
2956 {
2957 if (fIOWrite)
2958 {
2959 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
2960 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2961 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
2962 }
2963 else
2964 {
2965 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
2966 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2967 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
2968 }
2969 }
2970 else
2971 rc = VINF_EM_RAW_EMULATE_INSTR;
2972 }
2973 else
2974 {
2975 /* normal in/out */
2976 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
2977
2978 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2979
2980 if (fIOWrite)
2981 {
2982 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2983 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
2984 }
2985 else
2986 {
2987 uint32_t u32Val = 0;
2988
2989 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2990 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
2991 if (IOM_SUCCESS(rc))
2992 {
2993 /* Write back to the EAX register. */
2994 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2995 }
2996 }
2997 }
2998 /*
2999 * Handled the I/O return codes.
3000 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3001 */
3002 if (IOM_SUCCESS(rc))
3003 {
3004 /* Update EIP and continue execution. */
3005 pCtx->rip += cbInstr;
3006 if (RT_LIKELY(rc == VINF_SUCCESS))
3007 {
3008 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3009 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3010 {
3011 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3012 for (unsigned i=0;i<4;i++)
3013 {
3014 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3015
3016 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3017 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3018 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3019 {
3020 uint64_t uDR6;
3021
3022 Assert(CPUMIsGuestDebugStateActive(pVM));
3023
3024 uDR6 = ASMGetDR6();
3025
3026 /* Clear all breakpoint status flags and set the one we just hit. */
3027 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3028 uDR6 |= (uint64_t)RT_BIT(i);
3029
3030 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3031 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3032 * the contents have been read.
3033 */
3034 ASMSetDR6(uDR6);
3035
3036 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3037 pCtx->dr[7] &= ~X86_DR7_GD;
3038
3039 /* Paranoia. */
3040 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3041 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3042 pCtx->dr[7] |= 0x400; /* must be one */
3043
3044 /* Resync DR7 */
3045 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3046 AssertRC(rc);
3047
3048 /* Construct inject info. */
3049 intInfo = X86_XCPT_DB;
3050 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3051 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3052
3053 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3054 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3055 AssertRC(rc);
3056
3057 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3058 goto ResumeExecution;
3059 }
3060 }
3061 }
3062
3063 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3064 goto ResumeExecution;
3065 }
3066 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3067 break;
3068 }
3069
3070#ifdef VBOX_STRICT
3071 if (rc == VINF_IOM_HC_IOPORT_READ)
3072 Assert(!fIOWrite);
3073 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3074 Assert(fIOWrite);
3075 else
3076 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3077#endif
3078 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3079 break;
3080 }
3081
3082 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3083 LogFlow(("VMX_EXIT_TPR\n"));
3084 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3085 goto ResumeExecution;
3086
3087 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3088 goto ResumeExecution;
3089
3090 default:
3091 /* The rest is handled after syncing the entire CPU state. */
3092 break;
3093 }
3094
3095 /* Note: the guest state isn't entirely synced back at this stage. */
3096
3097 /* Investigate why there was a VM-exit. (part 2) */
3098 switch (exitReason)
3099 {
3100 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3101 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3102 case VMX_EXIT_EPT_VIOLATION:
3103 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3104 /* Already handled above. */
3105 break;
3106
3107 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3108 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3109 break;
3110
3111 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3112 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3113 rc = VINF_EM_RAW_INTERRUPT;
3114 AssertFailed(); /* Can't happen. Yet. */
3115 break;
3116
3117 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3118 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3119 rc = VINF_EM_RAW_INTERRUPT;
3120 AssertFailed(); /* Can't happen afaik. */
3121 break;
3122
3123 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3124 rc = VERR_EM_INTERPRETER;
3125 break;
3126
3127 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3128 /** Check if external interrupts are pending; if so, don't switch back. */
3129 pCtx->rip++; /* skip hlt */
3130 if ( pCtx->eflags.Bits.u1IF
3131 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
3132 goto ResumeExecution;
3133
3134 rc = VINF_EM_HALT;
3135 break;
3136
3137 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3138 AssertFailed(); /* can't happen. */
3139 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3140 break;
3141
3142 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3143 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3144 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3145 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3146 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3147 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3148 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3149 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3150 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3151 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3152 /** @todo inject #UD immediately */
3153 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3154 break;
3155
3156 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3157 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3158 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3159 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3160 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3161 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3162 /* already handled above */
3163 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3164 || rc == VINF_EM_RAW_INTERRUPT
3165 || rc == VERR_EM_INTERPRETER
3166 || rc == VINF_EM_RAW_EMULATE_INSTR
3167 || rc == VINF_PGM_SYNC_CR3
3168 || rc == VINF_IOM_HC_IOPORT_READ
3169 || rc == VINF_IOM_HC_IOPORT_WRITE
3170 || rc == VINF_EM_RAW_GUEST_TRAP
3171 || rc == VINF_TRPM_XCPT_DISPATCHED
3172 || rc == VINF_EM_RESCHEDULE_REM,
3173 ("rc = %d\n", rc));
3174 break;
3175
3176 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3177 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3178 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3179 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3180 rc = VERR_EM_INTERPRETER;
3181 break;
3182
3183 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3184 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3185 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3186 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3187 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3188 break;
3189
3190 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3191 Assert(rc == VINF_EM_RAW_INTERRUPT);
3192 break;
3193
3194 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3195 {
3196#ifdef VBOX_STRICT
3197 RTCCUINTREG val = 0;
3198
3199 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3200
3201 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3202 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3203
3204 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3205 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3206
3207 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3208 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3209
3210 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3211 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3212
3213 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3214 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3215
3216 VMX_LOG_SELREG(CS, "CS");
3217 VMX_LOG_SELREG(DS, "DS");
3218 VMX_LOG_SELREG(ES, "ES");
3219 VMX_LOG_SELREG(FS, "FS");
3220 VMX_LOG_SELREG(GS, "GS");
3221 VMX_LOG_SELREG(SS, "SS");
3222 VMX_LOG_SELREG(TR, "TR");
3223 VMX_LOG_SELREG(LDTR, "LDTR");
3224
3225 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3226 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3227 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3228 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3229#endif /* VBOX_STRICT */
3230 rc = VERR_VMX_INVALID_GUEST_STATE;
3231 break;
3232 }
3233
3234 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3235 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3236 default:
3237 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3238 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3239 break;
3240
3241 }
3242end:
3243
3244 /* Signal changes for the recompiler. */
3245 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3246
3247 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3248 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3249 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3250 {
3251 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3252 /* On the next entry we'll only sync the host context. */
3253 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3254 }
3255 else
3256 {
3257 /* On the next entry we'll sync everything. */
3258 /** @todo we can do better than this */
3259 /* Not in the VINF_PGM_CHANGE_MODE though! */
3260 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3261 }
3262
3263 /* translate into a less severe return code */
3264 if (rc == VERR_EM_INTERPRETER)
3265 rc = VINF_EM_RAW_EMULATE_INSTR;
3266 else
3267 /* Try to extract more information about what might have gone wrong here. */
3268 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3269 {
3270 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3271 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3272 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3273 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3274 }
3275
3276 STAM_STATS({
3277 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3278 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3279 });
3280 Log2(("X"));
3281 return rc;
3282}
3283
3284
3285/**
3286 * Enters the VT-x session
3287 *
3288 * @returns VBox status code.
3289 * @param pVM The VM to operate on.
3290 * @param pVCpu The VMCPU to operate on.
3291 * @param pCpu CPU info struct
3292 */
3293VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3294{
3295 Assert(pVM->hwaccm.s.vmx.fSupported);
3296
3297 unsigned cr4 = ASMGetCR4();
3298 if (!(cr4 & X86_CR4_VMXE))
3299 {
3300 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3301 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3302 }
3303
3304 /* Activate the VM Control Structure. */
3305 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3306 if (RT_FAILURE(rc))
3307 return rc;
3308
3309 pVCpu->hwaccm.s.fResumeVM = false;
3310 return VINF_SUCCESS;
3311}
3312
3313
3314/**
3315 * Leaves the VT-x session
3316 *
3317 * @returns VBox status code.
3318 * @param pVM The VM to operate on.
3319 * @param pVCpu The VMCPU to operate on.
3320 * @param pCtx CPU context
3321 */
3322VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3323{
3324 Assert(pVM->hwaccm.s.vmx.fSupported);
3325
3326 /* Save the guest debug state if necessary. */
3327 if (CPUMIsGuestDebugStateActive(pVM))
3328 {
3329 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3330
3331 /* Enable drx move intercepts again. */
3332 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3333 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3334 AssertRC(rc);
3335
3336 /* Resync the debug registers the next time. */
3337 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3338 }
3339 else
3340 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3341
3342 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3343 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3344 AssertRC(rc);
3345
3346 return VINF_SUCCESS;
3347}
3348
3349/**
3350 * Flush the TLB (EPT)
3351 *
3352 * @returns VBox status code.
3353 * @param pVM The VM to operate on.
3354 * @param pVCpu The VM CPU to operate on.
3355 * @param enmFlush Type of flush
3356 * @param GCPhys Physical address of the page to flush
3357 */
3358static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3359{
3360 uint64_t descriptor[2];
3361
3362 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3363 Assert(pVM->hwaccm.s.fNestedPaging);
3364 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3365 descriptor[1] = GCPhys;
3366 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3367 AssertRC(rc);
3368}
3369
3370#ifdef HWACCM_VTX_WITH_VPID
3371/**
3372 * Flush the TLB (EPT)
3373 *
3374 * @returns VBox status code.
3375 * @param pVM The VM to operate on.
3376 * @param pVCpu The VM CPU to operate on.
3377 * @param enmFlush Type of flush
3378 * @param GCPtr Virtual address of the page to flush
3379 */
3380static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3381{
3382#if HC_ARCH_BITS == 32
3383 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3384 if ( CPUMIsGuestInLongMode(pVM)
3385 && !VMX_IS_64BIT_HOST_MODE())
3386 {
3387 pVCpu->hwaccm.s.fForceTLBFlush = true;
3388 }
3389 else
3390#endif
3391 {
3392 uint64_t descriptor[2];
3393
3394 Assert(pVM->hwaccm.s.vmx.fVPID);
3395 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3396 descriptor[1] = GCPtr;
3397 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3398 AssertRC(rc);
3399 }
3400}
3401#endif /* HWACCM_VTX_WITH_VPID */
3402
3403/**
3404 * Invalidates a guest page
3405 *
3406 * @returns VBox status code.
3407 * @param pVM The VM to operate on.
3408 * @param pVCpu The VM CPU to operate on.
3409 * @param GCVirt Page to invalidate
3410 */
3411VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3412{
3413 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3414
3415 LogFlow(("VMXR0InvalidatePage %RGv\n", GCVirt));
3416
3417 /* Only relevant if we want to use VPID.
3418 * In the nested paging case we still see such calls, but
3419 * can safely ignore them. (e.g. after cr3 updates)
3420 */
3421#ifdef HWACCM_VTX_WITH_VPID
3422 /* Skip it if a TLB flush is already pending. */
3423 if ( !fFlushPending
3424 && pVM->hwaccm.s.vmx.fVPID)
3425 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3426#endif /* HWACCM_VTX_WITH_VPID */
3427
3428 return VINF_SUCCESS;
3429}
3430
3431/**
3432 * Invalidates a guest page by physical address
3433 *
3434 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3435 *
3436 * @returns VBox status code.
3437 * @param pVM The VM to operate on.
3438 * @param pVCpu The VM CPU to operate on.
3439 * @param GCPhys Page to invalidate
3440 */
3441VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3442{
3443 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3444
3445 Assert(pVM->hwaccm.s.fNestedPaging);
3446
3447 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3448
3449 /* Skip it if a TLB flush is already pending. */
3450 if (!fFlushPending)
3451 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3452
3453 return VINF_SUCCESS;
3454}
3455
3456/**
3457 * Report world switch error and dump some useful debug info
3458 *
3459 * @param pVM The VM to operate on.
3460 * @param pVCpu The VMCPU to operate on.
3461 * @param rc Return code
3462 * @param pCtx Current CPU context (not updated)
3463 */
3464static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3465{
3466 switch (rc)
3467 {
3468 case VERR_VMX_INVALID_VMXON_PTR:
3469 AssertFailed();
3470 break;
3471
3472 case VERR_VMX_UNABLE_TO_START_VM:
3473 case VERR_VMX_UNABLE_TO_RESUME_VM:
3474 {
3475 int rc;
3476 RTCCUINTREG exitReason, instrError;
3477
3478 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3479 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3480 AssertRC(rc);
3481 if (rc == VINF_SUCCESS)
3482 {
3483 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3484 Log(("Current stack %08x\n", &rc));
3485
3486 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3487 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3488
3489#ifdef VBOX_STRICT
3490 RTGDTR gdtr;
3491 PX86DESCHC pDesc;
3492 RTCCUINTREG val;
3493
3494 ASMGetGDTR(&gdtr);
3495
3496 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3497 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3498 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3499 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3500 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3501 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3502 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3503 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3504 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3505 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3506
3507 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3508 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3509
3510 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3511 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3512
3513 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3514 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3515
3516 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3517 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3518
3519 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3520 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3521
3522 if (val < gdtr.cbGdt)
3523 {
3524 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3525 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3526 }
3527
3528 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3529 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3530 if (val < gdtr.cbGdt)
3531 {
3532 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3533 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3534 }
3535
3536 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
3537 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3538 if (val < gdtr.cbGdt)
3539 {
3540 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3541 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3542 }
3543
3544 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
3545 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
3546 if (val < gdtr.cbGdt)
3547 {
3548 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3549 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3550 }
3551
3552 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
3553 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
3554 if (val < gdtr.cbGdt)
3555 {
3556 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3557 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3558 }
3559
3560 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
3561 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
3562 if (val < gdtr.cbGdt)
3563 {
3564 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3565 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3566 }
3567
3568 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
3569 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
3570 if (val < gdtr.cbGdt)
3571 {
3572 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3573 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3574 }
3575
3576 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3577 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
3578
3579 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3580 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
3581 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3582 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
3583
3584 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
3585 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3586
3587 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3588 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
3589
3590 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3591 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
3592
3593 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3594 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
3595 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3596 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
3597
3598# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3599 if (VMX_IS_64BIT_HOST_MODE())
3600 {
3601 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
3602 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
3603 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3604 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3605 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3606 }
3607# endif
3608#endif /* VBOX_STRICT */
3609 }
3610 break;
3611 }
3612
3613 default:
3614 /* impossible */
3615 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
3616 break;
3617 }
3618}
3619
3620#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3621/**
3622 * Prepares for and executes VMLAUNCH (64 bits guest mode)
3623 *
3624 * @returns VBox status code
3625 * @param fResume vmlauch/vmresume
3626 * @param pCtx Guest context
3627 * @param pCache VMCS cache
3628 * @param pVM The VM to operate on.
3629 * @param pVCpu The VMCPU to operate on.
3630 */
3631DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
3632{
3633 uint32_t aParam[6];
3634 PHWACCM_CPUINFO pCpu;
3635 RTHCPHYS pPageCpuPhys;
3636 int rc;
3637
3638 pCpu = HWACCMR0GetCurrentCpu();
3639 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3640
3641#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3642 pCache->uPos = 1;
3643 pCache->interPD = PGMGetInterPaeCR3(pVM);
3644 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
3645#endif
3646
3647#ifdef DEBUG
3648 pCache->TestIn.pPageCpuPhys = 0;
3649 pCache->TestIn.pVMCSPhys = 0;
3650 pCache->TestIn.pCache = 0;
3651 pCache->TestOut.pVMCSPhys = 0;
3652 pCache->TestOut.pCache = 0;
3653 pCache->TestOut.pCtx = 0;
3654 pCache->TestOut.eflags = 0;
3655#endif
3656
3657 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
3658 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
3659 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
3660 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
3661 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
3662 aParam[5] = 0;
3663
3664#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3665 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
3666 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
3667#endif
3668 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
3669
3670#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3671 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
3672 Assert(pCtx->dr[4] == 10);
3673 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
3674#endif
3675
3676#ifdef DEBUG
3677 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
3678 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
3679 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
3680 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
3681 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
3682 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
3683 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
3684#endif
3685 return rc;
3686}
3687
3688/**
3689 * Executes the specified handler in 64 mode
3690 *
3691 * @returns VBox status code.
3692 * @param pVM The VM to operate on.
3693 * @param pVCpu The VMCPU to operate on.
3694 * @param pCtx Guest context
3695 * @param pfnHandler RC handler
3696 * @param cbParam Number of parameters
3697 * @param paParam Array of 32 bits parameters
3698 */
3699VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
3700{
3701 int rc, rc2;
3702 PHWACCM_CPUINFO pCpu;
3703 RTHCPHYS pPageCpuPhys;
3704
3705 /* @todo This code is not guest SMP safe (hyper context) */
3706 AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
3707 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
3708 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
3709 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
3710
3711#ifdef VBOX_STRICT
3712 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
3713 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
3714
3715 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
3716 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
3717#endif
3718
3719 pCpu = HWACCMR0GetCurrentCpu();
3720 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3721
3722 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3723 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3724
3725 /* Leave VMX Root Mode. */
3726 VMXDisable();
3727
3728 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3729
3730 CPUMSetHyperESP(pVM, VMMGetStackRC(pVM));
3731 CPUMSetHyperEIP(pVM, pfnHandler);
3732 for (int i=(int)cbParam-1;i>=0;i--)
3733 CPUMPushHyper(pVM, paParam[i]);
3734
3735 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3736 /* Call switcher. */
3737 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
3738 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3739
3740 /* Make sure the VMX instructions don't cause #UD faults. */
3741 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
3742
3743 /* Enter VMX Root Mode */
3744 rc2 = VMXEnable(pPageCpuPhys);
3745 if (RT_FAILURE(rc2))
3746 {
3747 if (pVM)
3748 VMXR0CheckError(pVM, pVCpu, rc2);
3749 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3750 return VERR_VMX_VMXON_FAILED;
3751 }
3752
3753 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3754 AssertRCReturn(rc2, rc2);
3755#ifdef RT_OS_WINDOWS
3756 Assert(ASMGetFlags() & X86_EFL_IF);
3757#else
3758 Assert(!(ASMGetFlags() & X86_EFL_IF));
3759#endif
3760 return rc;
3761}
3762
3763#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
3764
3765
3766#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3767/**
3768 * Executes VMWRITE
3769 *
3770 * @returns VBox status code
3771 * @param pVCpu The VMCPU to operate on.
3772 * @param idxField VMCS index
3773 * @param u64Val 16, 32 or 64 bits value
3774 */
3775VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
3776{
3777 int rc;
3778
3779 switch (idxField)
3780 {
3781 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
3782 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
3783 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
3784 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
3785 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
3786 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
3787 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
3788 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
3789 case VMX_VMCS_GUEST_LINK_PTR_FULL:
3790 case VMX_VMCS_GUEST_PDPTR0_FULL:
3791 case VMX_VMCS_GUEST_PDPTR1_FULL:
3792 case VMX_VMCS_GUEST_PDPTR2_FULL:
3793 case VMX_VMCS_GUEST_PDPTR3_FULL:
3794 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
3795 case VMX_VMCS_GUEST_EFER_FULL:
3796 case VMX_VMCS_CTRL_EPTP_FULL:
3797 /* These fields consist of two parts, which are both writable in 32 bits mode. */
3798 rc = VMXWriteVMCS32(idxField, u64Val);
3799 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
3800 AssertRC(rc);
3801 return rc;
3802
3803 case VMX_VMCS64_GUEST_LDTR_BASE:
3804 case VMX_VMCS64_GUEST_TR_BASE:
3805 case VMX_VMCS64_GUEST_GDTR_BASE:
3806 case VMX_VMCS64_GUEST_IDTR_BASE:
3807 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3808 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3809 case VMX_VMCS64_GUEST_CR0:
3810 case VMX_VMCS64_GUEST_CR4:
3811 case VMX_VMCS64_GUEST_CR3:
3812 case VMX_VMCS64_GUEST_DR7:
3813 case VMX_VMCS64_GUEST_RIP:
3814 case VMX_VMCS64_GUEST_RSP:
3815 case VMX_VMCS64_GUEST_CS_BASE:
3816 case VMX_VMCS64_GUEST_DS_BASE:
3817 case VMX_VMCS64_GUEST_ES_BASE:
3818 case VMX_VMCS64_GUEST_FS_BASE:
3819 case VMX_VMCS64_GUEST_GS_BASE:
3820 case VMX_VMCS64_GUEST_SS_BASE:
3821 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
3822 if (u64Val >> 32ULL)
3823 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
3824 else
3825 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
3826
3827 return rc;
3828
3829 default:
3830 AssertMsgFailed(("Unexpected field %x\n", idxField));
3831 return VERR_INVALID_PARAMETER;
3832 }
3833}
3834
3835/**
3836 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
3837 *
3838 * @param pVCpu The VMCPU to operate on.
3839 * @param idxField VMCS field
3840 * @param u64Val Value
3841 */
3842VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
3843{
3844 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
3845
3846 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
3847
3848 /* Make sure there are no duplicates. */
3849 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
3850 {
3851 if (pCache->Write.aField[i] == idxField)
3852 {
3853 pCache->Write.aFieldVal[i] = u64Val;
3854 return VINF_SUCCESS;
3855 }
3856 }
3857
3858 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
3859 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
3860 pCache->Write.cValidEntries++;
3861 return VINF_SUCCESS;
3862}
3863
3864#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3865
3866#ifdef VBOX_STRICT
3867static bool vmxR0IsValidReadField(uint32_t idxField)
3868{
3869 switch(idxField)
3870 {
3871 case VMX_VMCS64_GUEST_RIP:
3872 case VMX_VMCS64_GUEST_RSP:
3873 case VMX_VMCS_GUEST_RFLAGS:
3874 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
3875 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
3876 case VMX_VMCS64_GUEST_CR0:
3877 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
3878 case VMX_VMCS64_GUEST_CR4:
3879 case VMX_VMCS64_GUEST_DR7:
3880 case VMX_VMCS32_GUEST_SYSENTER_CS:
3881 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3882 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3883 case VMX_VMCS32_GUEST_GDTR_LIMIT:
3884 case VMX_VMCS64_GUEST_GDTR_BASE:
3885 case VMX_VMCS32_GUEST_IDTR_LIMIT:
3886 case VMX_VMCS64_GUEST_IDTR_BASE:
3887 case VMX_VMCS16_GUEST_FIELD_CS:
3888 case VMX_VMCS32_GUEST_CS_LIMIT:
3889 case VMX_VMCS64_GUEST_CS_BASE:
3890 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
3891 case VMX_VMCS16_GUEST_FIELD_DS:
3892 case VMX_VMCS32_GUEST_DS_LIMIT:
3893 case VMX_VMCS64_GUEST_DS_BASE:
3894 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
3895 case VMX_VMCS16_GUEST_FIELD_ES:
3896 case VMX_VMCS32_GUEST_ES_LIMIT:
3897 case VMX_VMCS64_GUEST_ES_BASE:
3898 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
3899 case VMX_VMCS16_GUEST_FIELD_FS:
3900 case VMX_VMCS32_GUEST_FS_LIMIT:
3901 case VMX_VMCS64_GUEST_FS_BASE:
3902 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
3903 case VMX_VMCS16_GUEST_FIELD_GS:
3904 case VMX_VMCS32_GUEST_GS_LIMIT:
3905 case VMX_VMCS64_GUEST_GS_BASE:
3906 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
3907 case VMX_VMCS16_GUEST_FIELD_SS:
3908 case VMX_VMCS32_GUEST_SS_LIMIT:
3909 case VMX_VMCS64_GUEST_SS_BASE:
3910 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
3911 case VMX_VMCS16_GUEST_FIELD_LDTR:
3912 case VMX_VMCS32_GUEST_LDTR_LIMIT:
3913 case VMX_VMCS64_GUEST_LDTR_BASE:
3914 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
3915 case VMX_VMCS16_GUEST_FIELD_TR:
3916 case VMX_VMCS32_GUEST_TR_LIMIT:
3917 case VMX_VMCS64_GUEST_TR_BASE:
3918 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
3919 case VMX_VMCS32_RO_EXIT_REASON:
3920 case VMX_VMCS32_RO_VM_INSTR_ERROR:
3921 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
3922 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
3923 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
3924 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
3925 case VMX_VMCS_RO_EXIT_QUALIFICATION:
3926 case VMX_VMCS32_RO_IDT_INFO:
3927 case VMX_VMCS32_RO_IDT_ERRCODE:
3928 case VMX_VMCS64_GUEST_CR3:
3929 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
3930 return true;
3931 }
3932 return false;
3933}
3934
3935static bool vmxR0IsValidWriteField(uint32_t idxField)
3936{
3937 switch(idxField)
3938 {
3939 case VMX_VMCS64_GUEST_LDTR_BASE:
3940 case VMX_VMCS64_GUEST_TR_BASE:
3941 case VMX_VMCS64_GUEST_GDTR_BASE:
3942 case VMX_VMCS64_GUEST_IDTR_BASE:
3943 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3944 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3945 case VMX_VMCS64_GUEST_CR0:
3946 case VMX_VMCS64_GUEST_CR4:
3947 case VMX_VMCS64_GUEST_CR3:
3948 case VMX_VMCS64_GUEST_DR7:
3949 case VMX_VMCS64_GUEST_RIP:
3950 case VMX_VMCS64_GUEST_RSP:
3951 case VMX_VMCS64_GUEST_CS_BASE:
3952 case VMX_VMCS64_GUEST_DS_BASE:
3953 case VMX_VMCS64_GUEST_ES_BASE:
3954 case VMX_VMCS64_GUEST_FS_BASE:
3955 case VMX_VMCS64_GUEST_GS_BASE:
3956 case VMX_VMCS64_GUEST_SS_BASE:
3957 return true;
3958 }
3959 return false;
3960}
3961
3962#endif
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