VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 17687

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1/* $Id: HWVMXR0.cpp 17687 2009-03-11 12:34:29Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/param.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/string.h>
42#include "HWVMXR0.h"
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47#if defined(RT_ARCH_AMD64)
48# define VMX_IS_64BIT_HOST_MODE() (true)
49#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
50# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
51#else
52# define VMX_IS_64BIT_HOST_MODE() (false)
53#endif
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58/* IO operation lookup arrays. */
59static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
60static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
61
62#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
63/** See HWACCMR0A.asm. */
64extern "C" uint32_t g_fVMXIs64bitHost;
65#endif
66
67/*******************************************************************************
68* Local Functions *
69*******************************************************************************/
70static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
71static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
72static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
73static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
74static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
75static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
76static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
77#ifdef VBOX_STRICT
78static bool vmxR0IsValidReadField(uint32_t idxField);
79static bool vmxR0IsValidWriteField(uint32_t idxField);
80#endif
81
82static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
83{
84 if (rc == VERR_VMX_GENERIC)
85 {
86 RTCCUINTREG instrError;
87
88 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
89 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
90 }
91 pVM->hwaccm.s.lLastError = rc;
92}
93
94/**
95 * Sets up and activates VT-x on the current CPU
96 *
97 * @returns VBox status code.
98 * @param pCpu CPU info struct
99 * @param pVM The VM to operate on. (can be NULL after a resume!!)
100 * @param pvPageCpu Pointer to the global cpu page
101 * @param pPageCpuPhys Physical address of the global cpu page
102 */
103VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
104{
105 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
106 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
107
108#ifdef LOG_ENABLED
109 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
110#endif
111 if (pVM)
112 {
113 /* Set revision dword at the beginning of the VMXON structure. */
114 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
115 }
116
117 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
118 * (which can have very bad consequences!!!)
119 */
120
121 /* Make sure the VMX instructions don't cause #UD faults. */
122 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
123
124 /* Enter VMX Root Mode */
125 int rc = VMXEnable(pPageCpuPhys);
126 if (RT_FAILURE(rc))
127 {
128 if (pVM)
129 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
130 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
131 return VERR_VMX_VMXON_FAILED;
132 }
133 return VINF_SUCCESS;
134}
135
136/**
137 * Deactivates VT-x on the current CPU
138 *
139 * @returns VBox status code.
140 * @param pCpu CPU info struct
141 * @param pvPageCpu Pointer to the global cpu page
142 * @param pPageCpuPhys Physical address of the global cpu page
143 */
144VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
145{
146 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
147 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
148
149 /* Leave VMX Root Mode. */
150 VMXDisable();
151
152 /* And clear the X86_CR4_VMXE bit */
153 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
154
155#ifdef LOG_ENABLED
156 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
157#endif
158 return VINF_SUCCESS;
159}
160
161/**
162 * Does Ring-0 per VM VT-x init.
163 *
164 * @returns VBox status code.
165 * @param pVM The VM to operate on.
166 */
167VMMR0DECL(int) VMXR0InitVM(PVM pVM)
168{
169 int rc;
170
171#ifdef LOG_ENABLED
172 SUPR0Printf("VMXR0InitVM %x\n", pVM);
173#endif
174
175 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
176
177 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
178 {
179 /* Allocate one page for the virtual APIC mmio cache. */
180 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
181 AssertRC(rc);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
186 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
187 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
188 }
189 else
190 {
191 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
192 pVM->hwaccm.s.vmx.pAPIC = 0;
193 pVM->hwaccm.s.vmx.pAPICPhys = 0;
194 }
195
196 /* Allocate the MSR bitmap if this feature is supported. */
197 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
198 {
199 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
200 AssertRC(rc);
201 if (RT_FAILURE(rc))
202 return rc;
203
204 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
205 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
206 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
207 }
208
209#ifdef VBOX_WITH_CRASHDUMP_MAGIC
210 {
211 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
212 AssertRC(rc);
213 if (RT_FAILURE(rc))
214 return rc;
215
216 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
217 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
218
219 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
220 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
221 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
222 }
223#endif
224
225 /* Allocate VMCBs for all guest CPUs. */
226 for (unsigned i=0;i<pVM->cCPUs;i++)
227 {
228 PVMCPU pVCpu = &pVM->aCpus[i];
229
230 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
231
232 /* Allocate one page for the VM control structure (VMCS). */
233 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
234 AssertRC(rc);
235 if (RT_FAILURE(rc))
236 return rc;
237
238 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
239 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
240 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
241
242 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
243 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
244
245 /* Current guest paging mode. */
246 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
247
248#ifdef LOG_ENABLED
249 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
250#endif
251 }
252
253 return VINF_SUCCESS;
254}
255
256/**
257 * Does Ring-0 per VM VT-x termination.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262VMMR0DECL(int) VMXR0TermVM(PVM pVM)
263{
264 for (unsigned i=0;i<pVM->cCPUs;i++)
265 {
266 if (pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
267 {
268 RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, false);
269 pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
270 pVM->aCpus[i].hwaccm.s.vmx.pVMCS = 0;
271 pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys = 0;
272 }
273 }
274 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
275 {
276 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
277 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
278 pVM->hwaccm.s.vmx.pAPIC = 0;
279 pVM->hwaccm.s.vmx.pAPICPhys = 0;
280 }
281 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
282 {
283 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
284 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
285 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
286 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
287 }
288#ifdef VBOX_WITH_CRASHDUMP_MAGIC
289 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
290 {
291 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
292 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
293 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
294 pVM->hwaccm.s.vmx.pScratch = 0;
295 pVM->hwaccm.s.vmx.pScratchPhys = 0;
296 }
297#endif
298 return VINF_SUCCESS;
299}
300
301/**
302 * Sets up VT-x for the specified VM
303 *
304 * @returns VBox status code.
305 * @param pVM The VM to operate on.
306 */
307VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
308{
309 int rc = VINF_SUCCESS;
310 uint32_t val;
311
312 AssertReturn(pVM, VERR_INVALID_PARAMETER);
313
314 for (unsigned i=0;i<pVM->cCPUs;i++)
315 {
316 PVMCPU pVCpu = &pVM->aCpus[i];
317
318 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
319
320 /* Set revision dword at the beginning of the VMCS structure. */
321 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
322
323 /* Clear VM Control Structure. */
324 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
325 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
326 if (RT_FAILURE(rc))
327 goto vmx_end;
328
329 /* Activate the VM Control Structure. */
330 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
331 if (RT_FAILURE(rc))
332 goto vmx_end;
333
334 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
335 * Set required bits to one and zero according to the MSR capabilities.
336 */
337 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
338 /* External and non-maskable interrupts cause VM-exits. */
339 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
340 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
341
342 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
343 AssertRC(rc);
344
345 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
346 * Set required bits to one and zero according to the MSR capabilities.
347 */
348 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
349 /* Program which event cause VM-exits and which features we want to use. */
350 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
351 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
352 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
353 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
354 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
355 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
356
357 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
358 if (!pVM->hwaccm.s.fNestedPaging)
359 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
360 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
361 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
362
363 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
364 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
365 {
366 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
367 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
368 Assert(pVM->hwaccm.s.vmx.pAPIC);
369 }
370 else
371 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
372 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
373
374#ifdef VBOX_WITH_VTX_MSR_BITMAPS
375 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
376 {
377 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
378 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
379 }
380#endif
381
382 /* We will use the secondary control if it's present. */
383 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
384
385 /* Mask away the bits that the CPU doesn't support */
386 /** @todo make sure they don't conflict with the above requirements. */
387 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
388 pVCpu->hwaccm.s.vmx.proc_ctls = val;
389
390 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
391 AssertRC(rc);
392
393 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
394 {
395 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
396 * Set required bits to one and zero according to the MSR capabilities.
397 */
398 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
399 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
400
401#ifdef HWACCM_VTX_WITH_EPT
402 if (pVM->hwaccm.s.fNestedPaging)
403 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
404#endif /* HWACCM_VTX_WITH_EPT */
405#ifdef HWACCM_VTX_WITH_VPID
406 else
407 if (pVM->hwaccm.s.vmx.fVPID)
408 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
409#endif /* HWACCM_VTX_WITH_VPID */
410
411 /* Mask away the bits that the CPU doesn't support */
412 /** @todo make sure they don't conflict with the above requirements. */
413 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
414
415 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
416 AssertRC(rc);
417 }
418
419 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
420 * Set required bits to one and zero according to the MSR capabilities.
421 */
422 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
423 AssertRC(rc);
424
425 /* Forward all exception except #NM & #PF to the guest.
426 * We always need to check pagefaults since our shadow page table can be out of sync.
427 * And we always lazily sync the FPU & XMM state.
428 */
429
430 /** @todo Possible optimization:
431 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
432 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
433 * registers ourselves of course.
434 *
435 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
436 */
437
438 /* Don't filter page faults; all of them should cause a switch. */
439 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
441 AssertRC(rc);
442
443 /* Init TSC offset to zero. */
444 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
445 AssertRC(rc);
446
447 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
448 AssertRC(rc);
449
450 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
451 AssertRC(rc);
452
453 /* Set the MSR bitmap address. */
454 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
455 {
456 /* Optional */
457 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
458 AssertRC(rc);
459 }
460
461 /* Clear MSR controls. */
462 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
463 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
464 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
465 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
467 AssertRC(rc);
468
469 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
470 {
471 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
472 /* Optional */
473 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
474 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
475 AssertRC(rc);
476 }
477
478 /* Set link pointer to -1. Not currently used. */
479 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
480 AssertRC(rc);
481
482 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
483 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
484 AssertRC(rc);
485
486 /* Configure the VMCS read cache. */
487 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
488
489 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
490 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
491 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
492 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
493 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
494 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
495 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
496 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
497 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
498 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
499 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
500 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
501 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
502 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
503 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
504 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
505
506 VMX_SETUP_SELREG(ES, pCache);
507 VMX_SETUP_SELREG(SS, pCache);
508 VMX_SETUP_SELREG(CS, pCache);
509 VMX_SETUP_SELREG(DS, pCache);
510 VMX_SETUP_SELREG(FS, pCache);
511 VMX_SETUP_SELREG(GS, pCache);
512 VMX_SETUP_SELREG(LDTR, pCache);
513 VMX_SETUP_SELREG(TR, pCache);
514
515 /* Status code VMCS reads. */
516 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
517 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
518 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
525
526 if (pVM->hwaccm.s.fNestedPaging)
527 {
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
530 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
531 }
532 else
533 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
534 } /* for each VMCPU */
535
536 /* Choose the right TLB setup function. */
537 if (pVM->hwaccm.s.fNestedPaging)
538 {
539 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
540
541 /* Default values for flushing. */
542 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
543 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
544
545 /* If the capabilities specify we can do more, then make use of it. */
546 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
547 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
548 else
549 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
550 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
551
552 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
553 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
554 }
555#ifdef HWACCM_VTX_WITH_VPID
556 else
557 if (pVM->hwaccm.s.vmx.fVPID)
558 {
559 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
560
561 /* Default values for flushing. */
562 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
563 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
564
565 /* If the capabilities specify we can do more, then make use of it. */
566 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
567 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
568 else
569 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
570 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
571
572 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
574 }
575#endif /* HWACCM_VTX_WITH_VPID */
576 else
577 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
578
579vmx_end:
580 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
581 return rc;
582}
583
584
585/**
586 * Injects an event (trap or external interrupt)
587 *
588 * @returns VBox status code.
589 * @param pVM The VM to operate on.
590 * @param pVCpu The VMCPU to operate on.
591 * @param pCtx CPU Context
592 * @param intInfo VMX interrupt info
593 * @param cbInstr Opcode length of faulting instruction
594 * @param errCode Error code (optional)
595 */
596static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
597{
598 int rc;
599 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
600
601#ifdef VBOX_STRICT
602 if (iGate == 0xE)
603 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
604 else
605 if (iGate < 0x20)
606 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
607 else
608 {
609 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
610 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
611 Assert(pCtx->eflags.u32 & X86_EFL_IF);
612 }
613#endif
614
615#ifdef HWACCM_VMX_EMULATE_REALMODE
616 if (CPUMIsGuestInRealModeEx(pCtx))
617 {
618 RTGCPHYS GCPhysHandler;
619 uint16_t offset, ip;
620 RTSEL sel;
621
622 /* Injecting events doesn't work right with real mode emulation.
623 * (#GP if we try to inject external hardware interrupts)
624 * Inject the interrupt or trap directly instead.
625 *
626 * ASSUMES no access handlers for the bits we read or write below (should be safe).
627 */
628 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
629
630 /* Check if the interrupt handler is present. */
631 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
632 {
633 Log(("IDT cbIdt violation\n"));
634 if (iGate != X86_XCPT_DF)
635 {
636 RTGCUINTPTR intInfo;
637
638 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
639 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
640 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
641 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
642
643 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
644 }
645 Log(("Triple fault -> reset the VM!\n"));
646 return VINF_EM_RESET;
647 }
648 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
649 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
650 || iGate == 4)
651 {
652 ip = pCtx->ip + cbInstr;
653 }
654 else
655 ip = pCtx->ip;
656
657 /* Read the selector:offset pair of the interrupt handler. */
658 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
659#ifdef VBOX_WITH_NEW_PHYS_CODE
660 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
661 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
662#else
663 PGMPhysRead(pVM, GCPhysHandler, &offset, sizeof(offset));
664 PGMPhysRead(pVM, GCPhysHandler + 2, &sel, sizeof(sel));
665#endif
666
667 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
668
669 /* Construct the stack frame. */
670 /** @todo should check stack limit. */
671 pCtx->sp -= 2;
672 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
673#ifdef VBOX_WITH_NEW_PHYS_CODE
674 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
675#else
676 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t));
677#endif
678 pCtx->sp -= 2;
679 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
680#ifdef VBOX_WITH_NEW_PHYS_CODE
681 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
682#else
683 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t));
684#endif
685 pCtx->sp -= 2;
686 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
687#ifdef VBOX_WITH_NEW_PHYS_CODE
688 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
689#else
690 PGMPhysWrite(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip));
691#endif
692
693 /* Update the CPU state for executing the handler. */
694 pCtx->rip = offset;
695 pCtx->cs = sel;
696 pCtx->csHid.u64Base = sel << 4;
697 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
698
699 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
700 return VINF_SUCCESS;
701 }
702#endif /* HWACCM_VMX_EMULATE_REALMODE */
703
704 /* Set event injection state. */
705 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
706
707 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
708 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
709
710 AssertRC(rc);
711 return rc;
712}
713
714
715/**
716 * Checks for pending guest interrupts and injects them
717 *
718 * @returns VBox status code.
719 * @param pVM The VM to operate on.
720 * @param pVCpu The VMCPU to operate on.
721 * @param pCtx CPU Context
722 */
723static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
724{
725 int rc;
726
727 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
728 if (pVCpu->hwaccm.s.Event.fPending)
729 {
730 Log(("Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
731 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
732 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
733 AssertRC(rc);
734
735 pVCpu->hwaccm.s.Event.fPending = false;
736 return VINF_SUCCESS;
737 }
738
739 if (pVM->hwaccm.s.fInjectNMI)
740 {
741 RTGCUINTPTR intInfo;
742
743 intInfo = X86_XCPT_NMI;
744 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
745 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
746
747 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
748 AssertRC(rc);
749
750 pVM->hwaccm.s.fInjectNMI = false;
751 return VINF_SUCCESS;
752 }
753
754 /* When external interrupts are pending, we should exit the VM when IF is set. */
755 if ( !TRPMHasTrap(pVM)
756 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
757 {
758 if (!(pCtx->eflags.u32 & X86_EFL_IF))
759 {
760 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
761 {
762 LogFlow(("Enable irq window exit!\n"));
763 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
764 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
765 AssertRC(rc);
766 }
767 /* else nothing to do but wait */
768 }
769 else
770 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
771 {
772 uint8_t u8Interrupt;
773
774 rc = PDMGetInterrupt(pVM, &u8Interrupt);
775 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
776 if (RT_SUCCESS(rc))
777 {
778 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
779 AssertRC(rc);
780 }
781 else
782 {
783 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
784 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
785 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
786 /* Just continue */
787 }
788 }
789 else
790 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
791 }
792
793#ifdef VBOX_STRICT
794 if (TRPMHasTrap(pVM))
795 {
796 uint8_t u8Vector;
797 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
798 AssertRC(rc);
799 }
800#endif
801
802 if ( pCtx->eflags.u32 & X86_EFL_IF
803 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
804 && TRPMHasTrap(pVM)
805 )
806 {
807 uint8_t u8Vector;
808 int rc;
809 TRPMEVENT enmType;
810 RTGCUINTPTR intInfo;
811 RTGCUINT errCode;
812
813 /* If a new event is pending, then dispatch it now. */
814 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
815 AssertRC(rc);
816 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
817 Assert(enmType != TRPM_SOFTWARE_INT);
818
819 /* Clear the pending trap. */
820 rc = TRPMResetTrap(pVM);
821 AssertRC(rc);
822
823 intInfo = u8Vector;
824 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
825
826 if (enmType == TRPM_TRAP)
827 {
828 switch (u8Vector) {
829 case 8:
830 case 10:
831 case 11:
832 case 12:
833 case 13:
834 case 14:
835 case 17:
836 /* Valid error codes. */
837 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
838 break;
839 default:
840 break;
841 }
842 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
843 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
844 else
845 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
846 }
847 else
848 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
849
850 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
851 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
852 AssertRC(rc);
853 } /* if (interrupts can be dispatched) */
854
855 return VINF_SUCCESS;
856}
857
858/**
859 * Save the host state
860 *
861 * @returns VBox status code.
862 * @param pVM The VM to operate on.
863 * @param pVCpu The VMCPU to operate on.
864 */
865VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
866{
867 int rc = VINF_SUCCESS;
868
869 /*
870 * Host CPU Context
871 */
872 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
873 {
874 RTIDTR idtr;
875 RTGDTR gdtr;
876 RTSEL SelTR;
877 PX86DESCHC pDesc;
878 uintptr_t trBase;
879 RTSEL cs;
880 RTSEL ss;
881 uint64_t cr3;
882
883 /* Control registers */
884 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
885#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
886 if (VMX_IS_64BIT_HOST_MODE())
887 {
888 cr3 = hwaccmR0Get64bitCR3();
889 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
890 }
891 else
892#endif
893 {
894 cr3 = ASMGetCR3();
895 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
896 }
897 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
898 AssertRC(rc);
899 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
900 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
901 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
902
903 /* Selector registers. */
904#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
905 if (VMX_IS_64BIT_HOST_MODE())
906 {
907 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
908 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
909 }
910 else
911 {
912 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
913 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
914 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
915 }
916#else
917 cs = ASMGetCS();
918 ss = ASMGetSS();
919#endif
920 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
921 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
922 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
923 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
924 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
925 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
926#if HC_ARCH_BITS == 32
927 if (!VMX_IS_64BIT_HOST_MODE())
928 {
929 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
930 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
931 }
932#endif
933 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
934 SelTR = ASMGetTR();
935 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
936 AssertRC(rc);
937 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
938 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
939 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
940 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
941 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
942 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
943 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
944
945 /* GDTR & IDTR */
946#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
947 if (VMX_IS_64BIT_HOST_MODE())
948 {
949 X86XDTR64 gdtr64, idtr64;
950 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
951 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
952 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
953 AssertRC(rc);
954 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
955 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
956 gdtr.cbGdt = gdtr64.cb;
957 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
958 }
959 else
960#endif
961 {
962 ASMGetGDTR(&gdtr);
963 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
964 ASMGetIDTR(&idtr);
965 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
966 AssertRC(rc);
967 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
968 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
969 }
970
971
972 /* Save the base address of the TR selector. */
973 if (SelTR > gdtr.cbGdt)
974 {
975 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
976 return VERR_VMX_INVALID_HOST_STATE;
977 }
978
979#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
980 if (VMX_IS_64BIT_HOST_MODE())
981 {
982 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
983 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
984 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
985 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
986 AssertRC(rc);
987 }
988 else
989#endif
990 {
991 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
992#if HC_ARCH_BITS == 64
993 trBase = X86DESC64_BASE(*pDesc);
994#else
995 trBase = X86DESC_BASE(*pDesc);
996#endif
997 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
998 AssertRC(rc);
999 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
1000 }
1001
1002 /* FS and GS base. */
1003#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1004 if (VMX_IS_64BIT_HOST_MODE())
1005 {
1006 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
1007 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
1008 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
1009 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
1010 }
1011#endif
1012 AssertRC(rc);
1013
1014 /* Sysenter MSRs. */
1015 /** @todo expensive!! */
1016 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1017 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1018#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1019 if (VMX_IS_64BIT_HOST_MODE())
1020 {
1021 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1022 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1023 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1024 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1025 }
1026 else
1027 {
1028 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1029 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1030 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1031 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1032 }
1033#elif HC_ARCH_BITS == 32
1034 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1035 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1036 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1037 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1038#else
1039 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1040 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1041 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1042 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1043#endif
1044 AssertRC(rc);
1045
1046#if 0 /* @todo deal with 32/64 */
1047 /* Restore the host EFER - on CPUs that support it. */
1048 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1049 {
1050 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1051 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1052 AssertRC(rc);
1053 }
1054#endif
1055 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1056 }
1057 return rc;
1058}
1059
1060/**
1061 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1062 *
1063 * @param pVM The VM to operate on.
1064 * @param pVCpu The VMCPU to operate on.
1065 * @param pCtx Guest context
1066 */
1067static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1068{
1069 if (CPUMIsGuestInPAEModeEx(pCtx))
1070 {
1071 X86PDPE Pdpe;
1072
1073 for (unsigned i=0;i<4;i++)
1074 {
1075 Pdpe = PGMGstGetPaePDPtr(pVM, i);
1076 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1077 AssertRC(rc);
1078 }
1079 }
1080}
1081
1082/**
1083 * Update the exception bitmap according to the current CPU state
1084 *
1085 * @param pVM The VM to operate on.
1086 * @param pVCpu The VMCPU to operate on.
1087 * @param pCtx Guest context
1088 */
1089static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1090{
1091 uint32_t u32TrapMask;
1092 Assert(pCtx);
1093
1094 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1095#ifndef DEBUG
1096 if (pVM->hwaccm.s.fNestedPaging)
1097 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1098#endif
1099
1100 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1101 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1102 && !(pCtx->cr0 & X86_CR0_NE)
1103 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1104 {
1105 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1106 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1107 }
1108
1109#ifdef DEBUG /* till after branching, enable it by default then. */
1110 /* Intercept X86_XCPT_DB if stepping is enabled */
1111 if (DBGFIsStepping(pVM))
1112 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1113 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1114 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1115#endif
1116
1117#ifdef VBOX_STRICT
1118 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1119#endif
1120
1121# ifdef HWACCM_VMX_EMULATE_REALMODE
1122 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1123 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1124 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1125# endif /* HWACCM_VMX_EMULATE_REALMODE */
1126
1127 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1128 AssertRC(rc);
1129}
1130
1131/**
1132 * Loads the guest state
1133 *
1134 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1135 *
1136 * @returns VBox status code.
1137 * @param pVM The VM to operate on.
1138 * @param pVCpu The VMCPU to operate on.
1139 * @param pCtx Guest context
1140 */
1141VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1142{
1143 int rc = VINF_SUCCESS;
1144 RTGCUINTPTR val;
1145 X86EFLAGS eflags;
1146
1147 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1148 * Set required bits to one and zero according to the MSR capabilities.
1149 */
1150 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1151 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1152 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1153#if 0 /* @todo deal with 32/64 */
1154 /* Required for the EFER write below, not supported on all CPUs. */
1155 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1156#endif
1157 /* 64 bits guest mode? */
1158 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1159 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1160 /* else Must be zero when AMD64 is not available. */
1161
1162 /* Mask away the bits that the CPU doesn't support */
1163 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1164 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1165 AssertRC(rc);
1166
1167 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1168 * Set required bits to one and zero according to the MSR capabilities.
1169 */
1170 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1171
1172 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1173#if 0 /* @todo deal with 32/64 */
1174 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1175#else
1176 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1177#endif
1178
1179#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1180 if (VMX_IS_64BIT_HOST_MODE())
1181 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1182 /* else: Must be zero when AMD64 is not available. */
1183#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1184 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1185 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1186 else
1187 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1188#endif
1189 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1190 /* Don't acknowledge external interrupts on VM-exit. */
1191 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1192 AssertRC(rc);
1193
1194 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1195 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1196 {
1197#ifdef HWACCM_VMX_EMULATE_REALMODE
1198 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1199 {
1200 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1201 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1202 {
1203 /* Correct weird requirements for switching to protected mode. */
1204 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1205 && enmGuestMode >= PGMMODE_PROTECTED)
1206 {
1207 /* Flush the recompiler code cache as it's not unlikely
1208 * the guest will rewrite code it will later execute in real
1209 * mode (OpenBSD 4.0 is one such example)
1210 */
1211 REMFlushTBs(pVM);
1212
1213 /* DPL of all hidden selector registers must match the current CPL (0). */
1214 pCtx->csHid.Attr.n.u2Dpl = 0;
1215 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1216
1217 pCtx->dsHid.Attr.n.u2Dpl = 0;
1218 pCtx->esHid.Attr.n.u2Dpl = 0;
1219 pCtx->fsHid.Attr.n.u2Dpl = 0;
1220 pCtx->gsHid.Attr.n.u2Dpl = 0;
1221 pCtx->ssHid.Attr.n.u2Dpl = 0;
1222
1223 /* The limit must correspond to the granularity bit. */
1224 if (!pCtx->csHid.Attr.n.u1Granularity)
1225 pCtx->csHid.u32Limit &= 0xffff;
1226 if (!pCtx->dsHid.Attr.n.u1Granularity)
1227 pCtx->dsHid.u32Limit &= 0xffff;
1228 if (!pCtx->esHid.Attr.n.u1Granularity)
1229 pCtx->esHid.u32Limit &= 0xffff;
1230 if (!pCtx->fsHid.Attr.n.u1Granularity)
1231 pCtx->fsHid.u32Limit &= 0xffff;
1232 if (!pCtx->gsHid.Attr.n.u1Granularity)
1233 pCtx->gsHid.u32Limit &= 0xffff;
1234 if (!pCtx->ssHid.Attr.n.u1Granularity)
1235 pCtx->ssHid.u32Limit &= 0xffff;
1236 }
1237 else
1238 /* Switching from protected mode to real mode. */
1239 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1240 && enmGuestMode == PGMMODE_REAL)
1241 {
1242 /* The limit must also be set to 0xffff. */
1243 pCtx->csHid.u32Limit = 0xffff;
1244 pCtx->dsHid.u32Limit = 0xffff;
1245 pCtx->esHid.u32Limit = 0xffff;
1246 pCtx->fsHid.u32Limit = 0xffff;
1247 pCtx->gsHid.u32Limit = 0xffff;
1248 pCtx->ssHid.u32Limit = 0xffff;
1249
1250 Assert(pCtx->csHid.u64Base <= 0xfffff);
1251 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1252 Assert(pCtx->esHid.u64Base <= 0xfffff);
1253 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1254 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1255 }
1256 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1257 }
1258 else
1259 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1260 if ( CPUMIsGuestInRealModeEx(pCtx)
1261 && pCtx->csHid.u64Base == 0xffff0000)
1262 {
1263 pCtx->csHid.u64Base = 0xf0000;
1264 pCtx->cs = 0xf000;
1265 }
1266 }
1267#endif /* HWACCM_VMX_EMULATE_REALMODE */
1268
1269 VMX_WRITE_SELREG(ES, es);
1270 AssertRC(rc);
1271
1272 VMX_WRITE_SELREG(CS, cs);
1273 AssertRC(rc);
1274
1275 VMX_WRITE_SELREG(SS, ss);
1276 AssertRC(rc);
1277
1278 VMX_WRITE_SELREG(DS, ds);
1279 AssertRC(rc);
1280
1281 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1282 VMX_WRITE_SELREG(FS, fs);
1283 AssertRC(rc);
1284
1285 VMX_WRITE_SELREG(GS, gs);
1286 AssertRC(rc);
1287 }
1288
1289 /* Guest CPU context: LDTR. */
1290 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1291 {
1292 if (pCtx->ldtr == 0)
1293 {
1294 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1295 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1296 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1297 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1298 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1299 }
1300 else
1301 {
1302 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1303 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1304 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1305 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1306 }
1307 AssertRC(rc);
1308 }
1309 /* Guest CPU context: TR. */
1310 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1311 {
1312#ifdef HWACCM_VMX_EMULATE_REALMODE
1313 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1314 if (CPUMIsGuestInRealModeEx(pCtx))
1315 {
1316 RTGCPHYS GCPhys;
1317
1318 /* We convert it here every time as pci regions could be reconfigured. */
1319 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1320 AssertRC(rc);
1321
1322 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1323 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1324 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1325
1326 X86DESCATTR attr;
1327
1328 attr.u = 0;
1329 attr.n.u1Present = 1;
1330 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1331 val = attr.u;
1332 }
1333 else
1334#endif /* HWACCM_VMX_EMULATE_REALMODE */
1335 {
1336 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1337 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1338 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1339
1340 val = pCtx->trHid.Attr.u;
1341
1342 /* The TSS selector must be busy. */
1343 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1344 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1345 else
1346 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1347 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1348
1349 }
1350 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1351 AssertRC(rc);
1352 }
1353 /* Guest CPU context: GDTR. */
1354 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1355 {
1356 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1357 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1358 AssertRC(rc);
1359 }
1360 /* Guest CPU context: IDTR. */
1361 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1362 {
1363 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1364 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1365 AssertRC(rc);
1366 }
1367
1368 /*
1369 * Sysenter MSRs (unconditional)
1370 */
1371 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1372 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1373 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1374 AssertRC(rc);
1375
1376 /* Control registers */
1377 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1378 {
1379 val = pCtx->cr0;
1380 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1381 Log2(("Guest CR0-shadow %08x\n", val));
1382 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1383 {
1384 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1385 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1386 }
1387 else
1388 {
1389 /** @todo check if we support the old style mess correctly. */
1390 if (!(val & X86_CR0_NE))
1391 Log(("Forcing X86_CR0_NE!!!\n"));
1392
1393 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1394 }
1395 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1396 val |= X86_CR0_PE | X86_CR0_PG;
1397 if (pVM->hwaccm.s.fNestedPaging)
1398 {
1399 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1400 {
1401 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1402 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1403 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1404 }
1405 else
1406 {
1407 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1408 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1409 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1410 }
1411 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1412 AssertRC(rc);
1413 }
1414 else
1415 {
1416 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1417 val |= X86_CR0_WP;
1418 }
1419
1420 /* Always enable caching. */
1421 val &= ~(X86_CR0_CD|X86_CR0_NW);
1422
1423 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1424 Log2(("Guest CR0 %08x\n", val));
1425 /* CR0 flags owned by the host; if the guests attempts to change them, then
1426 * the VM will exit.
1427 */
1428 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1429 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1430 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1431 | X86_CR0_TS
1432 | X86_CR0_ET /* Bit not restored during VM-exit! */
1433 | X86_CR0_CD /* Bit not restored during VM-exit! */
1434 | X86_CR0_NW /* Bit not restored during VM-exit! */
1435 | X86_CR0_NE
1436 | X86_CR0_MP;
1437 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1438
1439 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1440 Log2(("Guest CR0-mask %08x\n", val));
1441 AssertRC(rc);
1442 }
1443 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1444 {
1445 /* CR4 */
1446 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1447 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1448 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1449 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1450
1451 if (!pVM->hwaccm.s.fNestedPaging)
1452 {
1453 switch(pVCpu->hwaccm.s.enmShadowMode)
1454 {
1455 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1456 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1457 case PGMMODE_32_BIT: /* 32-bit paging. */
1458 val &= ~X86_CR4_PAE;
1459 break;
1460
1461 case PGMMODE_PAE: /* PAE paging. */
1462 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1463 /** @todo use normal 32 bits paging */
1464 val |= X86_CR4_PAE;
1465 break;
1466
1467 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1468 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1469#ifdef VBOX_ENABLE_64_BITS_GUESTS
1470 break;
1471#else
1472 AssertFailed();
1473 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1474#endif
1475 default: /* shut up gcc */
1476 AssertFailed();
1477 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1478 }
1479 }
1480 else
1481 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1482 {
1483 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1484 val |= X86_CR4_PSE;
1485 /* Our identity mapping is a 32 bits page directory. */
1486 val &= ~X86_CR4_PAE;
1487 }
1488
1489#ifdef HWACCM_VMX_EMULATE_REALMODE
1490 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1491 if (CPUMIsGuestInRealModeEx(pCtx))
1492 val |= X86_CR4_VME;
1493#endif /* HWACCM_VMX_EMULATE_REALMODE */
1494
1495 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1496 Log2(("Guest CR4 %08x\n", val));
1497 /* CR4 flags owned by the host; if the guests attempts to change them, then
1498 * the VM will exit.
1499 */
1500 val = 0
1501#ifdef HWACCM_VMX_EMULATE_REALMODE
1502 | (pVM->hwaccm.s.vmx.pRealModeTSS ? X86_CR4_VME : 0)
1503#endif
1504 | X86_CR4_PAE
1505 | X86_CR4_PGE
1506 | X86_CR4_PSE
1507 | X86_CR4_VMXE;
1508 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1509
1510 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1511 Log2(("Guest CR4-mask %08x\n", val));
1512 AssertRC(rc);
1513 }
1514
1515 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1516 {
1517 if (pVM->hwaccm.s.fNestedPaging)
1518 {
1519 Assert(PGMGetHyperCR3(pVM));
1520 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVM);
1521
1522 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1523 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1524 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1525 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1526
1527 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1528 AssertRC(rc);
1529
1530 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1531 {
1532 RTGCPHYS GCPhys;
1533
1534 /* We convert it here every time as pci regions could be reconfigured. */
1535 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1536 AssertRC(rc);
1537
1538 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1539 * take care of the translation to host physical addresses.
1540 */
1541 val = GCPhys;
1542 }
1543 else
1544 {
1545 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1546 val = pCtx->cr3;
1547 /* Prefetch the four PDPT entries in PAE mode. */
1548 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1549 }
1550 }
1551 else
1552 {
1553 val = PGMGetHyperCR3(pVM);
1554 Assert(val || VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
1555 }
1556
1557 /* Save our shadow CR3 register. */
1558 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1559 AssertRC(rc);
1560 }
1561
1562 /* Debug registers. */
1563 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1564 {
1565 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1566 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1567
1568 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1569 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1570 pCtx->dr[7] |= 0x400; /* must be one */
1571
1572 /* Resync DR7 */
1573 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1574 AssertRC(rc);
1575
1576 /* Sync the debug state now if any breakpoint is armed. */
1577 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1578 && !CPUMIsGuestDebugStateActive(pVM)
1579 && !DBGFIsStepping(pVM))
1580 {
1581 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1582
1583 /* Disable drx move intercepts. */
1584 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1585 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1586 AssertRC(rc);
1587
1588 /* Save the host and load the guest debug state. */
1589 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1590 AssertRC(rc);
1591 }
1592
1593 /* IA32_DEBUGCTL MSR. */
1594 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1595 AssertRC(rc);
1596
1597 /** @todo do we really ever need this? */
1598 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1599 AssertRC(rc);
1600 }
1601
1602 /* EIP, ESP and EFLAGS */
1603 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1604 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1605 AssertRC(rc);
1606
1607 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1608 eflags = pCtx->eflags;
1609 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1610 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1611
1612#ifdef HWACCM_VMX_EMULATE_REALMODE
1613 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1614 if (CPUMIsGuestInRealModeEx(pCtx))
1615 {
1616 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1617
1618 eflags.Bits.u1VM = 1;
1619 eflags.Bits.u2IOPL = 3;
1620 }
1621#endif /* HWACCM_VMX_EMULATE_REALMODE */
1622 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1623 AssertRC(rc);
1624
1625 /* TSC offset. */
1626 uint64_t u64TSCOffset;
1627
1628 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1629 {
1630 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1631 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1632 AssertRC(rc);
1633
1634 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1635 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1636 AssertRC(rc);
1637 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1638 }
1639 else
1640 {
1641 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1642 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1643 AssertRC(rc);
1644 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1645 }
1646
1647 /* 64 bits guest mode? */
1648 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1649 {
1650#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1651 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1652#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1653 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1654#else
1655# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1656 if (!pVM->hwaccm.s.fAllow64BitGuests)
1657 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1658# endif
1659 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1660#endif
1661 /* Unconditionally update these as wrmsr might have changed them. */
1662 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1663 AssertRC(rc);
1664 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1665 AssertRC(rc);
1666 }
1667 else
1668 {
1669 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1670 }
1671
1672#if 0 /* @todo deal with 32/64 */
1673 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1674 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1675 {
1676 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1677 AssertRC(rc);
1678 }
1679#endif
1680
1681 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1682
1683 /* Done. */
1684 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1685
1686 return rc;
1687}
1688
1689/**
1690 * Syncs back the guest state
1691 *
1692 * @returns VBox status code.
1693 * @param pVM The VM to operate on.
1694 * @param pVCpu The VMCPU to operate on.
1695 * @param pCtx Guest context
1696 */
1697DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1698{
1699 RTGCUINTREG val, valShadow;
1700 RTGCUINTPTR uInterruptState;
1701 int rc;
1702
1703 /* Let's first sync back eip, esp, and eflags. */
1704 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1705 AssertRC(rc);
1706 pCtx->rip = val;
1707 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1708 AssertRC(rc);
1709 pCtx->rsp = val;
1710 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1711 AssertRC(rc);
1712 pCtx->eflags.u32 = val;
1713
1714 /* Take care of instruction fusing (sti, mov ss) */
1715 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1716 uInterruptState = val;
1717 if (uInterruptState != 0)
1718 {
1719 Assert(uInterruptState <= 2); /* only sti & mov ss */
1720 Log(("uInterruptState %x eip=%RGv\n", uInterruptState, pCtx->rip));
1721 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1722 }
1723 else
1724 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1725
1726 /* Control registers. */
1727 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1728 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1729 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1730 CPUMSetGuestCR0(pVM, val);
1731
1732 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1733 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1734 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1735 CPUMSetGuestCR4(pVM, val);
1736
1737 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1738 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1739 if ( pVM->hwaccm.s.fNestedPaging
1740 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1741 {
1742 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1743
1744 /* Can be updated behind our back in the nested paging case. */
1745 CPUMSetGuestCR2(pVM, pCache->cr2);
1746
1747 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1748
1749 if (val != pCtx->cr3)
1750 {
1751 CPUMSetGuestCR3(pVM, val);
1752 PGMUpdateCR3(pVM, val);
1753 }
1754 /* Prefetch the four PDPT entries in PAE mode. */
1755 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1756 }
1757
1758 /* Sync back DR7 here. */
1759 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1760 pCtx->dr[7] = val;
1761
1762 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1763 VMX_READ_SELREG(ES, es);
1764 VMX_READ_SELREG(SS, ss);
1765 VMX_READ_SELREG(CS, cs);
1766 VMX_READ_SELREG(DS, ds);
1767 VMX_READ_SELREG(FS, fs);
1768 VMX_READ_SELREG(GS, gs);
1769
1770 /*
1771 * System MSRs
1772 */
1773 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1774 pCtx->SysEnter.cs = val;
1775 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1776 pCtx->SysEnter.eip = val;
1777 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1778 pCtx->SysEnter.esp = val;
1779
1780 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1781 VMX_READ_SELREG(LDTR, ldtr);
1782
1783 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1784 pCtx->gdtr.cbGdt = val;
1785 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1786 pCtx->gdtr.pGdt = val;
1787
1788 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1789 pCtx->idtr.cbIdt = val;
1790 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1791 pCtx->idtr.pIdt = val;
1792
1793#ifdef HWACCM_VMX_EMULATE_REALMODE
1794 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1795 if (CPUMIsGuestInRealModeEx(pCtx))
1796 {
1797 /* Hide our emulation flags */
1798 pCtx->eflags.Bits.u1VM = 0;
1799 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1800
1801 /* Force a TR resync every time in case we switch modes. */
1802 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1803 }
1804 else
1805#endif /* HWACCM_VMX_EMULATE_REALMODE */
1806 {
1807 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1808 VMX_READ_SELREG(TR, tr);
1809 }
1810 return VINF_SUCCESS;
1811}
1812
1813/**
1814 * Dummy placeholder
1815 *
1816 * @param pVM The VM to operate on.
1817 * @param pVCpu The VMCPU to operate on.
1818 */
1819static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1820{
1821 NOREF(pVM);
1822 NOREF(pVCpu);
1823 return;
1824}
1825
1826/**
1827 * Setup the tagged TLB for EPT
1828 *
1829 * @returns VBox status code.
1830 * @param pVM The VM to operate on.
1831 * @param pVCpu The VMCPU to operate on.
1832 */
1833static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1834{
1835 PHWACCM_CPUINFO pCpu;
1836
1837 Assert(pVM->hwaccm.s.fNestedPaging);
1838 Assert(!pVM->hwaccm.s.vmx.fVPID);
1839
1840 /* Deal with tagged TLBs if VPID or EPT is supported. */
1841 pCpu = HWACCMR0GetCurrentCpu();
1842 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1843 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1844 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1845 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1846 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1847 {
1848 /* Force a TLB flush on VM entry. */
1849 pVCpu->hwaccm.s.fForceTLBFlush = true;
1850 }
1851 else
1852 Assert(!pCpu->fFlushTLB);
1853
1854 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1855 pCpu->fFlushTLB = false;
1856
1857 if (pVCpu->hwaccm.s.fForceTLBFlush)
1858 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1859
1860#ifdef VBOX_WITH_STATISTICS
1861 if (pVCpu->hwaccm.s.fForceTLBFlush)
1862 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1863 else
1864 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1865#endif
1866}
1867
1868#ifdef HWACCM_VTX_WITH_VPID
1869/**
1870 * Setup the tagged TLB for VPID
1871 *
1872 * @returns VBox status code.
1873 * @param pVM The VM to operate on.
1874 * @param pVCpu The VMCPU to operate on.
1875 */
1876static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1877{
1878 PHWACCM_CPUINFO pCpu;
1879
1880 Assert(pVM->hwaccm.s.vmx.fVPID);
1881 Assert(!pVM->hwaccm.s.fNestedPaging);
1882
1883 /* Deal with tagged TLBs if VPID or EPT is supported. */
1884 pCpu = HWACCMR0GetCurrentCpu();
1885 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1886 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1887 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1888 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1889 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1890 {
1891 /* Force a TLB flush on VM entry. */
1892 pVCpu->hwaccm.s.fForceTLBFlush = true;
1893 }
1894 else
1895 Assert(!pCpu->fFlushTLB);
1896
1897 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1898
1899 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1900 if (pVCpu->hwaccm.s.fForceTLBFlush)
1901 {
1902 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1903 || pCpu->fFlushTLB)
1904 {
1905 pCpu->fFlushTLB = false;
1906 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1907 pCpu->cTLBFlushes++;
1908 }
1909 else
1910 {
1911 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1912 pVCpu->hwaccm.s.fForceTLBFlush = false;
1913 }
1914
1915 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1916 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1917 }
1918 else
1919 {
1920 Assert(!pCpu->fFlushTLB);
1921
1922 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1923 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1924 }
1925 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1926 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1927 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1928
1929 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1930 AssertRC(rc);
1931
1932 if (pVCpu->hwaccm.s.fForceTLBFlush)
1933 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1934
1935#ifdef VBOX_WITH_STATISTICS
1936 if (pVCpu->hwaccm.s.fForceTLBFlush)
1937 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1938 else
1939 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1940#endif
1941}
1942#endif /* HWACCM_VTX_WITH_VPID */
1943
1944/**
1945 * Runs guest code in a VT-x VM.
1946 *
1947 * @returns VBox status code.
1948 * @param pVM The VM to operate on.
1949 * @param pVCpu The VMCPU to operate on.
1950 * @param pCtx Guest context
1951 */
1952VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1953{
1954 int rc = VINF_SUCCESS;
1955 RTGCUINTREG val;
1956 RTGCUINTREG exitReason, instrError, cbInstr;
1957 RTGCUINTPTR exitQualification;
1958 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1959 RTGCUINTPTR errCode, instrInfo;
1960 bool fSyncTPR = false;
1961 PHWACCM_CPUINFO pCpu = 0;
1962 unsigned cResume = 0;
1963#ifdef VBOX_STRICT
1964 RTCPUID idCpuCheck;
1965#endif
1966#ifdef VBOX_WITH_STATISTICS
1967 bool fStatEntryStarted = true;
1968 bool fStatExit2Started = false;
1969#endif
1970
1971 Log2(("\nE"));
1972
1973 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
1974
1975#ifdef VBOX_STRICT
1976 {
1977 RTCCUINTREG val;
1978
1979 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1980 AssertRC(rc);
1981 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1982
1983 /* allowed zero */
1984 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1985 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1986
1987 /* allowed one */
1988 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1989 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1990
1991 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1992 AssertRC(rc);
1993 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1994
1995 /* Must be set according to the MSR, but can be cleared in case of EPT. */
1996 if (pVM->hwaccm.s.fNestedPaging)
1997 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
1998 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1999 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2000
2001 /* allowed zero */
2002 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2003 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2004
2005 /* allowed one */
2006 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2007 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2008
2009 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2010 AssertRC(rc);
2011 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2012
2013 /* allowed zero */
2014 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2015 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2016
2017 /* allowed one */
2018 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2019 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2020
2021 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2022 AssertRC(rc);
2023 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2024
2025 /* allowed zero */
2026 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2027 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2028
2029 /* allowed one */
2030 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2031 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2032 }
2033#endif
2034
2035#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2036 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2037#endif
2038
2039 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2040 */
2041ResumeExecution:
2042 STAM_STATS({
2043 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2044 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2045 });
2046 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2047 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2048 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2049 Assert(!HWACCMR0SuspendPending());
2050
2051 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2052 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
2053 {
2054 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2055 rc = VINF_EM_RAW_INTERRUPT;
2056 goto end;
2057 }
2058
2059 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2060 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
2061 {
2062 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
2063 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
2064 {
2065 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2066 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2067 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2068 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2069 */
2070 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
2071 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2072 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2073 AssertRC(rc);
2074 }
2075 }
2076 else
2077 {
2078 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2079 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2080 AssertRC(rc);
2081 }
2082
2083 /* Check for pending actions that force us to go back to ring 3. */
2084 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER | VM_FF_PGM_NEED_HANDY_PAGES))
2085 {
2086 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
2087 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2088 rc = VINF_EM_RAW_TO_R3;
2089 goto end;
2090 }
2091 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2092 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
2093 {
2094 rc = VINF_EM_PENDING_REQUEST;
2095 goto end;
2096 }
2097
2098 /* When external interrupts are pending, we should exit the VM when IF is set. */
2099 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2100 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2101 if (RT_FAILURE(rc))
2102 goto end;
2103
2104 /** @todo check timers?? */
2105
2106 /* TPR caching using CR8 is only available in 64 bits mode */
2107 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2108 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2109 /**
2110 * @todo reduce overhead
2111 */
2112 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
2113 && pVM->hwaccm.s.vmx.pAPIC)
2114 {
2115 /* TPR caching in CR8 */
2116 uint8_t u8TPR;
2117 bool fPending;
2118
2119 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
2120 AssertRC(rc);
2121 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2122 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
2123
2124 /* Two options here:
2125 * - external interrupt pending, but masked by the TPR value.
2126 * -> a CR8 update that lower the current TPR value should cause an exit
2127 * - no pending interrupts
2128 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2129 */
2130 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
2131 AssertRC(rc);
2132
2133 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
2134 fSyncTPR = true;
2135 }
2136
2137#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2138 if ( pVM->hwaccm.s.fNestedPaging
2139# ifdef HWACCM_VTX_WITH_VPID
2140 || pVM->hwaccm.s.vmx.fVPID
2141# endif /* HWACCM_VTX_WITH_VPID */
2142 )
2143 {
2144 pCpu = HWACCMR0GetCurrentCpu();
2145 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2146 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2147 {
2148 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2149 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2150 else
2151 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2152 }
2153 if (pCpu->fFlushTLB)
2154 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2155 else
2156 if (pVCpu->hwaccm.s.fForceTLBFlush)
2157 LogFlow(("Manual TLB flush\n"));
2158 }
2159#endif
2160#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2161 PGMDynMapFlushAutoSet(pVCpu);
2162#endif
2163
2164 /*
2165 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2166 * (until the actual world switch)
2167 */
2168#ifdef VBOX_STRICT
2169 idCpuCheck = RTMpCpuId();
2170#endif
2171#ifdef LOG_LOGGING
2172 VMMR0LogFlushDisable(pVCpu);
2173#endif
2174 /* Save the host state first. */
2175 rc = VMXR0SaveHostState(pVM, pVCpu);
2176 if (rc != VINF_SUCCESS)
2177 goto end;
2178 /* Load the guest state */
2179 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2180 if (rc != VINF_SUCCESS)
2181 goto end;
2182
2183 /* Deal with tagged TLB setup and invalidation. */
2184 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2185
2186 /* Non-register state Guest Context */
2187 /** @todo change me according to cpu state */
2188 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2189 AssertRC(rc);
2190
2191 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2192
2193 /* Manual save and restore:
2194 * - General purpose registers except RIP, RSP
2195 *
2196 * Trashed:
2197 * - CR2 (we don't care)
2198 * - LDTR (reset to 0)
2199 * - DRx (presumably not changed at all)
2200 * - DR7 (reset to 0x400)
2201 * - EFLAGS (reset to RT_BIT(1); not relevant)
2202 *
2203 */
2204
2205
2206 /* All done! Let's start VM execution. */
2207 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2208#ifdef VBOX_STRICT
2209 Assert(idCpuCheck == RTMpCpuId());
2210#endif
2211
2212#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2213 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2214 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2215#endif
2216
2217 TMNotifyStartOfExecution(pVM);
2218 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2219 TMNotifyEndOfExecution(pVM);
2220
2221 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2222
2223 /* In case we execute a goto ResumeExecution later on. */
2224 pVCpu->hwaccm.s.fResumeVM = true;
2225 pVCpu->hwaccm.s.fForceTLBFlush = false;
2226
2227 /*
2228 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2229 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2230 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2231 */
2232 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2233 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2234
2235 if (rc != VINF_SUCCESS)
2236 {
2237 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2238 goto end;
2239 }
2240
2241 /* Success. Query the guest state and figure out what has happened. */
2242
2243 /* Investigate why there was a VM-exit. */
2244 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2245 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2246
2247 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2248 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2249 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2250 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2251 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2252 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2253 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2254 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2255 AssertRC(rc);
2256
2257 /* Sync back the guest state */
2258 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2259 AssertRC(rc);
2260
2261 /* Note! NOW IT'S SAFE FOR LOGGING! */
2262#ifdef LOG_LOGGING
2263 VMMR0LogFlushEnable(pVCpu);
2264#endif
2265 Log2(("Raw exit reason %08x\n", exitReason));
2266
2267 /* Check if an injected event was interrupted prematurely. */
2268 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2269 AssertRC(rc);
2270 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2271 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2272 /* Ignore 'int xx' as they'll be restarted anyway. */
2273 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2274 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2275 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2276 {
2277 pVCpu->hwaccm.s.Event.fPending = true;
2278 /* Error code present? */
2279 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2280 {
2281 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2282 AssertRC(rc);
2283 pVCpu->hwaccm.s.Event.errCode = val;
2284 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2285 }
2286 else
2287 {
2288 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2289 pVCpu->hwaccm.s.Event.errCode = 0;
2290 }
2291 }
2292#ifdef VBOX_STRICT
2293 else
2294 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2295 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2296 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2297 {
2298 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2299 }
2300
2301 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2302 HWACCMDumpRegs(pVM, pCtx);
2303#endif
2304
2305 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2306 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2307 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2308 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2309 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2310
2311 if (fSyncTPR)
2312 {
2313 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
2314 AssertRC(rc);
2315 }
2316
2317 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2318 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2319
2320 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2321 switch (exitReason)
2322 {
2323 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2324 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2325 {
2326 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2327
2328 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2329 {
2330 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2331 /* External interrupt; leave to allow it to be dispatched again. */
2332 rc = VINF_EM_RAW_INTERRUPT;
2333 break;
2334 }
2335 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2336 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2337 {
2338 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2339 /* External interrupt; leave to allow it to be dispatched again. */
2340 rc = VINF_EM_RAW_INTERRUPT;
2341 break;
2342
2343 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2344 AssertFailed(); /* can't come here; fails the first check. */
2345 break;
2346
2347 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2348 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2349 Assert(vector == 1 || vector == 3 || vector == 4);
2350 /* no break */
2351 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2352 Log2(("Hardware/software interrupt %d\n", vector));
2353 switch (vector)
2354 {
2355 case X86_XCPT_NM:
2356 {
2357 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2358
2359 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2360 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2361 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2362 if (rc == VINF_SUCCESS)
2363 {
2364 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2365
2366 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2367
2368 /* Continue execution. */
2369 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2370
2371 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2372 goto ResumeExecution;
2373 }
2374
2375 Log(("Forward #NM fault to the guest\n"));
2376 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2377 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2378 AssertRC(rc);
2379 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2380 goto ResumeExecution;
2381 }
2382
2383 case X86_XCPT_PF: /* Page fault */
2384 {
2385#ifdef DEBUG
2386 if (pVM->hwaccm.s.fNestedPaging)
2387 { /* A genuine pagefault.
2388 * Forward the trap to the guest by injecting the exception and resuming execution.
2389 */
2390 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2391
2392 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2393
2394 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2395
2396 /* Now we must update CR2. */
2397 pCtx->cr2 = exitQualification;
2398 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2399 AssertRC(rc);
2400
2401 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2402 goto ResumeExecution;
2403 }
2404#endif
2405 Assert(!pVM->hwaccm.s.fNestedPaging);
2406
2407 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2408 /* Exit qualification contains the linear address of the page fault. */
2409 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2410 TRPMSetErrorCode(pVM, errCode);
2411 TRPMSetFaultAddress(pVM, exitQualification);
2412
2413 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2414 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2415 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2416 if (rc == VINF_SUCCESS)
2417 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2418 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2419 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2420
2421 TRPMResetTrap(pVM);
2422
2423 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2424 goto ResumeExecution;
2425 }
2426 else
2427 if (rc == VINF_EM_RAW_GUEST_TRAP)
2428 { /* A genuine pagefault.
2429 * Forward the trap to the guest by injecting the exception and resuming execution.
2430 */
2431 Log2(("Forward page fault to the guest\n"));
2432
2433 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2434 /* The error code might have been changed. */
2435 errCode = TRPMGetErrorCode(pVM);
2436
2437 TRPMResetTrap(pVM);
2438
2439 /* Now we must update CR2. */
2440 pCtx->cr2 = exitQualification;
2441 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2442 AssertRC(rc);
2443
2444 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2445 goto ResumeExecution;
2446 }
2447#ifdef VBOX_STRICT
2448 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2449 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2450#endif
2451 /* Need to go back to the recompiler to emulate the instruction. */
2452 TRPMResetTrap(pVM);
2453 break;
2454 }
2455
2456 case X86_XCPT_MF: /* Floating point exception. */
2457 {
2458 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2459 if (!(pCtx->cr0 & X86_CR0_NE))
2460 {
2461 /* old style FPU error reporting needs some extra work. */
2462 /** @todo don't fall back to the recompiler, but do it manually. */
2463 rc = VINF_EM_RAW_EMULATE_INSTR;
2464 break;
2465 }
2466 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2467 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2468 AssertRC(rc);
2469
2470 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2471 goto ResumeExecution;
2472 }
2473
2474 case X86_XCPT_DB: /* Debug exception. */
2475 {
2476 uint64_t uDR6;
2477
2478 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2479 *
2480 * Exit qualification bits:
2481 * 3:0 B0-B3 which breakpoint condition was met
2482 * 12:4 Reserved (0)
2483 * 13 BD - debug register access detected
2484 * 14 BS - single step execution or branch taken
2485 * 63:15 Reserved (0)
2486 */
2487 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2488
2489 /* Note that we don't support guest and host-initiated debugging at the same time. */
2490 Assert(DBGFIsStepping(pVM) || CPUMIsGuestInRealModeEx(pCtx));
2491
2492 uDR6 = X86_DR6_INIT_VAL;
2493 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2494 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
2495 if (rc == VINF_EM_RAW_GUEST_TRAP)
2496 {
2497 /** @todo this isn't working, but we'll never get here normally. */
2498
2499 /* Update DR6 here. */
2500 pCtx->dr[6] = uDR6;
2501
2502 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2503 pCtx->dr[7] &= ~X86_DR7_GD;
2504
2505 /* Paranoia. */
2506 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2507 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2508 pCtx->dr[7] |= 0x400; /* must be one */
2509
2510 /* Resync DR7 */
2511 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2512 AssertRC(rc);
2513
2514 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2515 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2516 AssertRC(rc);
2517
2518 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2519 goto ResumeExecution;
2520 }
2521 /* Return to ring 3 to deal with the debug exit code. */
2522 break;
2523 }
2524
2525#ifdef DEBUG /* till after branching, enable by default after that. */
2526 case X86_XCPT_BP: /* Breakpoint. */
2527 {
2528 rc = DBGFR0Trap03Handler(pVM, CPUMCTX2CORE(pCtx));
2529 if (rc == VINF_EM_RAW_GUEST_TRAP)
2530 {
2531 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2532 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2533 AssertRC(rc);
2534 goto ResumeExecution;
2535 }
2536 if (rc == VINF_SUCCESS)
2537 goto ResumeExecution;
2538 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2539 break;
2540 }
2541#endif
2542
2543 case X86_XCPT_GP: /* General protection failure exception.*/
2544 {
2545 uint32_t cbSize;
2546
2547 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2548#ifdef VBOX_STRICT
2549 if (!CPUMIsGuestInRealModeEx(pCtx))
2550 {
2551 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2552 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2553 AssertRC(rc);
2554 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2555 goto ResumeExecution;
2556 }
2557#endif
2558 Assert(CPUMIsGuestInRealModeEx(pCtx));
2559
2560 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2561 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2562 if (rc == VINF_SUCCESS)
2563 {
2564 /* EIP has been updated already. */
2565
2566 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2567 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2568
2569 /* Only resume if successful. */
2570 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2571 goto ResumeExecution;
2572 }
2573 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2574 break;
2575 }
2576
2577#ifdef VBOX_STRICT
2578 case X86_XCPT_DE: /* Divide error. */
2579 case X86_XCPT_UD: /* Unknown opcode exception. */
2580 case X86_XCPT_SS: /* Stack segment exception. */
2581 case X86_XCPT_NP: /* Segment not present exception. */
2582 {
2583 switch(vector)
2584 {
2585 case X86_XCPT_DE:
2586 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2587 break;
2588 case X86_XCPT_UD:
2589 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2590 break;
2591 case X86_XCPT_SS:
2592 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2593 break;
2594 case X86_XCPT_NP:
2595 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2596 break;
2597 }
2598
2599 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2600 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2601 AssertRC(rc);
2602
2603 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2604 goto ResumeExecution;
2605 }
2606#endif
2607 default:
2608#ifdef HWACCM_VMX_EMULATE_REALMODE
2609 if (CPUMIsGuestInRealModeEx(pCtx))
2610 {
2611 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2612 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2613 AssertRC(rc);
2614
2615 /* Go back to ring 3 in case of a triple fault. */
2616 if ( vector == X86_XCPT_DF
2617 && rc == VINF_EM_RESET)
2618 break;
2619
2620 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2621 goto ResumeExecution;
2622 }
2623#endif
2624 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2625 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2626 break;
2627 } /* switch (vector) */
2628
2629 break;
2630
2631 default:
2632 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2633 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2634 break;
2635 }
2636
2637 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2638 break;
2639 }
2640
2641 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2642 {
2643 RTGCPHYS GCPhys;
2644
2645 Assert(pVM->hwaccm.s.fNestedPaging);
2646
2647 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2648 AssertRC(rc);
2649 Assert(((exitQualification >> 7) & 3) != 2);
2650
2651 /* Determine the kind of violation. */
2652 errCode = 0;
2653 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2654 errCode |= X86_TRAP_PF_ID;
2655
2656 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2657 errCode |= X86_TRAP_PF_RW;
2658
2659 /* If the page is present, then it's a page level protection fault. */
2660 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2661 errCode |= X86_TRAP_PF_P;
2662
2663 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2664
2665 /* GCPhys contains the guest physical address of the page fault. */
2666 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
2667 TRPMSetErrorCode(pVM, errCode);
2668 TRPMSetFaultAddress(pVM, GCPhys);
2669
2670 /* Handle the pagefault trap for the nested shadow table. */
2671 rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2672 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2673 if (rc == VINF_SUCCESS)
2674 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2675 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
2676 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
2677
2678 TRPMResetTrap(pVM);
2679
2680 goto ResumeExecution;
2681 }
2682
2683#ifdef VBOX_STRICT
2684 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2685 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2686#endif
2687 /* Need to go back to the recompiler to emulate the instruction. */
2688 TRPMResetTrap(pVM);
2689 break;
2690 }
2691
2692 case VMX_EXIT_EPT_MISCONFIG:
2693 {
2694 RTGCPHYS GCPhys;
2695
2696 Assert(pVM->hwaccm.s.fNestedPaging);
2697
2698 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2699 AssertRC(rc);
2700
2701 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
2702 break;
2703 }
2704
2705 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2706 /* Clear VM-exit on IF=1 change. */
2707 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2708 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2709 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2710 AssertRC(rc);
2711 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
2712 goto ResumeExecution; /* we check for pending guest interrupts there */
2713
2714 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2715 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2716 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
2717 /* Skip instruction and continue directly. */
2718 pCtx->rip += cbInstr;
2719 /* Continue execution.*/
2720 goto ResumeExecution;
2721
2722 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2723 {
2724 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2725 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
2726 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
2727 if (rc == VINF_SUCCESS)
2728 {
2729 /* Update EIP and continue execution. */
2730 Assert(cbInstr == 2);
2731 pCtx->rip += cbInstr;
2732 goto ResumeExecution;
2733 }
2734 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
2735 rc = VINF_EM_RAW_EMULATE_INSTR;
2736 break;
2737 }
2738
2739 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2740 {
2741 Log2(("VMX: Rdtsc\n"));
2742 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2743 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
2744 if (rc == VINF_SUCCESS)
2745 {
2746 /* Update EIP and continue execution. */
2747 Assert(cbInstr == 2);
2748 pCtx->rip += cbInstr;
2749 goto ResumeExecution;
2750 }
2751 AssertMsgFailed(("EMU: rdtsc failed with %Rrc\n", rc));
2752 rc = VINF_EM_RAW_EMULATE_INSTR;
2753 break;
2754 }
2755
2756 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2757 {
2758 Log2(("VMX: invlpg\n"));
2759 Assert(!pVM->hwaccm.s.fNestedPaging);
2760
2761 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2762 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
2763 if (rc == VINF_SUCCESS)
2764 {
2765 /* Update EIP and continue execution. */
2766 pCtx->rip += cbInstr;
2767 goto ResumeExecution;
2768 }
2769 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
2770 break;
2771 }
2772
2773 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2774 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2775 {
2776 uint32_t cbSize;
2777
2778 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2779 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
2780 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
2781 if (rc == VINF_SUCCESS)
2782 {
2783 /* EIP has been updated already. */
2784
2785 /* Only resume if successful. */
2786 goto ResumeExecution;
2787 }
2788 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
2789 break;
2790 }
2791
2792 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2793 {
2794 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2795
2796 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
2797 {
2798 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
2799 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
2800 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
2801 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
2802 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
2803 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
2804
2805 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
2806 {
2807 case 0:
2808 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
2809 break;
2810 case 2:
2811 break;
2812 case 3:
2813 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
2814 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2815 break;
2816 case 4:
2817 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2818 break;
2819 case 8:
2820 /* CR8 contains the APIC TPR */
2821 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2822 break;
2823
2824 default:
2825 AssertFailed();
2826 break;
2827 }
2828 /* Check if a sync operation is pending. */
2829 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2830 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2831 {
2832 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2833 AssertRC(rc);
2834 }
2835 break;
2836
2837 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
2838 Log2(("VMX: mov x, crx\n"));
2839 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
2840
2841 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
2842
2843 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
2844 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
2845
2846 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
2847 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
2848 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
2849 break;
2850
2851 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
2852 Log2(("VMX: clts\n"));
2853 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
2854 rc = EMInterpretCLTS(pVM);
2855 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2856 break;
2857
2858 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
2859 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
2860 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
2861 rc = EMInterpretLMSW(pVM, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
2862 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2863 break;
2864 }
2865
2866 /* Update EIP if no error occurred. */
2867 if (RT_SUCCESS(rc))
2868 pCtx->rip += cbInstr;
2869
2870 if (rc == VINF_SUCCESS)
2871 {
2872 /* Only resume if successful. */
2873 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2874 goto ResumeExecution;
2875 }
2876 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2877 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2878 break;
2879 }
2880
2881 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2882 {
2883 if (!DBGFIsStepping(pVM))
2884 {
2885 /* Disable drx move intercepts. */
2886 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
2887 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2888 AssertRC(rc);
2889
2890 /* Save the host and load the guest debug state. */
2891 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
2892 AssertRC(rc);
2893
2894#ifdef VBOX_WITH_STATISTICS
2895 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2896 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2897 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2898 else
2899 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2900#endif
2901
2902 goto ResumeExecution;
2903 }
2904
2905 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
2906 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
2907 {
2908 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
2909 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2910 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
2911 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
2912 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
2913 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2914 Log2(("DR7=%08x\n", pCtx->dr[7]));
2915 }
2916 else
2917 {
2918 Log2(("VMX: mov x, drx\n"));
2919 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2920 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
2921 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
2922 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
2923 }
2924 /* Update EIP if no error occurred. */
2925 if (RT_SUCCESS(rc))
2926 pCtx->rip += cbInstr;
2927
2928 if (rc == VINF_SUCCESS)
2929 {
2930 /* Only resume if successful. */
2931 goto ResumeExecution;
2932 }
2933 Assert(rc == VERR_EM_INTERPRETER);
2934 break;
2935 }
2936
2937 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2938 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2939 {
2940 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
2941 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
2942 uint32_t uPort;
2943 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
2944
2945 /** @todo necessary to make the distinction? */
2946 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
2947 {
2948 uPort = pCtx->edx & 0xffff;
2949 }
2950 else
2951 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
2952
2953 /* paranoia */
2954 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
2955 {
2956 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
2957 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
2958 break;
2959 }
2960
2961 uint32_t cbSize = g_aIOSize[uIOWidth];
2962
2963 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
2964 {
2965 /* ins/outs */
2966 DISCPUSTATE Cpu;
2967
2968 /* Disassemble manually to deal with segment prefixes. */
2969 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
2970 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
2971 rc = EMInterpretDisasOne(pVM, CPUMCTX2CORE(pCtx), &Cpu, NULL);
2972 if (rc == VINF_SUCCESS)
2973 {
2974 if (fIOWrite)
2975 {
2976 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
2977 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2978 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
2979 }
2980 else
2981 {
2982 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
2983 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2984 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
2985 }
2986 }
2987 else
2988 rc = VINF_EM_RAW_EMULATE_INSTR;
2989 }
2990 else
2991 {
2992 /* normal in/out */
2993 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
2994
2995 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
2996
2997 if (fIOWrite)
2998 {
2999 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3000 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3001 }
3002 else
3003 {
3004 uint32_t u32Val = 0;
3005
3006 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3007 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3008 if (IOM_SUCCESS(rc))
3009 {
3010 /* Write back to the EAX register. */
3011 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3012 }
3013 }
3014 }
3015 /*
3016 * Handled the I/O return codes.
3017 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3018 */
3019 if (IOM_SUCCESS(rc))
3020 {
3021 /* Update EIP and continue execution. */
3022 pCtx->rip += cbInstr;
3023 if (RT_LIKELY(rc == VINF_SUCCESS))
3024 {
3025 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3026 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3027 {
3028 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3029 for (unsigned i=0;i<4;i++)
3030 {
3031 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3032
3033 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3034 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3035 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3036 {
3037 uint64_t uDR6;
3038
3039 Assert(CPUMIsGuestDebugStateActive(pVM));
3040
3041 uDR6 = ASMGetDR6();
3042
3043 /* Clear all breakpoint status flags and set the one we just hit. */
3044 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3045 uDR6 |= (uint64_t)RT_BIT(i);
3046
3047 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3048 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3049 * the contents have been read.
3050 */
3051 ASMSetDR6(uDR6);
3052
3053 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3054 pCtx->dr[7] &= ~X86_DR7_GD;
3055
3056 /* Paranoia. */
3057 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3058 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3059 pCtx->dr[7] |= 0x400; /* must be one */
3060
3061 /* Resync DR7 */
3062 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3063 AssertRC(rc);
3064
3065 /* Construct inject info. */
3066 intInfo = X86_XCPT_DB;
3067 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3068 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3069
3070 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3071 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3072 AssertRC(rc);
3073
3074 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3075 goto ResumeExecution;
3076 }
3077 }
3078 }
3079
3080 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3081 goto ResumeExecution;
3082 }
3083 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3084 break;
3085 }
3086
3087#ifdef VBOX_STRICT
3088 if (rc == VINF_IOM_HC_IOPORT_READ)
3089 Assert(!fIOWrite);
3090 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3091 Assert(fIOWrite);
3092 else
3093 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3094#endif
3095 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3096 break;
3097 }
3098
3099 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3100 LogFlow(("VMX_EXIT_TPR\n"));
3101 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3102 goto ResumeExecution;
3103
3104 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3105 goto ResumeExecution;
3106
3107 default:
3108 /* The rest is handled after syncing the entire CPU state. */
3109 break;
3110 }
3111
3112 /* Note: the guest state isn't entirely synced back at this stage. */
3113
3114 /* Investigate why there was a VM-exit. (part 2) */
3115 switch (exitReason)
3116 {
3117 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3118 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3119 case VMX_EXIT_EPT_VIOLATION:
3120 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3121 /* Already handled above. */
3122 break;
3123
3124 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3125 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3126 break;
3127
3128 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3129 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3130 rc = VINF_EM_RAW_INTERRUPT;
3131 AssertFailed(); /* Can't happen. Yet. */
3132 break;
3133
3134 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3135 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3136 rc = VINF_EM_RAW_INTERRUPT;
3137 AssertFailed(); /* Can't happen afaik. */
3138 break;
3139
3140 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3141 rc = VERR_EM_INTERPRETER;
3142 break;
3143
3144 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3145 /** Check if external interrupts are pending; if so, don't switch back. */
3146 pCtx->rip++; /* skip hlt */
3147 if ( pCtx->eflags.Bits.u1IF
3148 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
3149 goto ResumeExecution;
3150
3151 rc = VINF_EM_HALT;
3152 break;
3153
3154 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3155 AssertFailed(); /* can't happen. */
3156 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3157 break;
3158
3159 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3160 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3161 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3162 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3163 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3164 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3165 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3166 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3167 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3168 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3169 /** @todo inject #UD immediately */
3170 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3171 break;
3172
3173 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3174 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3175 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3176 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3177 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3178 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3179 /* already handled above */
3180 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3181 || rc == VINF_EM_RAW_INTERRUPT
3182 || rc == VERR_EM_INTERPRETER
3183 || rc == VINF_EM_RAW_EMULATE_INSTR
3184 || rc == VINF_PGM_SYNC_CR3
3185 || rc == VINF_IOM_HC_IOPORT_READ
3186 || rc == VINF_IOM_HC_IOPORT_WRITE
3187 || rc == VINF_EM_RAW_GUEST_TRAP
3188 || rc == VINF_TRPM_XCPT_DISPATCHED
3189 || rc == VINF_EM_RESCHEDULE_REM,
3190 ("rc = %d\n", rc));
3191 break;
3192
3193 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3194 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3195 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3196 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3197 rc = VERR_EM_INTERPRETER;
3198 break;
3199
3200 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3201 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3202 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3203 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3204 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3205 break;
3206
3207 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3208 Assert(rc == VINF_EM_RAW_INTERRUPT);
3209 break;
3210
3211 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3212 {
3213#ifdef VBOX_STRICT
3214 RTCCUINTREG val = 0;
3215
3216 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3217
3218 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3219 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3220
3221 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3222 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3223
3224 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3225 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3226
3227 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3228 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3229
3230 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3231 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3232
3233 VMX_LOG_SELREG(CS, "CS");
3234 VMX_LOG_SELREG(DS, "DS");
3235 VMX_LOG_SELREG(ES, "ES");
3236 VMX_LOG_SELREG(FS, "FS");
3237 VMX_LOG_SELREG(GS, "GS");
3238 VMX_LOG_SELREG(SS, "SS");
3239 VMX_LOG_SELREG(TR, "TR");
3240 VMX_LOG_SELREG(LDTR, "LDTR");
3241
3242 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3243 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3244 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3245 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3246#endif /* VBOX_STRICT */
3247 rc = VERR_VMX_INVALID_GUEST_STATE;
3248 break;
3249 }
3250
3251 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3252 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3253 default:
3254 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3255 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3256 break;
3257
3258 }
3259end:
3260
3261 /* Signal changes for the recompiler. */
3262 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3263
3264 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3265 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3266 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3267 {
3268 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3269 /* On the next entry we'll only sync the host context. */
3270 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3271 }
3272 else
3273 {
3274 /* On the next entry we'll sync everything. */
3275 /** @todo we can do better than this */
3276 /* Not in the VINF_PGM_CHANGE_MODE though! */
3277 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3278 }
3279
3280 /* translate into a less severe return code */
3281 if (rc == VERR_EM_INTERPRETER)
3282 rc = VINF_EM_RAW_EMULATE_INSTR;
3283 else
3284 /* Try to extract more information about what might have gone wrong here. */
3285 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3286 {
3287 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3288 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3289 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3290 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3291 }
3292
3293 STAM_STATS({
3294 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3295 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3296 });
3297 Log2(("X"));
3298 return rc;
3299}
3300
3301
3302/**
3303 * Enters the VT-x session
3304 *
3305 * @returns VBox status code.
3306 * @param pVM The VM to operate on.
3307 * @param pVCpu The VMCPU to operate on.
3308 * @param pCpu CPU info struct
3309 */
3310VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3311{
3312 Assert(pVM->hwaccm.s.vmx.fSupported);
3313
3314 unsigned cr4 = ASMGetCR4();
3315 if (!(cr4 & X86_CR4_VMXE))
3316 {
3317 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3318 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3319 }
3320
3321 /* Activate the VM Control Structure. */
3322 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3323 if (RT_FAILURE(rc))
3324 return rc;
3325
3326 pVCpu->hwaccm.s.fResumeVM = false;
3327 return VINF_SUCCESS;
3328}
3329
3330
3331/**
3332 * Leaves the VT-x session
3333 *
3334 * @returns VBox status code.
3335 * @param pVM The VM to operate on.
3336 * @param pVCpu The VMCPU to operate on.
3337 * @param pCtx CPU context
3338 */
3339VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3340{
3341 Assert(pVM->hwaccm.s.vmx.fSupported);
3342
3343 /* Save the guest debug state if necessary. */
3344 if (CPUMIsGuestDebugStateActive(pVM))
3345 {
3346 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3347
3348 /* Enable drx move intercepts again. */
3349 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3350 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3351 AssertRC(rc);
3352
3353 /* Resync the debug registers the next time. */
3354 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3355 }
3356 else
3357 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3358
3359 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3360 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3361 AssertRC(rc);
3362
3363 return VINF_SUCCESS;
3364}
3365
3366/**
3367 * Flush the TLB (EPT)
3368 *
3369 * @returns VBox status code.
3370 * @param pVM The VM to operate on.
3371 * @param pVCpu The VM CPU to operate on.
3372 * @param enmFlush Type of flush
3373 * @param GCPhys Physical address of the page to flush
3374 */
3375static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3376{
3377 uint64_t descriptor[2];
3378
3379 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3380 Assert(pVM->hwaccm.s.fNestedPaging);
3381 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3382 descriptor[1] = GCPhys;
3383 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3384 AssertRC(rc);
3385}
3386
3387#ifdef HWACCM_VTX_WITH_VPID
3388/**
3389 * Flush the TLB (EPT)
3390 *
3391 * @returns VBox status code.
3392 * @param pVM The VM to operate on.
3393 * @param pVCpu The VM CPU to operate on.
3394 * @param enmFlush Type of flush
3395 * @param GCPtr Virtual address of the page to flush
3396 */
3397static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3398{
3399#if HC_ARCH_BITS == 32
3400 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3401 if ( CPUMIsGuestInLongMode(pVM)
3402 && !VMX_IS_64BIT_HOST_MODE())
3403 {
3404 pVCpu->hwaccm.s.fForceTLBFlush = true;
3405 }
3406 else
3407#endif
3408 {
3409 uint64_t descriptor[2];
3410
3411 Assert(pVM->hwaccm.s.vmx.fVPID);
3412 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3413 descriptor[1] = GCPtr;
3414 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3415 AssertRC(rc);
3416 }
3417}
3418#endif /* HWACCM_VTX_WITH_VPID */
3419
3420/**
3421 * Invalidates a guest page
3422 *
3423 * @returns VBox status code.
3424 * @param pVM The VM to operate on.
3425 * @param pVCpu The VM CPU to operate on.
3426 * @param GCVirt Page to invalidate
3427 */
3428VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3429{
3430 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3431
3432 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3433
3434 /* Only relevant if we want to use VPID.
3435 * In the nested paging case we still see such calls, but
3436 * can safely ignore them. (e.g. after cr3 updates)
3437 */
3438#ifdef HWACCM_VTX_WITH_VPID
3439 /* Skip it if a TLB flush is already pending. */
3440 if ( !fFlushPending
3441 && pVM->hwaccm.s.vmx.fVPID)
3442 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3443#endif /* HWACCM_VTX_WITH_VPID */
3444
3445 return VINF_SUCCESS;
3446}
3447
3448/**
3449 * Invalidates a guest page by physical address
3450 *
3451 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3452 *
3453 * @returns VBox status code.
3454 * @param pVM The VM to operate on.
3455 * @param pVCpu The VM CPU to operate on.
3456 * @param GCPhys Page to invalidate
3457 */
3458VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3459{
3460 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3461
3462 Assert(pVM->hwaccm.s.fNestedPaging);
3463
3464 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3465
3466 /* Skip it if a TLB flush is already pending. */
3467 if (!fFlushPending)
3468 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3469
3470 return VINF_SUCCESS;
3471}
3472
3473/**
3474 * Report world switch error and dump some useful debug info
3475 *
3476 * @param pVM The VM to operate on.
3477 * @param pVCpu The VMCPU to operate on.
3478 * @param rc Return code
3479 * @param pCtx Current CPU context (not updated)
3480 */
3481static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3482{
3483 switch (rc)
3484 {
3485 case VERR_VMX_INVALID_VMXON_PTR:
3486 AssertFailed();
3487 break;
3488
3489 case VERR_VMX_UNABLE_TO_START_VM:
3490 case VERR_VMX_UNABLE_TO_RESUME_VM:
3491 {
3492 int rc;
3493 RTCCUINTREG exitReason, instrError;
3494
3495 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3496 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3497 AssertRC(rc);
3498 if (rc == VINF_SUCCESS)
3499 {
3500 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3501 Log(("Current stack %08x\n", &rc));
3502
3503 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3504 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3505
3506#ifdef VBOX_STRICT
3507 RTGDTR gdtr;
3508 PX86DESCHC pDesc;
3509 RTCCUINTREG val;
3510
3511 ASMGetGDTR(&gdtr);
3512
3513 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3514 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3515 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3516 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3517 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3518 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3519 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3520 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3521 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3522 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3523
3524 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3525 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3526
3527 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3528 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3529
3530 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3531 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3532
3533 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3534 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3535
3536 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3537 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3538
3539 if (val < gdtr.cbGdt)
3540 {
3541 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3542 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3543 }
3544
3545 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3546 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3547 if (val < gdtr.cbGdt)
3548 {
3549 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3550 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3551 }
3552
3553 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
3554 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3555 if (val < gdtr.cbGdt)
3556 {
3557 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3558 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3559 }
3560
3561 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
3562 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
3563 if (val < gdtr.cbGdt)
3564 {
3565 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3566 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3567 }
3568
3569 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
3570 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
3571 if (val < gdtr.cbGdt)
3572 {
3573 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3574 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3575 }
3576
3577 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
3578 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
3579 if (val < gdtr.cbGdt)
3580 {
3581 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3582 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3583 }
3584
3585 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
3586 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
3587 if (val < gdtr.cbGdt)
3588 {
3589 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3590 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3591 }
3592
3593 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3594 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
3595
3596 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3597 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
3598 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3599 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
3600
3601 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
3602 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3603
3604 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3605 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
3606
3607 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3608 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
3609
3610 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3611 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
3612 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3613 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
3614
3615# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3616 if (VMX_IS_64BIT_HOST_MODE())
3617 {
3618 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
3619 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
3620 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3621 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3622 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3623 }
3624# endif
3625#endif /* VBOX_STRICT */
3626 }
3627 break;
3628 }
3629
3630 default:
3631 /* impossible */
3632 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
3633 break;
3634 }
3635}
3636
3637#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3638/**
3639 * Prepares for and executes VMLAUNCH (64 bits guest mode)
3640 *
3641 * @returns VBox status code
3642 * @param fResume vmlauch/vmresume
3643 * @param pCtx Guest context
3644 * @param pCache VMCS cache
3645 * @param pVM The VM to operate on.
3646 * @param pVCpu The VMCPU to operate on.
3647 */
3648DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
3649{
3650 uint32_t aParam[6];
3651 PHWACCM_CPUINFO pCpu;
3652 RTHCPHYS pPageCpuPhys;
3653 int rc;
3654
3655 pCpu = HWACCMR0GetCurrentCpu();
3656 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3657
3658#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3659 pCache->uPos = 1;
3660 pCache->interPD = PGMGetInterPaeCR3(pVM);
3661 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
3662#endif
3663
3664#ifdef DEBUG
3665 pCache->TestIn.pPageCpuPhys = 0;
3666 pCache->TestIn.pVMCSPhys = 0;
3667 pCache->TestIn.pCache = 0;
3668 pCache->TestOut.pVMCSPhys = 0;
3669 pCache->TestOut.pCache = 0;
3670 pCache->TestOut.pCtx = 0;
3671 pCache->TestOut.eflags = 0;
3672#endif
3673
3674 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
3675 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
3676 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
3677 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
3678 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
3679 aParam[5] = 0;
3680
3681#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3682 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
3683 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
3684#endif
3685 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
3686
3687#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3688 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
3689 Assert(pCtx->dr[4] == 10);
3690 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
3691#endif
3692
3693#ifdef DEBUG
3694 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
3695 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
3696 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
3697 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
3698 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
3699 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
3700 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
3701#endif
3702 return rc;
3703}
3704
3705/**
3706 * Executes the specified handler in 64 mode
3707 *
3708 * @returns VBox status code.
3709 * @param pVM The VM to operate on.
3710 * @param pVCpu The VMCPU to operate on.
3711 * @param pCtx Guest context
3712 * @param pfnHandler RC handler
3713 * @param cbParam Number of parameters
3714 * @param paParam Array of 32 bits parameters
3715 */
3716VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
3717{
3718 int rc, rc2;
3719 PHWACCM_CPUINFO pCpu;
3720 RTHCPHYS pPageCpuPhys;
3721
3722 /* @todo This code is not guest SMP safe (hyper context) */
3723 AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
3724 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
3725 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
3726 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
3727
3728#ifdef VBOX_STRICT
3729 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
3730 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
3731
3732 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
3733 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
3734#endif
3735
3736 pCpu = HWACCMR0GetCurrentCpu();
3737 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3738
3739 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3740 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3741
3742 /* Leave VMX Root Mode. */
3743 VMXDisable();
3744
3745 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3746
3747 CPUMSetHyperESP(pVM, VMMGetStackRC(pVM));
3748 CPUMSetHyperEIP(pVM, pfnHandler);
3749 for (int i=(int)cbParam-1;i>=0;i--)
3750 CPUMPushHyper(pVM, paParam[i]);
3751
3752 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3753 /* Call switcher. */
3754 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
3755 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3756
3757 /* Make sure the VMX instructions don't cause #UD faults. */
3758 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
3759
3760 /* Enter VMX Root Mode */
3761 rc2 = VMXEnable(pPageCpuPhys);
3762 if (RT_FAILURE(rc2))
3763 {
3764 if (pVM)
3765 VMXR0CheckError(pVM, pVCpu, rc2);
3766 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3767 return VERR_VMX_VMXON_FAILED;
3768 }
3769
3770 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3771 AssertRCReturn(rc2, rc2);
3772#ifdef RT_OS_WINDOWS
3773 Assert(ASMGetFlags() & X86_EFL_IF);
3774#else
3775 Assert(!(ASMGetFlags() & X86_EFL_IF));
3776#endif
3777 return rc;
3778}
3779
3780#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
3781
3782
3783#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3784/**
3785 * Executes VMWRITE
3786 *
3787 * @returns VBox status code
3788 * @param pVCpu The VMCPU to operate on.
3789 * @param idxField VMCS index
3790 * @param u64Val 16, 32 or 64 bits value
3791 */
3792VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
3793{
3794 int rc;
3795
3796 switch (idxField)
3797 {
3798 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
3799 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
3800 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
3801 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
3802 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
3803 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
3804 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
3805 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
3806 case VMX_VMCS_GUEST_LINK_PTR_FULL:
3807 case VMX_VMCS_GUEST_PDPTR0_FULL:
3808 case VMX_VMCS_GUEST_PDPTR1_FULL:
3809 case VMX_VMCS_GUEST_PDPTR2_FULL:
3810 case VMX_VMCS_GUEST_PDPTR3_FULL:
3811 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
3812 case VMX_VMCS_GUEST_EFER_FULL:
3813 case VMX_VMCS_CTRL_EPTP_FULL:
3814 /* These fields consist of two parts, which are both writable in 32 bits mode. */
3815 rc = VMXWriteVMCS32(idxField, u64Val);
3816 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
3817 AssertRC(rc);
3818 return rc;
3819
3820 case VMX_VMCS64_GUEST_LDTR_BASE:
3821 case VMX_VMCS64_GUEST_TR_BASE:
3822 case VMX_VMCS64_GUEST_GDTR_BASE:
3823 case VMX_VMCS64_GUEST_IDTR_BASE:
3824 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3825 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3826 case VMX_VMCS64_GUEST_CR0:
3827 case VMX_VMCS64_GUEST_CR4:
3828 case VMX_VMCS64_GUEST_CR3:
3829 case VMX_VMCS64_GUEST_DR7:
3830 case VMX_VMCS64_GUEST_RIP:
3831 case VMX_VMCS64_GUEST_RSP:
3832 case VMX_VMCS64_GUEST_CS_BASE:
3833 case VMX_VMCS64_GUEST_DS_BASE:
3834 case VMX_VMCS64_GUEST_ES_BASE:
3835 case VMX_VMCS64_GUEST_FS_BASE:
3836 case VMX_VMCS64_GUEST_GS_BASE:
3837 case VMX_VMCS64_GUEST_SS_BASE:
3838 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
3839 if (u64Val >> 32ULL)
3840 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
3841 else
3842 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
3843
3844 return rc;
3845
3846 default:
3847 AssertMsgFailed(("Unexpected field %x\n", idxField));
3848 return VERR_INVALID_PARAMETER;
3849 }
3850}
3851
3852/**
3853 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
3854 *
3855 * @param pVCpu The VMCPU to operate on.
3856 * @param idxField VMCS field
3857 * @param u64Val Value
3858 */
3859VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
3860{
3861 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
3862
3863 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
3864
3865 /* Make sure there are no duplicates. */
3866 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
3867 {
3868 if (pCache->Write.aField[i] == idxField)
3869 {
3870 pCache->Write.aFieldVal[i] = u64Val;
3871 return VINF_SUCCESS;
3872 }
3873 }
3874
3875 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
3876 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
3877 pCache->Write.cValidEntries++;
3878 return VINF_SUCCESS;
3879}
3880
3881#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3882
3883#ifdef VBOX_STRICT
3884static bool vmxR0IsValidReadField(uint32_t idxField)
3885{
3886 switch(idxField)
3887 {
3888 case VMX_VMCS64_GUEST_RIP:
3889 case VMX_VMCS64_GUEST_RSP:
3890 case VMX_VMCS_GUEST_RFLAGS:
3891 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
3892 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
3893 case VMX_VMCS64_GUEST_CR0:
3894 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
3895 case VMX_VMCS64_GUEST_CR4:
3896 case VMX_VMCS64_GUEST_DR7:
3897 case VMX_VMCS32_GUEST_SYSENTER_CS:
3898 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3899 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3900 case VMX_VMCS32_GUEST_GDTR_LIMIT:
3901 case VMX_VMCS64_GUEST_GDTR_BASE:
3902 case VMX_VMCS32_GUEST_IDTR_LIMIT:
3903 case VMX_VMCS64_GUEST_IDTR_BASE:
3904 case VMX_VMCS16_GUEST_FIELD_CS:
3905 case VMX_VMCS32_GUEST_CS_LIMIT:
3906 case VMX_VMCS64_GUEST_CS_BASE:
3907 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
3908 case VMX_VMCS16_GUEST_FIELD_DS:
3909 case VMX_VMCS32_GUEST_DS_LIMIT:
3910 case VMX_VMCS64_GUEST_DS_BASE:
3911 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
3912 case VMX_VMCS16_GUEST_FIELD_ES:
3913 case VMX_VMCS32_GUEST_ES_LIMIT:
3914 case VMX_VMCS64_GUEST_ES_BASE:
3915 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
3916 case VMX_VMCS16_GUEST_FIELD_FS:
3917 case VMX_VMCS32_GUEST_FS_LIMIT:
3918 case VMX_VMCS64_GUEST_FS_BASE:
3919 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
3920 case VMX_VMCS16_GUEST_FIELD_GS:
3921 case VMX_VMCS32_GUEST_GS_LIMIT:
3922 case VMX_VMCS64_GUEST_GS_BASE:
3923 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
3924 case VMX_VMCS16_GUEST_FIELD_SS:
3925 case VMX_VMCS32_GUEST_SS_LIMIT:
3926 case VMX_VMCS64_GUEST_SS_BASE:
3927 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
3928 case VMX_VMCS16_GUEST_FIELD_LDTR:
3929 case VMX_VMCS32_GUEST_LDTR_LIMIT:
3930 case VMX_VMCS64_GUEST_LDTR_BASE:
3931 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
3932 case VMX_VMCS16_GUEST_FIELD_TR:
3933 case VMX_VMCS32_GUEST_TR_LIMIT:
3934 case VMX_VMCS64_GUEST_TR_BASE:
3935 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
3936 case VMX_VMCS32_RO_EXIT_REASON:
3937 case VMX_VMCS32_RO_VM_INSTR_ERROR:
3938 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
3939 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
3940 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
3941 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
3942 case VMX_VMCS_RO_EXIT_QUALIFICATION:
3943 case VMX_VMCS32_RO_IDT_INFO:
3944 case VMX_VMCS32_RO_IDT_ERRCODE:
3945 case VMX_VMCS64_GUEST_CR3:
3946 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
3947 return true;
3948 }
3949 return false;
3950}
3951
3952static bool vmxR0IsValidWriteField(uint32_t idxField)
3953{
3954 switch(idxField)
3955 {
3956 case VMX_VMCS64_GUEST_LDTR_BASE:
3957 case VMX_VMCS64_GUEST_TR_BASE:
3958 case VMX_VMCS64_GUEST_GDTR_BASE:
3959 case VMX_VMCS64_GUEST_IDTR_BASE:
3960 case VMX_VMCS64_GUEST_SYSENTER_EIP:
3961 case VMX_VMCS64_GUEST_SYSENTER_ESP:
3962 case VMX_VMCS64_GUEST_CR0:
3963 case VMX_VMCS64_GUEST_CR4:
3964 case VMX_VMCS64_GUEST_CR3:
3965 case VMX_VMCS64_GUEST_DR7:
3966 case VMX_VMCS64_GUEST_RIP:
3967 case VMX_VMCS64_GUEST_RSP:
3968 case VMX_VMCS64_GUEST_CS_BASE:
3969 case VMX_VMCS64_GUEST_DS_BASE:
3970 case VMX_VMCS64_GUEST_ES_BASE:
3971 case VMX_VMCS64_GUEST_FS_BASE:
3972 case VMX_VMCS64_GUEST_GS_BASE:
3973 case VMX_VMCS64_GUEST_SS_BASE:
3974 return true;
3975 }
3976 return false;
3977}
3978
3979#endif
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