VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 19460

Last change on this file since 19460 was 19460, checked in by vboxsync, 16 years ago

HWACCM: play safe and only change the state to VMCPUSTATE_STARTED if it's VMCPUSTATE_STARTED_EXEC.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 166.3 KB
Line 
1/* $Id: HWVMXR0.cpp 19460 2009-05-06 19:46:33Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/param.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/string.h>
42#include "HWVMXR0.h"
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47#if defined(RT_ARCH_AMD64)
48# define VMX_IS_64BIT_HOST_MODE() (true)
49#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
50# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
51#else
52# define VMX_IS_64BIT_HOST_MODE() (false)
53#endif
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58/* IO operation lookup arrays. */
59static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
60static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
61
62#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
63/** See HWACCMR0A.asm. */
64extern "C" uint32_t g_fVMXIs64bitHost;
65#endif
66
67/*******************************************************************************
68* Local Functions *
69*******************************************************************************/
70static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
71static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
72static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
73static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
74static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
75static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
76static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
77#ifdef VBOX_STRICT
78static bool vmxR0IsValidReadField(uint32_t idxField);
79static bool vmxR0IsValidWriteField(uint32_t idxField);
80#endif
81
82static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
83{
84 if (rc == VERR_VMX_GENERIC)
85 {
86 RTCCUINTREG instrError;
87
88 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
89 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
90 }
91 pVM->hwaccm.s.lLastError = rc;
92}
93
94/**
95 * Sets up and activates VT-x on the current CPU
96 *
97 * @returns VBox status code.
98 * @param pCpu CPU info struct
99 * @param pVM The VM to operate on. (can be NULL after a resume!!)
100 * @param pvPageCpu Pointer to the global cpu page
101 * @param pPageCpuPhys Physical address of the global cpu page
102 */
103VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
104{
105 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
106 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
107
108#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
109 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
110#endif
111 if (pVM)
112 {
113 /* Set revision dword at the beginning of the VMXON structure. */
114 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
115 }
116
117 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
118 * (which can have very bad consequences!!!)
119 */
120
121 /* Make sure the VMX instructions don't cause #UD faults. */
122 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
123
124 /* Enter VMX Root Mode */
125 int rc = VMXEnable(pPageCpuPhys);
126 if (RT_FAILURE(rc))
127 {
128 if (pVM)
129 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
130 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
131 return VERR_VMX_VMXON_FAILED;
132 }
133 return VINF_SUCCESS;
134}
135
136/**
137 * Deactivates VT-x on the current CPU
138 *
139 * @returns VBox status code.
140 * @param pCpu CPU info struct
141 * @param pvPageCpu Pointer to the global cpu page
142 * @param pPageCpuPhys Physical address of the global cpu page
143 */
144VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
145{
146 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
147 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
148
149 /* Leave VMX Root Mode. */
150 VMXDisable();
151
152 /* And clear the X86_CR4_VMXE bit */
153 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
154
155#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
156 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
157#endif
158 return VINF_SUCCESS;
159}
160
161/**
162 * Does Ring-0 per VM VT-x init.
163 *
164 * @returns VBox status code.
165 * @param pVM The VM to operate on.
166 */
167VMMR0DECL(int) VMXR0InitVM(PVM pVM)
168{
169 int rc;
170
171#ifdef LOG_ENABLED
172 SUPR0Printf("VMXR0InitVM %x\n", pVM);
173#endif
174
175 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
176
177 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
178 {
179 /* Allocate one page for the virtual APIC mmio cache. */
180 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
181 AssertRC(rc);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
186 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
187 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
188 }
189 else
190 {
191 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
192 pVM->hwaccm.s.vmx.pAPIC = 0;
193 pVM->hwaccm.s.vmx.pAPICPhys = 0;
194 }
195
196 /* Allocate the MSR bitmap if this feature is supported. */
197 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
198 {
199 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
200 AssertRC(rc);
201 if (RT_FAILURE(rc))
202 return rc;
203
204 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
205 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
206 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
207 }
208
209#ifdef VBOX_WITH_CRASHDUMP_MAGIC
210 {
211 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
212 AssertRC(rc);
213 if (RT_FAILURE(rc))
214 return rc;
215
216 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
217 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
218
219 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
220 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
221 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
222 }
223#endif
224
225 /* Allocate VMCBs for all guest CPUs. */
226 for (unsigned i=0;i<pVM->cCPUs;i++)
227 {
228 PVMCPU pVCpu = &pVM->aCpus[i];
229
230 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
231
232 /* Allocate one page for the VM control structure (VMCS). */
233 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
234 AssertRC(rc);
235 if (RT_FAILURE(rc))
236 return rc;
237
238 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
239 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
240 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
241
242 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
243 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
244
245 /* Current guest paging mode. */
246 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
247
248#ifdef LOG_ENABLED
249 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
250#endif
251 }
252
253 return VINF_SUCCESS;
254}
255
256/**
257 * Does Ring-0 per VM VT-x termination.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262VMMR0DECL(int) VMXR0TermVM(PVM pVM)
263{
264 for (unsigned i=0;i<pVM->cCPUs;i++)
265 {
266 if (pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
267 {
268 RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, false);
269 pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
270 pVM->aCpus[i].hwaccm.s.vmx.pVMCS = 0;
271 pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys = 0;
272 }
273 }
274 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
275 {
276 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
277 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
278 pVM->hwaccm.s.vmx.pAPIC = 0;
279 pVM->hwaccm.s.vmx.pAPICPhys = 0;
280 }
281 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
282 {
283 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
284 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
285 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
286 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
287 }
288#ifdef VBOX_WITH_CRASHDUMP_MAGIC
289 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
290 {
291 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
292 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
293 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
294 pVM->hwaccm.s.vmx.pScratch = 0;
295 pVM->hwaccm.s.vmx.pScratchPhys = 0;
296 }
297#endif
298 return VINF_SUCCESS;
299}
300
301/**
302 * Sets up VT-x for the specified VM
303 *
304 * @returns VBox status code.
305 * @param pVM The VM to operate on.
306 */
307VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
308{
309 int rc = VINF_SUCCESS;
310 uint32_t val;
311
312 AssertReturn(pVM, VERR_INVALID_PARAMETER);
313
314 for (unsigned i=0;i<pVM->cCPUs;i++)
315 {
316 PVMCPU pVCpu = &pVM->aCpus[i];
317
318 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
319
320 /* Set revision dword at the beginning of the VMCS structure. */
321 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
322
323 /* Clear VM Control Structure. */
324 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
325 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
326 if (RT_FAILURE(rc))
327 goto vmx_end;
328
329 /* Activate the VM Control Structure. */
330 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
331 if (RT_FAILURE(rc))
332 goto vmx_end;
333
334 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
335 * Set required bits to one and zero according to the MSR capabilities.
336 */
337 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
338 /* External and non-maskable interrupts cause VM-exits. */
339 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
340 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
341
342 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
343 AssertRC(rc);
344
345 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
346 * Set required bits to one and zero according to the MSR capabilities.
347 */
348 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
349 /* Program which event cause VM-exits and which features we want to use. */
350 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
351 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
352 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
353 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
354 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
355 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
356
357 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
358 if (!pVM->hwaccm.s.fNestedPaging)
359 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
360 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
361 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
362
363 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
364 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
365 {
366 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
367 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
368 Assert(pVM->hwaccm.s.vmx.pAPIC);
369 }
370 else
371 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
372 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
373
374#ifdef VBOX_WITH_VTX_MSR_BITMAPS
375 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
376 {
377 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
378 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
379 }
380#endif
381
382 /* We will use the secondary control if it's present. */
383 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
384
385 /* Mask away the bits that the CPU doesn't support */
386 /** @todo make sure they don't conflict with the above requirements. */
387 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
388 pVCpu->hwaccm.s.vmx.proc_ctls = val;
389
390 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
391 AssertRC(rc);
392
393 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
394 {
395 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
396 * Set required bits to one and zero according to the MSR capabilities.
397 */
398 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
399 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
400
401#ifdef HWACCM_VTX_WITH_EPT
402 if (pVM->hwaccm.s.fNestedPaging)
403 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
404#endif /* HWACCM_VTX_WITH_EPT */
405#ifdef HWACCM_VTX_WITH_VPID
406 else
407 if (pVM->hwaccm.s.vmx.fVPID)
408 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
409#endif /* HWACCM_VTX_WITH_VPID */
410
411 /* Mask away the bits that the CPU doesn't support */
412 /** @todo make sure they don't conflict with the above requirements. */
413 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
414
415 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
416 AssertRC(rc);
417 }
418
419 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
420 * Set required bits to one and zero according to the MSR capabilities.
421 */
422 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
423 AssertRC(rc);
424
425 /* Forward all exception except #NM & #PF to the guest.
426 * We always need to check pagefaults since our shadow page table can be out of sync.
427 * And we always lazily sync the FPU & XMM state.
428 */
429
430 /** @todo Possible optimization:
431 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
432 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
433 * registers ourselves of course.
434 *
435 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
436 */
437
438 /* Don't filter page faults; all of them should cause a switch. */
439 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
441 AssertRC(rc);
442
443 /* Init TSC offset to zero. */
444 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
445 AssertRC(rc);
446
447 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
448 AssertRC(rc);
449
450 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
451 AssertRC(rc);
452
453 /* Set the MSR bitmap address. */
454 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
455 {
456 /* Optional */
457 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
458 AssertRC(rc);
459 }
460
461 /* Clear MSR controls. */
462 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
463 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
464 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
465 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
467 AssertRC(rc);
468
469 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
470 {
471 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
472 /* Optional */
473 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
474 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
475 AssertRC(rc);
476 }
477
478 /* Set link pointer to -1. Not currently used. */
479 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
480 AssertRC(rc);
481
482 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
483 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
484 AssertRC(rc);
485
486 /* Configure the VMCS read cache. */
487 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
488
489 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
490 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
491 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
492 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
493 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
494 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
495 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
496 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
497 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
498 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
499 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
500 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
501 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
502 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
503 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
504 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
505
506 VMX_SETUP_SELREG(ES, pCache);
507 VMX_SETUP_SELREG(SS, pCache);
508 VMX_SETUP_SELREG(CS, pCache);
509 VMX_SETUP_SELREG(DS, pCache);
510 VMX_SETUP_SELREG(FS, pCache);
511 VMX_SETUP_SELREG(GS, pCache);
512 VMX_SETUP_SELREG(LDTR, pCache);
513 VMX_SETUP_SELREG(TR, pCache);
514
515 /* Status code VMCS reads. */
516 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
517 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
518 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
525
526 if (pVM->hwaccm.s.fNestedPaging)
527 {
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
530 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
531 }
532 else
533 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
534 } /* for each VMCPU */
535
536 /* Choose the right TLB setup function. */
537 if (pVM->hwaccm.s.fNestedPaging)
538 {
539 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
540
541 /* Default values for flushing. */
542 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
543 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
544
545 /* If the capabilities specify we can do more, then make use of it. */
546 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
547 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
548 else
549 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
550 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
551
552 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
553 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
554 }
555#ifdef HWACCM_VTX_WITH_VPID
556 else
557 if (pVM->hwaccm.s.vmx.fVPID)
558 {
559 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
560
561 /* Default values for flushing. */
562 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
563 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
564
565 /* If the capabilities specify we can do more, then make use of it. */
566 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
567 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
568 else
569 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
570 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
571
572 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
574 }
575#endif /* HWACCM_VTX_WITH_VPID */
576 else
577 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
578
579vmx_end:
580 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
581 return rc;
582}
583
584
585/**
586 * Injects an event (trap or external interrupt)
587 *
588 * @returns VBox status code.
589 * @param pVM The VM to operate on.
590 * @param pVCpu The VMCPU to operate on.
591 * @param pCtx CPU Context
592 * @param intInfo VMX interrupt info
593 * @param cbInstr Opcode length of faulting instruction
594 * @param errCode Error code (optional)
595 */
596static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
597{
598 int rc;
599 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
600
601#ifdef VBOX_STRICT
602 if (iGate == 0xE)
603 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
604 else
605 if (iGate < 0x20)
606 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
607 else
608 {
609 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
610 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
611 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
612 }
613#endif
614
615#ifdef HWACCM_VMX_EMULATE_REALMODE
616 if (CPUMIsGuestInRealModeEx(pCtx))
617 {
618 RTGCPHYS GCPhysHandler;
619 uint16_t offset, ip;
620 RTSEL sel;
621
622 /* Injecting events doesn't work right with real mode emulation.
623 * (#GP if we try to inject external hardware interrupts)
624 * Inject the interrupt or trap directly instead.
625 *
626 * ASSUMES no access handlers for the bits we read or write below (should be safe).
627 */
628 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
629
630 /* Check if the interrupt handler is present. */
631 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
632 {
633 Log(("IDT cbIdt violation\n"));
634 if (iGate != X86_XCPT_DF)
635 {
636 RTGCUINTPTR intInfo;
637
638 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
639 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
640 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
641 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
642
643 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
644 }
645 Log(("Triple fault -> reset the VM!\n"));
646 return VINF_EM_RESET;
647 }
648 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
649 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
650 || iGate == 4)
651 {
652 ip = pCtx->ip + cbInstr;
653 }
654 else
655 ip = pCtx->ip;
656
657 /* Read the selector:offset pair of the interrupt handler. */
658 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
659 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
660 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
661
662 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
663
664 /* Construct the stack frame. */
665 /** @todo should check stack limit. */
666 pCtx->sp -= 2;
667 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
668 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
669 pCtx->sp -= 2;
670 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
671 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
672 pCtx->sp -= 2;
673 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
674 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
675
676 /* Update the CPU state for executing the handler. */
677 pCtx->rip = offset;
678 pCtx->cs = sel;
679 pCtx->csHid.u64Base = sel << 4;
680 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
681
682 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
683 return VINF_SUCCESS;
684 }
685#endif /* HWACCM_VMX_EMULATE_REALMODE */
686
687 /* Set event injection state. */
688 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
689
690 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
691 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
692
693 AssertRC(rc);
694 return rc;
695}
696
697
698/**
699 * Checks for pending guest interrupts and injects them
700 *
701 * @returns VBox status code.
702 * @param pVM The VM to operate on.
703 * @param pVCpu The VMCPU to operate on.
704 * @param pCtx CPU Context
705 */
706static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
707{
708 int rc;
709
710 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
711 if (pVCpu->hwaccm.s.Event.fPending)
712 {
713 Log(("Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
714 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
715 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
716 AssertRC(rc);
717
718 pVCpu->hwaccm.s.Event.fPending = false;
719 return VINF_SUCCESS;
720 }
721
722 if (pVM->hwaccm.s.fInjectNMI)
723 {
724 RTGCUINTPTR intInfo;
725
726 intInfo = X86_XCPT_NMI;
727 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
728 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
729
730 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
731 AssertRC(rc);
732
733 pVM->hwaccm.s.fInjectNMI = false;
734 return VINF_SUCCESS;
735 }
736
737 /* When external interrupts are pending, we should exit the VM when IF is set. */
738 if ( !TRPMHasTrap(pVCpu)
739 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
740 {
741 if (!(pCtx->eflags.u32 & X86_EFL_IF))
742 {
743 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
744 {
745 LogFlow(("Enable irq window exit!\n"));
746 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
747 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
748 AssertRC(rc);
749 }
750 /* else nothing to do but wait */
751 }
752 else
753 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
754 {
755 uint8_t u8Interrupt;
756
757 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
758 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
759 if (RT_SUCCESS(rc))
760 {
761 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
762 AssertRC(rc);
763 }
764 else
765 {
766 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
767 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
768 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
769 /* Just continue */
770 }
771 }
772 else
773 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
774 }
775
776#ifdef VBOX_STRICT
777 if (TRPMHasTrap(pVCpu))
778 {
779 uint8_t u8Vector;
780 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
781 AssertRC(rc);
782 }
783#endif
784
785 if ( pCtx->eflags.u32 & X86_EFL_IF
786 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
787 && TRPMHasTrap(pVCpu)
788 )
789 {
790 uint8_t u8Vector;
791 int rc;
792 TRPMEVENT enmType;
793 RTGCUINTPTR intInfo;
794 RTGCUINT errCode;
795
796 /* If a new event is pending, then dispatch it now. */
797 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
798 AssertRC(rc);
799 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
800 Assert(enmType != TRPM_SOFTWARE_INT);
801
802 /* Clear the pending trap. */
803 rc = TRPMResetTrap(pVCpu);
804 AssertRC(rc);
805
806 intInfo = u8Vector;
807 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
808
809 if (enmType == TRPM_TRAP)
810 {
811 switch (u8Vector) {
812 case 8:
813 case 10:
814 case 11:
815 case 12:
816 case 13:
817 case 14:
818 case 17:
819 /* Valid error codes. */
820 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
821 break;
822 default:
823 break;
824 }
825 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
826 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
827 else
828 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
829 }
830 else
831 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
832
833 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
834 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
835 AssertRC(rc);
836 } /* if (interrupts can be dispatched) */
837
838 return VINF_SUCCESS;
839}
840
841/**
842 * Save the host state
843 *
844 * @returns VBox status code.
845 * @param pVM The VM to operate on.
846 * @param pVCpu The VMCPU to operate on.
847 */
848VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
849{
850 int rc = VINF_SUCCESS;
851
852 /*
853 * Host CPU Context
854 */
855 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
856 {
857 RTIDTR idtr;
858 RTGDTR gdtr;
859 RTSEL SelTR;
860 PX86DESCHC pDesc;
861 uintptr_t trBase;
862 RTSEL cs;
863 RTSEL ss;
864 uint64_t cr3;
865
866 /* Control registers */
867 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
868#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
869 if (VMX_IS_64BIT_HOST_MODE())
870 {
871 cr3 = hwaccmR0Get64bitCR3();
872 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
873 }
874 else
875#endif
876 {
877 cr3 = ASMGetCR3();
878 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
879 }
880 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
881 AssertRC(rc);
882 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
883 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
884 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
885
886 /* Selector registers. */
887#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
888 if (VMX_IS_64BIT_HOST_MODE())
889 {
890 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
891 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
892 }
893 else
894 {
895 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
896 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
897 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
898 }
899#else
900 cs = ASMGetCS();
901 ss = ASMGetSS();
902#endif
903 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
904 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
905 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
906 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
907 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
908 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
909#if HC_ARCH_BITS == 32
910 if (!VMX_IS_64BIT_HOST_MODE())
911 {
912 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
913 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
914 }
915#endif
916 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
917 SelTR = ASMGetTR();
918 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
919 AssertRC(rc);
920 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
921 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
922 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
923 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
924 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
925 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
926 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
927
928 /* GDTR & IDTR */
929#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
930 if (VMX_IS_64BIT_HOST_MODE())
931 {
932 X86XDTR64 gdtr64, idtr64;
933 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
934 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
935 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
936 AssertRC(rc);
937 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
938 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
939 gdtr.cbGdt = gdtr64.cb;
940 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
941 }
942 else
943#endif
944 {
945 ASMGetGDTR(&gdtr);
946 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
947 ASMGetIDTR(&idtr);
948 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
949 AssertRC(rc);
950 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
951 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
952 }
953
954
955 /* Save the base address of the TR selector. */
956 if (SelTR > gdtr.cbGdt)
957 {
958 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
959 return VERR_VMX_INVALID_HOST_STATE;
960 }
961
962#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
963 if (VMX_IS_64BIT_HOST_MODE())
964 {
965 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
966 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
967 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
968 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
969 AssertRC(rc);
970 }
971 else
972#endif
973 {
974 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
975#if HC_ARCH_BITS == 64
976 trBase = X86DESC64_BASE(*pDesc);
977#else
978 trBase = X86DESC_BASE(*pDesc);
979#endif
980 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
981 AssertRC(rc);
982 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
983 }
984
985 /* FS and GS base. */
986#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
987 if (VMX_IS_64BIT_HOST_MODE())
988 {
989 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
990 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
991 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
992 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
993 }
994#endif
995 AssertRC(rc);
996
997 /* Sysenter MSRs. */
998 /** @todo expensive!! */
999 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1000 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1001#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1002 if (VMX_IS_64BIT_HOST_MODE())
1003 {
1004 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1005 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1006 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1007 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1008 }
1009 else
1010 {
1011 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1012 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1013 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1014 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1015 }
1016#elif HC_ARCH_BITS == 32
1017 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1018 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1019 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1020 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1021#else
1022 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1023 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1024 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1025 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1026#endif
1027 AssertRC(rc);
1028
1029#if 0 /* @todo deal with 32/64 */
1030 /* Restore the host EFER - on CPUs that support it. */
1031 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1032 {
1033 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1034 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1035 AssertRC(rc);
1036 }
1037#endif
1038 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1039 }
1040 return rc;
1041}
1042
1043/**
1044 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1045 *
1046 * @param pVM The VM to operate on.
1047 * @param pVCpu The VMCPU to operate on.
1048 * @param pCtx Guest context
1049 */
1050static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1051{
1052 if (CPUMIsGuestInPAEModeEx(pCtx))
1053 {
1054 X86PDPE Pdpe;
1055
1056 for (unsigned i=0;i<4;i++)
1057 {
1058 Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1059 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1060 AssertRC(rc);
1061 }
1062 }
1063}
1064
1065/**
1066 * Update the exception bitmap according to the current CPU state
1067 *
1068 * @param pVM The VM to operate on.
1069 * @param pVCpu The VMCPU to operate on.
1070 * @param pCtx Guest context
1071 */
1072static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1073{
1074 uint32_t u32TrapMask;
1075 Assert(pCtx);
1076
1077 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1078#ifndef DEBUG
1079 if (pVM->hwaccm.s.fNestedPaging)
1080 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1081#endif
1082
1083 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1084 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1085 && !(pCtx->cr0 & X86_CR0_NE)
1086 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1087 {
1088 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1089 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1090 }
1091
1092#ifdef DEBUG /* till after branching, enable it by default then. */
1093 /* Intercept X86_XCPT_DB if stepping is enabled */
1094 if (DBGFIsStepping(pVCpu))
1095 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1096 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1097 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1098#endif
1099
1100#ifdef VBOX_STRICT
1101 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1102#endif
1103
1104# ifdef HWACCM_VMX_EMULATE_REALMODE
1105 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1106 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1107 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1108# endif /* HWACCM_VMX_EMULATE_REALMODE */
1109
1110 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1111 AssertRC(rc);
1112}
1113
1114/**
1115 * Loads the guest state
1116 *
1117 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1118 *
1119 * @returns VBox status code.
1120 * @param pVM The VM to operate on.
1121 * @param pVCpu The VMCPU to operate on.
1122 * @param pCtx Guest context
1123 */
1124VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1125{
1126 int rc = VINF_SUCCESS;
1127 RTGCUINTPTR val;
1128 X86EFLAGS eflags;
1129
1130 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1131 * Set required bits to one and zero according to the MSR capabilities.
1132 */
1133 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1134 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1135 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1136#if 0 /* @todo deal with 32/64 */
1137 /* Required for the EFER write below, not supported on all CPUs. */
1138 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1139#endif
1140 /* 64 bits guest mode? */
1141 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1142 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1143 /* else Must be zero when AMD64 is not available. */
1144
1145 /* Mask away the bits that the CPU doesn't support */
1146 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1147 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1148 AssertRC(rc);
1149
1150 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1151 * Set required bits to one and zero according to the MSR capabilities.
1152 */
1153 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1154
1155 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1156#if 0 /* @todo deal with 32/64 */
1157 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1158#else
1159 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1160#endif
1161
1162#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1163 if (VMX_IS_64BIT_HOST_MODE())
1164 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1165 /* else: Must be zero when AMD64 is not available. */
1166#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1167 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1168 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1169 else
1170 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1171#endif
1172 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1173 /* Don't acknowledge external interrupts on VM-exit. */
1174 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1175 AssertRC(rc);
1176
1177 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1178 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1179 {
1180#ifdef HWACCM_VMX_EMULATE_REALMODE
1181 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1182 {
1183 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1184 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1185 {
1186 /* Correct weird requirements for switching to protected mode. */
1187 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1188 && enmGuestMode >= PGMMODE_PROTECTED)
1189 {
1190 /* Flush the recompiler code cache as it's not unlikely
1191 * the guest will rewrite code it will later execute in real
1192 * mode (OpenBSD 4.0 is one such example)
1193 */
1194 REMFlushTBs(pVM);
1195
1196 /* DPL of all hidden selector registers must match the current CPL (0). */
1197 pCtx->csHid.Attr.n.u2Dpl = 0;
1198 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1199
1200 pCtx->dsHid.Attr.n.u2Dpl = 0;
1201 pCtx->esHid.Attr.n.u2Dpl = 0;
1202 pCtx->fsHid.Attr.n.u2Dpl = 0;
1203 pCtx->gsHid.Attr.n.u2Dpl = 0;
1204 pCtx->ssHid.Attr.n.u2Dpl = 0;
1205
1206 /* The limit must correspond to the granularity bit. */
1207 if (!pCtx->csHid.Attr.n.u1Granularity)
1208 pCtx->csHid.u32Limit &= 0xffff;
1209 if (!pCtx->dsHid.Attr.n.u1Granularity)
1210 pCtx->dsHid.u32Limit &= 0xffff;
1211 if (!pCtx->esHid.Attr.n.u1Granularity)
1212 pCtx->esHid.u32Limit &= 0xffff;
1213 if (!pCtx->fsHid.Attr.n.u1Granularity)
1214 pCtx->fsHid.u32Limit &= 0xffff;
1215 if (!pCtx->gsHid.Attr.n.u1Granularity)
1216 pCtx->gsHid.u32Limit &= 0xffff;
1217 if (!pCtx->ssHid.Attr.n.u1Granularity)
1218 pCtx->ssHid.u32Limit &= 0xffff;
1219 }
1220 else
1221 /* Switching from protected mode to real mode. */
1222 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1223 && enmGuestMode == PGMMODE_REAL)
1224 {
1225 /* The limit must also be set to 0xffff. */
1226 pCtx->csHid.u32Limit = 0xffff;
1227 pCtx->dsHid.u32Limit = 0xffff;
1228 pCtx->esHid.u32Limit = 0xffff;
1229 pCtx->fsHid.u32Limit = 0xffff;
1230 pCtx->gsHid.u32Limit = 0xffff;
1231 pCtx->ssHid.u32Limit = 0xffff;
1232
1233 Assert(pCtx->csHid.u64Base <= 0xfffff);
1234 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1235 Assert(pCtx->esHid.u64Base <= 0xfffff);
1236 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1237 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1238 }
1239 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1240 }
1241 else
1242 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1243 if ( CPUMIsGuestInRealModeEx(pCtx)
1244 && pCtx->csHid.u64Base == 0xffff0000)
1245 {
1246 pCtx->csHid.u64Base = 0xf0000;
1247 pCtx->cs = 0xf000;
1248 }
1249 }
1250#endif /* HWACCM_VMX_EMULATE_REALMODE */
1251
1252 VMX_WRITE_SELREG(ES, es);
1253 AssertRC(rc);
1254
1255 VMX_WRITE_SELREG(CS, cs);
1256 AssertRC(rc);
1257
1258 VMX_WRITE_SELREG(SS, ss);
1259 AssertRC(rc);
1260
1261 VMX_WRITE_SELREG(DS, ds);
1262 AssertRC(rc);
1263
1264 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1265 VMX_WRITE_SELREG(FS, fs);
1266 AssertRC(rc);
1267
1268 VMX_WRITE_SELREG(GS, gs);
1269 AssertRC(rc);
1270 }
1271
1272 /* Guest CPU context: LDTR. */
1273 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1274 {
1275 if (pCtx->ldtr == 0)
1276 {
1277 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1278 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1279 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1280 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1281 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1282 }
1283 else
1284 {
1285 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1286 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1287 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1288 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1289 }
1290 AssertRC(rc);
1291 }
1292 /* Guest CPU context: TR. */
1293 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1294 {
1295#ifdef HWACCM_VMX_EMULATE_REALMODE
1296 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1297 if (CPUMIsGuestInRealModeEx(pCtx))
1298 {
1299 RTGCPHYS GCPhys;
1300
1301 /* We convert it here every time as pci regions could be reconfigured. */
1302 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1303 AssertRC(rc);
1304
1305 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1306 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1307 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1308
1309 X86DESCATTR attr;
1310
1311 attr.u = 0;
1312 attr.n.u1Present = 1;
1313 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1314 val = attr.u;
1315 }
1316 else
1317#endif /* HWACCM_VMX_EMULATE_REALMODE */
1318 {
1319 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1320 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1321 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1322
1323 val = pCtx->trHid.Attr.u;
1324
1325 /* The TSS selector must be busy. */
1326 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1327 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1328 else
1329 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1330 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1331
1332 }
1333 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1334 AssertRC(rc);
1335 }
1336 /* Guest CPU context: GDTR. */
1337 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1338 {
1339 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1340 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1341 AssertRC(rc);
1342 }
1343 /* Guest CPU context: IDTR. */
1344 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1345 {
1346 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1347 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1348 AssertRC(rc);
1349 }
1350
1351 /*
1352 * Sysenter MSRs (unconditional)
1353 */
1354 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1355 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1356 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1357 AssertRC(rc);
1358
1359 /* Control registers */
1360 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1361 {
1362 val = pCtx->cr0;
1363 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1364 Log2(("Guest CR0-shadow %08x\n", val));
1365 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1366 {
1367 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1368 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1369 }
1370 else
1371 {
1372 /** @todo check if we support the old style mess correctly. */
1373 if (!(val & X86_CR0_NE))
1374 Log(("Forcing X86_CR0_NE!!!\n"));
1375
1376 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1377 }
1378 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1379 val |= X86_CR0_PE | X86_CR0_PG;
1380 if (pVM->hwaccm.s.fNestedPaging)
1381 {
1382 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1383 {
1384 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1385 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1386 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1387 }
1388 else
1389 {
1390 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1391 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1392 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1393 }
1394 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1395 AssertRC(rc);
1396 }
1397 else
1398 {
1399 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1400 val |= X86_CR0_WP;
1401 }
1402
1403 /* Always enable caching. */
1404 val &= ~(X86_CR0_CD|X86_CR0_NW);
1405
1406 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1407 Log2(("Guest CR0 %08x\n", val));
1408 /* CR0 flags owned by the host; if the guests attempts to change them, then
1409 * the VM will exit.
1410 */
1411 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1412 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1413 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1414 | X86_CR0_TS
1415 | X86_CR0_ET /* Bit not restored during VM-exit! */
1416 | X86_CR0_CD /* Bit not restored during VM-exit! */
1417 | X86_CR0_NW /* Bit not restored during VM-exit! */
1418 | X86_CR0_NE
1419 | X86_CR0_MP;
1420 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1421
1422 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1423 Log2(("Guest CR0-mask %08x\n", val));
1424 AssertRC(rc);
1425 }
1426 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1427 {
1428 /* CR4 */
1429 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1430 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1431 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1432 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1433
1434 if (!pVM->hwaccm.s.fNestedPaging)
1435 {
1436 switch(pVCpu->hwaccm.s.enmShadowMode)
1437 {
1438 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1439 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1440 case PGMMODE_32_BIT: /* 32-bit paging. */
1441 val &= ~X86_CR4_PAE;
1442 break;
1443
1444 case PGMMODE_PAE: /* PAE paging. */
1445 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1446 /** @todo use normal 32 bits paging */
1447 val |= X86_CR4_PAE;
1448 break;
1449
1450 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1451 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1452#ifdef VBOX_ENABLE_64_BITS_GUESTS
1453 break;
1454#else
1455 AssertFailed();
1456 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1457#endif
1458 default: /* shut up gcc */
1459 AssertFailed();
1460 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1461 }
1462 }
1463 else
1464 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1465 {
1466 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1467 val |= X86_CR4_PSE;
1468 /* Our identity mapping is a 32 bits page directory. */
1469 val &= ~X86_CR4_PAE;
1470 }
1471
1472 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1473 Log2(("Guest CR4 %08x\n", val));
1474 /* CR4 flags owned by the host; if the guests attempts to change them, then
1475 * the VM will exit.
1476 */
1477 val = 0
1478 | X86_CR4_PAE
1479 | X86_CR4_PGE
1480 | X86_CR4_PSE
1481 | X86_CR4_VMXE;
1482 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1483
1484 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1485 Log2(("Guest CR4-mask %08x\n", val));
1486 AssertRC(rc);
1487 }
1488
1489 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1490 {
1491 if (pVM->hwaccm.s.fNestedPaging)
1492 {
1493 Assert(PGMGetHyperCR3(pVCpu));
1494 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1495
1496 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1497 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1498 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1499 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1500
1501 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1502 AssertRC(rc);
1503
1504 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1505 {
1506 RTGCPHYS GCPhys;
1507
1508 /* We convert it here every time as pci regions could be reconfigured. */
1509 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1510 AssertRC(rc);
1511
1512 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1513 * take care of the translation to host physical addresses.
1514 */
1515 val = GCPhys;
1516 }
1517 else
1518 {
1519 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1520 val = pCtx->cr3;
1521 /* Prefetch the four PDPT entries in PAE mode. */
1522 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1523 }
1524 }
1525 else
1526 {
1527 val = PGMGetHyperCR3(pVCpu);
1528 Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1529 }
1530
1531 /* Save our shadow CR3 register. */
1532 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1533 AssertRC(rc);
1534 }
1535
1536 /* Debug registers. */
1537 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1538 {
1539 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1540 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1541
1542 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1543 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1544 pCtx->dr[7] |= 0x400; /* must be one */
1545
1546 /* Resync DR7 */
1547 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1548 AssertRC(rc);
1549
1550 /* Sync the debug state now if any breakpoint is armed. */
1551 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1552 && !CPUMIsGuestDebugStateActive(pVCpu)
1553 && !DBGFIsStepping(pVCpu))
1554 {
1555 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1556
1557 /* Disable drx move intercepts. */
1558 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1559 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1560 AssertRC(rc);
1561
1562 /* Save the host and load the guest debug state. */
1563 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1564 AssertRC(rc);
1565 }
1566
1567 /* IA32_DEBUGCTL MSR. */
1568 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1569 AssertRC(rc);
1570
1571 /** @todo do we really ever need this? */
1572 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1573 AssertRC(rc);
1574 }
1575
1576 /* EIP, ESP and EFLAGS */
1577 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1578 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1579 AssertRC(rc);
1580
1581 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1582 eflags = pCtx->eflags;
1583 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1584 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1585
1586#ifdef HWACCM_VMX_EMULATE_REALMODE
1587 /* Real mode emulation using v86 mode. */
1588 if (CPUMIsGuestInRealModeEx(pCtx))
1589 {
1590 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1591
1592 eflags.Bits.u1VM = 1;
1593 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1594 }
1595#endif /* HWACCM_VMX_EMULATE_REALMODE */
1596 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1597 AssertRC(rc);
1598
1599 /* TSC offset. */
1600 uint64_t u64TSCOffset;
1601
1602 if (TMCpuTickCanUseRealTSC(pVCpu, &u64TSCOffset))
1603 {
1604 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1605 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1606 AssertRC(rc);
1607
1608 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1609 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1610 AssertRC(rc);
1611 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1612 }
1613 else
1614 {
1615 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1616 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1617 AssertRC(rc);
1618 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1619 }
1620
1621 /* 64 bits guest mode? */
1622 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1623 {
1624#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1625 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1626#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1627 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1628#else
1629# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1630 if (!pVM->hwaccm.s.fAllow64BitGuests)
1631 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1632# endif
1633 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1634#endif
1635 /* Unconditionally update these as wrmsr might have changed them. */
1636 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1637 AssertRC(rc);
1638 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1639 AssertRC(rc);
1640 }
1641 else
1642 {
1643 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1644 }
1645
1646#if 0 /* @todo deal with 32/64 */
1647 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1648 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1649 {
1650 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1651 AssertRC(rc);
1652 }
1653#endif
1654
1655 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1656
1657 /* Done. */
1658 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1659
1660 return rc;
1661}
1662
1663/**
1664 * Syncs back the guest state
1665 *
1666 * @returns VBox status code.
1667 * @param pVM The VM to operate on.
1668 * @param pVCpu The VMCPU to operate on.
1669 * @param pCtx Guest context
1670 */
1671DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1672{
1673 RTGCUINTREG val, valShadow;
1674 RTGCUINTPTR uInterruptState;
1675 int rc;
1676
1677 /* Let's first sync back eip, esp, and eflags. */
1678 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1679 AssertRC(rc);
1680 pCtx->rip = val;
1681 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1682 AssertRC(rc);
1683 pCtx->rsp = val;
1684 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1685 AssertRC(rc);
1686 pCtx->eflags.u32 = val;
1687
1688 /* Take care of instruction fusing (sti, mov ss) */
1689 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1690 uInterruptState = val;
1691 if (uInterruptState != 0)
1692 {
1693 Assert(uInterruptState <= 2); /* only sti & mov ss */
1694 Log(("uInterruptState %x eip=%RGv\n", uInterruptState, pCtx->rip));
1695 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1696 }
1697 else
1698 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1699
1700 /* Control registers. */
1701 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1702 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1703 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1704 CPUMSetGuestCR0(pVCpu, val);
1705
1706 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1707 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1708 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1709 CPUMSetGuestCR4(pVCpu, val);
1710
1711 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1712 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1713 if ( pVM->hwaccm.s.fNestedPaging
1714 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1715 {
1716 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1717
1718 /* Can be updated behind our back in the nested paging case. */
1719 CPUMSetGuestCR2(pVCpu, pCache->cr2);
1720
1721 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1722
1723 if (val != pCtx->cr3)
1724 {
1725 CPUMSetGuestCR3(pVCpu, val);
1726 PGMUpdateCR3(pVCpu, val);
1727 }
1728 /* Prefetch the four PDPT entries in PAE mode. */
1729 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1730 }
1731
1732 /* Sync back DR7 here. */
1733 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1734 pCtx->dr[7] = val;
1735
1736 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1737 VMX_READ_SELREG(ES, es);
1738 VMX_READ_SELREG(SS, ss);
1739 VMX_READ_SELREG(CS, cs);
1740 VMX_READ_SELREG(DS, ds);
1741 VMX_READ_SELREG(FS, fs);
1742 VMX_READ_SELREG(GS, gs);
1743
1744 /*
1745 * System MSRs
1746 */
1747 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1748 pCtx->SysEnter.cs = val;
1749 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1750 pCtx->SysEnter.eip = val;
1751 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1752 pCtx->SysEnter.esp = val;
1753
1754 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1755 VMX_READ_SELREG(LDTR, ldtr);
1756
1757 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1758 pCtx->gdtr.cbGdt = val;
1759 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1760 pCtx->gdtr.pGdt = val;
1761
1762 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1763 pCtx->idtr.cbIdt = val;
1764 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1765 pCtx->idtr.pIdt = val;
1766
1767#ifdef HWACCM_VMX_EMULATE_REALMODE
1768 /* Real mode emulation using v86 mode. */
1769 if (CPUMIsGuestInRealModeEx(pCtx))
1770 {
1771 /* Hide our emulation flags */
1772 pCtx->eflags.Bits.u1VM = 0;
1773
1774 /* Restore original IOPL setting as we always use 0. */
1775 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1776
1777 /* Force a TR resync every time in case we switch modes. */
1778 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1779 }
1780 else
1781#endif /* HWACCM_VMX_EMULATE_REALMODE */
1782 {
1783 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1784 VMX_READ_SELREG(TR, tr);
1785 }
1786 return VINF_SUCCESS;
1787}
1788
1789/**
1790 * Dummy placeholder
1791 *
1792 * @param pVM The VM to operate on.
1793 * @param pVCpu The VMCPU to operate on.
1794 */
1795static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1796{
1797 NOREF(pVM);
1798 NOREF(pVCpu);
1799 return;
1800}
1801
1802/**
1803 * Setup the tagged TLB for EPT
1804 *
1805 * @returns VBox status code.
1806 * @param pVM The VM to operate on.
1807 * @param pVCpu The VMCPU to operate on.
1808 */
1809static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1810{
1811 PHWACCM_CPUINFO pCpu;
1812
1813 Assert(pVM->hwaccm.s.fNestedPaging);
1814 Assert(!pVM->hwaccm.s.vmx.fVPID);
1815
1816 /* Deal with tagged TLBs if VPID or EPT is supported. */
1817 pCpu = HWACCMR0GetCurrentCpu();
1818 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1819 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1820 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1821 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1822 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1823 {
1824 /* Force a TLB flush on VM entry. */
1825 pVCpu->hwaccm.s.fForceTLBFlush = true;
1826 }
1827 else
1828 Assert(!pCpu->fFlushTLB);
1829
1830 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1831 pCpu->fFlushTLB = false;
1832
1833 if (pVCpu->hwaccm.s.fForceTLBFlush)
1834 {
1835 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1836 }
1837 else
1838 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1839 {
1840 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1841 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1842 for (unsigned i=0;i<pVCpu->hwaccm.s.cTlbShootdownPages;i++)
1843 {
1844 /* aTlbShootdownPages contains physical addresses in this case. */
1845 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.aTlbShootdownPages[i]);
1846 }
1847 }
1848 pVCpu->hwaccm.s.cTlbShootdownPages = 0;
1849 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1850
1851#ifdef VBOX_WITH_STATISTICS
1852 if (pVCpu->hwaccm.s.fForceTLBFlush)
1853 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1854 else
1855 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1856#endif
1857}
1858
1859#ifdef HWACCM_VTX_WITH_VPID
1860/**
1861 * Setup the tagged TLB for VPID
1862 *
1863 * @returns VBox status code.
1864 * @param pVM The VM to operate on.
1865 * @param pVCpu The VMCPU to operate on.
1866 */
1867static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1868{
1869 PHWACCM_CPUINFO pCpu;
1870
1871 Assert(pVM->hwaccm.s.vmx.fVPID);
1872 Assert(!pVM->hwaccm.s.fNestedPaging);
1873
1874 /* Deal with tagged TLBs if VPID or EPT is supported. */
1875 pCpu = HWACCMR0GetCurrentCpu();
1876 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1877 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1878 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1879 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1880 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1881 {
1882 /* Force a TLB flush on VM entry. */
1883 pVCpu->hwaccm.s.fForceTLBFlush = true;
1884 }
1885 else
1886 Assert(!pCpu->fFlushTLB);
1887
1888 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1889
1890 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1891 if (pVCpu->hwaccm.s.fForceTLBFlush)
1892 {
1893 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1894 || pCpu->fFlushTLB)
1895 {
1896 pCpu->fFlushTLB = false;
1897 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1898 pCpu->cTLBFlushes++;
1899 }
1900 else
1901 {
1902 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1903 pVCpu->hwaccm.s.fForceTLBFlush = false;
1904 }
1905
1906 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1907 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1908 }
1909 else
1910 {
1911 Assert(!pCpu->fFlushTLB);
1912 Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
1913
1914 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1915 {
1916 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1917 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1918 for (unsigned i=0;i<pVCpu->hwaccm.s.cTlbShootdownPages;i++)
1919 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.aTlbShootdownPages[i]);
1920 }
1921 }
1922 pVCpu->hwaccm.s.cTlbShootdownPages = 0;
1923 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1924
1925 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1926 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1927 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1928
1929 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1930 AssertRC(rc);
1931
1932 if (pVCpu->hwaccm.s.fForceTLBFlush)
1933 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1934
1935#ifdef VBOX_WITH_STATISTICS
1936 if (pVCpu->hwaccm.s.fForceTLBFlush)
1937 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1938 else
1939 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1940#endif
1941}
1942#endif /* HWACCM_VTX_WITH_VPID */
1943
1944/**
1945 * Runs guest code in a VT-x VM.
1946 *
1947 * @returns VBox status code.
1948 * @param pVM The VM to operate on.
1949 * @param pVCpu The VMCPU to operate on.
1950 * @param pCtx Guest context
1951 */
1952VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1953{
1954 int rc = VINF_SUCCESS;
1955 RTGCUINTREG val;
1956 RTGCUINTREG exitReason = VMX_EXIT_INVALID;
1957 RTGCUINTREG instrError, cbInstr;
1958 RTGCUINTPTR exitQualification;
1959 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1960 RTGCUINTPTR errCode, instrInfo;
1961 bool fSyncTPR = false;
1962 PHWACCM_CPUINFO pCpu = 0;
1963 unsigned cResume = 0;
1964#ifdef VBOX_STRICT
1965 RTCPUID idCpuCheck;
1966#endif
1967#ifdef VBOX_WITH_STATISTICS
1968 bool fStatEntryStarted = true;
1969 bool fStatExit2Started = false;
1970#endif
1971
1972 Log2(("\nE"));
1973
1974 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
1975
1976#ifdef VBOX_STRICT
1977 {
1978 RTCCUINTREG val;
1979
1980 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1981 AssertRC(rc);
1982 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1983
1984 /* allowed zero */
1985 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1986 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1987
1988 /* allowed one */
1989 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1990 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1991
1992 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1993 AssertRC(rc);
1994 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1995
1996 /* Must be set according to the MSR, but can be cleared in case of EPT. */
1997 if (pVM->hwaccm.s.fNestedPaging)
1998 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
1999 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2000 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2001
2002 /* allowed zero */
2003 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2004 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2005
2006 /* allowed one */
2007 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2008 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2009
2010 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2011 AssertRC(rc);
2012 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2013
2014 /* allowed zero */
2015 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2016 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2017
2018 /* allowed one */
2019 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2020 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2021
2022 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2023 AssertRC(rc);
2024 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2025
2026 /* allowed zero */
2027 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2028 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2029
2030 /* allowed one */
2031 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2032 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2033 }
2034#endif
2035
2036#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2037 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2038#endif
2039
2040 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2041 */
2042ResumeExecution:
2043 STAM_STATS({
2044 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2045 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2046 });
2047 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2048 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2049 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2050 Assert(!HWACCMR0SuspendPending());
2051
2052 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2053 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
2054 {
2055 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2056 rc = VINF_EM_RAW_INTERRUPT;
2057 goto end;
2058 }
2059
2060 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2061 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2062 {
2063 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2064 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2065 {
2066 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2067 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2068 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2069 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2070 */
2071 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2072 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2073 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2074 AssertRC(rc);
2075 }
2076 }
2077 else
2078 {
2079 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2080 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2081 AssertRC(rc);
2082 }
2083
2084 /* Check for pending actions that force us to go back to ring 3. */
2085 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2086 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2087 {
2088 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2089 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2090 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2091 goto end;
2092 }
2093 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2094 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2095 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2096 {
2097 rc = VINF_EM_PENDING_REQUEST;
2098 goto end;
2099 }
2100
2101 /* When external interrupts are pending, we should exit the VM when IF is set. */
2102 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2103 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2104 if (RT_FAILURE(rc))
2105 goto end;
2106
2107 /** @todo check timers?? */
2108
2109 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2110
2111 /* TPR caching using CR8 is only available in 64 bits mode */
2112 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2113 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2114 /**
2115 * @todo reduce overhead
2116 */
2117 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
2118 && pVM->hwaccm.s.vmx.pAPIC)
2119 {
2120 /* TPR caching in CR8 */
2121 uint8_t u8TPR;
2122 bool fPending;
2123
2124 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
2125 AssertRC(rc);
2126 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2127 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
2128
2129 /* Two options here:
2130 * - external interrupt pending, but masked by the TPR value.
2131 * -> a CR8 update that lower the current TPR value should cause an exit
2132 * - no pending interrupts
2133 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2134 */
2135 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
2136 AssertRC(rc);
2137
2138 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
2139 fSyncTPR = true;
2140 }
2141
2142#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2143 if ( pVM->hwaccm.s.fNestedPaging
2144# ifdef HWACCM_VTX_WITH_VPID
2145 || pVM->hwaccm.s.vmx.fVPID
2146# endif /* HWACCM_VTX_WITH_VPID */
2147 )
2148 {
2149 pCpu = HWACCMR0GetCurrentCpu();
2150 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2151 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2152 {
2153 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2154 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2155 else
2156 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2157 }
2158 if (pCpu->fFlushTLB)
2159 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2160 else
2161 if (pVCpu->hwaccm.s.fForceTLBFlush)
2162 LogFlow(("Manual TLB flush\n"));
2163 }
2164#endif
2165#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2166 PGMDynMapFlushAutoSet(pVCpu);
2167#endif
2168
2169 /*
2170 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2171 * (until the actual world switch)
2172 */
2173#ifdef VBOX_STRICT
2174 idCpuCheck = RTMpCpuId();
2175#endif
2176#ifdef LOG_LOGGING
2177 VMMR0LogFlushDisable(pVCpu);
2178#endif
2179 /* Save the host state first. */
2180 rc = VMXR0SaveHostState(pVM, pVCpu);
2181 if (rc != VINF_SUCCESS)
2182 goto end;
2183 /* Load the guest state */
2184 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2185 if (rc != VINF_SUCCESS)
2186 goto end;
2187
2188 /* Deal with tagged TLB setup and invalidation. */
2189 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2190
2191 /* Non-register state Guest Context */
2192 /** @todo change me according to cpu state */
2193 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2194 AssertRC(rc);
2195
2196 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2197
2198 /* Manual save and restore:
2199 * - General purpose registers except RIP, RSP
2200 *
2201 * Trashed:
2202 * - CR2 (we don't care)
2203 * - LDTR (reset to 0)
2204 * - DRx (presumably not changed at all)
2205 * - DR7 (reset to 0x400)
2206 * - EFLAGS (reset to RT_BIT(1); not relevant)
2207 *
2208 */
2209
2210
2211 /* All done! Let's start VM execution. */
2212 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2213#ifdef VBOX_STRICT
2214 Assert(idCpuCheck == RTMpCpuId());
2215#endif
2216
2217#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2218 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2219 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2220#endif
2221
2222 TMNotifyStartOfExecution(pVCpu);
2223 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2224 TMNotifyEndOfExecution(pVCpu);
2225 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2226
2227 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2228
2229 /* In case we execute a goto ResumeExecution later on. */
2230 pVCpu->hwaccm.s.fResumeVM = true;
2231 pVCpu->hwaccm.s.fForceTLBFlush = false;
2232
2233 /*
2234 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2235 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2236 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2237 */
2238 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2239 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2240
2241 if (rc != VINF_SUCCESS)
2242 {
2243 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2244 goto end;
2245 }
2246
2247 /* Success. Query the guest state and figure out what has happened. */
2248
2249 /* Investigate why there was a VM-exit. */
2250 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2251 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2252
2253 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2254 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2255 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2256 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2257 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2258 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2259 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2260 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2261 AssertRC(rc);
2262
2263 /* Sync back the guest state */
2264 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2265 AssertRC(rc);
2266
2267 /* Note! NOW IT'S SAFE FOR LOGGING! */
2268#ifdef LOG_LOGGING
2269 VMMR0LogFlushEnable(pVCpu);
2270#endif
2271 Log2(("Raw exit reason %08x\n", exitReason));
2272
2273 /* Check if an injected event was interrupted prematurely. */
2274 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2275 AssertRC(rc);
2276 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2277 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2278 /* Ignore 'int xx' as they'll be restarted anyway. */
2279 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2280 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2281 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2282 {
2283 pVCpu->hwaccm.s.Event.fPending = true;
2284 /* Error code present? */
2285 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2286 {
2287 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2288 AssertRC(rc);
2289 pVCpu->hwaccm.s.Event.errCode = val;
2290 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2291 }
2292 else
2293 {
2294 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2295 pVCpu->hwaccm.s.Event.errCode = 0;
2296 }
2297 }
2298#ifdef VBOX_STRICT
2299 else
2300 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2301 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2302 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2303 {
2304 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2305 }
2306
2307 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2308 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2309#endif
2310
2311 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2312 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2313 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2314 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2315 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2316
2317 if (fSyncTPR)
2318 {
2319 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
2320 AssertRC(rc);
2321 }
2322
2323 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2324 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2325
2326 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2327 switch (exitReason)
2328 {
2329 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2330 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2331 {
2332 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2333
2334 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2335 {
2336 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2337 /* External interrupt; leave to allow it to be dispatched again. */
2338 rc = VINF_EM_RAW_INTERRUPT;
2339 break;
2340 }
2341 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2342 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2343 {
2344 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2345 /* External interrupt; leave to allow it to be dispatched again. */
2346 rc = VINF_EM_RAW_INTERRUPT;
2347 break;
2348
2349 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2350 AssertFailed(); /* can't come here; fails the first check. */
2351 break;
2352
2353 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2354 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2355 Assert(vector == 1 || vector == 3 || vector == 4);
2356 /* no break */
2357 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2358 Log2(("Hardware/software interrupt %d\n", vector));
2359 switch (vector)
2360 {
2361 case X86_XCPT_NM:
2362 {
2363 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2364
2365 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2366 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2367 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2368 if (rc == VINF_SUCCESS)
2369 {
2370 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2371
2372 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2373
2374 /* Continue execution. */
2375 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2376
2377 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2378 goto ResumeExecution;
2379 }
2380
2381 Log(("Forward #NM fault to the guest\n"));
2382 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2383 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2384 AssertRC(rc);
2385 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2386 goto ResumeExecution;
2387 }
2388
2389 case X86_XCPT_PF: /* Page fault */
2390 {
2391#ifdef DEBUG
2392 if (pVM->hwaccm.s.fNestedPaging)
2393 { /* A genuine pagefault.
2394 * Forward the trap to the guest by injecting the exception and resuming execution.
2395 */
2396 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2397
2398 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2399
2400 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2401
2402 /* Now we must update CR2. */
2403 pCtx->cr2 = exitQualification;
2404 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2405 AssertRC(rc);
2406
2407 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2408 goto ResumeExecution;
2409 }
2410#endif
2411 Assert(!pVM->hwaccm.s.fNestedPaging);
2412
2413 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2414 /* Exit qualification contains the linear address of the page fault. */
2415 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2416 TRPMSetErrorCode(pVCpu, errCode);
2417 TRPMSetFaultAddress(pVCpu, exitQualification);
2418
2419 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2420 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2421 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2422 if (rc == VINF_SUCCESS)
2423 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2424 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2425 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2426
2427 TRPMResetTrap(pVCpu);
2428
2429 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2430 goto ResumeExecution;
2431 }
2432 else
2433 if (rc == VINF_EM_RAW_GUEST_TRAP)
2434 { /* A genuine pagefault.
2435 * Forward the trap to the guest by injecting the exception and resuming execution.
2436 */
2437 Log2(("Forward page fault to the guest\n"));
2438
2439 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2440 /* The error code might have been changed. */
2441 errCode = TRPMGetErrorCode(pVCpu);
2442
2443 TRPMResetTrap(pVCpu);
2444
2445 /* Now we must update CR2. */
2446 pCtx->cr2 = exitQualification;
2447 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2448 AssertRC(rc);
2449
2450 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2451 goto ResumeExecution;
2452 }
2453#ifdef VBOX_STRICT
2454 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2455 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2456#endif
2457 /* Need to go back to the recompiler to emulate the instruction. */
2458 TRPMResetTrap(pVCpu);
2459 break;
2460 }
2461
2462 case X86_XCPT_MF: /* Floating point exception. */
2463 {
2464 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2465 if (!(pCtx->cr0 & X86_CR0_NE))
2466 {
2467 /* old style FPU error reporting needs some extra work. */
2468 /** @todo don't fall back to the recompiler, but do it manually. */
2469 rc = VINF_EM_RAW_EMULATE_INSTR;
2470 break;
2471 }
2472 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2473 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2474 AssertRC(rc);
2475
2476 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2477 goto ResumeExecution;
2478 }
2479
2480 case X86_XCPT_DB: /* Debug exception. */
2481 {
2482 uint64_t uDR6;
2483
2484 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2485 *
2486 * Exit qualification bits:
2487 * 3:0 B0-B3 which breakpoint condition was met
2488 * 12:4 Reserved (0)
2489 * 13 BD - debug register access detected
2490 * 14 BS - single step execution or branch taken
2491 * 63:15 Reserved (0)
2492 */
2493 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2494
2495 /* Note that we don't support guest and host-initiated debugging at the same time. */
2496 Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx));
2497
2498 uDR6 = X86_DR6_INIT_VAL;
2499 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2500 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
2501 if (rc == VINF_EM_RAW_GUEST_TRAP)
2502 {
2503 /** @todo this isn't working, but we'll never get here normally. */
2504
2505 /* Update DR6 here. */
2506 pCtx->dr[6] = uDR6;
2507
2508 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2509 pCtx->dr[7] &= ~X86_DR7_GD;
2510
2511 /* Paranoia. */
2512 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2513 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2514 pCtx->dr[7] |= 0x400; /* must be one */
2515
2516 /* Resync DR7 */
2517 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2518 AssertRC(rc);
2519
2520 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2521 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2522 AssertRC(rc);
2523
2524 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2525 goto ResumeExecution;
2526 }
2527 /* Return to ring 3 to deal with the debug exit code. */
2528 break;
2529 }
2530
2531 case X86_XCPT_BP: /* Breakpoint. */
2532 {
2533 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2534 if (rc == VINF_EM_RAW_GUEST_TRAP)
2535 {
2536 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2537 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2538 AssertRC(rc);
2539 goto ResumeExecution;
2540 }
2541 if (rc == VINF_SUCCESS)
2542 goto ResumeExecution;
2543 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2544 break;
2545 }
2546
2547 case X86_XCPT_GP: /* General protection failure exception.*/
2548 {
2549 uint32_t cbOp;
2550 uint32_t cbSize;
2551 DISCPUSTATE Cpu;
2552
2553 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2554#ifdef VBOX_STRICT
2555 if (!CPUMIsGuestInRealModeEx(pCtx))
2556 {
2557 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2558 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2559 AssertRC(rc);
2560 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2561 goto ResumeExecution;
2562 }
2563#endif
2564 Assert(CPUMIsGuestInRealModeEx(pCtx));
2565
2566 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2567
2568 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2569 if (RT_SUCCESS(rc))
2570 {
2571 bool fUpdateRIP = true;
2572
2573 Assert(cbOp == Cpu.opsize);
2574 switch (Cpu.pCurInstr->opcode)
2575 {
2576 case OP_CLI:
2577 pCtx->eflags.Bits.u1IF = 0;
2578 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2579 break;
2580
2581 case OP_STI:
2582 pCtx->eflags.Bits.u1IF = 1;
2583 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2584 break;
2585
2586 case OP_HLT:
2587 fUpdateRIP = false;
2588 rc = VINF_EM_HALT;
2589 pCtx->rip += Cpu.opsize;
2590 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2591 break;
2592
2593 case OP_POPF:
2594 {
2595 RTGCPTR GCPtrStack;
2596 uint32_t cbParm;
2597 uint32_t uMask;
2598 X86EFLAGS eflags;
2599
2600 if (Cpu.prefix & PREFIX_OPSIZE)
2601 {
2602 cbParm = 4;
2603 uMask = 0xffffffff;
2604 }
2605 else
2606 {
2607 cbParm = 2;
2608 uMask = 0xffff;
2609 }
2610
2611 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2612 if (RT_FAILURE(rc))
2613 {
2614 rc = VERR_EM_INTERPRETER;
2615 break;
2616 }
2617 eflags.u = 0;
2618 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2619 if (RT_FAILURE(rc))
2620 {
2621 rc = VERR_EM_INTERPRETER;
2622 break;
2623 }
2624 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2625 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
2626 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
2627 pCtx->eflags.Bits.u1RF = 0;
2628 pCtx->esp += cbParm;
2629 pCtx->esp &= uMask;
2630
2631 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2632 break;
2633 }
2634
2635 case OP_PUSHF:
2636 {
2637 RTGCPTR GCPtrStack;
2638 uint32_t cbParm;
2639 uint32_t uMask;
2640 X86EFLAGS eflags;
2641
2642 if (Cpu.prefix & PREFIX_OPSIZE)
2643 {
2644 cbParm = 4;
2645 uMask = 0xffffffff;
2646 }
2647 else
2648 {
2649 cbParm = 2;
2650 uMask = 0xffff;
2651 }
2652
2653 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2654 if (RT_FAILURE(rc))
2655 {
2656 rc = VERR_EM_INTERPRETER;
2657 break;
2658 }
2659 eflags = pCtx->eflags;
2660 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2661 eflags.Bits.u1RF = 0;
2662 eflags.Bits.u1VM = 0;
2663
2664 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2665 if (RT_FAILURE(rc))
2666 {
2667 rc = VERR_EM_INTERPRETER;
2668 break;
2669 }
2670 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2671 pCtx->esp -= cbParm;
2672 pCtx->esp &= uMask;
2673 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2674 break;
2675 }
2676
2677 case OP_IRET:
2678 {
2679 RTGCPTR GCPtrStack;
2680 uint32_t uMask = 0xffff;
2681 uint16_t aIretFrame[3];
2682
2683 if (Cpu.prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
2684 {
2685 rc = VERR_EM_INTERPRETER;
2686 break;
2687 }
2688
2689 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2690 if (RT_FAILURE(rc))
2691 {
2692 rc = VERR_EM_INTERPRETER;
2693 break;
2694 }
2695 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2696 if (RT_FAILURE(rc))
2697 {
2698 rc = VERR_EM_INTERPRETER;
2699 break;
2700 }
2701 pCtx->ip = aIretFrame[0];
2702 pCtx->cs = aIretFrame[1];
2703 pCtx->csHid.u64Base = pCtx->cs << 4;
2704 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2705 pCtx->sp += sizeof(aIretFrame);
2706
2707 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2708 fUpdateRIP = false;
2709 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2710 break;
2711 }
2712
2713 case OP_INT:
2714 {
2715 RTGCUINTPTR intInfo;
2716
2717 LogFlow(("Realmode: INT %x\n", Cpu.param1.parval & 0xff));
2718 intInfo = Cpu.param1.parval & 0xff;
2719 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2720 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2721
2722 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2723 AssertRC(rc);
2724 fUpdateRIP = false;
2725 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2726 break;
2727 }
2728
2729 case OP_INTO:
2730 {
2731 if (pCtx->eflags.Bits.u1OF)
2732 {
2733 RTGCUINTPTR intInfo;
2734
2735 LogFlow(("Realmode: INTO\n"));
2736 intInfo = X86_XCPT_OF;
2737 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2738 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2739
2740 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2741 AssertRC(rc);
2742 fUpdateRIP = false;
2743 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2744 }
2745 break;
2746 }
2747
2748 case OP_INT3:
2749 {
2750 RTGCUINTPTR intInfo;
2751
2752 LogFlow(("Realmode: INT 3\n"));
2753 intInfo = 3;
2754 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2755 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2756
2757 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2758 AssertRC(rc);
2759 fUpdateRIP = false;
2760 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2761 break;
2762 }
2763
2764 default:
2765 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2766 break;
2767 }
2768
2769 if (rc == VINF_SUCCESS)
2770 {
2771 if (fUpdateRIP)
2772 pCtx->rip += cbOp; /* Move on to the next instruction. */
2773
2774 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2775 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2776
2777 /* Only resume if successful. */
2778 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2779 goto ResumeExecution;
2780 }
2781 }
2782 else
2783 rc = VERR_EM_INTERPRETER;
2784
2785 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2786 break;
2787 }
2788
2789#ifdef VBOX_STRICT
2790 case X86_XCPT_DE: /* Divide error. */
2791 case X86_XCPT_UD: /* Unknown opcode exception. */
2792 case X86_XCPT_SS: /* Stack segment exception. */
2793 case X86_XCPT_NP: /* Segment not present exception. */
2794 {
2795 switch(vector)
2796 {
2797 case X86_XCPT_DE:
2798 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2799 break;
2800 case X86_XCPT_UD:
2801 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2802 break;
2803 case X86_XCPT_SS:
2804 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2805 break;
2806 case X86_XCPT_NP:
2807 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2808 break;
2809 }
2810
2811 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2812 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2813 AssertRC(rc);
2814
2815 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2816 goto ResumeExecution;
2817 }
2818#endif
2819 default:
2820#ifdef HWACCM_VMX_EMULATE_REALMODE
2821 if (CPUMIsGuestInRealModeEx(pCtx))
2822 {
2823 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2824 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2825 AssertRC(rc);
2826
2827 /* Go back to ring 3 in case of a triple fault. */
2828 if ( vector == X86_XCPT_DF
2829 && rc == VINF_EM_RESET)
2830 break;
2831
2832 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2833 goto ResumeExecution;
2834 }
2835#endif
2836 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2837 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2838 break;
2839 } /* switch (vector) */
2840
2841 break;
2842
2843 default:
2844 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2845 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2846 break;
2847 }
2848
2849 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2850 break;
2851 }
2852
2853 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2854 {
2855 RTGCPHYS GCPhys;
2856
2857 Assert(pVM->hwaccm.s.fNestedPaging);
2858
2859 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2860 AssertRC(rc);
2861 Assert(((exitQualification >> 7) & 3) != 2);
2862
2863 /* Determine the kind of violation. */
2864 errCode = 0;
2865 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2866 errCode |= X86_TRAP_PF_ID;
2867
2868 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2869 errCode |= X86_TRAP_PF_RW;
2870
2871 /* If the page is present, then it's a page level protection fault. */
2872 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2873 errCode |= X86_TRAP_PF_P;
2874
2875 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2876
2877 /* GCPhys contains the guest physical address of the page fault. */
2878 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2879 TRPMSetErrorCode(pVCpu, errCode);
2880 TRPMSetFaultAddress(pVCpu, GCPhys);
2881
2882 /* Handle the pagefault trap for the nested shadow table. */
2883 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2884 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2885 if (rc == VINF_SUCCESS)
2886 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2887 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
2888 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
2889
2890 TRPMResetTrap(pVCpu);
2891
2892 goto ResumeExecution;
2893 }
2894
2895#ifdef VBOX_STRICT
2896 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2897 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2898#endif
2899 /* Need to go back to the recompiler to emulate the instruction. */
2900 TRPMResetTrap(pVCpu);
2901 break;
2902 }
2903
2904 case VMX_EXIT_EPT_MISCONFIG:
2905 {
2906 RTGCPHYS GCPhys;
2907
2908 Assert(pVM->hwaccm.s.fNestedPaging);
2909
2910 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2911 AssertRC(rc);
2912
2913 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
2914 break;
2915 }
2916
2917 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2918 /* Clear VM-exit on IF=1 change. */
2919 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2920 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2921 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2922 AssertRC(rc);
2923 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
2924 goto ResumeExecution; /* we check for pending guest interrupts there */
2925
2926 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2927 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2928 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
2929 /* Skip instruction and continue directly. */
2930 pCtx->rip += cbInstr;
2931 /* Continue execution.*/
2932 goto ResumeExecution;
2933
2934 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2935 {
2936 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2937 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
2938 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2939 if (rc == VINF_SUCCESS)
2940 {
2941 /* Update EIP and continue execution. */
2942 Assert(cbInstr == 2);
2943 pCtx->rip += cbInstr;
2944 goto ResumeExecution;
2945 }
2946 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
2947 rc = VINF_EM_RAW_EMULATE_INSTR;
2948 break;
2949 }
2950
2951 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2952 {
2953 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
2954 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
2955 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2956 if (rc == VINF_SUCCESS)
2957 {
2958 /* Update EIP and continue execution. */
2959 Assert(cbInstr == 2);
2960 pCtx->rip += cbInstr;
2961 goto ResumeExecution;
2962 }
2963 rc = VINF_EM_RAW_EMULATE_INSTR;
2964 break;
2965 }
2966
2967 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2968 {
2969 Log2(("VMX: Rdtsc\n"));
2970 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2971 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2972 if (rc == VINF_SUCCESS)
2973 {
2974 /* Update EIP and continue execution. */
2975 Assert(cbInstr == 2);
2976 pCtx->rip += cbInstr;
2977 goto ResumeExecution;
2978 }
2979 rc = VINF_EM_RAW_EMULATE_INSTR;
2980 break;
2981 }
2982
2983 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2984 {
2985 Log2(("VMX: invlpg\n"));
2986 Assert(!pVM->hwaccm.s.fNestedPaging);
2987
2988 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2989 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
2990 if (rc == VINF_SUCCESS)
2991 {
2992 /* Update EIP and continue execution. */
2993 pCtx->rip += cbInstr;
2994 goto ResumeExecution;
2995 }
2996 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
2997 break;
2998 }
2999
3000 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3001 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3002 {
3003 uint32_t cbSize;
3004
3005 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3006 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3007 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3008 if (rc == VINF_SUCCESS)
3009 {
3010 /* EIP has been updated already. */
3011
3012 /* Only resume if successful. */
3013 goto ResumeExecution;
3014 }
3015 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
3016 break;
3017 }
3018
3019 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3020 {
3021 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3022
3023 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3024 {
3025 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3026 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3027 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3028 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3029 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3030 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3031
3032 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3033 {
3034 case 0:
3035 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3036 break;
3037 case 2:
3038 break;
3039 case 3:
3040 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3041 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3042 break;
3043 case 4:
3044 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3045 break;
3046 case 8:
3047 /* CR8 contains the APIC TPR */
3048 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3049 break;
3050
3051 default:
3052 AssertFailed();
3053 break;
3054 }
3055 /* Check if a sync operation is pending. */
3056 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3057 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3058 {
3059 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3060 AssertRC(rc);
3061 }
3062 break;
3063
3064 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3065 Log2(("VMX: mov x, crx\n"));
3066 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3067
3068 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3069
3070 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3071 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3072
3073 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3074 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3075 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3076 break;
3077
3078 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3079 Log2(("VMX: clts\n"));
3080 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3081 rc = EMInterpretCLTS(pVM, pVCpu);
3082 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3083 break;
3084
3085 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3086 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3087 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3088 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3089 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3090 break;
3091 }
3092
3093 /* Update EIP if no error occurred. */
3094 if (RT_SUCCESS(rc))
3095 pCtx->rip += cbInstr;
3096
3097 if (rc == VINF_SUCCESS)
3098 {
3099 /* Only resume if successful. */
3100 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3101 goto ResumeExecution;
3102 }
3103 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3104 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3105 break;
3106 }
3107
3108 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3109 {
3110 if (!DBGFIsStepping(pVCpu))
3111 {
3112 /* Disable drx move intercepts. */
3113 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3114 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3115 AssertRC(rc);
3116
3117 /* Save the host and load the guest debug state. */
3118 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3119 AssertRC(rc);
3120
3121#ifdef VBOX_WITH_STATISTICS
3122 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3123 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3124 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3125 else
3126 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3127#endif
3128
3129 goto ResumeExecution;
3130 }
3131
3132 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3133 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3134 {
3135 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3136 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3137 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3138 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3139 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3140 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3141 Log2(("DR7=%08x\n", pCtx->dr[7]));
3142 }
3143 else
3144 {
3145 Log2(("VMX: mov x, drx\n"));
3146 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3147 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3148 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3149 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3150 }
3151 /* Update EIP if no error occurred. */
3152 if (RT_SUCCESS(rc))
3153 pCtx->rip += cbInstr;
3154
3155 if (rc == VINF_SUCCESS)
3156 {
3157 /* Only resume if successful. */
3158 goto ResumeExecution;
3159 }
3160 Assert(rc == VERR_EM_INTERPRETER);
3161 break;
3162 }
3163
3164 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3165 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3166 {
3167 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3168 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3169 uint32_t uPort;
3170 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3171
3172 /** @todo necessary to make the distinction? */
3173 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3174 {
3175 uPort = pCtx->edx & 0xffff;
3176 }
3177 else
3178 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3179
3180 /* paranoia */
3181 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3182 {
3183 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3184 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3185 break;
3186 }
3187
3188 uint32_t cbSize = g_aIOSize[uIOWidth];
3189
3190 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3191 {
3192 /* ins/outs */
3193 DISCPUSTATE Cpu;
3194
3195 /* Disassemble manually to deal with segment prefixes. */
3196 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3197 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3198 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, NULL);
3199 if (rc == VINF_SUCCESS)
3200 {
3201 if (fIOWrite)
3202 {
3203 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3204 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3205 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
3206 }
3207 else
3208 {
3209 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3210 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3211 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
3212 }
3213 }
3214 else
3215 rc = VINF_EM_RAW_EMULATE_INSTR;
3216 }
3217 else
3218 {
3219 /* normal in/out */
3220 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3221
3222 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3223
3224 if (fIOWrite)
3225 {
3226 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3227 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3228 }
3229 else
3230 {
3231 uint32_t u32Val = 0;
3232
3233 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3234 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3235 if (IOM_SUCCESS(rc))
3236 {
3237 /* Write back to the EAX register. */
3238 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3239 }
3240 }
3241 }
3242 /*
3243 * Handled the I/O return codes.
3244 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3245 */
3246 if (IOM_SUCCESS(rc))
3247 {
3248 /* Update EIP and continue execution. */
3249 pCtx->rip += cbInstr;
3250 if (RT_LIKELY(rc == VINF_SUCCESS))
3251 {
3252 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3253 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3254 {
3255 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3256 for (unsigned i=0;i<4;i++)
3257 {
3258 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3259
3260 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3261 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3262 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3263 {
3264 uint64_t uDR6;
3265
3266 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3267
3268 uDR6 = ASMGetDR6();
3269
3270 /* Clear all breakpoint status flags and set the one we just hit. */
3271 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3272 uDR6 |= (uint64_t)RT_BIT(i);
3273
3274 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3275 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3276 * the contents have been read.
3277 */
3278 ASMSetDR6(uDR6);
3279
3280 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3281 pCtx->dr[7] &= ~X86_DR7_GD;
3282
3283 /* Paranoia. */
3284 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3285 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3286 pCtx->dr[7] |= 0x400; /* must be one */
3287
3288 /* Resync DR7 */
3289 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3290 AssertRC(rc);
3291
3292 /* Construct inject info. */
3293 intInfo = X86_XCPT_DB;
3294 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3295 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3296
3297 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3298 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3299 AssertRC(rc);
3300
3301 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3302 goto ResumeExecution;
3303 }
3304 }
3305 }
3306
3307 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3308 goto ResumeExecution;
3309 }
3310 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3311 break;
3312 }
3313
3314#ifdef VBOX_STRICT
3315 if (rc == VINF_IOM_HC_IOPORT_READ)
3316 Assert(!fIOWrite);
3317 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3318 Assert(fIOWrite);
3319 else
3320 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3321#endif
3322 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3323 break;
3324 }
3325
3326 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3327 LogFlow(("VMX_EXIT_TPR\n"));
3328 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3329 goto ResumeExecution;
3330
3331 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3332 goto ResumeExecution;
3333
3334 default:
3335 /* The rest is handled after syncing the entire CPU state. */
3336 break;
3337 }
3338
3339 /* Note: the guest state isn't entirely synced back at this stage. */
3340
3341 /* Investigate why there was a VM-exit. (part 2) */
3342 switch (exitReason)
3343 {
3344 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3345 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3346 case VMX_EXIT_EPT_VIOLATION:
3347 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3348 /* Already handled above. */
3349 break;
3350
3351 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3352 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3353 break;
3354
3355 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3356 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3357 rc = VINF_EM_RAW_INTERRUPT;
3358 AssertFailed(); /* Can't happen. Yet. */
3359 break;
3360
3361 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3362 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3363 rc = VINF_EM_RAW_INTERRUPT;
3364 AssertFailed(); /* Can't happen afaik. */
3365 break;
3366
3367 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3368 rc = VERR_EM_INTERPRETER;
3369 break;
3370
3371 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3372 /** Check if external interrupts are pending; if so, don't switch back. */
3373 pCtx->rip++; /* skip hlt */
3374 if ( pCtx->eflags.Bits.u1IF
3375 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3376 goto ResumeExecution;
3377
3378 rc = VINF_EM_HALT;
3379 break;
3380
3381 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3382 AssertFailed(); /* can't happen. */
3383 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3384 break;
3385
3386 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3387 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3388 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3389 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3390 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3391 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3392 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3393 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3394 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3395 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3396 /** @todo inject #UD immediately */
3397 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3398 break;
3399
3400 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3401 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3402 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3403 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3404 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3405 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3406 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3407 /* already handled above */
3408 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3409 || rc == VINF_EM_RAW_INTERRUPT
3410 || rc == VERR_EM_INTERPRETER
3411 || rc == VINF_EM_RAW_EMULATE_INSTR
3412 || rc == VINF_PGM_SYNC_CR3
3413 || rc == VINF_IOM_HC_IOPORT_READ
3414 || rc == VINF_IOM_HC_IOPORT_WRITE
3415 || rc == VINF_EM_RAW_GUEST_TRAP
3416 || rc == VINF_TRPM_XCPT_DISPATCHED
3417 || rc == VINF_EM_RESCHEDULE_REM,
3418 ("rc = %d\n", rc));
3419 break;
3420
3421 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3422 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3423 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3424 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3425 rc = VERR_EM_INTERPRETER;
3426 break;
3427
3428 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3429 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3430 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3431 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3432 break;
3433
3434 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3435 Assert(rc == VINF_EM_RAW_INTERRUPT);
3436 break;
3437
3438 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3439 {
3440#ifdef VBOX_STRICT
3441 RTCCUINTREG val = 0;
3442
3443 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3444
3445 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3446 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3447
3448 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3449 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3450
3451 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3452 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3453
3454 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3455 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3456
3457 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3458 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3459
3460 VMX_LOG_SELREG(CS, "CS");
3461 VMX_LOG_SELREG(DS, "DS");
3462 VMX_LOG_SELREG(ES, "ES");
3463 VMX_LOG_SELREG(FS, "FS");
3464 VMX_LOG_SELREG(GS, "GS");
3465 VMX_LOG_SELREG(SS, "SS");
3466 VMX_LOG_SELREG(TR, "TR");
3467 VMX_LOG_SELREG(LDTR, "LDTR");
3468
3469 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3470 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3471 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3472 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3473#endif /* VBOX_STRICT */
3474 rc = VERR_VMX_INVALID_GUEST_STATE;
3475 break;
3476 }
3477
3478 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3479 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3480 default:
3481 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3482 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3483 break;
3484
3485 }
3486end:
3487
3488 /* Signal changes for the recompiler. */
3489 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3490
3491 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3492 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3493 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3494 {
3495 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3496 /* On the next entry we'll only sync the host context. */
3497 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3498 }
3499 else
3500 {
3501 /* On the next entry we'll sync everything. */
3502 /** @todo we can do better than this */
3503 /* Not in the VINF_PGM_CHANGE_MODE though! */
3504 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3505 }
3506
3507 /* translate into a less severe return code */
3508 if (rc == VERR_EM_INTERPRETER)
3509 rc = VINF_EM_RAW_EMULATE_INSTR;
3510 else
3511 /* Try to extract more information about what might have gone wrong here. */
3512 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3513 {
3514 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3515 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3516 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3517 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3518 }
3519
3520 /* Just set the correct state here instead of trying to catch every goto above. */
3521 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
3522
3523 STAM_STATS({
3524 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3525 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3526 });
3527 Log2(("X"));
3528 return rc;
3529}
3530
3531
3532/**
3533 * Enters the VT-x session
3534 *
3535 * @returns VBox status code.
3536 * @param pVM The VM to operate on.
3537 * @param pVCpu The VMCPU to operate on.
3538 * @param pCpu CPU info struct
3539 */
3540VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3541{
3542 Assert(pVM->hwaccm.s.vmx.fSupported);
3543
3544 unsigned cr4 = ASMGetCR4();
3545 if (!(cr4 & X86_CR4_VMXE))
3546 {
3547 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3548 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3549 }
3550
3551 /* Activate the VM Control Structure. */
3552 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3553 if (RT_FAILURE(rc))
3554 return rc;
3555
3556 pVCpu->hwaccm.s.fResumeVM = false;
3557 return VINF_SUCCESS;
3558}
3559
3560
3561/**
3562 * Leaves the VT-x session
3563 *
3564 * @returns VBox status code.
3565 * @param pVM The VM to operate on.
3566 * @param pVCpu The VMCPU to operate on.
3567 * @param pCtx CPU context
3568 */
3569VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3570{
3571 Assert(pVM->hwaccm.s.vmx.fSupported);
3572
3573 /* Save the guest debug state if necessary. */
3574 if (CPUMIsGuestDebugStateActive(pVCpu))
3575 {
3576 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3577
3578 /* Enable drx move intercepts again. */
3579 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3580 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3581 AssertRC(rc);
3582
3583 /* Resync the debug registers the next time. */
3584 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3585 }
3586 else
3587 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3588
3589 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3590 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3591 AssertRC(rc);
3592
3593 return VINF_SUCCESS;
3594}
3595
3596/**
3597 * Flush the TLB (EPT)
3598 *
3599 * @returns VBox status code.
3600 * @param pVM The VM to operate on.
3601 * @param pVCpu The VM CPU to operate on.
3602 * @param enmFlush Type of flush
3603 * @param GCPhys Physical address of the page to flush
3604 */
3605static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3606{
3607 uint64_t descriptor[2];
3608
3609 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3610 Assert(pVM->hwaccm.s.fNestedPaging);
3611 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3612 descriptor[1] = GCPhys;
3613 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3614 AssertRC(rc);
3615}
3616
3617#ifdef HWACCM_VTX_WITH_VPID
3618/**
3619 * Flush the TLB (EPT)
3620 *
3621 * @returns VBox status code.
3622 * @param pVM The VM to operate on.
3623 * @param pVCpu The VM CPU to operate on.
3624 * @param enmFlush Type of flush
3625 * @param GCPtr Virtual address of the page to flush
3626 */
3627static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3628{
3629#if HC_ARCH_BITS == 32
3630 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3631 if ( CPUMIsGuestInLongMode(pVCpu)
3632 && !VMX_IS_64BIT_HOST_MODE())
3633 {
3634 pVCpu->hwaccm.s.fForceTLBFlush = true;
3635 }
3636 else
3637#endif
3638 {
3639 uint64_t descriptor[2];
3640
3641 Assert(pVM->hwaccm.s.vmx.fVPID);
3642 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3643 descriptor[1] = GCPtr;
3644 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3645 AssertRC(rc);
3646 }
3647}
3648#endif /* HWACCM_VTX_WITH_VPID */
3649
3650/**
3651 * Invalidates a guest page
3652 *
3653 * @returns VBox status code.
3654 * @param pVM The VM to operate on.
3655 * @param pVCpu The VM CPU to operate on.
3656 * @param GCVirt Page to invalidate
3657 */
3658VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3659{
3660 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3661
3662 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3663
3664 /* Only relevant if we want to use VPID.
3665 * In the nested paging case we still see such calls, but
3666 * can safely ignore them. (e.g. after cr3 updates)
3667 */
3668#ifdef HWACCM_VTX_WITH_VPID
3669 /* Skip it if a TLB flush is already pending. */
3670 if ( !fFlushPending
3671 && pVM->hwaccm.s.vmx.fVPID)
3672 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3673#endif /* HWACCM_VTX_WITH_VPID */
3674
3675 return VINF_SUCCESS;
3676}
3677
3678/**
3679 * Invalidates a guest page by physical address
3680 *
3681 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3682 *
3683 * @returns VBox status code.
3684 * @param pVM The VM to operate on.
3685 * @param pVCpu The VM CPU to operate on.
3686 * @param GCPhys Page to invalidate
3687 */
3688VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3689{
3690 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3691
3692 Assert(pVM->hwaccm.s.fNestedPaging);
3693
3694 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3695
3696 /* Skip it if a TLB flush is already pending. */
3697 if (!fFlushPending)
3698 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3699
3700 return VINF_SUCCESS;
3701}
3702
3703/**
3704 * Report world switch error and dump some useful debug info
3705 *
3706 * @param pVM The VM to operate on.
3707 * @param pVCpu The VMCPU to operate on.
3708 * @param rc Return code
3709 * @param pCtx Current CPU context (not updated)
3710 */
3711static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3712{
3713 switch (rc)
3714 {
3715 case VERR_VMX_INVALID_VMXON_PTR:
3716 AssertFailed();
3717 break;
3718
3719 case VERR_VMX_UNABLE_TO_START_VM:
3720 case VERR_VMX_UNABLE_TO_RESUME_VM:
3721 {
3722 int rc;
3723 RTCCUINTREG exitReason, instrError;
3724
3725 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3726 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3727 AssertRC(rc);
3728 if (rc == VINF_SUCCESS)
3729 {
3730 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3731 Log(("Current stack %08x\n", &rc));
3732
3733 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3734 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3735
3736#ifdef VBOX_STRICT
3737 RTGDTR gdtr;
3738 PX86DESCHC pDesc;
3739 RTCCUINTREG val;
3740
3741 ASMGetGDTR(&gdtr);
3742
3743 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3744 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3745 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3746 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3747 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3748 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3749 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3750 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3751 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3752 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3753
3754 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3755 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3756
3757 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3758 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3759
3760 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3761 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3762
3763 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3764 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3765
3766 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3767 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3768
3769 if (val < gdtr.cbGdt)
3770 {
3771 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3772 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3773 }
3774
3775 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3776 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3777 if (val < gdtr.cbGdt)
3778 {
3779 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3780 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3781 }
3782
3783 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
3784 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3785 if (val < gdtr.cbGdt)
3786 {
3787 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3788 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3789 }
3790
3791 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
3792 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
3793 if (val < gdtr.cbGdt)
3794 {
3795 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3796 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3797 }
3798
3799 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
3800 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
3801 if (val < gdtr.cbGdt)
3802 {
3803 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3804 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3805 }
3806
3807 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
3808 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
3809 if (val < gdtr.cbGdt)
3810 {
3811 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3812 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3813 }
3814
3815 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
3816 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
3817 if (val < gdtr.cbGdt)
3818 {
3819 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3820 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3821 }
3822
3823 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3824 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
3825
3826 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3827 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
3828 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3829 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
3830
3831 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
3832 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3833
3834 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3835 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
3836
3837 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3838 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
3839
3840 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3841 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
3842 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3843 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
3844
3845# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3846 if (VMX_IS_64BIT_HOST_MODE())
3847 {
3848 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
3849 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
3850 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3851 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3852 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3853 }
3854# endif
3855#endif /* VBOX_STRICT */
3856 }
3857 break;
3858 }
3859
3860 default:
3861 /* impossible */
3862 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
3863 break;
3864 }
3865}
3866
3867#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3868/**
3869 * Prepares for and executes VMLAUNCH (64 bits guest mode)
3870 *
3871 * @returns VBox status code
3872 * @param fResume vmlauch/vmresume
3873 * @param pCtx Guest context
3874 * @param pCache VMCS cache
3875 * @param pVM The VM to operate on.
3876 * @param pVCpu The VMCPU to operate on.
3877 */
3878DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
3879{
3880 uint32_t aParam[6];
3881 PHWACCM_CPUINFO pCpu;
3882 RTHCPHYS pPageCpuPhys;
3883 int rc;
3884
3885 pCpu = HWACCMR0GetCurrentCpu();
3886 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3887
3888#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3889 pCache->uPos = 1;
3890 pCache->interPD = PGMGetInterPaeCR3(pVM);
3891 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
3892#endif
3893
3894#ifdef DEBUG
3895 pCache->TestIn.pPageCpuPhys = 0;
3896 pCache->TestIn.pVMCSPhys = 0;
3897 pCache->TestIn.pCache = 0;
3898 pCache->TestOut.pVMCSPhys = 0;
3899 pCache->TestOut.pCache = 0;
3900 pCache->TestOut.pCtx = 0;
3901 pCache->TestOut.eflags = 0;
3902#endif
3903
3904 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
3905 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
3906 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
3907 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
3908 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
3909 aParam[5] = 0;
3910
3911#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3912 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
3913 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
3914#endif
3915 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
3916
3917#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3918 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
3919 Assert(pCtx->dr[4] == 10);
3920 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
3921#endif
3922
3923#ifdef DEBUG
3924 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
3925 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
3926 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
3927 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
3928 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
3929 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
3930 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
3931#endif
3932 return rc;
3933}
3934
3935/**
3936 * Executes the specified handler in 64 mode
3937 *
3938 * @returns VBox status code.
3939 * @param pVM The VM to operate on.
3940 * @param pVCpu The VMCPU to operate on.
3941 * @param pCtx Guest context
3942 * @param pfnHandler RC handler
3943 * @param cbParam Number of parameters
3944 * @param paParam Array of 32 bits parameters
3945 */
3946VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
3947{
3948 int rc, rc2;
3949 PHWACCM_CPUINFO pCpu;
3950 RTHCPHYS pPageCpuPhys;
3951
3952 /* @todo This code is not guest SMP safe (hyper stack) */
3953 AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
3954 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
3955 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
3956 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
3957
3958#ifdef VBOX_STRICT
3959 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
3960 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
3961
3962 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
3963 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
3964#endif
3965
3966 pCpu = HWACCMR0GetCurrentCpu();
3967 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3968
3969 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3970 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3971
3972 /* Leave VMX Root Mode. */
3973 VMXDisable();
3974
3975 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3976
3977 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
3978 CPUMSetHyperEIP(pVCpu, pfnHandler);
3979 for (int i=(int)cbParam-1;i>=0;i--)
3980 CPUMPushHyper(pVCpu, paParam[i]);
3981
3982 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3983 /* Call switcher. */
3984 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
3985 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3986
3987 /* Make sure the VMX instructions don't cause #UD faults. */
3988 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
3989
3990 /* Enter VMX Root Mode */
3991 rc2 = VMXEnable(pPageCpuPhys);
3992 if (RT_FAILURE(rc2))
3993 {
3994 if (pVM)
3995 VMXR0CheckError(pVM, pVCpu, rc2);
3996 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3997 return VERR_VMX_VMXON_FAILED;
3998 }
3999
4000 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4001 AssertRCReturn(rc2, rc2);
4002#ifdef RT_OS_WINDOWS
4003 Assert(ASMGetFlags() & X86_EFL_IF);
4004#else
4005 Assert(!(ASMGetFlags() & X86_EFL_IF));
4006#endif
4007 return rc;
4008}
4009
4010#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4011
4012
4013#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4014/**
4015 * Executes VMWRITE
4016 *
4017 * @returns VBox status code
4018 * @param pVCpu The VMCPU to operate on.
4019 * @param idxField VMCS index
4020 * @param u64Val 16, 32 or 64 bits value
4021 */
4022VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4023{
4024 int rc;
4025
4026 switch (idxField)
4027 {
4028 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4029 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4030 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4031 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4032 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4033 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4034 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4035 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4036 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4037 case VMX_VMCS_GUEST_PDPTR0_FULL:
4038 case VMX_VMCS_GUEST_PDPTR1_FULL:
4039 case VMX_VMCS_GUEST_PDPTR2_FULL:
4040 case VMX_VMCS_GUEST_PDPTR3_FULL:
4041 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4042 case VMX_VMCS_GUEST_EFER_FULL:
4043 case VMX_VMCS_CTRL_EPTP_FULL:
4044 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4045 rc = VMXWriteVMCS32(idxField, u64Val);
4046 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4047 AssertRC(rc);
4048 return rc;
4049
4050 case VMX_VMCS64_GUEST_LDTR_BASE:
4051 case VMX_VMCS64_GUEST_TR_BASE:
4052 case VMX_VMCS64_GUEST_GDTR_BASE:
4053 case VMX_VMCS64_GUEST_IDTR_BASE:
4054 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4055 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4056 case VMX_VMCS64_GUEST_CR0:
4057 case VMX_VMCS64_GUEST_CR4:
4058 case VMX_VMCS64_GUEST_CR3:
4059 case VMX_VMCS64_GUEST_DR7:
4060 case VMX_VMCS64_GUEST_RIP:
4061 case VMX_VMCS64_GUEST_RSP:
4062 case VMX_VMCS64_GUEST_CS_BASE:
4063 case VMX_VMCS64_GUEST_DS_BASE:
4064 case VMX_VMCS64_GUEST_ES_BASE:
4065 case VMX_VMCS64_GUEST_FS_BASE:
4066 case VMX_VMCS64_GUEST_GS_BASE:
4067 case VMX_VMCS64_GUEST_SS_BASE:
4068 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4069 if (u64Val >> 32ULL)
4070 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4071 else
4072 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4073
4074 return rc;
4075
4076 default:
4077 AssertMsgFailed(("Unexpected field %x\n", idxField));
4078 return VERR_INVALID_PARAMETER;
4079 }
4080}
4081
4082/**
4083 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4084 *
4085 * @param pVCpu The VMCPU to operate on.
4086 * @param idxField VMCS field
4087 * @param u64Val Value
4088 */
4089VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4090{
4091 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4092
4093 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4094
4095 /* Make sure there are no duplicates. */
4096 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4097 {
4098 if (pCache->Write.aField[i] == idxField)
4099 {
4100 pCache->Write.aFieldVal[i] = u64Val;
4101 return VINF_SUCCESS;
4102 }
4103 }
4104
4105 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4106 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4107 pCache->Write.cValidEntries++;
4108 return VINF_SUCCESS;
4109}
4110
4111#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4112
4113#ifdef VBOX_STRICT
4114static bool vmxR0IsValidReadField(uint32_t idxField)
4115{
4116 switch(idxField)
4117 {
4118 case VMX_VMCS64_GUEST_RIP:
4119 case VMX_VMCS64_GUEST_RSP:
4120 case VMX_VMCS_GUEST_RFLAGS:
4121 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4122 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4123 case VMX_VMCS64_GUEST_CR0:
4124 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4125 case VMX_VMCS64_GUEST_CR4:
4126 case VMX_VMCS64_GUEST_DR7:
4127 case VMX_VMCS32_GUEST_SYSENTER_CS:
4128 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4129 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4130 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4131 case VMX_VMCS64_GUEST_GDTR_BASE:
4132 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4133 case VMX_VMCS64_GUEST_IDTR_BASE:
4134 case VMX_VMCS16_GUEST_FIELD_CS:
4135 case VMX_VMCS32_GUEST_CS_LIMIT:
4136 case VMX_VMCS64_GUEST_CS_BASE:
4137 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4138 case VMX_VMCS16_GUEST_FIELD_DS:
4139 case VMX_VMCS32_GUEST_DS_LIMIT:
4140 case VMX_VMCS64_GUEST_DS_BASE:
4141 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4142 case VMX_VMCS16_GUEST_FIELD_ES:
4143 case VMX_VMCS32_GUEST_ES_LIMIT:
4144 case VMX_VMCS64_GUEST_ES_BASE:
4145 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4146 case VMX_VMCS16_GUEST_FIELD_FS:
4147 case VMX_VMCS32_GUEST_FS_LIMIT:
4148 case VMX_VMCS64_GUEST_FS_BASE:
4149 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4150 case VMX_VMCS16_GUEST_FIELD_GS:
4151 case VMX_VMCS32_GUEST_GS_LIMIT:
4152 case VMX_VMCS64_GUEST_GS_BASE:
4153 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4154 case VMX_VMCS16_GUEST_FIELD_SS:
4155 case VMX_VMCS32_GUEST_SS_LIMIT:
4156 case VMX_VMCS64_GUEST_SS_BASE:
4157 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4158 case VMX_VMCS16_GUEST_FIELD_LDTR:
4159 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4160 case VMX_VMCS64_GUEST_LDTR_BASE:
4161 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4162 case VMX_VMCS16_GUEST_FIELD_TR:
4163 case VMX_VMCS32_GUEST_TR_LIMIT:
4164 case VMX_VMCS64_GUEST_TR_BASE:
4165 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4166 case VMX_VMCS32_RO_EXIT_REASON:
4167 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4168 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4169 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4170 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4171 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4172 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4173 case VMX_VMCS32_RO_IDT_INFO:
4174 case VMX_VMCS32_RO_IDT_ERRCODE:
4175 case VMX_VMCS64_GUEST_CR3:
4176 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4177 return true;
4178 }
4179 return false;
4180}
4181
4182static bool vmxR0IsValidWriteField(uint32_t idxField)
4183{
4184 switch(idxField)
4185 {
4186 case VMX_VMCS64_GUEST_LDTR_BASE:
4187 case VMX_VMCS64_GUEST_TR_BASE:
4188 case VMX_VMCS64_GUEST_GDTR_BASE:
4189 case VMX_VMCS64_GUEST_IDTR_BASE:
4190 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4191 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4192 case VMX_VMCS64_GUEST_CR0:
4193 case VMX_VMCS64_GUEST_CR4:
4194 case VMX_VMCS64_GUEST_CR3:
4195 case VMX_VMCS64_GUEST_DR7:
4196 case VMX_VMCS64_GUEST_RIP:
4197 case VMX_VMCS64_GUEST_RSP:
4198 case VMX_VMCS64_GUEST_CS_BASE:
4199 case VMX_VMCS64_GUEST_DS_BASE:
4200 case VMX_VMCS64_GUEST_ES_BASE:
4201 case VMX_VMCS64_GUEST_FS_BASE:
4202 case VMX_VMCS64_GUEST_GS_BASE:
4203 case VMX_VMCS64_GUEST_SS_BASE:
4204 return true;
4205 }
4206 return false;
4207}
4208
4209#endif
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette