VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 19818

Last change on this file since 19818 was 19818, checked in by vboxsync, 16 years ago

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1/* $Id: HWVMXR0.cpp 19818 2009-05-19 12:17:57Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/param.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/string.h>
42#include "HWVMXR0.h"
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47#if defined(RT_ARCH_AMD64)
48# define VMX_IS_64BIT_HOST_MODE() (true)
49#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
50# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
51#else
52# define VMX_IS_64BIT_HOST_MODE() (false)
53#endif
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58/* IO operation lookup arrays. */
59static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
60static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
61
62#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
63/** See HWACCMR0A.asm. */
64extern "C" uint32_t g_fVMXIs64bitHost;
65#endif
66
67/*******************************************************************************
68* Local Functions *
69*******************************************************************************/
70static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
71static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
72static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
73static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
74static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
75static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
76static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
77#ifdef VBOX_STRICT
78static bool vmxR0IsValidReadField(uint32_t idxField);
79static bool vmxR0IsValidWriteField(uint32_t idxField);
80#endif
81
82static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
83{
84 if (rc == VERR_VMX_GENERIC)
85 {
86 RTCCUINTREG instrError;
87
88 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
89 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
90 }
91 pVM->hwaccm.s.lLastError = rc;
92}
93
94/**
95 * Sets up and activates VT-x on the current CPU
96 *
97 * @returns VBox status code.
98 * @param pCpu CPU info struct
99 * @param pVM The VM to operate on. (can be NULL after a resume!!)
100 * @param pvPageCpu Pointer to the global cpu page
101 * @param pPageCpuPhys Physical address of the global cpu page
102 */
103VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
104{
105 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
106 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
107
108#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
109 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
110#endif
111 if (pVM)
112 {
113 /* Set revision dword at the beginning of the VMXON structure. */
114 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
115 }
116
117 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
118 * (which can have very bad consequences!!!)
119 */
120
121 /* Make sure the VMX instructions don't cause #UD faults. */
122 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
123
124 /* Enter VMX Root Mode */
125 int rc = VMXEnable(pPageCpuPhys);
126 if (RT_FAILURE(rc))
127 {
128 if (pVM)
129 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
130 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
131 return VERR_VMX_VMXON_FAILED;
132 }
133 return VINF_SUCCESS;
134}
135
136/**
137 * Deactivates VT-x on the current CPU
138 *
139 * @returns VBox status code.
140 * @param pCpu CPU info struct
141 * @param pvPageCpu Pointer to the global cpu page
142 * @param pPageCpuPhys Physical address of the global cpu page
143 */
144VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
145{
146 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
147 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
148
149 /* Leave VMX Root Mode. */
150 VMXDisable();
151
152 /* And clear the X86_CR4_VMXE bit */
153 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
154
155#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
156 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
157#endif
158 return VINF_SUCCESS;
159}
160
161/**
162 * Does Ring-0 per VM VT-x init.
163 *
164 * @returns VBox status code.
165 * @param pVM The VM to operate on.
166 */
167VMMR0DECL(int) VMXR0InitVM(PVM pVM)
168{
169 int rc;
170
171#ifdef LOG_ENABLED
172 SUPR0Printf("VMXR0InitVM %x\n", pVM);
173#endif
174
175 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
176
177 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
178 {
179 /* Allocate one page for the virtual APIC mmio cache. */
180 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
181 AssertRC(rc);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
186 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
187 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
188 }
189 else
190 {
191 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
192 pVM->hwaccm.s.vmx.pAPIC = 0;
193 pVM->hwaccm.s.vmx.pAPICPhys = 0;
194 }
195
196 /* Allocate the MSR bitmap if this feature is supported. */
197 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
198 {
199 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
200 AssertRC(rc);
201 if (RT_FAILURE(rc))
202 return rc;
203
204 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
205 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
206 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
207 }
208
209#ifdef VBOX_WITH_CRASHDUMP_MAGIC
210 {
211 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
212 AssertRC(rc);
213 if (RT_FAILURE(rc))
214 return rc;
215
216 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
217 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
218
219 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
220 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
221 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
222 }
223#endif
224
225 /* Allocate VMCBs for all guest CPUs. */
226 for (unsigned i=0;i<pVM->cCPUs;i++)
227 {
228 PVMCPU pVCpu = &pVM->aCpus[i];
229
230 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
231
232 /* Allocate one page for the VM control structure (VMCS). */
233 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
234 AssertRC(rc);
235 if (RT_FAILURE(rc))
236 return rc;
237
238 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
239 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
240 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
241
242 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
243 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
244
245 /* Current guest paging mode. */
246 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
247
248#ifdef LOG_ENABLED
249 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
250#endif
251 }
252
253 return VINF_SUCCESS;
254}
255
256/**
257 * Does Ring-0 per VM VT-x termination.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262VMMR0DECL(int) VMXR0TermVM(PVM pVM)
263{
264 for (unsigned i=0;i<pVM->cCPUs;i++)
265 {
266 if (pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
267 {
268 RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, false);
269 pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
270 pVM->aCpus[i].hwaccm.s.vmx.pVMCS = 0;
271 pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys = 0;
272 }
273 }
274 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
275 {
276 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
277 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
278 pVM->hwaccm.s.vmx.pAPIC = 0;
279 pVM->hwaccm.s.vmx.pAPICPhys = 0;
280 }
281 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
282 {
283 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
284 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
285 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
286 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
287 }
288#ifdef VBOX_WITH_CRASHDUMP_MAGIC
289 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
290 {
291 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
292 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
293 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
294 pVM->hwaccm.s.vmx.pScratch = 0;
295 pVM->hwaccm.s.vmx.pScratchPhys = 0;
296 }
297#endif
298 return VINF_SUCCESS;
299}
300
301/**
302 * Sets up VT-x for the specified VM
303 *
304 * @returns VBox status code.
305 * @param pVM The VM to operate on.
306 */
307VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
308{
309 int rc = VINF_SUCCESS;
310 uint32_t val;
311
312 AssertReturn(pVM, VERR_INVALID_PARAMETER);
313
314 for (unsigned i=0;i<pVM->cCPUs;i++)
315 {
316 PVMCPU pVCpu = &pVM->aCpus[i];
317
318 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
319
320 /* Set revision dword at the beginning of the VMCS structure. */
321 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
322
323 /* Clear VM Control Structure. */
324 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
325 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
326 if (RT_FAILURE(rc))
327 goto vmx_end;
328
329 /* Activate the VM Control Structure. */
330 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
331 if (RT_FAILURE(rc))
332 goto vmx_end;
333
334 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
335 * Set required bits to one and zero according to the MSR capabilities.
336 */
337 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
338 /* External and non-maskable interrupts cause VM-exits. */
339 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
340 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
341
342 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
343 AssertRC(rc);
344
345 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
346 * Set required bits to one and zero according to the MSR capabilities.
347 */
348 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
349 /* Program which event cause VM-exits and which features we want to use. */
350 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
351 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
352 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
353 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
354 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
355 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
356
357 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
358 if (!pVM->hwaccm.s.fNestedPaging)
359 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
360 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
361 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
362
363 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
364 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
365 {
366 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
367 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
368 Assert(pVM->hwaccm.s.vmx.pAPIC);
369 }
370 else
371 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
372 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
373
374#ifdef VBOX_WITH_VTX_MSR_BITMAPS
375 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
376 {
377 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
378 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
379 }
380#endif
381
382 /* We will use the secondary control if it's present. */
383 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
384
385 /* Mask away the bits that the CPU doesn't support */
386 /** @todo make sure they don't conflict with the above requirements. */
387 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
388 pVCpu->hwaccm.s.vmx.proc_ctls = val;
389
390 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
391 AssertRC(rc);
392
393 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
394 {
395 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
396 * Set required bits to one and zero according to the MSR capabilities.
397 */
398 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
399 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
400
401#ifdef HWACCM_VTX_WITH_EPT
402 if (pVM->hwaccm.s.fNestedPaging)
403 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
404#endif /* HWACCM_VTX_WITH_EPT */
405#ifdef HWACCM_VTX_WITH_VPID
406 else
407 if (pVM->hwaccm.s.vmx.fVPID)
408 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
409#endif /* HWACCM_VTX_WITH_VPID */
410
411 /* Mask away the bits that the CPU doesn't support */
412 /** @todo make sure they don't conflict with the above requirements. */
413 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
414
415 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
416 AssertRC(rc);
417 }
418
419 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
420 * Set required bits to one and zero according to the MSR capabilities.
421 */
422 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
423 AssertRC(rc);
424
425 /* Forward all exception except #NM & #PF to the guest.
426 * We always need to check pagefaults since our shadow page table can be out of sync.
427 * And we always lazily sync the FPU & XMM state.
428 */
429
430 /** @todo Possible optimization:
431 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
432 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
433 * registers ourselves of course.
434 *
435 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
436 */
437
438 /* Don't filter page faults; all of them should cause a switch. */
439 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
441 AssertRC(rc);
442
443 /* Init TSC offset to zero. */
444 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
445 AssertRC(rc);
446
447 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
448 AssertRC(rc);
449
450 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
451 AssertRC(rc);
452
453 /* Set the MSR bitmap address. */
454 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
455 {
456 /* Optional */
457 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
458 AssertRC(rc);
459 }
460
461 /* Clear MSR controls. */
462 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
463 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
464 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
465 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
467 AssertRC(rc);
468
469 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
470 {
471 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
472 /* Optional */
473 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
474 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
475 AssertRC(rc);
476 }
477
478 /* Set link pointer to -1. Not currently used. */
479 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
480 AssertRC(rc);
481
482 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
483 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
484 AssertRC(rc);
485
486 /* Configure the VMCS read cache. */
487 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
488
489 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
490 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
491 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
492 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
493 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
494 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
495 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
496 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
497 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
498 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
499 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
500 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
501 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
502 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
503 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
504 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
505
506 VMX_SETUP_SELREG(ES, pCache);
507 VMX_SETUP_SELREG(SS, pCache);
508 VMX_SETUP_SELREG(CS, pCache);
509 VMX_SETUP_SELREG(DS, pCache);
510 VMX_SETUP_SELREG(FS, pCache);
511 VMX_SETUP_SELREG(GS, pCache);
512 VMX_SETUP_SELREG(LDTR, pCache);
513 VMX_SETUP_SELREG(TR, pCache);
514
515 /* Status code VMCS reads. */
516 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
517 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
518 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
525
526 if (pVM->hwaccm.s.fNestedPaging)
527 {
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
530 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
531 }
532 else
533 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
534 } /* for each VMCPU */
535
536 /* Choose the right TLB setup function. */
537 if (pVM->hwaccm.s.fNestedPaging)
538 {
539 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
540
541 /* Default values for flushing. */
542 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
543 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
544
545 /* If the capabilities specify we can do more, then make use of it. */
546 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
547 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
548 else
549 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
550 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
551
552 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
553 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
554 }
555#ifdef HWACCM_VTX_WITH_VPID
556 else
557 if (pVM->hwaccm.s.vmx.fVPID)
558 {
559 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
560
561 /* Default values for flushing. */
562 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
563 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
564
565 /* If the capabilities specify we can do more, then make use of it. */
566 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
567 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
568 else
569 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
570 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
571
572 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
574 }
575#endif /* HWACCM_VTX_WITH_VPID */
576 else
577 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
578
579vmx_end:
580 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
581 return rc;
582}
583
584
585/**
586 * Injects an event (trap or external interrupt)
587 *
588 * @returns VBox status code.
589 * @param pVM The VM to operate on.
590 * @param pVCpu The VMCPU to operate on.
591 * @param pCtx CPU Context
592 * @param intInfo VMX interrupt info
593 * @param cbInstr Opcode length of faulting instruction
594 * @param errCode Error code (optional)
595 */
596static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
597{
598 int rc;
599 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
600
601#ifdef VBOX_STRICT
602 if (iGate == 0xE)
603 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
604 else
605 if (iGate < 0x20)
606 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
607 else
608 {
609 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
610 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
611 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
612 }
613#endif
614
615#ifdef HWACCM_VMX_EMULATE_REALMODE
616 if (CPUMIsGuestInRealModeEx(pCtx))
617 {
618 RTGCPHYS GCPhysHandler;
619 uint16_t offset, ip;
620 RTSEL sel;
621
622 /* Injecting events doesn't work right with real mode emulation.
623 * (#GP if we try to inject external hardware interrupts)
624 * Inject the interrupt or trap directly instead.
625 *
626 * ASSUMES no access handlers for the bits we read or write below (should be safe).
627 */
628 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
629
630 /* Check if the interrupt handler is present. */
631 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
632 {
633 Log(("IDT cbIdt violation\n"));
634 if (iGate != X86_XCPT_DF)
635 {
636 RTGCUINTPTR intInfo;
637
638 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
639 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
640 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
641 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
642
643 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
644 }
645 Log(("Triple fault -> reset the VM!\n"));
646 return VINF_EM_RESET;
647 }
648 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
649 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
650 || iGate == 4)
651 {
652 ip = pCtx->ip + cbInstr;
653 }
654 else
655 ip = pCtx->ip;
656
657 /* Read the selector:offset pair of the interrupt handler. */
658 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
659 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
660 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
661
662 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
663
664 /* Construct the stack frame. */
665 /** @todo should check stack limit. */
666 pCtx->sp -= 2;
667 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
668 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
669 pCtx->sp -= 2;
670 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
671 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
672 pCtx->sp -= 2;
673 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
674 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
675
676 /* Update the CPU state for executing the handler. */
677 pCtx->rip = offset;
678 pCtx->cs = sel;
679 pCtx->csHid.u64Base = sel << 4;
680 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
681
682 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
683 return VINF_SUCCESS;
684 }
685#endif /* HWACCM_VMX_EMULATE_REALMODE */
686
687 /* Set event injection state. */
688 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
689
690 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
691 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
692
693 AssertRC(rc);
694 return rc;
695}
696
697
698/**
699 * Checks for pending guest interrupts and injects them
700 *
701 * @returns VBox status code.
702 * @param pVM The VM to operate on.
703 * @param pVCpu The VMCPU to operate on.
704 * @param pCtx CPU Context
705 */
706static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
707{
708 int rc;
709
710 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
711 if (pVCpu->hwaccm.s.Event.fPending)
712 {
713 Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
714 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
715 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
716 AssertRC(rc);
717
718 pVCpu->hwaccm.s.Event.fPending = false;
719 return VINF_SUCCESS;
720 }
721
722 if (pVM->hwaccm.s.fInjectNMI)
723 {
724 RTGCUINTPTR intInfo;
725
726 intInfo = X86_XCPT_NMI;
727 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
728 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
729
730 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
731 AssertRC(rc);
732
733 pVM->hwaccm.s.fInjectNMI = false;
734 return VINF_SUCCESS;
735 }
736
737 /* When external interrupts are pending, we should exit the VM when IF is set. */
738 if ( !TRPMHasTrap(pVCpu)
739 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
740 {
741 if (!(pCtx->eflags.u32 & X86_EFL_IF))
742 {
743 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
744 {
745 LogFlow(("Enable irq window exit!\n"));
746 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
747 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
748 AssertRC(rc);
749 }
750 /* else nothing to do but wait */
751 }
752 else
753 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
754 {
755 uint8_t u8Interrupt;
756
757 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
758 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
759 if (RT_SUCCESS(rc))
760 {
761 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
762 AssertRC(rc);
763 }
764 else
765 {
766 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
767 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
768 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
769 /* Just continue */
770 }
771 }
772 else
773 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
774 }
775
776#ifdef VBOX_STRICT
777 if (TRPMHasTrap(pVCpu))
778 {
779 uint8_t u8Vector;
780 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
781 AssertRC(rc);
782 }
783#endif
784
785 if ( (pCtx->eflags.u32 & X86_EFL_IF)
786 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
787 && TRPMHasTrap(pVCpu)
788 )
789 {
790 uint8_t u8Vector;
791 int rc;
792 TRPMEVENT enmType;
793 RTGCUINTPTR intInfo;
794 RTGCUINT errCode;
795
796 /* If a new event is pending, then dispatch it now. */
797 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
798 AssertRC(rc);
799 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
800 Assert(enmType != TRPM_SOFTWARE_INT);
801
802 /* Clear the pending trap. */
803 rc = TRPMResetTrap(pVCpu);
804 AssertRC(rc);
805
806 intInfo = u8Vector;
807 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
808
809 if (enmType == TRPM_TRAP)
810 {
811 switch (u8Vector) {
812 case 8:
813 case 10:
814 case 11:
815 case 12:
816 case 13:
817 case 14:
818 case 17:
819 /* Valid error codes. */
820 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
821 break;
822 default:
823 break;
824 }
825 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
826 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
827 else
828 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
829 }
830 else
831 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
832
833 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
834 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
835 AssertRC(rc);
836 } /* if (interrupts can be dispatched) */
837
838 return VINF_SUCCESS;
839}
840
841/**
842 * Save the host state
843 *
844 * @returns VBox status code.
845 * @param pVM The VM to operate on.
846 * @param pVCpu The VMCPU to operate on.
847 */
848VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
849{
850 int rc = VINF_SUCCESS;
851
852 /*
853 * Host CPU Context
854 */
855 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
856 {
857 RTIDTR idtr;
858 RTGDTR gdtr;
859 RTSEL SelTR;
860 PX86DESCHC pDesc;
861 uintptr_t trBase;
862 RTSEL cs;
863 RTSEL ss;
864 uint64_t cr3;
865
866 /* Control registers */
867 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
868#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
869 if (VMX_IS_64BIT_HOST_MODE())
870 {
871 cr3 = hwaccmR0Get64bitCR3();
872 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
873 }
874 else
875#endif
876 {
877 cr3 = ASMGetCR3();
878 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
879 }
880 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
881 AssertRC(rc);
882 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
883 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
884 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
885
886 /* Selector registers. */
887#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
888 if (VMX_IS_64BIT_HOST_MODE())
889 {
890 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
891 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
892 }
893 else
894 {
895 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
896 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
897 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
898 }
899#else
900 cs = ASMGetCS();
901 ss = ASMGetSS();
902#endif
903 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
904 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
905 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
906 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
907 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
908 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
909#if HC_ARCH_BITS == 32
910 if (!VMX_IS_64BIT_HOST_MODE())
911 {
912 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
913 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
914 }
915#endif
916 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
917 SelTR = ASMGetTR();
918 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
919 AssertRC(rc);
920 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
921 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
922 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
923 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
924 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
925 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
926 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
927
928 /* GDTR & IDTR */
929#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
930 if (VMX_IS_64BIT_HOST_MODE())
931 {
932 X86XDTR64 gdtr64, idtr64;
933 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
934 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
935 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
936 AssertRC(rc);
937 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
938 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
939 gdtr.cbGdt = gdtr64.cb;
940 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
941 }
942 else
943#endif
944 {
945 ASMGetGDTR(&gdtr);
946 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
947 ASMGetIDTR(&idtr);
948 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
949 AssertRC(rc);
950 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
951 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
952 }
953
954
955 /* Save the base address of the TR selector. */
956 if (SelTR > gdtr.cbGdt)
957 {
958 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
959 return VERR_VMX_INVALID_HOST_STATE;
960 }
961
962#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
963 if (VMX_IS_64BIT_HOST_MODE())
964 {
965 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
966 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
967 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
968 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
969 AssertRC(rc);
970 }
971 else
972#endif
973 {
974 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
975#if HC_ARCH_BITS == 64
976 trBase = X86DESC64_BASE(*pDesc);
977#else
978 trBase = X86DESC_BASE(*pDesc);
979#endif
980 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
981 AssertRC(rc);
982 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
983 }
984
985 /* FS and GS base. */
986#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
987 if (VMX_IS_64BIT_HOST_MODE())
988 {
989 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
990 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
991 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
992 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
993 }
994#endif
995 AssertRC(rc);
996
997 /* Sysenter MSRs. */
998 /** @todo expensive!! */
999 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1000 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1001#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1002 if (VMX_IS_64BIT_HOST_MODE())
1003 {
1004 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1005 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1006 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1007 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1008 }
1009 else
1010 {
1011 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1012 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1013 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1014 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1015 }
1016#elif HC_ARCH_BITS == 32
1017 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1018 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1019 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1020 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1021#else
1022 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1023 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1024 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1025 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1026#endif
1027 AssertRC(rc);
1028
1029#if 0 /* @todo deal with 32/64 */
1030 /* Restore the host EFER - on CPUs that support it. */
1031 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1032 {
1033 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1034 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1035 AssertRC(rc);
1036 }
1037#endif
1038 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1039 }
1040 return rc;
1041}
1042
1043/**
1044 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1045 *
1046 * @param pVM The VM to operate on.
1047 * @param pVCpu The VMCPU to operate on.
1048 * @param pCtx Guest context
1049 */
1050static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1051{
1052 if (CPUMIsGuestInPAEModeEx(pCtx))
1053 {
1054 X86PDPE Pdpe;
1055
1056 for (unsigned i=0;i<4;i++)
1057 {
1058 Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1059 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1060 AssertRC(rc);
1061 }
1062 }
1063}
1064
1065/**
1066 * Update the exception bitmap according to the current CPU state
1067 *
1068 * @param pVM The VM to operate on.
1069 * @param pVCpu The VMCPU to operate on.
1070 * @param pCtx Guest context
1071 */
1072static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1073{
1074 uint32_t u32TrapMask;
1075 Assert(pCtx);
1076
1077 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1078#ifndef DEBUG
1079 if (pVM->hwaccm.s.fNestedPaging)
1080 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1081#endif
1082
1083 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1084 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1085 && !(pCtx->cr0 & X86_CR0_NE)
1086 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1087 {
1088 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1089 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1090 }
1091
1092#ifdef DEBUG /* till after branching, enable it by default then. */
1093 /* Intercept X86_XCPT_DB if stepping is enabled */
1094 if (DBGFIsStepping(pVCpu))
1095 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1096 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1097 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1098#endif
1099
1100#ifdef VBOX_STRICT
1101 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1102#endif
1103
1104# ifdef HWACCM_VMX_EMULATE_REALMODE
1105 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1106 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1107 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1108# endif /* HWACCM_VMX_EMULATE_REALMODE */
1109
1110 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1111 AssertRC(rc);
1112}
1113
1114/**
1115 * Loads the guest state
1116 *
1117 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1118 *
1119 * @returns VBox status code.
1120 * @param pVM The VM to operate on.
1121 * @param pVCpu The VMCPU to operate on.
1122 * @param pCtx Guest context
1123 */
1124VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1125{
1126 int rc = VINF_SUCCESS;
1127 RTGCUINTPTR val;
1128 X86EFLAGS eflags;
1129
1130 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1131 * Set required bits to one and zero according to the MSR capabilities.
1132 */
1133 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1134 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1135 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1136#if 0 /* @todo deal with 32/64 */
1137 /* Required for the EFER write below, not supported on all CPUs. */
1138 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1139#endif
1140 /* 64 bits guest mode? */
1141 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1142 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1143 /* else Must be zero when AMD64 is not available. */
1144
1145 /* Mask away the bits that the CPU doesn't support */
1146 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1147 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1148 AssertRC(rc);
1149
1150 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1151 * Set required bits to one and zero according to the MSR capabilities.
1152 */
1153 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1154
1155 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1156#if 0 /* @todo deal with 32/64 */
1157 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1158#else
1159 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1160#endif
1161
1162#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1163 if (VMX_IS_64BIT_HOST_MODE())
1164 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1165 /* else: Must be zero when AMD64 is not available. */
1166#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1167 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1168 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1169 else
1170 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1171#endif
1172 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1173 /* Don't acknowledge external interrupts on VM-exit. */
1174 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1175 AssertRC(rc);
1176
1177 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1178 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1179 {
1180#ifdef HWACCM_VMX_EMULATE_REALMODE
1181 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1182 {
1183 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1184 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1185 {
1186 /* Correct weird requirements for switching to protected mode. */
1187 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1188 && enmGuestMode >= PGMMODE_PROTECTED)
1189 {
1190 /* Flush the recompiler code cache as it's not unlikely
1191 * the guest will rewrite code it will later execute in real
1192 * mode (OpenBSD 4.0 is one such example)
1193 */
1194 REMFlushTBs(pVM);
1195
1196 /* DPL of all hidden selector registers must match the current CPL (0). */
1197 pCtx->csHid.Attr.n.u2Dpl = 0;
1198 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1199
1200 pCtx->dsHid.Attr.n.u2Dpl = 0;
1201 pCtx->esHid.Attr.n.u2Dpl = 0;
1202 pCtx->fsHid.Attr.n.u2Dpl = 0;
1203 pCtx->gsHid.Attr.n.u2Dpl = 0;
1204 pCtx->ssHid.Attr.n.u2Dpl = 0;
1205
1206 /* The limit must correspond to the granularity bit. */
1207 if (!pCtx->csHid.Attr.n.u1Granularity)
1208 pCtx->csHid.u32Limit &= 0xffff;
1209 if (!pCtx->dsHid.Attr.n.u1Granularity)
1210 pCtx->dsHid.u32Limit &= 0xffff;
1211 if (!pCtx->esHid.Attr.n.u1Granularity)
1212 pCtx->esHid.u32Limit &= 0xffff;
1213 if (!pCtx->fsHid.Attr.n.u1Granularity)
1214 pCtx->fsHid.u32Limit &= 0xffff;
1215 if (!pCtx->gsHid.Attr.n.u1Granularity)
1216 pCtx->gsHid.u32Limit &= 0xffff;
1217 if (!pCtx->ssHid.Attr.n.u1Granularity)
1218 pCtx->ssHid.u32Limit &= 0xffff;
1219 }
1220 else
1221 /* Switching from protected mode to real mode. */
1222 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1223 && enmGuestMode == PGMMODE_REAL)
1224 {
1225 /* The limit must also be set to 0xffff. */
1226 pCtx->csHid.u32Limit = 0xffff;
1227 pCtx->dsHid.u32Limit = 0xffff;
1228 pCtx->esHid.u32Limit = 0xffff;
1229 pCtx->fsHid.u32Limit = 0xffff;
1230 pCtx->gsHid.u32Limit = 0xffff;
1231 pCtx->ssHid.u32Limit = 0xffff;
1232
1233 Assert(pCtx->csHid.u64Base <= 0xfffff);
1234 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1235 Assert(pCtx->esHid.u64Base <= 0xfffff);
1236 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1237 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1238 }
1239 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1240 }
1241 else
1242 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1243 if ( CPUMIsGuestInRealModeEx(pCtx)
1244 && pCtx->csHid.u64Base == 0xffff0000)
1245 {
1246 pCtx->csHid.u64Base = 0xf0000;
1247 pCtx->cs = 0xf000;
1248 }
1249 }
1250#endif /* HWACCM_VMX_EMULATE_REALMODE */
1251
1252 VMX_WRITE_SELREG(ES, es);
1253 AssertRC(rc);
1254
1255 VMX_WRITE_SELREG(CS, cs);
1256 AssertRC(rc);
1257
1258 VMX_WRITE_SELREG(SS, ss);
1259 AssertRC(rc);
1260
1261 VMX_WRITE_SELREG(DS, ds);
1262 AssertRC(rc);
1263
1264 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1265 VMX_WRITE_SELREG(FS, fs);
1266 AssertRC(rc);
1267
1268 VMX_WRITE_SELREG(GS, gs);
1269 AssertRC(rc);
1270 }
1271
1272 /* Guest CPU context: LDTR. */
1273 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1274 {
1275 if (pCtx->ldtr == 0)
1276 {
1277 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1278 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1279 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1280 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1281 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1282 }
1283 else
1284 {
1285 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1286 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1287 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1288 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1289 }
1290 AssertRC(rc);
1291 }
1292 /* Guest CPU context: TR. */
1293 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1294 {
1295#ifdef HWACCM_VMX_EMULATE_REALMODE
1296 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1297 if (CPUMIsGuestInRealModeEx(pCtx))
1298 {
1299 RTGCPHYS GCPhys;
1300
1301 /* We convert it here every time as pci regions could be reconfigured. */
1302 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1303 AssertRC(rc);
1304
1305 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1306 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1307 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1308
1309 X86DESCATTR attr;
1310
1311 attr.u = 0;
1312 attr.n.u1Present = 1;
1313 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1314 val = attr.u;
1315 }
1316 else
1317#endif /* HWACCM_VMX_EMULATE_REALMODE */
1318 {
1319 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1320 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1321 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1322
1323 val = pCtx->trHid.Attr.u;
1324
1325 /* The TSS selector must be busy. */
1326 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1327 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1328 else
1329 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1330 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1331
1332 }
1333 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1334 AssertRC(rc);
1335 }
1336 /* Guest CPU context: GDTR. */
1337 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1338 {
1339 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1340 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1341 AssertRC(rc);
1342 }
1343 /* Guest CPU context: IDTR. */
1344 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1345 {
1346 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1347 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1348 AssertRC(rc);
1349 }
1350
1351 /*
1352 * Sysenter MSRs (unconditional)
1353 */
1354 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1355 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1356 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1357 AssertRC(rc);
1358
1359 /* Control registers */
1360 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1361 {
1362 val = pCtx->cr0;
1363 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1364 Log2(("Guest CR0-shadow %08x\n", val));
1365 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1366 {
1367 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1368 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1369 }
1370 else
1371 {
1372 /** @todo check if we support the old style mess correctly. */
1373 if (!(val & X86_CR0_NE))
1374 Log(("Forcing X86_CR0_NE!!!\n"));
1375
1376 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1377 }
1378 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1379 val |= X86_CR0_PE | X86_CR0_PG;
1380 if (pVM->hwaccm.s.fNestedPaging)
1381 {
1382 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1383 {
1384 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1385 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1386 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1387 }
1388 else
1389 {
1390 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1391 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1392 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1393 }
1394 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1395 AssertRC(rc);
1396 }
1397 else
1398 {
1399 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1400 val |= X86_CR0_WP;
1401 }
1402
1403 /* Always enable caching. */
1404 val &= ~(X86_CR0_CD|X86_CR0_NW);
1405
1406 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1407 Log2(("Guest CR0 %08x\n", val));
1408 /* CR0 flags owned by the host; if the guests attempts to change them, then
1409 * the VM will exit.
1410 */
1411 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1412 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1413 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1414 | X86_CR0_TS
1415 | X86_CR0_ET /* Bit not restored during VM-exit! */
1416 | X86_CR0_CD /* Bit not restored during VM-exit! */
1417 | X86_CR0_NW /* Bit not restored during VM-exit! */
1418 | X86_CR0_NE
1419 | X86_CR0_MP;
1420 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1421
1422 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1423 Log2(("Guest CR0-mask %08x\n", val));
1424 AssertRC(rc);
1425 }
1426 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1427 {
1428 /* CR4 */
1429 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1430 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1431 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1432 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1433
1434 if (!pVM->hwaccm.s.fNestedPaging)
1435 {
1436 switch(pVCpu->hwaccm.s.enmShadowMode)
1437 {
1438 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1439 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1440 case PGMMODE_32_BIT: /* 32-bit paging. */
1441 val &= ~X86_CR4_PAE;
1442 break;
1443
1444 case PGMMODE_PAE: /* PAE paging. */
1445 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1446 /** @todo use normal 32 bits paging */
1447 val |= X86_CR4_PAE;
1448 break;
1449
1450 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1451 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1452#ifdef VBOX_ENABLE_64_BITS_GUESTS
1453 break;
1454#else
1455 AssertFailed();
1456 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1457#endif
1458 default: /* shut up gcc */
1459 AssertFailed();
1460 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1461 }
1462 }
1463 else
1464 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1465 {
1466 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1467 val |= X86_CR4_PSE;
1468 /* Our identity mapping is a 32 bits page directory. */
1469 val &= ~X86_CR4_PAE;
1470 }
1471
1472 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1473 Log2(("Guest CR4 %08x\n", val));
1474 /* CR4 flags owned by the host; if the guests attempts to change them, then
1475 * the VM will exit.
1476 */
1477 val = 0
1478 | X86_CR4_PAE
1479 | X86_CR4_PGE
1480 | X86_CR4_PSE
1481 | X86_CR4_VMXE;
1482 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1483
1484 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1485 Log2(("Guest CR4-mask %08x\n", val));
1486 AssertRC(rc);
1487 }
1488
1489 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1490 {
1491 if (pVM->hwaccm.s.fNestedPaging)
1492 {
1493 Assert(PGMGetHyperCR3(pVCpu));
1494 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1495
1496 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1497 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1498 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1499 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1500
1501 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1502 AssertRC(rc);
1503
1504 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1505 {
1506 RTGCPHYS GCPhys;
1507
1508 /* We convert it here every time as pci regions could be reconfigured. */
1509 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1510 AssertRC(rc);
1511
1512 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1513 * take care of the translation to host physical addresses.
1514 */
1515 val = GCPhys;
1516 }
1517 else
1518 {
1519 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1520 val = pCtx->cr3;
1521 /* Prefetch the four PDPT entries in PAE mode. */
1522 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1523 }
1524 }
1525 else
1526 {
1527 val = PGMGetHyperCR3(pVCpu);
1528 Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1529 }
1530
1531 /* Save our shadow CR3 register. */
1532 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1533 AssertRC(rc);
1534 }
1535
1536 /* Debug registers. */
1537 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1538 {
1539 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1540 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1541
1542 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1543 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1544 pCtx->dr[7] |= 0x400; /* must be one */
1545
1546 /* Resync DR7 */
1547 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1548 AssertRC(rc);
1549
1550 /* Sync the debug state now if any breakpoint is armed. */
1551 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1552 && !CPUMIsGuestDebugStateActive(pVCpu)
1553 && !DBGFIsStepping(pVCpu))
1554 {
1555 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1556
1557 /* Disable drx move intercepts. */
1558 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1559 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1560 AssertRC(rc);
1561
1562 /* Save the host and load the guest debug state. */
1563 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1564 AssertRC(rc);
1565 }
1566
1567 /* IA32_DEBUGCTL MSR. */
1568 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1569 AssertRC(rc);
1570
1571 /** @todo do we really ever need this? */
1572 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1573 AssertRC(rc);
1574 }
1575
1576 /* EIP, ESP and EFLAGS */
1577 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1578 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1579 AssertRC(rc);
1580
1581 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1582 eflags = pCtx->eflags;
1583 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1584 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1585
1586#ifdef HWACCM_VMX_EMULATE_REALMODE
1587 /* Real mode emulation using v86 mode. */
1588 if (CPUMIsGuestInRealModeEx(pCtx))
1589 {
1590 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1591
1592 eflags.Bits.u1VM = 1;
1593 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1594 }
1595#endif /* HWACCM_VMX_EMULATE_REALMODE */
1596 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1597 AssertRC(rc);
1598
1599 /* TSC offset. */
1600 uint64_t u64TSCOffset;
1601
1602 if (TMCpuTickCanUseRealTSC(pVCpu, &u64TSCOffset))
1603 {
1604 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1605 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1606 AssertRC(rc);
1607
1608 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1609 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1610 AssertRC(rc);
1611 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1612 }
1613 else
1614 {
1615 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1616 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1617 AssertRC(rc);
1618 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1619 }
1620
1621 /* 64 bits guest mode? */
1622 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1623 {
1624#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1625 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1626#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1627 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1628#else
1629# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1630 if (!pVM->hwaccm.s.fAllow64BitGuests)
1631 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1632# endif
1633 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1634#endif
1635 /* Unconditionally update these as wrmsr might have changed them. */
1636 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1637 AssertRC(rc);
1638 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1639 AssertRC(rc);
1640 }
1641 else
1642 {
1643 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1644 }
1645
1646#if 0 /* @todo deal with 32/64 */
1647 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1648 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1649 {
1650 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1651 AssertRC(rc);
1652 }
1653#endif
1654
1655 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1656
1657 /* Done. */
1658 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1659
1660 return rc;
1661}
1662
1663/**
1664 * Syncs back the guest state
1665 *
1666 * @returns VBox status code.
1667 * @param pVM The VM to operate on.
1668 * @param pVCpu The VMCPU to operate on.
1669 * @param pCtx Guest context
1670 */
1671DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1672{
1673 RTGCUINTREG val, valShadow;
1674 RTGCUINTPTR uInterruptState;
1675 int rc;
1676
1677 /* Let's first sync back eip, esp, and eflags. */
1678 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1679 AssertRC(rc);
1680 pCtx->rip = val;
1681 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1682 AssertRC(rc);
1683 pCtx->rsp = val;
1684 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1685 AssertRC(rc);
1686 pCtx->eflags.u32 = val;
1687
1688 /* Take care of instruction fusing (sti, mov ss) */
1689 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1690 uInterruptState = val;
1691 if (uInterruptState != 0)
1692 {
1693 Assert(uInterruptState <= 2); /* only sti & mov ss */
1694 Log(("uInterruptState %x eip=%RGv\n", uInterruptState, pCtx->rip));
1695 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1696 }
1697 else
1698 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1699
1700 /* Control registers. */
1701 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1702 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1703 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1704 CPUMSetGuestCR0(pVCpu, val);
1705
1706 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1707 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1708 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1709 CPUMSetGuestCR4(pVCpu, val);
1710
1711 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1712 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1713 if ( pVM->hwaccm.s.fNestedPaging
1714 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1715 {
1716 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1717
1718 /* Can be updated behind our back in the nested paging case. */
1719 CPUMSetGuestCR2(pVCpu, pCache->cr2);
1720
1721 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1722
1723 if (val != pCtx->cr3)
1724 {
1725 CPUMSetGuestCR3(pVCpu, val);
1726 PGMUpdateCR3(pVCpu, val);
1727 }
1728 /* Prefetch the four PDPT entries in PAE mode. */
1729 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1730 }
1731
1732 /* Sync back DR7 here. */
1733 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1734 pCtx->dr[7] = val;
1735
1736 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1737 VMX_READ_SELREG(ES, es);
1738 VMX_READ_SELREG(SS, ss);
1739 VMX_READ_SELREG(CS, cs);
1740 VMX_READ_SELREG(DS, ds);
1741 VMX_READ_SELREG(FS, fs);
1742 VMX_READ_SELREG(GS, gs);
1743
1744 /*
1745 * System MSRs
1746 */
1747 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1748 pCtx->SysEnter.cs = val;
1749 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1750 pCtx->SysEnter.eip = val;
1751 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1752 pCtx->SysEnter.esp = val;
1753
1754 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1755 VMX_READ_SELREG(LDTR, ldtr);
1756
1757 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1758 pCtx->gdtr.cbGdt = val;
1759 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1760 pCtx->gdtr.pGdt = val;
1761
1762 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1763 pCtx->idtr.cbIdt = val;
1764 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1765 pCtx->idtr.pIdt = val;
1766
1767#ifdef HWACCM_VMX_EMULATE_REALMODE
1768 /* Real mode emulation using v86 mode. */
1769 if (CPUMIsGuestInRealModeEx(pCtx))
1770 {
1771 /* Hide our emulation flags */
1772 pCtx->eflags.Bits.u1VM = 0;
1773
1774 /* Restore original IOPL setting as we always use 0. */
1775 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1776
1777 /* Force a TR resync every time in case we switch modes. */
1778 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1779 }
1780 else
1781#endif /* HWACCM_VMX_EMULATE_REALMODE */
1782 {
1783 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1784 VMX_READ_SELREG(TR, tr);
1785 }
1786 return VINF_SUCCESS;
1787}
1788
1789/**
1790 * Dummy placeholder
1791 *
1792 * @param pVM The VM to operate on.
1793 * @param pVCpu The VMCPU to operate on.
1794 */
1795static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1796{
1797 NOREF(pVM);
1798 NOREF(pVCpu);
1799 return;
1800}
1801
1802/**
1803 * Setup the tagged TLB for EPT
1804 *
1805 * @returns VBox status code.
1806 * @param pVM The VM to operate on.
1807 * @param pVCpu The VMCPU to operate on.
1808 */
1809static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1810{
1811 PHWACCM_CPUINFO pCpu;
1812
1813 Assert(pVM->hwaccm.s.fNestedPaging);
1814 Assert(!pVM->hwaccm.s.vmx.fVPID);
1815
1816 /* Deal with tagged TLBs if VPID or EPT is supported. */
1817 pCpu = HWACCMR0GetCurrentCpu();
1818 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1819 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1820 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1821 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1822 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1823 {
1824 /* Force a TLB flush on VM entry. */
1825 pVCpu->hwaccm.s.fForceTLBFlush = true;
1826 }
1827 else
1828 Assert(!pCpu->fFlushTLB);
1829
1830 /* Check for tlb shootdown flushes. */
1831 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1832 pVCpu->hwaccm.s.fForceTLBFlush = true;
1833
1834 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1835 pCpu->fFlushTLB = false;
1836
1837 if (pVCpu->hwaccm.s.fForceTLBFlush)
1838 {
1839 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1840 }
1841 else
1842 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1843 {
1844 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1845 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1846 for (unsigned i=0;i<pVCpu->hwaccm.s.cTlbShootdownPages;i++)
1847 {
1848 /* aTlbShootdownPages contains physical addresses in this case. */
1849 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.aTlbShootdownPages[i]);
1850 }
1851 }
1852 pVCpu->hwaccm.s.cTlbShootdownPages = 0;
1853 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1854
1855#ifdef VBOX_WITH_STATISTICS
1856 if (pVCpu->hwaccm.s.fForceTLBFlush)
1857 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1858 else
1859 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1860#endif
1861}
1862
1863#ifdef HWACCM_VTX_WITH_VPID
1864/**
1865 * Setup the tagged TLB for VPID
1866 *
1867 * @returns VBox status code.
1868 * @param pVM The VM to operate on.
1869 * @param pVCpu The VMCPU to operate on.
1870 */
1871static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1872{
1873 PHWACCM_CPUINFO pCpu;
1874
1875 Assert(pVM->hwaccm.s.vmx.fVPID);
1876 Assert(!pVM->hwaccm.s.fNestedPaging);
1877
1878 /* Deal with tagged TLBs if VPID or EPT is supported. */
1879 pCpu = HWACCMR0GetCurrentCpu();
1880 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1881 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1882 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1883 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1884 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1885 {
1886 /* Force a TLB flush on VM entry. */
1887 pVCpu->hwaccm.s.fForceTLBFlush = true;
1888 }
1889 else
1890 Assert(!pCpu->fFlushTLB);
1891
1892 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1893
1894 /* Check for tlb shootdown flushes. */
1895 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1896 pVCpu->hwaccm.s.fForceTLBFlush = true;
1897
1898 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1899 if (pVCpu->hwaccm.s.fForceTLBFlush)
1900 {
1901 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1902 || pCpu->fFlushTLB)
1903 {
1904 pCpu->fFlushTLB = false;
1905 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1906 pCpu->cTLBFlushes++;
1907 }
1908 else
1909 {
1910 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1911 pVCpu->hwaccm.s.fForceTLBFlush = false;
1912 }
1913
1914 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1915 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1916 }
1917 else
1918 {
1919 Assert(!pCpu->fFlushTLB);
1920 Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
1921
1922 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1923 {
1924 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1925 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1926 for (unsigned i=0;i<pVCpu->hwaccm.s.cTlbShootdownPages;i++)
1927 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.aTlbShootdownPages[i]);
1928 }
1929 }
1930 pVCpu->hwaccm.s.cTlbShootdownPages = 0;
1931 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1932
1933 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1934 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1935 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1936
1937 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1938 AssertRC(rc);
1939
1940 if (pVCpu->hwaccm.s.fForceTLBFlush)
1941 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1942
1943#ifdef VBOX_WITH_STATISTICS
1944 if (pVCpu->hwaccm.s.fForceTLBFlush)
1945 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1946 else
1947 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1948#endif
1949}
1950#endif /* HWACCM_VTX_WITH_VPID */
1951
1952/**
1953 * Runs guest code in a VT-x VM.
1954 *
1955 * @returns VBox status code.
1956 * @param pVM The VM to operate on.
1957 * @param pVCpu The VMCPU to operate on.
1958 * @param pCtx Guest context
1959 */
1960VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1961{
1962 int rc = VINF_SUCCESS;
1963 RTGCUINTREG val;
1964 RTGCUINTREG exitReason = VMX_EXIT_INVALID;
1965 RTGCUINTREG instrError, cbInstr;
1966 RTGCUINTPTR exitQualification;
1967 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1968 RTGCUINTPTR errCode, instrInfo;
1969 bool fSyncTPR = false;
1970 PHWACCM_CPUINFO pCpu = 0;
1971 RTCCUINTREG uOldEFlags;
1972 unsigned cResume = 0;
1973#ifdef VBOX_STRICT
1974 RTCPUID idCpuCheck;
1975#endif
1976#ifdef VBOX_WITH_STATISTICS
1977 bool fStatEntryStarted = true;
1978 bool fStatExit2Started = false;
1979#endif
1980
1981 Log2(("\nE"));
1982
1983 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
1984
1985#ifdef VBOX_STRICT
1986 {
1987 RTCCUINTREG val;
1988
1989 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1990 AssertRC(rc);
1991 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1992
1993 /* allowed zero */
1994 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1995 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1996
1997 /* allowed one */
1998 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1999 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
2000
2001 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
2002 AssertRC(rc);
2003 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
2004
2005 /* Must be set according to the MSR, but can be cleared in case of EPT. */
2006 if (pVM->hwaccm.s.fNestedPaging)
2007 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
2008 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2009 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2010
2011 /* allowed zero */
2012 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2013 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2014
2015 /* allowed one */
2016 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2017 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2018
2019 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2020 AssertRC(rc);
2021 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2022
2023 /* allowed zero */
2024 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2025 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2026
2027 /* allowed one */
2028 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2029 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2030
2031 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2032 AssertRC(rc);
2033 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2034
2035 /* allowed zero */
2036 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2037 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2038
2039 /* allowed one */
2040 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2041 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2042 }
2043#endif
2044
2045#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2046 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2047#endif
2048
2049 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2050 */
2051ResumeExecution:
2052 STAM_STATS({
2053 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2054 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2055 });
2056 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2057 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2058 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2059 Assert(!HWACCMR0SuspendPending());
2060
2061 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2062 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
2063 {
2064 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2065 rc = VINF_EM_RAW_INTERRUPT;
2066 goto end;
2067 }
2068
2069 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2070 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2071 {
2072 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2073 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2074 {
2075 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2076 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2077 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2078 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2079 */
2080 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2081 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2082 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2083 AssertRC(rc);
2084 }
2085 }
2086 else
2087 {
2088 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2089 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2090 AssertRC(rc);
2091 }
2092
2093 /* Check for pending actions that force us to go back to ring 3. */
2094 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2095 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2096 {
2097 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2098 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2099 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2100 goto end;
2101 }
2102 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2103 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2104 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2105 {
2106 rc = VINF_EM_PENDING_REQUEST;
2107 goto end;
2108 }
2109
2110 /* When external interrupts are pending, we should exit the VM when IF is set. */
2111 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2112 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2113 if (RT_FAILURE(rc))
2114 goto end;
2115
2116 /** @todo check timers?? */
2117
2118 /* TPR caching using CR8 is only available in 64 bits mode */
2119 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2120 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2121 /**
2122 * @todo reduce overhead
2123 */
2124 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
2125 && pVM->hwaccm.s.vmx.pAPIC)
2126 {
2127 /* TPR caching in CR8 */
2128 uint8_t u8TPR;
2129 bool fPending;
2130
2131 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
2132 AssertRC(rc);
2133 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2134 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
2135
2136 /* Two options here:
2137 * - external interrupt pending, but masked by the TPR value.
2138 * -> a CR8 update that lower the current TPR value should cause an exit
2139 * - no pending interrupts
2140 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2141 */
2142 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
2143 AssertRC(rc);
2144
2145 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
2146 fSyncTPR = true;
2147 }
2148
2149#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2150 if ( pVM->hwaccm.s.fNestedPaging
2151# ifdef HWACCM_VTX_WITH_VPID
2152 || pVM->hwaccm.s.vmx.fVPID
2153# endif /* HWACCM_VTX_WITH_VPID */
2154 )
2155 {
2156 pCpu = HWACCMR0GetCurrentCpu();
2157 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2158 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2159 {
2160 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2161 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2162 else
2163 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2164 }
2165 if (pCpu->fFlushTLB)
2166 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2167 else
2168 if (pVCpu->hwaccm.s.fForceTLBFlush)
2169 LogFlow(("Manual TLB flush\n"));
2170 }
2171#endif
2172#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2173 PGMDynMapFlushAutoSet(pVCpu);
2174#endif
2175
2176 /*
2177 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2178 * (until the actual world switch)
2179 */
2180#ifdef VBOX_STRICT
2181 idCpuCheck = RTMpCpuId();
2182#endif
2183#ifdef LOG_LOGGING
2184 VMMR0LogFlushDisable(pVCpu);
2185#endif
2186 /* Save the host state first. */
2187 rc = VMXR0SaveHostState(pVM, pVCpu);
2188 if (rc != VINF_SUCCESS)
2189 goto end;
2190 /* Load the guest state */
2191 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2192 if (rc != VINF_SUCCESS)
2193 goto end;
2194
2195 /* Disable interrupts to make sure a poke will interrupt execution.
2196 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
2197 */
2198 uOldEFlags = ASMIntDisableFlags();
2199 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2200
2201 /* Deal with tagged TLB setup and invalidation. */
2202 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2203
2204 /* Non-register state Guest Context */
2205 /** @todo change me according to cpu state */
2206 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2207 AssertRC(rc);
2208
2209 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2210
2211 /* Manual save and restore:
2212 * - General purpose registers except RIP, RSP
2213 *
2214 * Trashed:
2215 * - CR2 (we don't care)
2216 * - LDTR (reset to 0)
2217 * - DRx (presumably not changed at all)
2218 * - DR7 (reset to 0x400)
2219 * - EFLAGS (reset to RT_BIT(1); not relevant)
2220 *
2221 */
2222
2223
2224 /* All done! Let's start VM execution. */
2225 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2226#ifdef VBOX_STRICT
2227 Assert(idCpuCheck == RTMpCpuId());
2228#endif
2229
2230#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2231 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2232 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2233#endif
2234
2235 TMNotifyStartOfExecution(pVCpu);
2236 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2237 TMNotifyEndOfExecution(pVCpu);
2238 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2239 ASMSetFlags(uOldEFlags);
2240
2241 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2242
2243 /* In case we execute a goto ResumeExecution later on. */
2244 pVCpu->hwaccm.s.fResumeVM = true;
2245 pVCpu->hwaccm.s.fForceTLBFlush = false;
2246
2247 /*
2248 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2249 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2250 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2251 */
2252 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2253 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2254
2255 if (rc != VINF_SUCCESS)
2256 {
2257 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2258 goto end;
2259 }
2260
2261 /* Success. Query the guest state and figure out what has happened. */
2262
2263 /* Investigate why there was a VM-exit. */
2264 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2265 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2266
2267 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2268 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2269 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2270 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2271 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2272 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2273 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2274 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2275 AssertRC(rc);
2276
2277 /* Sync back the guest state */
2278 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2279 AssertRC(rc);
2280
2281 /* Note! NOW IT'S SAFE FOR LOGGING! */
2282#ifdef LOG_LOGGING
2283 VMMR0LogFlushEnable(pVCpu);
2284#endif
2285 Log2(("Raw exit reason %08x\n", exitReason));
2286
2287 /* Check if an injected event was interrupted prematurely. */
2288 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2289 AssertRC(rc);
2290 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2291 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2292 /* Ignore 'int xx' as they'll be restarted anyway. */
2293 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2294 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2295 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2296 {
2297 Assert(!pVCpu->hwaccm.s.Event.fPending);
2298 pVCpu->hwaccm.s.Event.fPending = true;
2299 /* Error code present? */
2300 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2301 {
2302 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2303 AssertRC(rc);
2304 pVCpu->hwaccm.s.Event.errCode = val;
2305 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2306 }
2307 else
2308 {
2309 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2310 pVCpu->hwaccm.s.Event.errCode = 0;
2311 }
2312 }
2313#ifdef VBOX_STRICT
2314 else
2315 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2316 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2317 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2318 {
2319 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2320 }
2321
2322 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2323 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2324#endif
2325
2326 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2327 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2328 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2329 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2330 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2331
2332 if (fSyncTPR)
2333 {
2334 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
2335 AssertRC(rc);
2336 }
2337
2338 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2339 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2340
2341 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2342 switch (exitReason)
2343 {
2344 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2345 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2346 {
2347 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2348
2349 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2350 {
2351 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2352 /* External interrupt; leave to allow it to be dispatched again. */
2353 rc = VINF_EM_RAW_INTERRUPT;
2354 break;
2355 }
2356 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2357 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2358 {
2359 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2360 /* External interrupt; leave to allow it to be dispatched again. */
2361 rc = VINF_EM_RAW_INTERRUPT;
2362 break;
2363
2364 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2365 AssertFailed(); /* can't come here; fails the first check. */
2366 break;
2367
2368 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2369 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2370 Assert(vector == 1 || vector == 3 || vector == 4);
2371 /* no break */
2372 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2373 Log2(("Hardware/software interrupt %d\n", vector));
2374 switch (vector)
2375 {
2376 case X86_XCPT_NM:
2377 {
2378 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2379
2380 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2381 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2382 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2383 if (rc == VINF_SUCCESS)
2384 {
2385 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2386
2387 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2388
2389 /* Continue execution. */
2390 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2391
2392 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2393 goto ResumeExecution;
2394 }
2395
2396 Log(("Forward #NM fault to the guest\n"));
2397 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2398 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2399 AssertRC(rc);
2400 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2401 goto ResumeExecution;
2402 }
2403
2404 case X86_XCPT_PF: /* Page fault */
2405 {
2406#ifdef DEBUG
2407 if (pVM->hwaccm.s.fNestedPaging)
2408 { /* A genuine pagefault.
2409 * Forward the trap to the guest by injecting the exception and resuming execution.
2410 */
2411 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2412
2413 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2414
2415 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2416
2417 /* Now we must update CR2. */
2418 pCtx->cr2 = exitQualification;
2419 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2420 AssertRC(rc);
2421
2422 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2423 goto ResumeExecution;
2424 }
2425#endif
2426 Assert(!pVM->hwaccm.s.fNestedPaging);
2427
2428 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2429 /* Exit qualification contains the linear address of the page fault. */
2430 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2431 TRPMSetErrorCode(pVCpu, errCode);
2432 TRPMSetFaultAddress(pVCpu, exitQualification);
2433
2434 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2435 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2436 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2437 if (rc == VINF_SUCCESS)
2438 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2439 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2440 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2441
2442 TRPMResetTrap(pVCpu);
2443
2444 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2445 goto ResumeExecution;
2446 }
2447 else
2448 if (rc == VINF_EM_RAW_GUEST_TRAP)
2449 { /* A genuine pagefault.
2450 * Forward the trap to the guest by injecting the exception and resuming execution.
2451 */
2452 Log2(("Forward page fault to the guest\n"));
2453
2454 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2455 /* The error code might have been changed. */
2456 errCode = TRPMGetErrorCode(pVCpu);
2457
2458 TRPMResetTrap(pVCpu);
2459
2460 /* Now we must update CR2. */
2461 pCtx->cr2 = exitQualification;
2462 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2463 AssertRC(rc);
2464
2465 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2466 goto ResumeExecution;
2467 }
2468#ifdef VBOX_STRICT
2469 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2470 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2471#endif
2472 /* Need to go back to the recompiler to emulate the instruction. */
2473 TRPMResetTrap(pVCpu);
2474 break;
2475 }
2476
2477 case X86_XCPT_MF: /* Floating point exception. */
2478 {
2479 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2480 if (!(pCtx->cr0 & X86_CR0_NE))
2481 {
2482 /* old style FPU error reporting needs some extra work. */
2483 /** @todo don't fall back to the recompiler, but do it manually. */
2484 rc = VINF_EM_RAW_EMULATE_INSTR;
2485 break;
2486 }
2487 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2488 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2489 AssertRC(rc);
2490
2491 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2492 goto ResumeExecution;
2493 }
2494
2495 case X86_XCPT_DB: /* Debug exception. */
2496 {
2497 uint64_t uDR6;
2498
2499 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2500 *
2501 * Exit qualification bits:
2502 * 3:0 B0-B3 which breakpoint condition was met
2503 * 12:4 Reserved (0)
2504 * 13 BD - debug register access detected
2505 * 14 BS - single step execution or branch taken
2506 * 63:15 Reserved (0)
2507 */
2508 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2509
2510 /* Note that we don't support guest and host-initiated debugging at the same time. */
2511 Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx));
2512
2513 uDR6 = X86_DR6_INIT_VAL;
2514 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2515 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
2516 if (rc == VINF_EM_RAW_GUEST_TRAP)
2517 {
2518 /** @todo this isn't working, but we'll never get here normally. */
2519
2520 /* Update DR6 here. */
2521 pCtx->dr[6] = uDR6;
2522
2523 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2524 pCtx->dr[7] &= ~X86_DR7_GD;
2525
2526 /* Paranoia. */
2527 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2528 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2529 pCtx->dr[7] |= 0x400; /* must be one */
2530
2531 /* Resync DR7 */
2532 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2533 AssertRC(rc);
2534
2535 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2536 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2537 AssertRC(rc);
2538
2539 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2540 goto ResumeExecution;
2541 }
2542 /* Return to ring 3 to deal with the debug exit code. */
2543 break;
2544 }
2545
2546 case X86_XCPT_BP: /* Breakpoint. */
2547 {
2548 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2549 if (rc == VINF_EM_RAW_GUEST_TRAP)
2550 {
2551 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2552 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2553 AssertRC(rc);
2554 goto ResumeExecution;
2555 }
2556 if (rc == VINF_SUCCESS)
2557 goto ResumeExecution;
2558 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2559 break;
2560 }
2561
2562 case X86_XCPT_GP: /* General protection failure exception.*/
2563 {
2564 uint32_t cbOp;
2565 uint32_t cbSize;
2566 DISCPUSTATE Cpu;
2567
2568 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2569#ifdef VBOX_STRICT
2570 if (!CPUMIsGuestInRealModeEx(pCtx))
2571 {
2572 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2573 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2574 AssertRC(rc);
2575 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2576 goto ResumeExecution;
2577 }
2578#endif
2579 Assert(CPUMIsGuestInRealModeEx(pCtx));
2580
2581 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2582
2583 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2584 if (RT_SUCCESS(rc))
2585 {
2586 bool fUpdateRIP = true;
2587
2588 Assert(cbOp == Cpu.opsize);
2589 switch (Cpu.pCurInstr->opcode)
2590 {
2591 case OP_CLI:
2592 pCtx->eflags.Bits.u1IF = 0;
2593 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2594 break;
2595
2596 case OP_STI:
2597 pCtx->eflags.Bits.u1IF = 1;
2598 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2599 break;
2600
2601 case OP_HLT:
2602 fUpdateRIP = false;
2603 rc = VINF_EM_HALT;
2604 pCtx->rip += Cpu.opsize;
2605 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2606 break;
2607
2608 case OP_POPF:
2609 {
2610 RTGCPTR GCPtrStack;
2611 uint32_t cbParm;
2612 uint32_t uMask;
2613 X86EFLAGS eflags;
2614
2615 if (Cpu.prefix & PREFIX_OPSIZE)
2616 {
2617 cbParm = 4;
2618 uMask = 0xffffffff;
2619 }
2620 else
2621 {
2622 cbParm = 2;
2623 uMask = 0xffff;
2624 }
2625
2626 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2627 if (RT_FAILURE(rc))
2628 {
2629 rc = VERR_EM_INTERPRETER;
2630 break;
2631 }
2632 eflags.u = 0;
2633 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2634 if (RT_FAILURE(rc))
2635 {
2636 rc = VERR_EM_INTERPRETER;
2637 break;
2638 }
2639 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2640 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
2641 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
2642 pCtx->eflags.Bits.u1RF = 0;
2643 pCtx->esp += cbParm;
2644 pCtx->esp &= uMask;
2645
2646 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2647 break;
2648 }
2649
2650 case OP_PUSHF:
2651 {
2652 RTGCPTR GCPtrStack;
2653 uint32_t cbParm;
2654 uint32_t uMask;
2655 X86EFLAGS eflags;
2656
2657 if (Cpu.prefix & PREFIX_OPSIZE)
2658 {
2659 cbParm = 4;
2660 uMask = 0xffffffff;
2661 }
2662 else
2663 {
2664 cbParm = 2;
2665 uMask = 0xffff;
2666 }
2667
2668 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2669 if (RT_FAILURE(rc))
2670 {
2671 rc = VERR_EM_INTERPRETER;
2672 break;
2673 }
2674 eflags = pCtx->eflags;
2675 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2676 eflags.Bits.u1RF = 0;
2677 eflags.Bits.u1VM = 0;
2678
2679 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2680 if (RT_FAILURE(rc))
2681 {
2682 rc = VERR_EM_INTERPRETER;
2683 break;
2684 }
2685 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2686 pCtx->esp -= cbParm;
2687 pCtx->esp &= uMask;
2688 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2689 break;
2690 }
2691
2692 case OP_IRET:
2693 {
2694 RTGCPTR GCPtrStack;
2695 uint32_t uMask = 0xffff;
2696 uint16_t aIretFrame[3];
2697
2698 if (Cpu.prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
2699 {
2700 rc = VERR_EM_INTERPRETER;
2701 break;
2702 }
2703
2704 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2705 if (RT_FAILURE(rc))
2706 {
2707 rc = VERR_EM_INTERPRETER;
2708 break;
2709 }
2710 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2711 if (RT_FAILURE(rc))
2712 {
2713 rc = VERR_EM_INTERPRETER;
2714 break;
2715 }
2716 pCtx->ip = aIretFrame[0];
2717 pCtx->cs = aIretFrame[1];
2718 pCtx->csHid.u64Base = pCtx->cs << 4;
2719 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2720 pCtx->sp += sizeof(aIretFrame);
2721
2722 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2723 fUpdateRIP = false;
2724 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2725 break;
2726 }
2727
2728 case OP_INT:
2729 {
2730 RTGCUINTPTR intInfo;
2731
2732 LogFlow(("Realmode: INT %x\n", Cpu.param1.parval & 0xff));
2733 intInfo = Cpu.param1.parval & 0xff;
2734 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2735 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2736
2737 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2738 AssertRC(rc);
2739 fUpdateRIP = false;
2740 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2741 break;
2742 }
2743
2744 case OP_INTO:
2745 {
2746 if (pCtx->eflags.Bits.u1OF)
2747 {
2748 RTGCUINTPTR intInfo;
2749
2750 LogFlow(("Realmode: INTO\n"));
2751 intInfo = X86_XCPT_OF;
2752 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2753 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2754
2755 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2756 AssertRC(rc);
2757 fUpdateRIP = false;
2758 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2759 }
2760 break;
2761 }
2762
2763 case OP_INT3:
2764 {
2765 RTGCUINTPTR intInfo;
2766
2767 LogFlow(("Realmode: INT 3\n"));
2768 intInfo = 3;
2769 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2770 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2771
2772 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2773 AssertRC(rc);
2774 fUpdateRIP = false;
2775 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2776 break;
2777 }
2778
2779 default:
2780 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2781 break;
2782 }
2783
2784 if (rc == VINF_SUCCESS)
2785 {
2786 if (fUpdateRIP)
2787 pCtx->rip += cbOp; /* Move on to the next instruction. */
2788
2789 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2790 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2791
2792 /* Only resume if successful. */
2793 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2794 goto ResumeExecution;
2795 }
2796 }
2797 else
2798 rc = VERR_EM_INTERPRETER;
2799
2800 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2801 break;
2802 }
2803
2804#ifdef VBOX_STRICT
2805 case X86_XCPT_DE: /* Divide error. */
2806 case X86_XCPT_UD: /* Unknown opcode exception. */
2807 case X86_XCPT_SS: /* Stack segment exception. */
2808 case X86_XCPT_NP: /* Segment not present exception. */
2809 {
2810 switch(vector)
2811 {
2812 case X86_XCPT_DE:
2813 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2814 break;
2815 case X86_XCPT_UD:
2816 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2817 break;
2818 case X86_XCPT_SS:
2819 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2820 break;
2821 case X86_XCPT_NP:
2822 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2823 break;
2824 }
2825
2826 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2827 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2828 AssertRC(rc);
2829
2830 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2831 goto ResumeExecution;
2832 }
2833#endif
2834 default:
2835#ifdef HWACCM_VMX_EMULATE_REALMODE
2836 if (CPUMIsGuestInRealModeEx(pCtx))
2837 {
2838 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2839 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2840 AssertRC(rc);
2841
2842 /* Go back to ring 3 in case of a triple fault. */
2843 if ( vector == X86_XCPT_DF
2844 && rc == VINF_EM_RESET)
2845 break;
2846
2847 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2848 goto ResumeExecution;
2849 }
2850#endif
2851 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2852 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2853 break;
2854 } /* switch (vector) */
2855
2856 break;
2857
2858 default:
2859 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2860 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2861 break;
2862 }
2863
2864 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2865 break;
2866 }
2867
2868 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2869 {
2870 RTGCPHYS GCPhys;
2871
2872 Assert(pVM->hwaccm.s.fNestedPaging);
2873
2874 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2875 AssertRC(rc);
2876 Assert(((exitQualification >> 7) & 3) != 2);
2877
2878 /* Determine the kind of violation. */
2879 errCode = 0;
2880 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2881 errCode |= X86_TRAP_PF_ID;
2882
2883 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2884 errCode |= X86_TRAP_PF_RW;
2885
2886 /* If the page is present, then it's a page level protection fault. */
2887 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2888 errCode |= X86_TRAP_PF_P;
2889
2890 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2891
2892 /* GCPhys contains the guest physical address of the page fault. */
2893 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2894 TRPMSetErrorCode(pVCpu, errCode);
2895 TRPMSetFaultAddress(pVCpu, GCPhys);
2896
2897 /* Handle the pagefault trap for the nested shadow table. */
2898 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2899 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2900 if (rc == VINF_SUCCESS)
2901 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2902 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
2903 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
2904
2905 TRPMResetTrap(pVCpu);
2906
2907 goto ResumeExecution;
2908 }
2909
2910#ifdef VBOX_STRICT
2911 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2912 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2913#endif
2914 /* Need to go back to the recompiler to emulate the instruction. */
2915 TRPMResetTrap(pVCpu);
2916 break;
2917 }
2918
2919 case VMX_EXIT_EPT_MISCONFIG:
2920 {
2921 RTGCPHYS GCPhys;
2922
2923 Assert(pVM->hwaccm.s.fNestedPaging);
2924
2925 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2926 AssertRC(rc);
2927
2928 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
2929 break;
2930 }
2931
2932 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2933 /* Clear VM-exit on IF=1 change. */
2934 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2935 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2936 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2937 AssertRC(rc);
2938 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
2939 goto ResumeExecution; /* we check for pending guest interrupts there */
2940
2941 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2942 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2943 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
2944 /* Skip instruction and continue directly. */
2945 pCtx->rip += cbInstr;
2946 /* Continue execution.*/
2947 goto ResumeExecution;
2948
2949 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2950 {
2951 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2952 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
2953 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2954 if (rc == VINF_SUCCESS)
2955 {
2956 /* Update EIP and continue execution. */
2957 Assert(cbInstr == 2);
2958 pCtx->rip += cbInstr;
2959 goto ResumeExecution;
2960 }
2961 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
2962 rc = VINF_EM_RAW_EMULATE_INSTR;
2963 break;
2964 }
2965
2966 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2967 {
2968 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
2969 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
2970 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2971 if (rc == VINF_SUCCESS)
2972 {
2973 /* Update EIP and continue execution. */
2974 Assert(cbInstr == 2);
2975 pCtx->rip += cbInstr;
2976 goto ResumeExecution;
2977 }
2978 rc = VINF_EM_RAW_EMULATE_INSTR;
2979 break;
2980 }
2981
2982 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2983 {
2984 Log2(("VMX: Rdtsc\n"));
2985 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2986 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2987 if (rc == VINF_SUCCESS)
2988 {
2989 /* Update EIP and continue execution. */
2990 Assert(cbInstr == 2);
2991 pCtx->rip += cbInstr;
2992 goto ResumeExecution;
2993 }
2994 rc = VINF_EM_RAW_EMULATE_INSTR;
2995 break;
2996 }
2997
2998 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2999 {
3000 Log2(("VMX: invlpg\n"));
3001 Assert(!pVM->hwaccm.s.fNestedPaging);
3002
3003 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
3004 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
3005 if (rc == VINF_SUCCESS)
3006 {
3007 /* Update EIP and continue execution. */
3008 pCtx->rip += cbInstr;
3009 goto ResumeExecution;
3010 }
3011 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
3012 break;
3013 }
3014
3015 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3016 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3017 {
3018 uint32_t cbSize;
3019
3020 STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
3021
3022 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3023 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3024 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3025 if (rc == VINF_SUCCESS)
3026 {
3027 /* EIP has been updated already. */
3028
3029 /* Only resume if successful. */
3030 goto ResumeExecution;
3031 }
3032 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
3033 break;
3034 }
3035
3036 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3037 {
3038 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3039
3040 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3041 {
3042 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3043 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3044 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3045 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3046 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3047 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3048
3049 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3050 {
3051 case 0:
3052 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3053 break;
3054 case 2:
3055 break;
3056 case 3:
3057 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3058 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3059 break;
3060 case 4:
3061 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3062 break;
3063 case 8:
3064 /* CR8 contains the APIC TPR */
3065 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3066 break;
3067
3068 default:
3069 AssertFailed();
3070 break;
3071 }
3072 /* Check if a sync operation is pending. */
3073 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3074 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3075 {
3076 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3077 AssertRC(rc);
3078 }
3079 break;
3080
3081 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3082 Log2(("VMX: mov x, crx\n"));
3083 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3084
3085 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3086
3087 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3088 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3089
3090 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3091 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3092 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3093 break;
3094
3095 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3096 Log2(("VMX: clts\n"));
3097 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3098 rc = EMInterpretCLTS(pVM, pVCpu);
3099 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3100 break;
3101
3102 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3103 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3104 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3105 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3106 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3107 break;
3108 }
3109
3110 /* Update EIP if no error occurred. */
3111 if (RT_SUCCESS(rc))
3112 pCtx->rip += cbInstr;
3113
3114 if (rc == VINF_SUCCESS)
3115 {
3116 /* Only resume if successful. */
3117 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3118 goto ResumeExecution;
3119 }
3120 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3121 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3122 break;
3123 }
3124
3125 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3126 {
3127 if (!DBGFIsStepping(pVCpu))
3128 {
3129 /* Disable drx move intercepts. */
3130 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3131 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3132 AssertRC(rc);
3133
3134 /* Save the host and load the guest debug state. */
3135 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3136 AssertRC(rc);
3137
3138#ifdef VBOX_WITH_STATISTICS
3139 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3140 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3141 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3142 else
3143 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3144#endif
3145
3146 goto ResumeExecution;
3147 }
3148
3149 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3150 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3151 {
3152 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3153 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3154 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3155 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3156 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3157 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3158 Log2(("DR7=%08x\n", pCtx->dr[7]));
3159 }
3160 else
3161 {
3162 Log2(("VMX: mov x, drx\n"));
3163 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3164 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3165 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3166 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3167 }
3168 /* Update EIP if no error occurred. */
3169 if (RT_SUCCESS(rc))
3170 pCtx->rip += cbInstr;
3171
3172 if (rc == VINF_SUCCESS)
3173 {
3174 /* Only resume if successful. */
3175 goto ResumeExecution;
3176 }
3177 Assert(rc == VERR_EM_INTERPRETER);
3178 break;
3179 }
3180
3181 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3182 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3183 {
3184 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3185 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3186 uint32_t uPort;
3187 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3188
3189 /** @todo necessary to make the distinction? */
3190 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3191 {
3192 uPort = pCtx->edx & 0xffff;
3193 }
3194 else
3195 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3196
3197 /* paranoia */
3198 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3199 {
3200 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3201 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3202 break;
3203 }
3204
3205 uint32_t cbSize = g_aIOSize[uIOWidth];
3206
3207 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3208 {
3209 /* ins/outs */
3210 DISCPUSTATE Cpu;
3211
3212 /* Disassemble manually to deal with segment prefixes. */
3213 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3214 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3215 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, NULL);
3216 if (rc == VINF_SUCCESS)
3217 {
3218 if (fIOWrite)
3219 {
3220 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3221 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3222 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
3223 }
3224 else
3225 {
3226 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3227 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3228 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
3229 }
3230 }
3231 else
3232 rc = VINF_EM_RAW_EMULATE_INSTR;
3233 }
3234 else
3235 {
3236 /* normal in/out */
3237 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3238
3239 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3240
3241 if (fIOWrite)
3242 {
3243 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3244 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3245 }
3246 else
3247 {
3248 uint32_t u32Val = 0;
3249
3250 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3251 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3252 if (IOM_SUCCESS(rc))
3253 {
3254 /* Write back to the EAX register. */
3255 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3256 }
3257 }
3258 }
3259 /*
3260 * Handled the I/O return codes.
3261 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3262 */
3263 if (IOM_SUCCESS(rc))
3264 {
3265 /* Update EIP and continue execution. */
3266 pCtx->rip += cbInstr;
3267 if (RT_LIKELY(rc == VINF_SUCCESS))
3268 {
3269 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3270 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3271 {
3272 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3273 for (unsigned i=0;i<4;i++)
3274 {
3275 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3276
3277 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3278 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3279 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3280 {
3281 uint64_t uDR6;
3282
3283 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3284
3285 uDR6 = ASMGetDR6();
3286
3287 /* Clear all breakpoint status flags and set the one we just hit. */
3288 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3289 uDR6 |= (uint64_t)RT_BIT(i);
3290
3291 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3292 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3293 * the contents have been read.
3294 */
3295 ASMSetDR6(uDR6);
3296
3297 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3298 pCtx->dr[7] &= ~X86_DR7_GD;
3299
3300 /* Paranoia. */
3301 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3302 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3303 pCtx->dr[7] |= 0x400; /* must be one */
3304
3305 /* Resync DR7 */
3306 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3307 AssertRC(rc);
3308
3309 /* Construct inject info. */
3310 intInfo = X86_XCPT_DB;
3311 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3312 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3313
3314 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3315 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3316 AssertRC(rc);
3317
3318 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3319 goto ResumeExecution;
3320 }
3321 }
3322 }
3323
3324 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3325 goto ResumeExecution;
3326 }
3327 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3328 break;
3329 }
3330
3331#ifdef VBOX_STRICT
3332 if (rc == VINF_IOM_HC_IOPORT_READ)
3333 Assert(!fIOWrite);
3334 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3335 Assert(fIOWrite);
3336 else
3337 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3338#endif
3339 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3340 break;
3341 }
3342
3343 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3344 LogFlow(("VMX_EXIT_TPR\n"));
3345 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3346 goto ResumeExecution;
3347
3348 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3349 goto ResumeExecution;
3350
3351 default:
3352 /* The rest is handled after syncing the entire CPU state. */
3353 break;
3354 }
3355
3356 /* Note: the guest state isn't entirely synced back at this stage. */
3357
3358 /* Investigate why there was a VM-exit. (part 2) */
3359 switch (exitReason)
3360 {
3361 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3362 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3363 case VMX_EXIT_EPT_VIOLATION:
3364 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3365 /* Already handled above. */
3366 break;
3367
3368 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3369 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3370 break;
3371
3372 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3373 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3374 rc = VINF_EM_RAW_INTERRUPT;
3375 AssertFailed(); /* Can't happen. Yet. */
3376 break;
3377
3378 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3379 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3380 rc = VINF_EM_RAW_INTERRUPT;
3381 AssertFailed(); /* Can't happen afaik. */
3382 break;
3383
3384 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3385 rc = VERR_EM_INTERPRETER;
3386 break;
3387
3388 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3389 /** Check if external interrupts are pending; if so, don't switch back. */
3390 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
3391 pCtx->rip++; /* skip hlt */
3392 if ( pCtx->eflags.Bits.u1IF
3393 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3394 goto ResumeExecution;
3395
3396 rc = VINF_EM_HALT;
3397 break;
3398
3399 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3400 Log2(("VMX: mwait\n"));
3401 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
3402 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3403 if ( rc == VINF_EM_HALT
3404 || rc == VINF_SUCCESS)
3405 {
3406 /* Update EIP and continue execution. */
3407 pCtx->rip += cbInstr;
3408
3409 /** Check if external interrupts are pending; if so, don't switch back. */
3410 if ( rc == VINF_SUCCESS
3411 || ( rc == VINF_EM_HALT
3412 && pCtx->eflags.Bits.u1IF
3413 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3414 )
3415 goto ResumeExecution;
3416 }
3417 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
3418 break;
3419
3420 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3421 AssertFailed(); /* can't happen. */
3422 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3423 break;
3424
3425 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3426 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3427 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3428 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3429 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3430 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3431 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3432 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3433 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3434 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3435 /** @todo inject #UD immediately */
3436 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3437 break;
3438
3439 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3440 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3441 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3442 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3443 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3444 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3445 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3446 /* already handled above */
3447 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3448 || rc == VINF_EM_RAW_INTERRUPT
3449 || rc == VERR_EM_INTERPRETER
3450 || rc == VINF_EM_RAW_EMULATE_INSTR
3451 || rc == VINF_PGM_SYNC_CR3
3452 || rc == VINF_IOM_HC_IOPORT_READ
3453 || rc == VINF_IOM_HC_IOPORT_WRITE
3454 || rc == VINF_EM_RAW_GUEST_TRAP
3455 || rc == VINF_TRPM_XCPT_DISPATCHED
3456 || rc == VINF_EM_RESCHEDULE_REM,
3457 ("rc = %d\n", rc));
3458 break;
3459
3460 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3461 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3462 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3463 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3464 rc = VERR_EM_INTERPRETER;
3465 break;
3466
3467 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3468 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3469 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3470 break;
3471
3472 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3473 Assert(rc == VINF_EM_RAW_INTERRUPT);
3474 break;
3475
3476 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3477 {
3478#ifdef VBOX_STRICT
3479 RTCCUINTREG val = 0;
3480
3481 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3482
3483 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3484 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3485
3486 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3487 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3488
3489 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3490 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3491
3492 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3493 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3494
3495 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3496 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3497
3498 VMX_LOG_SELREG(CS, "CS");
3499 VMX_LOG_SELREG(DS, "DS");
3500 VMX_LOG_SELREG(ES, "ES");
3501 VMX_LOG_SELREG(FS, "FS");
3502 VMX_LOG_SELREG(GS, "GS");
3503 VMX_LOG_SELREG(SS, "SS");
3504 VMX_LOG_SELREG(TR, "TR");
3505 VMX_LOG_SELREG(LDTR, "LDTR");
3506
3507 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3508 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3509 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3510 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3511#endif /* VBOX_STRICT */
3512 rc = VERR_VMX_INVALID_GUEST_STATE;
3513 break;
3514 }
3515
3516 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3517 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3518 default:
3519 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3520 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3521 break;
3522
3523 }
3524end:
3525
3526 /* Signal changes for the recompiler. */
3527 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3528
3529 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3530 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3531 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3532 {
3533 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3534 /* On the next entry we'll only sync the host context. */
3535 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3536 }
3537 else
3538 {
3539 /* On the next entry we'll sync everything. */
3540 /** @todo we can do better than this */
3541 /* Not in the VINF_PGM_CHANGE_MODE though! */
3542 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3543 }
3544
3545 /* translate into a less severe return code */
3546 if (rc == VERR_EM_INTERPRETER)
3547 rc = VINF_EM_RAW_EMULATE_INSTR;
3548 else
3549 /* Try to extract more information about what might have gone wrong here. */
3550 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3551 {
3552 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3553 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3554 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3555 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3556 }
3557
3558 /* Just set the correct state here instead of trying to catch every goto above. */
3559 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
3560
3561 STAM_STATS({
3562 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3563 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3564 });
3565 Log2(("X"));
3566 return rc;
3567}
3568
3569
3570/**
3571 * Enters the VT-x session
3572 *
3573 * @returns VBox status code.
3574 * @param pVM The VM to operate on.
3575 * @param pVCpu The VMCPU to operate on.
3576 * @param pCpu CPU info struct
3577 */
3578VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3579{
3580 Assert(pVM->hwaccm.s.vmx.fSupported);
3581
3582 unsigned cr4 = ASMGetCR4();
3583 if (!(cr4 & X86_CR4_VMXE))
3584 {
3585 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3586 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3587 }
3588
3589 /* Activate the VM Control Structure. */
3590 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3591 if (RT_FAILURE(rc))
3592 return rc;
3593
3594 pVCpu->hwaccm.s.fResumeVM = false;
3595 return VINF_SUCCESS;
3596}
3597
3598
3599/**
3600 * Leaves the VT-x session
3601 *
3602 * @returns VBox status code.
3603 * @param pVM The VM to operate on.
3604 * @param pVCpu The VMCPU to operate on.
3605 * @param pCtx CPU context
3606 */
3607VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3608{
3609 Assert(pVM->hwaccm.s.vmx.fSupported);
3610
3611 /* Save the guest debug state if necessary. */
3612 if (CPUMIsGuestDebugStateActive(pVCpu))
3613 {
3614 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3615
3616 /* Enable drx move intercepts again. */
3617 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3618 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3619 AssertRC(rc);
3620
3621 /* Resync the debug registers the next time. */
3622 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3623 }
3624 else
3625 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3626
3627 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3628 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3629 AssertRC(rc);
3630
3631 return VINF_SUCCESS;
3632}
3633
3634/**
3635 * Flush the TLB (EPT)
3636 *
3637 * @returns VBox status code.
3638 * @param pVM The VM to operate on.
3639 * @param pVCpu The VM CPU to operate on.
3640 * @param enmFlush Type of flush
3641 * @param GCPhys Physical address of the page to flush
3642 */
3643static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3644{
3645 uint64_t descriptor[2];
3646
3647 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3648 Assert(pVM->hwaccm.s.fNestedPaging);
3649 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3650 descriptor[1] = GCPhys;
3651 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3652 AssertRC(rc);
3653}
3654
3655#ifdef HWACCM_VTX_WITH_VPID
3656/**
3657 * Flush the TLB (EPT)
3658 *
3659 * @returns VBox status code.
3660 * @param pVM The VM to operate on.
3661 * @param pVCpu The VM CPU to operate on.
3662 * @param enmFlush Type of flush
3663 * @param GCPtr Virtual address of the page to flush
3664 */
3665static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3666{
3667#if HC_ARCH_BITS == 32
3668 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3669 if ( CPUMIsGuestInLongMode(pVCpu)
3670 && !VMX_IS_64BIT_HOST_MODE())
3671 {
3672 pVCpu->hwaccm.s.fForceTLBFlush = true;
3673 }
3674 else
3675#endif
3676 {
3677 uint64_t descriptor[2];
3678
3679 Assert(pVM->hwaccm.s.vmx.fVPID);
3680 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3681 descriptor[1] = GCPtr;
3682 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3683 AssertRC(rc);
3684 }
3685}
3686#endif /* HWACCM_VTX_WITH_VPID */
3687
3688/**
3689 * Invalidates a guest page
3690 *
3691 * @returns VBox status code.
3692 * @param pVM The VM to operate on.
3693 * @param pVCpu The VM CPU to operate on.
3694 * @param GCVirt Page to invalidate
3695 */
3696VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3697{
3698 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3699
3700 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3701
3702 /* Only relevant if we want to use VPID.
3703 * In the nested paging case we still see such calls, but
3704 * can safely ignore them. (e.g. after cr3 updates)
3705 */
3706#ifdef HWACCM_VTX_WITH_VPID
3707 /* Skip it if a TLB flush is already pending. */
3708 if ( !fFlushPending
3709 && pVM->hwaccm.s.vmx.fVPID)
3710 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3711#endif /* HWACCM_VTX_WITH_VPID */
3712
3713 return VINF_SUCCESS;
3714}
3715
3716/**
3717 * Invalidates a guest page by physical address
3718 *
3719 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3720 *
3721 * @returns VBox status code.
3722 * @param pVM The VM to operate on.
3723 * @param pVCpu The VM CPU to operate on.
3724 * @param GCPhys Page to invalidate
3725 */
3726VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3727{
3728 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3729
3730 Assert(pVM->hwaccm.s.fNestedPaging);
3731
3732 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3733
3734 /* Skip it if a TLB flush is already pending. */
3735 if (!fFlushPending)
3736 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3737
3738 return VINF_SUCCESS;
3739}
3740
3741/**
3742 * Report world switch error and dump some useful debug info
3743 *
3744 * @param pVM The VM to operate on.
3745 * @param pVCpu The VMCPU to operate on.
3746 * @param rc Return code
3747 * @param pCtx Current CPU context (not updated)
3748 */
3749static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3750{
3751 switch (rc)
3752 {
3753 case VERR_VMX_INVALID_VMXON_PTR:
3754 AssertFailed();
3755 break;
3756
3757 case VERR_VMX_UNABLE_TO_START_VM:
3758 case VERR_VMX_UNABLE_TO_RESUME_VM:
3759 {
3760 int rc;
3761 RTCCUINTREG exitReason, instrError;
3762
3763 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3764 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3765 AssertRC(rc);
3766 if (rc == VINF_SUCCESS)
3767 {
3768 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3769 Log(("Current stack %08x\n", &rc));
3770
3771 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3772 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3773
3774#ifdef VBOX_STRICT
3775 RTGDTR gdtr;
3776 PX86DESCHC pDesc;
3777 RTCCUINTREG val;
3778
3779 ASMGetGDTR(&gdtr);
3780
3781 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3782 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3783 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3784 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3785 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3786 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3787 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3788 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3789 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3790 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3791
3792 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3793 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3794
3795 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3796 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3797
3798 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3799 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3800
3801 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3802 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3803
3804 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3805 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3806
3807 if (val < gdtr.cbGdt)
3808 {
3809 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3810 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3811 }
3812
3813 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3814 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3815 if (val < gdtr.cbGdt)
3816 {
3817 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3818 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3819 }
3820
3821 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
3822 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3823 if (val < gdtr.cbGdt)
3824 {
3825 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3826 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3827 }
3828
3829 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
3830 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
3831 if (val < gdtr.cbGdt)
3832 {
3833 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3834 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3835 }
3836
3837 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
3838 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
3839 if (val < gdtr.cbGdt)
3840 {
3841 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3842 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3843 }
3844
3845 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
3846 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
3847 if (val < gdtr.cbGdt)
3848 {
3849 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3850 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3851 }
3852
3853 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
3854 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
3855 if (val < gdtr.cbGdt)
3856 {
3857 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3858 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3859 }
3860
3861 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3862 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
3863
3864 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3865 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
3866 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3867 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
3868
3869 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
3870 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3871
3872 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3873 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
3874
3875 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3876 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
3877
3878 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3879 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
3880 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3881 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
3882
3883# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3884 if (VMX_IS_64BIT_HOST_MODE())
3885 {
3886 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
3887 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
3888 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3889 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3890 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3891 }
3892# endif
3893#endif /* VBOX_STRICT */
3894 }
3895 break;
3896 }
3897
3898 default:
3899 /* impossible */
3900 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
3901 break;
3902 }
3903}
3904
3905#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3906/**
3907 * Prepares for and executes VMLAUNCH (64 bits guest mode)
3908 *
3909 * @returns VBox status code
3910 * @param fResume vmlauch/vmresume
3911 * @param pCtx Guest context
3912 * @param pCache VMCS cache
3913 * @param pVM The VM to operate on.
3914 * @param pVCpu The VMCPU to operate on.
3915 */
3916DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
3917{
3918 uint32_t aParam[6];
3919 PHWACCM_CPUINFO pCpu;
3920 RTHCPHYS pPageCpuPhys;
3921 int rc;
3922
3923 pCpu = HWACCMR0GetCurrentCpu();
3924 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3925
3926#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3927 pCache->uPos = 1;
3928 pCache->interPD = PGMGetInterPaeCR3(pVM);
3929 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
3930#endif
3931
3932#ifdef DEBUG
3933 pCache->TestIn.pPageCpuPhys = 0;
3934 pCache->TestIn.pVMCSPhys = 0;
3935 pCache->TestIn.pCache = 0;
3936 pCache->TestOut.pVMCSPhys = 0;
3937 pCache->TestOut.pCache = 0;
3938 pCache->TestOut.pCtx = 0;
3939 pCache->TestOut.eflags = 0;
3940#endif
3941
3942 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
3943 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
3944 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
3945 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
3946 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
3947 aParam[5] = 0;
3948
3949#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3950 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
3951 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
3952#endif
3953 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
3954
3955#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3956 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
3957 Assert(pCtx->dr[4] == 10);
3958 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
3959#endif
3960
3961#ifdef DEBUG
3962 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
3963 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
3964 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
3965 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
3966 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
3967 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
3968 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
3969#endif
3970 return rc;
3971}
3972
3973/**
3974 * Executes the specified handler in 64 mode
3975 *
3976 * @returns VBox status code.
3977 * @param pVM The VM to operate on.
3978 * @param pVCpu The VMCPU to operate on.
3979 * @param pCtx Guest context
3980 * @param pfnHandler RC handler
3981 * @param cbParam Number of parameters
3982 * @param paParam Array of 32 bits parameters
3983 */
3984VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
3985{
3986 int rc, rc2;
3987 PHWACCM_CPUINFO pCpu;
3988 RTHCPHYS pPageCpuPhys;
3989
3990 /* @todo This code is not guest SMP safe (hyper stack) */
3991 AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
3992 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
3993 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
3994 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
3995
3996#ifdef VBOX_STRICT
3997 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
3998 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
3999
4000 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
4001 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
4002#endif
4003
4004 pCpu = HWACCMR0GetCurrentCpu();
4005 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4006
4007 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4008 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4009
4010 /* Leave VMX Root Mode. */
4011 VMXDisable();
4012
4013 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4014
4015 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
4016 CPUMSetHyperEIP(pVCpu, pfnHandler);
4017 for (int i=(int)cbParam-1;i>=0;i--)
4018 CPUMPushHyper(pVCpu, paParam[i]);
4019
4020 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4021 /* Call switcher. */
4022 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
4023 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4024
4025 /* Make sure the VMX instructions don't cause #UD faults. */
4026 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
4027
4028 /* Enter VMX Root Mode */
4029 rc2 = VMXEnable(pPageCpuPhys);
4030 if (RT_FAILURE(rc2))
4031 {
4032 if (pVM)
4033 VMXR0CheckError(pVM, pVCpu, rc2);
4034 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4035 return VERR_VMX_VMXON_FAILED;
4036 }
4037
4038 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4039 AssertRCReturn(rc2, rc2);
4040#ifdef RT_OS_WINDOWS
4041 Assert(ASMGetFlags() & X86_EFL_IF);
4042#else
4043 Assert(!(ASMGetFlags() & X86_EFL_IF));
4044#endif
4045 return rc;
4046}
4047
4048#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4049
4050
4051#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4052/**
4053 * Executes VMWRITE
4054 *
4055 * @returns VBox status code
4056 * @param pVCpu The VMCPU to operate on.
4057 * @param idxField VMCS index
4058 * @param u64Val 16, 32 or 64 bits value
4059 */
4060VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4061{
4062 int rc;
4063
4064 switch (idxField)
4065 {
4066 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4067 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4068 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4069 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4070 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4071 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4072 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4073 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4074 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4075 case VMX_VMCS_GUEST_PDPTR0_FULL:
4076 case VMX_VMCS_GUEST_PDPTR1_FULL:
4077 case VMX_VMCS_GUEST_PDPTR2_FULL:
4078 case VMX_VMCS_GUEST_PDPTR3_FULL:
4079 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4080 case VMX_VMCS_GUEST_EFER_FULL:
4081 case VMX_VMCS_CTRL_EPTP_FULL:
4082 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4083 rc = VMXWriteVMCS32(idxField, u64Val);
4084 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4085 AssertRC(rc);
4086 return rc;
4087
4088 case VMX_VMCS64_GUEST_LDTR_BASE:
4089 case VMX_VMCS64_GUEST_TR_BASE:
4090 case VMX_VMCS64_GUEST_GDTR_BASE:
4091 case VMX_VMCS64_GUEST_IDTR_BASE:
4092 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4093 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4094 case VMX_VMCS64_GUEST_CR0:
4095 case VMX_VMCS64_GUEST_CR4:
4096 case VMX_VMCS64_GUEST_CR3:
4097 case VMX_VMCS64_GUEST_DR7:
4098 case VMX_VMCS64_GUEST_RIP:
4099 case VMX_VMCS64_GUEST_RSP:
4100 case VMX_VMCS64_GUEST_CS_BASE:
4101 case VMX_VMCS64_GUEST_DS_BASE:
4102 case VMX_VMCS64_GUEST_ES_BASE:
4103 case VMX_VMCS64_GUEST_FS_BASE:
4104 case VMX_VMCS64_GUEST_GS_BASE:
4105 case VMX_VMCS64_GUEST_SS_BASE:
4106 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4107 if (u64Val >> 32ULL)
4108 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4109 else
4110 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4111
4112 return rc;
4113
4114 default:
4115 AssertMsgFailed(("Unexpected field %x\n", idxField));
4116 return VERR_INVALID_PARAMETER;
4117 }
4118}
4119
4120/**
4121 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4122 *
4123 * @param pVCpu The VMCPU to operate on.
4124 * @param idxField VMCS field
4125 * @param u64Val Value
4126 */
4127VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4128{
4129 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4130
4131 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4132
4133 /* Make sure there are no duplicates. */
4134 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4135 {
4136 if (pCache->Write.aField[i] == idxField)
4137 {
4138 pCache->Write.aFieldVal[i] = u64Val;
4139 return VINF_SUCCESS;
4140 }
4141 }
4142
4143 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4144 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4145 pCache->Write.cValidEntries++;
4146 return VINF_SUCCESS;
4147}
4148
4149#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4150
4151#ifdef VBOX_STRICT
4152static bool vmxR0IsValidReadField(uint32_t idxField)
4153{
4154 switch(idxField)
4155 {
4156 case VMX_VMCS64_GUEST_RIP:
4157 case VMX_VMCS64_GUEST_RSP:
4158 case VMX_VMCS_GUEST_RFLAGS:
4159 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4160 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4161 case VMX_VMCS64_GUEST_CR0:
4162 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4163 case VMX_VMCS64_GUEST_CR4:
4164 case VMX_VMCS64_GUEST_DR7:
4165 case VMX_VMCS32_GUEST_SYSENTER_CS:
4166 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4167 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4168 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4169 case VMX_VMCS64_GUEST_GDTR_BASE:
4170 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4171 case VMX_VMCS64_GUEST_IDTR_BASE:
4172 case VMX_VMCS16_GUEST_FIELD_CS:
4173 case VMX_VMCS32_GUEST_CS_LIMIT:
4174 case VMX_VMCS64_GUEST_CS_BASE:
4175 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4176 case VMX_VMCS16_GUEST_FIELD_DS:
4177 case VMX_VMCS32_GUEST_DS_LIMIT:
4178 case VMX_VMCS64_GUEST_DS_BASE:
4179 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4180 case VMX_VMCS16_GUEST_FIELD_ES:
4181 case VMX_VMCS32_GUEST_ES_LIMIT:
4182 case VMX_VMCS64_GUEST_ES_BASE:
4183 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4184 case VMX_VMCS16_GUEST_FIELD_FS:
4185 case VMX_VMCS32_GUEST_FS_LIMIT:
4186 case VMX_VMCS64_GUEST_FS_BASE:
4187 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4188 case VMX_VMCS16_GUEST_FIELD_GS:
4189 case VMX_VMCS32_GUEST_GS_LIMIT:
4190 case VMX_VMCS64_GUEST_GS_BASE:
4191 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4192 case VMX_VMCS16_GUEST_FIELD_SS:
4193 case VMX_VMCS32_GUEST_SS_LIMIT:
4194 case VMX_VMCS64_GUEST_SS_BASE:
4195 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4196 case VMX_VMCS16_GUEST_FIELD_LDTR:
4197 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4198 case VMX_VMCS64_GUEST_LDTR_BASE:
4199 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4200 case VMX_VMCS16_GUEST_FIELD_TR:
4201 case VMX_VMCS32_GUEST_TR_LIMIT:
4202 case VMX_VMCS64_GUEST_TR_BASE:
4203 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4204 case VMX_VMCS32_RO_EXIT_REASON:
4205 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4206 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4207 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4208 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4209 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4210 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4211 case VMX_VMCS32_RO_IDT_INFO:
4212 case VMX_VMCS32_RO_IDT_ERRCODE:
4213 case VMX_VMCS64_GUEST_CR3:
4214 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4215 return true;
4216 }
4217 return false;
4218}
4219
4220static bool vmxR0IsValidWriteField(uint32_t idxField)
4221{
4222 switch(idxField)
4223 {
4224 case VMX_VMCS64_GUEST_LDTR_BASE:
4225 case VMX_VMCS64_GUEST_TR_BASE:
4226 case VMX_VMCS64_GUEST_GDTR_BASE:
4227 case VMX_VMCS64_GUEST_IDTR_BASE:
4228 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4229 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4230 case VMX_VMCS64_GUEST_CR0:
4231 case VMX_VMCS64_GUEST_CR4:
4232 case VMX_VMCS64_GUEST_CR3:
4233 case VMX_VMCS64_GUEST_DR7:
4234 case VMX_VMCS64_GUEST_RIP:
4235 case VMX_VMCS64_GUEST_RSP:
4236 case VMX_VMCS64_GUEST_CS_BASE:
4237 case VMX_VMCS64_GUEST_DS_BASE:
4238 case VMX_VMCS64_GUEST_ES_BASE:
4239 case VMX_VMCS64_GUEST_FS_BASE:
4240 case VMX_VMCS64_GUEST_GS_BASE:
4241 case VMX_VMCS64_GUEST_SS_BASE:
4242 return true;
4243 }
4244 return false;
4245}
4246
4247#endif
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