VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 20667

Last change on this file since 20667 was 20667, checked in by vboxsync, 15 years ago

Wrong assertion
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 175.1 KB
Line 
1/* $Id: HWVMXR0.cpp 20667 2009-06-17 13:10:23Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/param.h>
41#include <iprt/string.h>
42#include <iprt/time.h>
43#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
44# include <iprt/thread.h>
45#endif
46#include "HWVMXR0.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51#if defined(RT_ARCH_AMD64)
52# define VMX_IS_64BIT_HOST_MODE() (true)
53#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
54# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
55#else
56# define VMX_IS_64BIT_HOST_MODE() (false)
57#endif
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62/* IO operation lookup arrays. */
63static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
65
66#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
67/** See HWACCMR0A.asm. */
68extern "C" uint32_t g_fVMXIs64bitHost;
69#endif
70
71/*******************************************************************************
72* Local Functions *
73*******************************************************************************/
74static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
75static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
76static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
77static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
78static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
79static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
80static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
81#ifdef VBOX_STRICT
82static bool vmxR0IsValidReadField(uint32_t idxField);
83static bool vmxR0IsValidWriteField(uint32_t idxField);
84#endif
85
86static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
87{
88 if (rc == VERR_VMX_GENERIC)
89 {
90 RTCCUINTREG instrError;
91
92 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
93 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
94 }
95 pVM->hwaccm.s.lLastError = rc;
96}
97
98/**
99 * Sets up and activates VT-x on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pVM The VM to operate on. (can be NULL after a resume!!)
104 * @param pvPageCpu Pointer to the global cpu page
105 * @param pPageCpuPhys Physical address of the global cpu page
106 */
107VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
108{
109 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
110 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
111
112#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
113 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
114#endif
115 if (pVM)
116 {
117 /* Set revision dword at the beginning of the VMXON structure. */
118 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
119 }
120
121 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
122 * (which can have very bad consequences!!!)
123 */
124
125 /* Make sure the VMX instructions don't cause #UD faults. */
126 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
127
128 /* Enter VMX Root Mode */
129 int rc = VMXEnable(pPageCpuPhys);
130 if (RT_FAILURE(rc))
131 {
132 if (pVM)
133 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
134 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
135 return VERR_VMX_VMXON_FAILED;
136 }
137 return VINF_SUCCESS;
138}
139
140/**
141 * Deactivates VT-x on the current CPU
142 *
143 * @returns VBox status code.
144 * @param pCpu CPU info struct
145 * @param pvPageCpu Pointer to the global cpu page
146 * @param pPageCpuPhys Physical address of the global cpu page
147 */
148VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
149{
150 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
151 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
152
153 /* Leave VMX Root Mode. */
154 VMXDisable();
155
156 /* And clear the X86_CR4_VMXE bit */
157 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
158
159#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
160 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
161#endif
162 return VINF_SUCCESS;
163}
164
165/**
166 * Does Ring-0 per VM VT-x init.
167 *
168 * @returns VBox status code.
169 * @param pVM The VM to operate on.
170 */
171VMMR0DECL(int) VMXR0InitVM(PVM pVM)
172{
173 int rc;
174
175#ifdef LOG_ENABLED
176 SUPR0Printf("VMXR0InitVM %x\n", pVM);
177#endif
178
179 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
180
181 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
182 {
183 /* Allocate one page for the APIC physical page (serves for filtering accesses). */
184 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185 AssertRC(rc);
186 if (RT_FAILURE(rc))
187 return rc;
188
189 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
190 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
191 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
192 }
193 else
194 {
195 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
196 pVM->hwaccm.s.vmx.pAPIC = 0;
197 pVM->hwaccm.s.vmx.pAPICPhys = 0;
198 }
199
200 /* Allocate the MSR bitmap if this feature is supported. */
201 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
202 {
203 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
204 AssertRC(rc);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
209 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
210 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
211 }
212
213#ifdef VBOX_WITH_CRASHDUMP_MAGIC
214 {
215 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
216 AssertRC(rc);
217 if (RT_FAILURE(rc))
218 return rc;
219
220 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
221 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
222
223 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
224 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
225 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
226 }
227#endif
228
229 /* Allocate VMCBs for all guest CPUs. */
230 for (unsigned i=0;i<pVM->cCPUs;i++)
231 {
232 PVMCPU pVCpu = &pVM->aCpus[i];
233
234 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
235
236 /* Allocate one page for the VM control structure (VMCS). */
237 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
238 AssertRC(rc);
239 if (RT_FAILURE(rc))
240 return rc;
241
242 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
243 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
244 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
245
246 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
247 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
248
249 /* Allocate one page for the virtual APIC page for TPR caching. */
250 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
251 AssertRC(rc);
252 if (RT_FAILURE(rc))
253 return rc;
254
255 pVCpu->hwaccm.s.vmx.pVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
256 pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
257 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
258
259 /* Current guest paging mode. */
260 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
261
262#ifdef LOG_ENABLED
263 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
264#endif
265 }
266
267 return VINF_SUCCESS;
268}
269
270/**
271 * Does Ring-0 per VM VT-x termination.
272 *
273 * @returns VBox status code.
274 * @param pVM The VM to operate on.
275 */
276VMMR0DECL(int) VMXR0TermVM(PVM pVM)
277{
278 for (unsigned i=0;i<pVM->cCPUs;i++)
279 {
280 PVMCPU pVCpu = &pVM->aCpus[i];
281
282 if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
283 {
284 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
285 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
286 pVCpu->hwaccm.s.vmx.pVMCS = 0;
287 pVCpu->hwaccm.s.vmx.pVMCSPhys = 0;
288 }
289 if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
290 {
291 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
292 pVCpu->hwaccm.s.vmx.pMemObjVAPIC = NIL_RTR0MEMOBJ;
293 pVCpu->hwaccm.s.vmx.pVAPIC = 0;
294 pVCpu->hwaccm.s.vmx.pVAPICPhys = 0;
295 }
296 }
297 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
298 {
299 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
300 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
301 pVM->hwaccm.s.vmx.pAPIC = 0;
302 pVM->hwaccm.s.vmx.pAPICPhys = 0;
303 }
304 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
305 {
306 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
307 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
308 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
309 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
310 }
311#ifdef VBOX_WITH_CRASHDUMP_MAGIC
312 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
313 {
314 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
315 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
316 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
317 pVM->hwaccm.s.vmx.pScratch = 0;
318 pVM->hwaccm.s.vmx.pScratchPhys = 0;
319 }
320#endif
321 return VINF_SUCCESS;
322}
323
324/**
325 * Sets up VT-x for the specified VM
326 *
327 * @returns VBox status code.
328 * @param pVM The VM to operate on.
329 */
330VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
331{
332 int rc = VINF_SUCCESS;
333 uint32_t val;
334
335 AssertReturn(pVM, VERR_INVALID_PARAMETER);
336
337 for (unsigned i=0;i<pVM->cCPUs;i++)
338 {
339 PVMCPU pVCpu = &pVM->aCpus[i];
340
341 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
342
343 /* Set revision dword at the beginning of the VMCS structure. */
344 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
345
346 /* Clear VM Control Structure. */
347 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
348 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
349 if (RT_FAILURE(rc))
350 goto vmx_end;
351
352 /* Activate the VM Control Structure. */
353 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
354 if (RT_FAILURE(rc))
355 goto vmx_end;
356
357 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
358 * Set required bits to one and zero according to the MSR capabilities.
359 */
360 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
361 /* External and non-maskable interrupts cause VM-exits. */
362 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
363 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
364
365 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
366 AssertRC(rc);
367
368 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
369 * Set required bits to one and zero according to the MSR capabilities.
370 */
371 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
372 /* Program which event cause VM-exits and which features we want to use. */
373 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
374 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
375 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
376 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
377 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
378 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
379
380 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
381 if (!pVM->hwaccm.s.fNestedPaging)
382 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
383 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
384 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
385
386 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
387 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
388 {
389 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
390 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
391 Assert(pVM->hwaccm.s.vmx.pAPIC);
392 }
393 else
394 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
395 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
396
397#ifdef VBOX_WITH_VTX_MSR_BITMAPS
398 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
399 {
400 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
401 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
402 }
403#endif
404
405 /* We will use the secondary control if it's present. */
406 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
407
408 /* Mask away the bits that the CPU doesn't support */
409 /** @todo make sure they don't conflict with the above requirements. */
410 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
411 pVCpu->hwaccm.s.vmx.proc_ctls = val;
412
413 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
414 AssertRC(rc);
415
416 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
417 {
418 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
419 * Set required bits to one and zero according to the MSR capabilities.
420 */
421 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
422 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
423
424#ifdef HWACCM_VTX_WITH_EPT
425 if (pVM->hwaccm.s.fNestedPaging)
426 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
427#endif /* HWACCM_VTX_WITH_EPT */
428#ifdef HWACCM_VTX_WITH_VPID
429 else
430 if (pVM->hwaccm.s.vmx.fVPID)
431 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
432#endif /* HWACCM_VTX_WITH_VPID */
433
434 if (pVM->hwaccm.s.fHasIoApic)
435 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC;
436
437 /* Mask away the bits that the CPU doesn't support */
438 /** @todo make sure they don't conflict with the above requirements. */
439 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
440 pVCpu->hwaccm.s.vmx.proc_ctls2 = val;
441 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
442 AssertRC(rc);
443 }
444
445 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
446 * Set required bits to one and zero according to the MSR capabilities.
447 */
448 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
449 AssertRC(rc);
450
451 /* Forward all exception except #NM & #PF to the guest.
452 * We always need to check pagefaults since our shadow page table can be out of sync.
453 * And we always lazily sync the FPU & XMM state.
454 */
455
456 /** @todo Possible optimization:
457 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
458 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
459 * registers ourselves of course.
460 *
461 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
462 */
463
464 /* Don't filter page faults; all of them should cause a switch. */
465 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
467 AssertRC(rc);
468
469 /* Init TSC offset to zero. */
470 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
471 AssertRC(rc);
472
473 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
474 AssertRC(rc);
475
476 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
477 AssertRC(rc);
478
479 /* Set the MSR bitmap address. */
480 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
481 {
482 /* Optional */
483 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
484 AssertRC(rc);
485 }
486
487 /* Clear MSR controls. */
488 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
489 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
490 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
491 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
492 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
493 AssertRC(rc);
494
495 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
496 {
497 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
498 /* Optional */
499 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
500 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
501
502 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
503 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
504
505 AssertRC(rc);
506 }
507
508 /* Set link pointer to -1. Not currently used. */
509 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
510 AssertRC(rc);
511
512 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
513 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
514 AssertRC(rc);
515
516 /* Configure the VMCS read cache. */
517 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
518
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
525 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
526 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
527 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
530 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
531 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
532 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
533 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
534 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
535
536 VMX_SETUP_SELREG(ES, pCache);
537 VMX_SETUP_SELREG(SS, pCache);
538 VMX_SETUP_SELREG(CS, pCache);
539 VMX_SETUP_SELREG(DS, pCache);
540 VMX_SETUP_SELREG(FS, pCache);
541 VMX_SETUP_SELREG(GS, pCache);
542 VMX_SETUP_SELREG(LDTR, pCache);
543 VMX_SETUP_SELREG(TR, pCache);
544
545 /* Status code VMCS reads. */
546 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
547 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
548 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
549 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
550 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
551 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
552 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
553 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
554 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
555
556 if (pVM->hwaccm.s.fNestedPaging)
557 {
558 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
559 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
560 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
561 }
562 else
563 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
564 } /* for each VMCPU */
565
566 /* Choose the right TLB setup function. */
567 if (pVM->hwaccm.s.fNestedPaging)
568 {
569 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
570
571 /* Default values for flushing. */
572 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
574
575 /* If the capabilities specify we can do more, then make use of it. */
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
577 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
578 else
579 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
580 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
581
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
583 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
584 }
585#ifdef HWACCM_VTX_WITH_VPID
586 else
587 if (pVM->hwaccm.s.vmx.fVPID)
588 {
589 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
590
591 /* Default values for flushing. */
592 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
593 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
594
595 /* If the capabilities specify we can do more, then make use of it. */
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
597 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
598 else
599 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
600 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
601
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
603 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
604 }
605#endif /* HWACCM_VTX_WITH_VPID */
606 else
607 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
608
609vmx_end:
610 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
611 return rc;
612}
613
614
615/**
616 * Injects an event (trap or external interrupt)
617 *
618 * @returns VBox status code.
619 * @param pVM The VM to operate on.
620 * @param pVCpu The VMCPU to operate on.
621 * @param pCtx CPU Context
622 * @param intInfo VMX interrupt info
623 * @param cbInstr Opcode length of faulting instruction
624 * @param errCode Error code (optional)
625 */
626static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
627{
628 int rc;
629 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
630
631#ifdef VBOX_WITH_STATISTICS
632 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
633#endif
634
635#ifdef VBOX_STRICT
636 if (iGate == 0xE)
637 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
638 else
639 if (iGate < 0x20)
640 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
641 else
642 {
643 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
644 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
645 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
646 }
647#endif
648
649#ifdef HWACCM_VMX_EMULATE_REALMODE
650 if (CPUMIsGuestInRealModeEx(pCtx))
651 {
652 RTGCPHYS GCPhysHandler;
653 uint16_t offset, ip;
654 RTSEL sel;
655
656 /* Injecting events doesn't work right with real mode emulation.
657 * (#GP if we try to inject external hardware interrupts)
658 * Inject the interrupt or trap directly instead.
659 *
660 * ASSUMES no access handlers for the bits we read or write below (should be safe).
661 */
662 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
663
664 /* Check if the interrupt handler is present. */
665 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
666 {
667 Log(("IDT cbIdt violation\n"));
668 if (iGate != X86_XCPT_DF)
669 {
670 RTGCUINTPTR intInfo;
671
672 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
673 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
674 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
675 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
676
677 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
678 }
679 Log(("Triple fault -> reset the VM!\n"));
680 return VINF_EM_RESET;
681 }
682 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
683 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
684 || iGate == 4)
685 {
686 ip = pCtx->ip + cbInstr;
687 }
688 else
689 ip = pCtx->ip;
690
691 /* Read the selector:offset pair of the interrupt handler. */
692 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
693 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
694 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
695
696 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
697
698 /* Construct the stack frame. */
699 /** @todo should check stack limit. */
700 pCtx->sp -= 2;
701 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
702 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
703 pCtx->sp -= 2;
704 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
705 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
706 pCtx->sp -= 2;
707 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
708 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
709
710 /* Update the CPU state for executing the handler. */
711 pCtx->rip = offset;
712 pCtx->cs = sel;
713 pCtx->csHid.u64Base = sel << 4;
714 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
715
716 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
717 return VINF_SUCCESS;
718 }
719#endif /* HWACCM_VMX_EMULATE_REALMODE */
720
721 /* Set event injection state. */
722 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
723
724 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
725 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
726
727 AssertRC(rc);
728 return rc;
729}
730
731
732/**
733 * Checks for pending guest interrupts and injects them
734 *
735 * @returns VBox status code.
736 * @param pVM The VM to operate on.
737 * @param pVCpu The VMCPU to operate on.
738 * @param pCtx CPU Context
739 */
740static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
741{
742 int rc;
743
744 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
745 if (pVCpu->hwaccm.s.Event.fPending)
746 {
747 Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
748 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
749 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
750 AssertRC(rc);
751
752 pVCpu->hwaccm.s.Event.fPending = false;
753 return VINF_SUCCESS;
754 }
755
756 if (pVM->hwaccm.s.fInjectNMI)
757 {
758 RTGCUINTPTR intInfo;
759
760 intInfo = X86_XCPT_NMI;
761 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
762 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
763
764 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
765 AssertRC(rc);
766
767 pVM->hwaccm.s.fInjectNMI = false;
768 return VINF_SUCCESS;
769 }
770
771 /* When external interrupts are pending, we should exit the VM when IF is set. */
772 if ( !TRPMHasTrap(pVCpu)
773 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
774 {
775 if (!(pCtx->eflags.u32 & X86_EFL_IF))
776 {
777 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
778 {
779 LogFlow(("Enable irq window exit!\n"));
780 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
781 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
782 AssertRC(rc);
783 }
784 /* else nothing to do but wait */
785 }
786 else
787 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
788 {
789 uint8_t u8Interrupt;
790
791 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
792 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
793 if (RT_SUCCESS(rc))
794 {
795 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
796 AssertRC(rc);
797 }
798 else
799 {
800 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
801 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
802 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
803 /* Just continue */
804 }
805 }
806 else
807 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
808 }
809
810#ifdef VBOX_STRICT
811 if (TRPMHasTrap(pVCpu))
812 {
813 uint8_t u8Vector;
814 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
815 AssertRC(rc);
816 }
817#endif
818
819 if ( (pCtx->eflags.u32 & X86_EFL_IF)
820 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
821 && TRPMHasTrap(pVCpu)
822 )
823 {
824 uint8_t u8Vector;
825 int rc;
826 TRPMEVENT enmType;
827 RTGCUINTPTR intInfo;
828 RTGCUINT errCode;
829
830 /* If a new event is pending, then dispatch it now. */
831 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
832 AssertRC(rc);
833 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
834 Assert(enmType != TRPM_SOFTWARE_INT);
835
836 /* Clear the pending trap. */
837 rc = TRPMResetTrap(pVCpu);
838 AssertRC(rc);
839
840 intInfo = u8Vector;
841 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
842
843 if (enmType == TRPM_TRAP)
844 {
845 switch (u8Vector) {
846 case 8:
847 case 10:
848 case 11:
849 case 12:
850 case 13:
851 case 14:
852 case 17:
853 /* Valid error codes. */
854 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
855 break;
856 default:
857 break;
858 }
859 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
860 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
861 else
862 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
863 }
864 else
865 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
866
867 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
868 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
869 AssertRC(rc);
870 } /* if (interrupts can be dispatched) */
871
872 return VINF_SUCCESS;
873}
874
875/**
876 * Save the host state
877 *
878 * @returns VBox status code.
879 * @param pVM The VM to operate on.
880 * @param pVCpu The VMCPU to operate on.
881 */
882VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
883{
884 int rc = VINF_SUCCESS;
885
886 /*
887 * Host CPU Context
888 */
889 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
890 {
891 RTIDTR idtr;
892 RTGDTR gdtr;
893 RTSEL SelTR;
894 PX86DESCHC pDesc;
895 uintptr_t trBase;
896 RTSEL cs;
897 RTSEL ss;
898 uint64_t cr3;
899
900 /* Control registers */
901 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
902#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
903 if (VMX_IS_64BIT_HOST_MODE())
904 {
905 cr3 = hwaccmR0Get64bitCR3();
906 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
907 }
908 else
909#endif
910 {
911 cr3 = ASMGetCR3();
912 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
913 }
914 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
915 AssertRC(rc);
916 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
917 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
918 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
919
920 /* Selector registers. */
921#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
922 if (VMX_IS_64BIT_HOST_MODE())
923 {
924 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
925 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
926 }
927 else
928 {
929 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
930 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
931 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
932 }
933#else
934 cs = ASMGetCS();
935 ss = ASMGetSS();
936#endif
937 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
938 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
939 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
940 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
941 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
942 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
943#if HC_ARCH_BITS == 32
944 if (!VMX_IS_64BIT_HOST_MODE())
945 {
946 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
947 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
948 }
949#endif
950 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
951 SelTR = ASMGetTR();
952 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
953 AssertRC(rc);
954 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
955 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
956 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
957 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
958 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
959 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
960 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
961
962 /* GDTR & IDTR */
963#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
964 if (VMX_IS_64BIT_HOST_MODE())
965 {
966 X86XDTR64 gdtr64, idtr64;
967 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
968 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
969 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
970 AssertRC(rc);
971 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
972 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
973 gdtr.cbGdt = gdtr64.cb;
974 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
975 }
976 else
977#endif
978 {
979 ASMGetGDTR(&gdtr);
980 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
981 ASMGetIDTR(&idtr);
982 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
983 AssertRC(rc);
984 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
985 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
986 }
987
988
989 /* Save the base address of the TR selector. */
990 if (SelTR > gdtr.cbGdt)
991 {
992 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
993 return VERR_VMX_INVALID_HOST_STATE;
994 }
995
996#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
997 if (VMX_IS_64BIT_HOST_MODE())
998 {
999 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
1000 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
1001 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
1002 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
1003 AssertRC(rc);
1004 }
1005 else
1006#endif
1007 {
1008 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
1009#if HC_ARCH_BITS == 64
1010 trBase = X86DESC64_BASE(*pDesc);
1011#else
1012 trBase = X86DESC_BASE(*pDesc);
1013#endif
1014 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
1015 AssertRC(rc);
1016 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
1017 }
1018
1019 /* FS and GS base. */
1020#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1021 if (VMX_IS_64BIT_HOST_MODE())
1022 {
1023 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
1024 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
1025 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
1026 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
1027 }
1028#endif
1029 AssertRC(rc);
1030
1031 /* Sysenter MSRs. */
1032 /** @todo expensive!! */
1033 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1034 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1035#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1036 if (VMX_IS_64BIT_HOST_MODE())
1037 {
1038 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1039 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1040 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1041 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1042 }
1043 else
1044 {
1045 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1046 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1047 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1048 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1049 }
1050#elif HC_ARCH_BITS == 32
1051 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1052 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1053 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1054 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1055#else
1056 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1057 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1058 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1059 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1060#endif
1061 AssertRC(rc);
1062
1063#if 0 /* @todo deal with 32/64 */
1064 /* Restore the host EFER - on CPUs that support it. */
1065 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1066 {
1067 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1068 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1069 AssertRC(rc);
1070 }
1071#endif
1072 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1073 }
1074 return rc;
1075}
1076
1077/**
1078 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1079 *
1080 * @param pVM The VM to operate on.
1081 * @param pVCpu The VMCPU to operate on.
1082 * @param pCtx Guest context
1083 */
1084static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1085{
1086 if (CPUMIsGuestInPAEModeEx(pCtx))
1087 {
1088 X86PDPE Pdpe;
1089
1090 for (unsigned i=0;i<4;i++)
1091 {
1092 Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1093 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1094 AssertRC(rc);
1095 }
1096 }
1097}
1098
1099/**
1100 * Update the exception bitmap according to the current CPU state
1101 *
1102 * @param pVM The VM to operate on.
1103 * @param pVCpu The VMCPU to operate on.
1104 * @param pCtx Guest context
1105 */
1106static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1107{
1108 uint32_t u32TrapMask;
1109 Assert(pCtx);
1110
1111 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1112#ifndef DEBUG
1113 if (pVM->hwaccm.s.fNestedPaging)
1114 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1115#endif
1116
1117 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1118 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1119 && !(pCtx->cr0 & X86_CR0_NE)
1120 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1121 {
1122 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1123 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1124 }
1125
1126#ifdef DEBUG /* till after branching, enable it by default then. */
1127 /* Intercept X86_XCPT_DB if stepping is enabled */
1128 if (DBGFIsStepping(pVCpu))
1129 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1130 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1131 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1132#endif
1133
1134#ifdef VBOX_STRICT
1135 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1136#endif
1137
1138# ifdef HWACCM_VMX_EMULATE_REALMODE
1139 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1140 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1141 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1142# endif /* HWACCM_VMX_EMULATE_REALMODE */
1143
1144 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1145 AssertRC(rc);
1146}
1147
1148/**
1149 * Loads the guest state
1150 *
1151 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1152 *
1153 * @returns VBox status code.
1154 * @param pVM The VM to operate on.
1155 * @param pVCpu The VMCPU to operate on.
1156 * @param pCtx Guest context
1157 */
1158VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1159{
1160 int rc = VINF_SUCCESS;
1161 RTGCUINTPTR val;
1162 X86EFLAGS eflags;
1163
1164 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1165 * Set required bits to one and zero according to the MSR capabilities.
1166 */
1167 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1168 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1169 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1170#if 0 /* @todo deal with 32/64 */
1171 /* Required for the EFER write below, not supported on all CPUs. */
1172 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1173#endif
1174 /* 64 bits guest mode? */
1175 if (CPUMIsGuestInLongModeEx(pCtx))
1176 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1177 /* else Must be zero when AMD64 is not available. */
1178
1179 /* Mask away the bits that the CPU doesn't support */
1180 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1181 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1182 AssertRC(rc);
1183
1184 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1185 * Set required bits to one and zero according to the MSR capabilities.
1186 */
1187 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1188
1189 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1190#if 0 /* @todo deal with 32/64 */
1191 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1192#else
1193 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1194#endif
1195
1196#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1197 if (VMX_IS_64BIT_HOST_MODE())
1198 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1199 /* else: Must be zero when AMD64 is not available. */
1200#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1201 if (CPUMIsGuestInLongModeEx(pCtx))
1202 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1203 else
1204 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1205#endif
1206 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1207 /* Don't acknowledge external interrupts on VM-exit. */
1208 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1209 AssertRC(rc);
1210
1211 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1212 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1213 {
1214#ifdef HWACCM_VMX_EMULATE_REALMODE
1215 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1216 {
1217 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1218 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1219 {
1220 /* Correct weird requirements for switching to protected mode. */
1221 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1222 && enmGuestMode >= PGMMODE_PROTECTED)
1223 {
1224 /* Flush the recompiler code cache as it's not unlikely
1225 * the guest will rewrite code it will later execute in real
1226 * mode (OpenBSD 4.0 is one such example)
1227 */
1228 REMFlushTBs(pVM);
1229
1230 /* DPL of all hidden selector registers must match the current CPL (0). */
1231 pCtx->csHid.Attr.n.u2Dpl = 0;
1232 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1233
1234 pCtx->dsHid.Attr.n.u2Dpl = 0;
1235 pCtx->esHid.Attr.n.u2Dpl = 0;
1236 pCtx->fsHid.Attr.n.u2Dpl = 0;
1237 pCtx->gsHid.Attr.n.u2Dpl = 0;
1238 pCtx->ssHid.Attr.n.u2Dpl = 0;
1239
1240 /* The limit must correspond to the granularity bit. */
1241 if (!pCtx->csHid.Attr.n.u1Granularity)
1242 pCtx->csHid.u32Limit &= 0xffff;
1243 if (!pCtx->dsHid.Attr.n.u1Granularity)
1244 pCtx->dsHid.u32Limit &= 0xffff;
1245 if (!pCtx->esHid.Attr.n.u1Granularity)
1246 pCtx->esHid.u32Limit &= 0xffff;
1247 if (!pCtx->fsHid.Attr.n.u1Granularity)
1248 pCtx->fsHid.u32Limit &= 0xffff;
1249 if (!pCtx->gsHid.Attr.n.u1Granularity)
1250 pCtx->gsHid.u32Limit &= 0xffff;
1251 if (!pCtx->ssHid.Attr.n.u1Granularity)
1252 pCtx->ssHid.u32Limit &= 0xffff;
1253 }
1254 else
1255 /* Switching from protected mode to real mode. */
1256 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1257 && enmGuestMode == PGMMODE_REAL)
1258 {
1259 /* The limit must also be set to 0xffff. */
1260 pCtx->csHid.u32Limit = 0xffff;
1261 pCtx->dsHid.u32Limit = 0xffff;
1262 pCtx->esHid.u32Limit = 0xffff;
1263 pCtx->fsHid.u32Limit = 0xffff;
1264 pCtx->gsHid.u32Limit = 0xffff;
1265 pCtx->ssHid.u32Limit = 0xffff;
1266
1267 Assert(pCtx->csHid.u64Base <= 0xfffff);
1268 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1269 Assert(pCtx->esHid.u64Base <= 0xfffff);
1270 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1271 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1272 }
1273 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1274 }
1275 else
1276 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1277 if ( CPUMIsGuestInRealModeEx(pCtx)
1278 && pCtx->csHid.u64Base == 0xffff0000)
1279 {
1280 pCtx->csHid.u64Base = 0xf0000;
1281 pCtx->cs = 0xf000;
1282 }
1283 }
1284#endif /* HWACCM_VMX_EMULATE_REALMODE */
1285
1286 VMX_WRITE_SELREG(ES, es);
1287 AssertRC(rc);
1288
1289 VMX_WRITE_SELREG(CS, cs);
1290 AssertRC(rc);
1291
1292 VMX_WRITE_SELREG(SS, ss);
1293 AssertRC(rc);
1294
1295 VMX_WRITE_SELREG(DS, ds);
1296 AssertRC(rc);
1297
1298 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1299 VMX_WRITE_SELREG(FS, fs);
1300 AssertRC(rc);
1301
1302 VMX_WRITE_SELREG(GS, gs);
1303 AssertRC(rc);
1304 }
1305
1306 /* Guest CPU context: LDTR. */
1307 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1308 {
1309 if (pCtx->ldtr == 0)
1310 {
1311 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1312 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1313 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1314 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1315 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1316 }
1317 else
1318 {
1319 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1320 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1321 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1322 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1323 }
1324 AssertRC(rc);
1325 }
1326 /* Guest CPU context: TR. */
1327 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1328 {
1329#ifdef HWACCM_VMX_EMULATE_REALMODE
1330 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1331 if (CPUMIsGuestInRealModeEx(pCtx))
1332 {
1333 RTGCPHYS GCPhys;
1334
1335 /* We convert it here every time as pci regions could be reconfigured. */
1336 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1337 AssertRC(rc);
1338
1339 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1340 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1341 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1342
1343 X86DESCATTR attr;
1344
1345 attr.u = 0;
1346 attr.n.u1Present = 1;
1347 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1348 val = attr.u;
1349 }
1350 else
1351#endif /* HWACCM_VMX_EMULATE_REALMODE */
1352 {
1353 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1354 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1355 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1356
1357 val = pCtx->trHid.Attr.u;
1358
1359 /* The TSS selector must be busy. */
1360 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1361 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1362 else
1363 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1364 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1365
1366 }
1367 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1368 AssertRC(rc);
1369 }
1370 /* Guest CPU context: GDTR. */
1371 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1372 {
1373 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1374 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1375 AssertRC(rc);
1376 }
1377 /* Guest CPU context: IDTR. */
1378 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1379 {
1380 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1381 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1382 AssertRC(rc);
1383 }
1384
1385 /*
1386 * Sysenter MSRs (unconditional)
1387 */
1388 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1389 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1390 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1391 AssertRC(rc);
1392
1393 /* Control registers */
1394 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1395 {
1396 val = pCtx->cr0;
1397 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1398 Log2(("Guest CR0-shadow %08x\n", val));
1399 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1400 {
1401 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1402 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1403 }
1404 else
1405 {
1406 /** @todo check if we support the old style mess correctly. */
1407 if (!(val & X86_CR0_NE))
1408 Log(("Forcing X86_CR0_NE!!!\n"));
1409
1410 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1411 }
1412 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1413 val |= X86_CR0_PE | X86_CR0_PG;
1414 if (pVM->hwaccm.s.fNestedPaging)
1415 {
1416 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1417 {
1418 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1419 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1420 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1421 }
1422 else
1423 {
1424 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1425 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1426 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1427 }
1428 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1429 AssertRC(rc);
1430 }
1431 else
1432 {
1433 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1434 val |= X86_CR0_WP;
1435 }
1436
1437 /* Always enable caching. */
1438 val &= ~(X86_CR0_CD|X86_CR0_NW);
1439
1440 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1441 Log2(("Guest CR0 %08x\n", val));
1442 /* CR0 flags owned by the host; if the guests attempts to change them, then
1443 * the VM will exit.
1444 */
1445 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1446 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1447 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1448 | X86_CR0_TS
1449 | X86_CR0_ET /* Bit not restored during VM-exit! */
1450 | X86_CR0_CD /* Bit not restored during VM-exit! */
1451 | X86_CR0_NW /* Bit not restored during VM-exit! */
1452 | X86_CR0_NE
1453 | X86_CR0_MP;
1454 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1455
1456 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1457 Log2(("Guest CR0-mask %08x\n", val));
1458 AssertRC(rc);
1459 }
1460 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1461 {
1462 /* CR4 */
1463 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1464 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1465 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1466 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1467
1468 if (!pVM->hwaccm.s.fNestedPaging)
1469 {
1470 switch(pVCpu->hwaccm.s.enmShadowMode)
1471 {
1472 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1473 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1474 case PGMMODE_32_BIT: /* 32-bit paging. */
1475 val &= ~X86_CR4_PAE;
1476 break;
1477
1478 case PGMMODE_PAE: /* PAE paging. */
1479 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1480 /** @todo use normal 32 bits paging */
1481 val |= X86_CR4_PAE;
1482 break;
1483
1484 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1485 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1486#ifdef VBOX_ENABLE_64_BITS_GUESTS
1487 break;
1488#else
1489 AssertFailed();
1490 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1491#endif
1492 default: /* shut up gcc */
1493 AssertFailed();
1494 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1495 }
1496 }
1497 else
1498 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1499 {
1500 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1501 val |= X86_CR4_PSE;
1502 /* Our identity mapping is a 32 bits page directory. */
1503 val &= ~X86_CR4_PAE;
1504 }
1505
1506 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1507 Log2(("Guest CR4 %08x\n", val));
1508 /* CR4 flags owned by the host; if the guests attempts to change them, then
1509 * the VM will exit.
1510 */
1511 val = 0
1512 | X86_CR4_PAE
1513 | X86_CR4_PGE
1514 | X86_CR4_PSE
1515 | X86_CR4_VMXE;
1516 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1517
1518 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1519 Log2(("Guest CR4-mask %08x\n", val));
1520 AssertRC(rc);
1521 }
1522
1523 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1524 {
1525 if (pVM->hwaccm.s.fNestedPaging)
1526 {
1527 Assert(PGMGetHyperCR3(pVCpu));
1528 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1529
1530 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1531 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1532 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1533 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1534
1535 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1536 AssertRC(rc);
1537
1538 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1539 {
1540 RTGCPHYS GCPhys;
1541
1542 /* We convert it here every time as pci regions could be reconfigured. */
1543 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1544 AssertRC(rc);
1545
1546 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1547 * take care of the translation to host physical addresses.
1548 */
1549 val = GCPhys;
1550 }
1551 else
1552 {
1553 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1554 val = pCtx->cr3;
1555 /* Prefetch the four PDPT entries in PAE mode. */
1556 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1557 }
1558 }
1559 else
1560 {
1561 val = PGMGetHyperCR3(pVCpu);
1562 Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1563 }
1564
1565 /* Save our shadow CR3 register. */
1566 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1567 AssertRC(rc);
1568 }
1569
1570 /* Debug registers. */
1571 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1572 {
1573 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1574 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1575
1576 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1577 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1578 pCtx->dr[7] |= 0x400; /* must be one */
1579
1580 /* Resync DR7 */
1581 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1582 AssertRC(rc);
1583
1584 /* Sync the debug state now if any breakpoint is armed. */
1585 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1586 && !CPUMIsGuestDebugStateActive(pVCpu)
1587 && !DBGFIsStepping(pVCpu))
1588 {
1589 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1590
1591 /* Disable drx move intercepts. */
1592 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1593 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1594 AssertRC(rc);
1595
1596 /* Save the host and load the guest debug state. */
1597 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1598 AssertRC(rc);
1599 }
1600
1601 /* IA32_DEBUGCTL MSR. */
1602 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1603 AssertRC(rc);
1604
1605 /** @todo do we really ever need this? */
1606 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1607 AssertRC(rc);
1608 }
1609
1610 /* EIP, ESP and EFLAGS */
1611 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1612 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1613 AssertRC(rc);
1614
1615 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1616 eflags = pCtx->eflags;
1617 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1618 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1619
1620#ifdef HWACCM_VMX_EMULATE_REALMODE
1621 /* Real mode emulation using v86 mode. */
1622 if (CPUMIsGuestInRealModeEx(pCtx))
1623 {
1624 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1625
1626 eflags.Bits.u1VM = 1;
1627 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1628 }
1629#endif /* HWACCM_VMX_EMULATE_REALMODE */
1630 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1631 AssertRC(rc);
1632
1633 /* TSC offset. */
1634 uint64_t u64TSCOffset;
1635
1636 if (TMCpuTickCanUseRealTSC(pVCpu, &u64TSCOffset))
1637 {
1638 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1639 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1640 AssertRC(rc);
1641
1642 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1643 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1644 AssertRC(rc);
1645 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1646 }
1647 else
1648 {
1649 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1650 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1651 AssertRC(rc);
1652 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1653 }
1654
1655 /* 64 bits guest mode? */
1656 if (CPUMIsGuestInLongModeEx(pCtx))
1657 {
1658#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1659 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1660#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1661 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1662#else
1663# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1664 if (!pVM->hwaccm.s.fAllow64BitGuests)
1665 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1666# endif
1667 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1668#endif
1669 /* Unconditionally update these as wrmsr might have changed them. */
1670 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1671 AssertRC(rc);
1672 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1673 AssertRC(rc);
1674 }
1675 else
1676 {
1677 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1678 }
1679
1680#if 0 /* @todo deal with 32/64 */
1681 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1682 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1683 {
1684 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1685 AssertRC(rc);
1686 }
1687#endif
1688
1689 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1690
1691 /* Done. */
1692 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1693
1694 return rc;
1695}
1696
1697/**
1698 * Syncs back the guest state
1699 *
1700 * @returns VBox status code.
1701 * @param pVM The VM to operate on.
1702 * @param pVCpu The VMCPU to operate on.
1703 * @param pCtx Guest context
1704 */
1705DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1706{
1707 RTGCUINTREG val, valShadow;
1708 RTGCUINTPTR uInterruptState;
1709 int rc;
1710
1711 /* Let's first sync back eip, esp, and eflags. */
1712 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1713 AssertRC(rc);
1714 pCtx->rip = val;
1715 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1716 AssertRC(rc);
1717 pCtx->rsp = val;
1718 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1719 AssertRC(rc);
1720 pCtx->eflags.u32 = val;
1721
1722 /* Take care of instruction fusing (sti, mov ss) */
1723 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1724 uInterruptState = val;
1725 if (uInterruptState != 0)
1726 {
1727 Assert(uInterruptState <= 2); /* only sti & mov ss */
1728 Log(("uInterruptState %x eip=%RGv\n", (uint32_t)uInterruptState, pCtx->rip));
1729 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1730 }
1731 else
1732 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1733
1734 /* Control registers. */
1735 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1736 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1737 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1738 CPUMSetGuestCR0(pVCpu, val);
1739
1740 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1741 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1742 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1743 CPUMSetGuestCR4(pVCpu, val);
1744
1745 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1746 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1747 if ( pVM->hwaccm.s.fNestedPaging
1748 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1749 {
1750 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1751
1752 /* Can be updated behind our back in the nested paging case. */
1753 CPUMSetGuestCR2(pVCpu, pCache->cr2);
1754
1755 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1756
1757 if (val != pCtx->cr3)
1758 {
1759 CPUMSetGuestCR3(pVCpu, val);
1760 PGMUpdateCR3(pVCpu, val);
1761 }
1762 /* Prefetch the four PDPT entries in PAE mode. */
1763 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1764 }
1765
1766 /* Sync back DR7 here. */
1767 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1768 pCtx->dr[7] = val;
1769
1770 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1771 VMX_READ_SELREG(ES, es);
1772 VMX_READ_SELREG(SS, ss);
1773 VMX_READ_SELREG(CS, cs);
1774 VMX_READ_SELREG(DS, ds);
1775 VMX_READ_SELREG(FS, fs);
1776 VMX_READ_SELREG(GS, gs);
1777
1778 /*
1779 * System MSRs
1780 */
1781 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1782 pCtx->SysEnter.cs = val;
1783 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1784 pCtx->SysEnter.eip = val;
1785 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1786 pCtx->SysEnter.esp = val;
1787
1788 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1789 VMX_READ_SELREG(LDTR, ldtr);
1790
1791 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1792 pCtx->gdtr.cbGdt = val;
1793 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1794 pCtx->gdtr.pGdt = val;
1795
1796 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1797 pCtx->idtr.cbIdt = val;
1798 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1799 pCtx->idtr.pIdt = val;
1800
1801#ifdef HWACCM_VMX_EMULATE_REALMODE
1802 /* Real mode emulation using v86 mode. */
1803 if (CPUMIsGuestInRealModeEx(pCtx))
1804 {
1805 /* Hide our emulation flags */
1806 pCtx->eflags.Bits.u1VM = 0;
1807
1808 /* Restore original IOPL setting as we always use 0. */
1809 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1810
1811 /* Force a TR resync every time in case we switch modes. */
1812 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1813 }
1814 else
1815#endif /* HWACCM_VMX_EMULATE_REALMODE */
1816 {
1817 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1818 VMX_READ_SELREG(TR, tr);
1819 }
1820 return VINF_SUCCESS;
1821}
1822
1823/**
1824 * Dummy placeholder
1825 *
1826 * @param pVM The VM to operate on.
1827 * @param pVCpu The VMCPU to operate on.
1828 */
1829static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1830{
1831 NOREF(pVM);
1832 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1833 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1834 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1835 return;
1836}
1837
1838/**
1839 * Setup the tagged TLB for EPT
1840 *
1841 * @returns VBox status code.
1842 * @param pVM The VM to operate on.
1843 * @param pVCpu The VMCPU to operate on.
1844 */
1845static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1846{
1847 PHWACCM_CPUINFO pCpu;
1848
1849 Assert(pVM->hwaccm.s.fNestedPaging);
1850 Assert(!pVM->hwaccm.s.vmx.fVPID);
1851
1852 /* Deal with tagged TLBs if VPID or EPT is supported. */
1853 pCpu = HWACCMR0GetCurrentCpu();
1854 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1855 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1856 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1857 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1858 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1859 {
1860 /* Force a TLB flush on VM entry. */
1861 pVCpu->hwaccm.s.fForceTLBFlush = true;
1862 }
1863 else
1864 Assert(!pCpu->fFlushTLB);
1865
1866 /* Check for tlb shootdown flushes. */
1867 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1868 pVCpu->hwaccm.s.fForceTLBFlush = true;
1869
1870 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1871 pCpu->fFlushTLB = false;
1872
1873 if (pVCpu->hwaccm.s.fForceTLBFlush)
1874 {
1875 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1876 }
1877 else
1878 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1879 {
1880 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1881 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1882
1883 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1884 {
1885 /* aTlbShootdownPages contains physical addresses in this case. */
1886 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1887 }
1888 }
1889 pVCpu->hwaccm.s.TlbShootdown.cPages= 0;
1890 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1891
1892#ifdef VBOX_WITH_STATISTICS
1893 if (pVCpu->hwaccm.s.fForceTLBFlush)
1894 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1895 else
1896 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1897#endif
1898}
1899
1900#ifdef HWACCM_VTX_WITH_VPID
1901/**
1902 * Setup the tagged TLB for VPID
1903 *
1904 * @returns VBox status code.
1905 * @param pVM The VM to operate on.
1906 * @param pVCpu The VMCPU to operate on.
1907 */
1908static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1909{
1910 PHWACCM_CPUINFO pCpu;
1911
1912 Assert(pVM->hwaccm.s.vmx.fVPID);
1913 Assert(!pVM->hwaccm.s.fNestedPaging);
1914
1915 /* Deal with tagged TLBs if VPID or EPT is supported. */
1916 pCpu = HWACCMR0GetCurrentCpu();
1917 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1918 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1919 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1920 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1921 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1922 {
1923 /* Force a TLB flush on VM entry. */
1924 pVCpu->hwaccm.s.fForceTLBFlush = true;
1925 }
1926 else
1927 Assert(!pCpu->fFlushTLB);
1928
1929 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1930
1931 /* Check for tlb shootdown flushes. */
1932 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1933 pVCpu->hwaccm.s.fForceTLBFlush = true;
1934
1935 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1936 if (pVCpu->hwaccm.s.fForceTLBFlush)
1937 {
1938 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1939 || pCpu->fFlushTLB)
1940 {
1941 pCpu->fFlushTLB = false;
1942 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1943 pCpu->cTLBFlushes++;
1944 }
1945 else
1946 {
1947 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1948 pVCpu->hwaccm.s.fForceTLBFlush = false;
1949 }
1950
1951 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1952 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1953 }
1954 else
1955 {
1956 Assert(!pCpu->fFlushTLB);
1957 Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
1958
1959 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1960 {
1961 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1962 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1963 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1964 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1965 }
1966 }
1967 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1968 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1969
1970 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1971 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1972 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1973
1974 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1975 AssertRC(rc);
1976
1977 if (pVCpu->hwaccm.s.fForceTLBFlush)
1978 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1979
1980#ifdef VBOX_WITH_STATISTICS
1981 if (pVCpu->hwaccm.s.fForceTLBFlush)
1982 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1983 else
1984 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1985#endif
1986}
1987#endif /* HWACCM_VTX_WITH_VPID */
1988
1989/**
1990 * Runs guest code in a VT-x VM.
1991 *
1992 * @returns VBox status code.
1993 * @param pVM The VM to operate on.
1994 * @param pVCpu The VMCPU to operate on.
1995 * @param pCtx Guest context
1996 */
1997VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1998{
1999 int rc = VINF_SUCCESS;
2000 RTGCUINTREG val;
2001 RTGCUINTREG exitReason = VMX_EXIT_INVALID;
2002 RTGCUINTREG instrError, cbInstr;
2003 RTGCUINTPTR exitQualification = 0;
2004 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
2005 RTGCUINTPTR errCode, instrInfo;
2006 bool fSetupTPRCaching = false;
2007 uint8_t u8LastTPR = 0;
2008 PHWACCM_CPUINFO pCpu = 0;
2009 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
2010 unsigned cResume = 0;
2011#ifdef VBOX_STRICT
2012 RTCPUID idCpuCheck;
2013#endif
2014#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2015 uint64_t u64LastTime = RTTimeMilliTS();
2016#endif
2017#ifdef VBOX_WITH_STATISTICS
2018 bool fStatEntryStarted = true;
2019 bool fStatExit2Started = false;
2020#endif
2021
2022 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
2023
2024 /* Check if we need to use TPR shadowing. */
2025 if ( CPUMIsGuestInLongModeEx(pCtx)
2026 || ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2027 && pVM->hwaccm.s.fHasIoApic)
2028 )
2029 {
2030 fSetupTPRCaching = true;
2031 }
2032
2033 Log2(("\nE"));
2034
2035 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
2036
2037#ifdef VBOX_STRICT
2038 {
2039 RTCCUINTREG val;
2040
2041 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
2042 AssertRC(rc);
2043 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
2044
2045 /* allowed zero */
2046 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
2047 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
2048
2049 /* allowed one */
2050 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
2051 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
2052
2053 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
2054 AssertRC(rc);
2055 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
2056
2057 /* Must be set according to the MSR, but can be cleared in case of EPT. */
2058 if (pVM->hwaccm.s.fNestedPaging)
2059 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
2060 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2061 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2062
2063 /* allowed zero */
2064 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2065 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2066
2067 /* allowed one */
2068 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2069 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2070
2071 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2072 AssertRC(rc);
2073 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2074
2075 /* allowed zero */
2076 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2077 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2078
2079 /* allowed one */
2080 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2081 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2082
2083 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2084 AssertRC(rc);
2085 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2086
2087 /* allowed zero */
2088 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2089 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2090
2091 /* allowed one */
2092 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2093 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2094 }
2095#endif
2096
2097#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2098 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2099#endif
2100
2101 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2102 */
2103ResumeExecution:
2104 STAM_STATS({
2105 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2106 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2107 });
2108 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2109 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2110 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2111 Assert(!HWACCMR0SuspendPending());
2112
2113 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2114 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
2115 {
2116 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2117 rc = VINF_EM_RAW_INTERRUPT;
2118 goto end;
2119 }
2120
2121 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2122 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2123 {
2124 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2125 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2126 {
2127 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2128 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2129 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2130 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2131 */
2132 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2133 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2134 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2135 AssertRC(rc);
2136 }
2137 }
2138 else
2139 {
2140 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2141 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2142 AssertRC(rc);
2143 }
2144
2145#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2146 if (RT_UNLIKELY(cResume & 0xf) == 0)
2147 {
2148 uint64_t u64CurTime = RTTimeMilliTS();
2149
2150 if (RT_UNLIKELY(u64CurTime > u64LastTime))
2151 {
2152 u64LastTime = u64CurTime;
2153 TMTimerPollVoid(pVM, pVCpu);
2154 }
2155 }
2156#endif
2157
2158 /* Check for pending actions that force us to go back to ring 3. */
2159#ifdef DEBUG
2160 /* Intercept X86_XCPT_DB if stepping is enabled */
2161 if (!DBGFIsStepping(pVCpu))
2162#endif
2163 {
2164 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2165 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2166 {
2167 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2168 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2169 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2170 goto end;
2171 }
2172 }
2173
2174 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2175 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2176 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2177 {
2178 rc = VINF_EM_PENDING_REQUEST;
2179 goto end;
2180 }
2181
2182#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2183 /*
2184 * Exit to ring-3 preemption/work is pending.
2185 *
2186 * Interrupts are disabled before the call to make sure we don't miss any interrupt
2187 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
2188 * further down, but VMXR0CheckPendingInterrupt makes that impossible.)
2189 *
2190 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
2191 * shootdowns rely on this.
2192 */
2193 uOldEFlags = ASMIntDisableFlags();
2194 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2195 {
2196 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
2197 rc = VINF_EM_RAW_INTERRUPT;
2198 goto end;
2199 }
2200 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2201#endif
2202
2203 /* When external interrupts are pending, we should exit the VM when IF is set. */
2204 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2205 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2206 if (RT_FAILURE(rc))
2207 goto end;
2208
2209 /** @todo check timers?? */
2210
2211 /* TPR caching using CR8 is only available in 64 bits mode */
2212 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2213 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2214 /**
2215 * @todo query and update the TPR only when it could have been changed (mmio access & wrmsr (x2apic))
2216 */
2217 if (fSetupTPRCaching)
2218 {
2219 /* TPR caching in CR8 */
2220 bool fPending;
2221
2222 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
2223 AssertRC(rc);
2224 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2225 pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8LastTPR;
2226
2227 /* Two options here:
2228 * - external interrupt pending, but masked by the TPR value.
2229 * -> a CR8 update that lower the current TPR value should cause an exit
2230 * - no pending interrupts
2231 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2232 */
2233 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
2234 AssertRC(rc);
2235 }
2236
2237#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2238 if ( pVM->hwaccm.s.fNestedPaging
2239# ifdef HWACCM_VTX_WITH_VPID
2240 || pVM->hwaccm.s.vmx.fVPID
2241# endif /* HWACCM_VTX_WITH_VPID */
2242 )
2243 {
2244 pCpu = HWACCMR0GetCurrentCpu();
2245 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2246 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2247 {
2248 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2249 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2250 else
2251 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2252 }
2253 if (pCpu->fFlushTLB)
2254 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2255 else
2256 if (pVCpu->hwaccm.s.fForceTLBFlush)
2257 LogFlow(("Manual TLB flush\n"));
2258 }
2259#endif
2260#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2261 PGMDynMapFlushAutoSet(pVCpu);
2262#endif
2263
2264 /*
2265 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2266 * (until the actual world switch)
2267 */
2268#ifdef VBOX_STRICT
2269 idCpuCheck = RTMpCpuId();
2270#endif
2271#ifdef LOG_ENABLED
2272 VMMR0LogFlushDisable(pVCpu);
2273#endif
2274 /* Save the host state first. */
2275 rc = VMXR0SaveHostState(pVM, pVCpu);
2276 if (rc != VINF_SUCCESS)
2277 goto end;
2278 /* Load the guest state */
2279 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2280 if (rc != VINF_SUCCESS)
2281 goto end;
2282
2283#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2284 /* Disable interrupts to make sure a poke will interrupt execution.
2285 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
2286 */
2287 uOldEFlags = ASMIntDisableFlags();
2288 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2289#endif
2290
2291 /* Deal with tagged TLB setup and invalidation. */
2292 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2293
2294 /* Non-register state Guest Context */
2295 /** @todo change me according to cpu state */
2296 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2297 AssertRC(rc);
2298
2299 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2300
2301 /* Manual save and restore:
2302 * - General purpose registers except RIP, RSP
2303 *
2304 * Trashed:
2305 * - CR2 (we don't care)
2306 * - LDTR (reset to 0)
2307 * - DRx (presumably not changed at all)
2308 * - DR7 (reset to 0x400)
2309 * - EFLAGS (reset to RT_BIT(1); not relevant)
2310 *
2311 */
2312
2313
2314 /* All done! Let's start VM execution. */
2315 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2316 Assert(idCpuCheck == RTMpCpuId());
2317
2318#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2319 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2320 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2321#endif
2322
2323 TMNotifyStartOfExecution(pVCpu);
2324 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2325 TMNotifyEndOfExecution(pVCpu);
2326 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2327 Assert(!(ASMGetFlags() & X86_EFL_IF));
2328 ASMSetFlags(uOldEFlags);
2329#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2330 uOldEFlags = ~(RTCCUINTREG)0;
2331#endif
2332
2333 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2334
2335 /* In case we execute a goto ResumeExecution later on. */
2336 pVCpu->hwaccm.s.fResumeVM = true;
2337 pVCpu->hwaccm.s.fForceTLBFlush = false;
2338
2339 /*
2340 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2341 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2342 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2343 */
2344 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2345 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2346
2347 if (rc != VINF_SUCCESS)
2348 {
2349 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2350 goto end;
2351 }
2352
2353 /* Success. Query the guest state and figure out what has happened. */
2354
2355 /* Investigate why there was a VM-exit. */
2356 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2357 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2358
2359 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2360 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2361 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2362 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2363 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2364 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2365 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2366 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2367 AssertRC(rc);
2368
2369 /* Sync back the guest state */
2370 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2371 AssertRC(rc);
2372
2373 /* Note! NOW IT'S SAFE FOR LOGGING! */
2374#ifdef LOG_ENABLED
2375 VMMR0LogFlushEnable(pVCpu);
2376#endif
2377 Log2(("Raw exit reason %08x\n", exitReason));
2378
2379 /* Check if an injected event was interrupted prematurely. */
2380 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2381 AssertRC(rc);
2382 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2383 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2384 /* Ignore 'int xx' as they'll be restarted anyway. */
2385 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2386 /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
2387 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2388 {
2389 Assert(!pVCpu->hwaccm.s.Event.fPending);
2390 pVCpu->hwaccm.s.Event.fPending = true;
2391 /* Error code present? */
2392 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2393 {
2394 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2395 AssertRC(rc);
2396 pVCpu->hwaccm.s.Event.errCode = val;
2397 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2398 }
2399 else
2400 {
2401 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2402 pVCpu->hwaccm.s.Event.errCode = 0;
2403 }
2404 }
2405#ifdef VBOX_STRICT
2406 else
2407 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2408 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2409 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2410 {
2411 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2412 }
2413
2414 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2415 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2416#endif
2417
2418 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2419 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2420 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2421 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2422 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2423
2424 /* Sync back the TPR if it was changed. */
2425 if ( fSetupTPRCaching
2426 && u8LastTPR != pVCpu->hwaccm.s.vmx.pVAPIC[0x80])
2427 {
2428 rc = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);
2429 AssertRC(rc);
2430 }
2431
2432 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2433 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2434
2435 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2436 switch (exitReason)
2437 {
2438 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2439 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2440 {
2441 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2442
2443 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2444 {
2445 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2446 /* External interrupt; leave to allow it to be dispatched again. */
2447 rc = VINF_EM_RAW_INTERRUPT;
2448 break;
2449 }
2450 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2451 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2452 {
2453 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2454 /* External interrupt; leave to allow it to be dispatched again. */
2455 rc = VINF_EM_RAW_INTERRUPT;
2456 break;
2457
2458 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2459 AssertFailed(); /* can't come here; fails the first check. */
2460 break;
2461
2462 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2463 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2464 Assert(vector == 1 || vector == 3 || vector == 4);
2465 /* no break */
2466 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2467 Log2(("Hardware/software interrupt %d\n", vector));
2468 switch (vector)
2469 {
2470 case X86_XCPT_NM:
2471 {
2472 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2473
2474 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2475 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2476 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2477 if (rc == VINF_SUCCESS)
2478 {
2479 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2480
2481 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2482
2483 /* Continue execution. */
2484 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2485
2486 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2487 goto ResumeExecution;
2488 }
2489
2490 Log(("Forward #NM fault to the guest\n"));
2491 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2492 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2493 AssertRC(rc);
2494 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2495 goto ResumeExecution;
2496 }
2497
2498 case X86_XCPT_PF: /* Page fault */
2499 {
2500#ifdef DEBUG
2501 if (pVM->hwaccm.s.fNestedPaging)
2502 { /* A genuine pagefault.
2503 * Forward the trap to the guest by injecting the exception and resuming execution.
2504 */
2505 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2506
2507 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2508
2509 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2510
2511 /* Now we must update CR2. */
2512 pCtx->cr2 = exitQualification;
2513 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2514 AssertRC(rc);
2515
2516 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2517 goto ResumeExecution;
2518 }
2519#endif
2520 Assert(!pVM->hwaccm.s.fNestedPaging);
2521
2522 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2523 /* Exit qualification contains the linear address of the page fault. */
2524 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2525 TRPMSetErrorCode(pVCpu, errCode);
2526 TRPMSetFaultAddress(pVCpu, exitQualification);
2527
2528 /* Shortcut for APIC TPR reads and writes. */
2529 if ( (exitQualification & 0xfff) == 0x080
2530 && !(errCode & X86_TRAP_PF_P) /* not present */
2531 && fSetupTPRCaching
2532 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
2533 {
2534 RTGCPHYS GCPhysApicBase, GCPhys;
2535 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
2536 GCPhysApicBase &= PAGE_BASE_GC_MASK;
2537
2538 rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
2539 if ( rc == VINF_SUCCESS
2540 && GCPhys == GCPhysApicBase)
2541 {
2542 Log(("Enable VT-x virtual APIC access filtering\n"));
2543 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
2544 AssertRC(rc);
2545 }
2546 }
2547
2548 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2549 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2550 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2551 if (rc == VINF_SUCCESS)
2552 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2553 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2554 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2555
2556 TRPMResetTrap(pVCpu);
2557
2558 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2559 goto ResumeExecution;
2560 }
2561 else
2562 if (rc == VINF_EM_RAW_GUEST_TRAP)
2563 { /* A genuine pagefault.
2564 * Forward the trap to the guest by injecting the exception and resuming execution.
2565 */
2566 Log2(("Forward page fault to the guest\n"));
2567
2568 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2569 /* The error code might have been changed. */
2570 errCode = TRPMGetErrorCode(pVCpu);
2571
2572 TRPMResetTrap(pVCpu);
2573
2574 /* Now we must update CR2. */
2575 pCtx->cr2 = exitQualification;
2576 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2577 AssertRC(rc);
2578
2579 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2580 goto ResumeExecution;
2581 }
2582#ifdef VBOX_STRICT
2583 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2584 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2585#endif
2586 /* Need to go back to the recompiler to emulate the instruction. */
2587 TRPMResetTrap(pVCpu);
2588 break;
2589 }
2590
2591 case X86_XCPT_MF: /* Floating point exception. */
2592 {
2593 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2594 if (!(pCtx->cr0 & X86_CR0_NE))
2595 {
2596 /* old style FPU error reporting needs some extra work. */
2597 /** @todo don't fall back to the recompiler, but do it manually. */
2598 rc = VINF_EM_RAW_EMULATE_INSTR;
2599 break;
2600 }
2601 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2602 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2603 AssertRC(rc);
2604
2605 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2606 goto ResumeExecution;
2607 }
2608
2609 case X86_XCPT_DB: /* Debug exception. */
2610 {
2611 uint64_t uDR6;
2612
2613 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2614 *
2615 * Exit qualification bits:
2616 * 3:0 B0-B3 which breakpoint condition was met
2617 * 12:4 Reserved (0)
2618 * 13 BD - debug register access detected
2619 * 14 BS - single step execution or branch taken
2620 * 63:15 Reserved (0)
2621 */
2622 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2623
2624 /* Note that we don't support guest and host-initiated debugging at the same time. */
2625 Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx));
2626
2627 uDR6 = X86_DR6_INIT_VAL;
2628 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2629 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
2630 if (rc == VINF_EM_RAW_GUEST_TRAP)
2631 {
2632 /** @todo this isn't working, but we'll never get here normally. */
2633
2634 /* Update DR6 here. */
2635 pCtx->dr[6] = uDR6;
2636
2637 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2638 pCtx->dr[7] &= ~X86_DR7_GD;
2639
2640 /* Paranoia. */
2641 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2642 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2643 pCtx->dr[7] |= 0x400; /* must be one */
2644
2645 /* Resync DR7 */
2646 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2647 AssertRC(rc);
2648
2649 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2650 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2651 AssertRC(rc);
2652
2653 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2654 goto ResumeExecution;
2655 }
2656 /* Return to ring 3 to deal with the debug exit code. */
2657 break;
2658 }
2659
2660 case X86_XCPT_BP: /* Breakpoint. */
2661 {
2662 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2663 if (rc == VINF_EM_RAW_GUEST_TRAP)
2664 {
2665 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2666 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2667 AssertRC(rc);
2668 goto ResumeExecution;
2669 }
2670 if (rc == VINF_SUCCESS)
2671 goto ResumeExecution;
2672 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2673 break;
2674 }
2675
2676 case X86_XCPT_GP: /* General protection failure exception.*/
2677 {
2678 uint32_t cbOp;
2679 uint32_t cbSize;
2680 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2681
2682 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2683#ifdef VBOX_STRICT
2684 if (!CPUMIsGuestInRealModeEx(pCtx))
2685 {
2686 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2687 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2688 AssertRC(rc);
2689 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2690 goto ResumeExecution;
2691 }
2692#endif
2693 Assert(CPUMIsGuestInRealModeEx(pCtx));
2694
2695 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2696
2697 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2698 if (RT_SUCCESS(rc))
2699 {
2700 bool fUpdateRIP = true;
2701
2702 Assert(cbOp == pDis->opsize);
2703 switch (pDis->pCurInstr->opcode)
2704 {
2705 case OP_CLI:
2706 pCtx->eflags.Bits.u1IF = 0;
2707 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2708 break;
2709
2710 case OP_STI:
2711 pCtx->eflags.Bits.u1IF = 1;
2712 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2713 break;
2714
2715 case OP_HLT:
2716 fUpdateRIP = false;
2717 rc = VINF_EM_HALT;
2718 pCtx->rip += pDis->opsize;
2719 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2720 break;
2721
2722 case OP_POPF:
2723 {
2724 RTGCPTR GCPtrStack;
2725 uint32_t cbParm;
2726 uint32_t uMask;
2727 X86EFLAGS eflags;
2728
2729 if (pDis->prefix & PREFIX_OPSIZE)
2730 {
2731 cbParm = 4;
2732 uMask = 0xffffffff;
2733 }
2734 else
2735 {
2736 cbParm = 2;
2737 uMask = 0xffff;
2738 }
2739
2740 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2741 if (RT_FAILURE(rc))
2742 {
2743 rc = VERR_EM_INTERPRETER;
2744 break;
2745 }
2746 eflags.u = 0;
2747 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2748 if (RT_FAILURE(rc))
2749 {
2750 rc = VERR_EM_INTERPRETER;
2751 break;
2752 }
2753 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2754 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
2755 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
2756 pCtx->eflags.Bits.u1RF = 0;
2757 pCtx->esp += cbParm;
2758 pCtx->esp &= uMask;
2759
2760 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2761 break;
2762 }
2763
2764 case OP_PUSHF:
2765 {
2766 RTGCPTR GCPtrStack;
2767 uint32_t cbParm;
2768 uint32_t uMask;
2769 X86EFLAGS eflags;
2770
2771 if (pDis->prefix & PREFIX_OPSIZE)
2772 {
2773 cbParm = 4;
2774 uMask = 0xffffffff;
2775 }
2776 else
2777 {
2778 cbParm = 2;
2779 uMask = 0xffff;
2780 }
2781
2782 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2783 if (RT_FAILURE(rc))
2784 {
2785 rc = VERR_EM_INTERPRETER;
2786 break;
2787 }
2788 eflags = pCtx->eflags;
2789 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2790 eflags.Bits.u1RF = 0;
2791 eflags.Bits.u1VM = 0;
2792
2793 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2794 if (RT_FAILURE(rc))
2795 {
2796 rc = VERR_EM_INTERPRETER;
2797 break;
2798 }
2799 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2800 pCtx->esp -= cbParm;
2801 pCtx->esp &= uMask;
2802 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2803 break;
2804 }
2805
2806 case OP_IRET:
2807 {
2808 RTGCPTR GCPtrStack;
2809 uint32_t uMask = 0xffff;
2810 uint16_t aIretFrame[3];
2811
2812 if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
2813 {
2814 rc = VERR_EM_INTERPRETER;
2815 break;
2816 }
2817
2818 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2819 if (RT_FAILURE(rc))
2820 {
2821 rc = VERR_EM_INTERPRETER;
2822 break;
2823 }
2824 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2825 if (RT_FAILURE(rc))
2826 {
2827 rc = VERR_EM_INTERPRETER;
2828 break;
2829 }
2830 pCtx->ip = aIretFrame[0];
2831 pCtx->cs = aIretFrame[1];
2832 pCtx->csHid.u64Base = pCtx->cs << 4;
2833 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2834 pCtx->sp += sizeof(aIretFrame);
2835
2836 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2837 fUpdateRIP = false;
2838 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2839 break;
2840 }
2841
2842 case OP_INT:
2843 {
2844 RTGCUINTPTR intInfo;
2845
2846 LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
2847 intInfo = pDis->param1.parval & 0xff;
2848 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2849 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2850
2851 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2852 AssertRC(rc);
2853 fUpdateRIP = false;
2854 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2855 break;
2856 }
2857
2858 case OP_INTO:
2859 {
2860 if (pCtx->eflags.Bits.u1OF)
2861 {
2862 RTGCUINTPTR intInfo;
2863
2864 LogFlow(("Realmode: INTO\n"));
2865 intInfo = X86_XCPT_OF;
2866 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2867 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2868
2869 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2870 AssertRC(rc);
2871 fUpdateRIP = false;
2872 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2873 }
2874 break;
2875 }
2876
2877 case OP_INT3:
2878 {
2879 RTGCUINTPTR intInfo;
2880
2881 LogFlow(("Realmode: INT 3\n"));
2882 intInfo = 3;
2883 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2884 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2885
2886 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2887 AssertRC(rc);
2888 fUpdateRIP = false;
2889 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2890 break;
2891 }
2892
2893 default:
2894 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
2895 break;
2896 }
2897
2898 if (rc == VINF_SUCCESS)
2899 {
2900 if (fUpdateRIP)
2901 pCtx->rip += cbOp; /* Move on to the next instruction. */
2902
2903 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2904 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2905
2906 /* Only resume if successful. */
2907 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2908 goto ResumeExecution;
2909 }
2910 }
2911 else
2912 rc = VERR_EM_INTERPRETER;
2913
2914 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2915 break;
2916 }
2917
2918#ifdef VBOX_STRICT
2919 case X86_XCPT_DE: /* Divide error. */
2920 case X86_XCPT_UD: /* Unknown opcode exception. */
2921 case X86_XCPT_SS: /* Stack segment exception. */
2922 case X86_XCPT_NP: /* Segment not present exception. */
2923 {
2924 switch(vector)
2925 {
2926 case X86_XCPT_DE:
2927 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2928 break;
2929 case X86_XCPT_UD:
2930 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2931 break;
2932 case X86_XCPT_SS:
2933 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2934 break;
2935 case X86_XCPT_NP:
2936 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2937 break;
2938 }
2939
2940 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2941 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2942 AssertRC(rc);
2943
2944 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2945 goto ResumeExecution;
2946 }
2947#endif
2948 default:
2949#ifdef HWACCM_VMX_EMULATE_REALMODE
2950 if (CPUMIsGuestInRealModeEx(pCtx))
2951 {
2952 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2953 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2954 AssertRC(rc);
2955
2956 /* Go back to ring 3 in case of a triple fault. */
2957 if ( vector == X86_XCPT_DF
2958 && rc == VINF_EM_RESET)
2959 break;
2960
2961 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2962 goto ResumeExecution;
2963 }
2964#endif
2965 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2966 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2967 break;
2968 } /* switch (vector) */
2969
2970 break;
2971
2972 default:
2973 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2974 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2975 break;
2976 }
2977
2978 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2979 break;
2980 }
2981
2982 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2983 {
2984 RTGCPHYS GCPhys;
2985
2986 Assert(pVM->hwaccm.s.fNestedPaging);
2987
2988 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2989 AssertRC(rc);
2990 Assert(((exitQualification >> 7) & 3) != 2);
2991
2992 /* Determine the kind of violation. */
2993 errCode = 0;
2994 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2995 errCode |= X86_TRAP_PF_ID;
2996
2997 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2998 errCode |= X86_TRAP_PF_RW;
2999
3000 /* If the page is present, then it's a page level protection fault. */
3001 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
3002 {
3003 errCode |= X86_TRAP_PF_P;
3004 }
3005 else {
3006 /* Shortcut for APIC TPR reads and writes. */
3007 if ( (GCPhys & 0xfff) == 0x080
3008 && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
3009 && fSetupTPRCaching
3010 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
3011 {
3012 RTGCPHYS GCPhysApicBase;
3013 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
3014 GCPhysApicBase &= PAGE_BASE_GC_MASK;
3015 if (GCPhys == GCPhysApicBase + 0x80)
3016 {
3017 Log(("Enable VT-x virtual APIC access filtering\n"));
3018 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
3019 AssertRC(rc);
3020 }
3021 }
3022 }
3023 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
3024
3025 /* GCPhys contains the guest physical address of the page fault. */
3026 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
3027 TRPMSetErrorCode(pVCpu, errCode);
3028 TRPMSetFaultAddress(pVCpu, GCPhys);
3029
3030 /* Handle the pagefault trap for the nested shadow table. */
3031 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
3032 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
3033 if (rc == VINF_SUCCESS)
3034 { /* We've successfully synced our shadow pages, so let's just continue execution. */
3035 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
3036 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
3037
3038 TRPMResetTrap(pVCpu);
3039
3040 goto ResumeExecution;
3041 }
3042
3043#ifdef VBOX_STRICT
3044 if (rc != VINF_EM_RAW_EMULATE_INSTR)
3045 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
3046#endif
3047 /* Need to go back to the recompiler to emulate the instruction. */
3048 TRPMResetTrap(pVCpu);
3049 break;
3050 }
3051
3052 case VMX_EXIT_EPT_MISCONFIG:
3053 {
3054 RTGCPHYS GCPhys;
3055
3056 Assert(pVM->hwaccm.s.fNestedPaging);
3057
3058 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3059 AssertRC(rc);
3060
3061 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
3062 break;
3063 }
3064
3065 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3066 /* Clear VM-exit on IF=1 change. */
3067 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
3068 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
3069 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3070 AssertRC(rc);
3071 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
3072 goto ResumeExecution; /* we check for pending guest interrupts there */
3073
3074 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
3075 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
3076 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
3077 /* Skip instruction and continue directly. */
3078 pCtx->rip += cbInstr;
3079 /* Continue execution.*/
3080 goto ResumeExecution;
3081
3082 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3083 {
3084 Log2(("VMX: Cpuid %x\n", pCtx->eax));
3085 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
3086 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3087 if (rc == VINF_SUCCESS)
3088 {
3089 /* Update EIP and continue execution. */
3090 Assert(cbInstr == 2);
3091 pCtx->rip += cbInstr;
3092 goto ResumeExecution;
3093 }
3094 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
3095 rc = VINF_EM_RAW_EMULATE_INSTR;
3096 break;
3097 }
3098
3099 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3100 {
3101 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
3102 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
3103 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3104 if (rc == VINF_SUCCESS)
3105 {
3106 /* Update EIP and continue execution. */
3107 Assert(cbInstr == 2);
3108 pCtx->rip += cbInstr;
3109 goto ResumeExecution;
3110 }
3111 rc = VINF_EM_RAW_EMULATE_INSTR;
3112 break;
3113 }
3114
3115 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3116 {
3117 Log2(("VMX: Rdtsc\n"));
3118 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
3119 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3120 if (rc == VINF_SUCCESS)
3121 {
3122 /* Update EIP and continue execution. */
3123 Assert(cbInstr == 2);
3124 pCtx->rip += cbInstr;
3125 goto ResumeExecution;
3126 }
3127 rc = VINF_EM_RAW_EMULATE_INSTR;
3128 break;
3129 }
3130
3131 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3132 {
3133 Log2(("VMX: invlpg\n"));
3134 Assert(!pVM->hwaccm.s.fNestedPaging);
3135
3136 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
3137 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
3138 if (rc == VINF_SUCCESS)
3139 {
3140 /* Update EIP and continue execution. */
3141 pCtx->rip += cbInstr;
3142 goto ResumeExecution;
3143 }
3144 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
3145 break;
3146 }
3147
3148 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3149 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3150 {
3151 uint32_t cbSize;
3152
3153 STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
3154
3155 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3156 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3157 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3158 if (rc == VINF_SUCCESS)
3159 {
3160 /* EIP has been updated already. */
3161
3162 /* Only resume if successful. */
3163 goto ResumeExecution;
3164 }
3165 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
3166 break;
3167 }
3168
3169 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3170 {
3171 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3172
3173 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3174 {
3175 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3176 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3177 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3178 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3179 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3180 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3181
3182 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3183 {
3184 case 0:
3185 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3186 break;
3187 case 2:
3188 break;
3189 case 3:
3190 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3191 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3192 break;
3193 case 4:
3194 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3195 break;
3196 case 8:
3197 /* CR8 contains the APIC TPR */
3198 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3199 break;
3200
3201 default:
3202 AssertFailed();
3203 break;
3204 }
3205 /* Check if a sync operation is pending. */
3206 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3207 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3208 {
3209 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3210 AssertRC(rc);
3211 }
3212 break;
3213
3214 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3215 Log2(("VMX: mov x, crx\n"));
3216 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3217
3218 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3219
3220 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3221 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3222
3223 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3224 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3225 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3226 break;
3227
3228 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3229 Log2(("VMX: clts\n"));
3230 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3231 rc = EMInterpretCLTS(pVM, pVCpu);
3232 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3233 break;
3234
3235 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3236 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3237 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3238 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3239 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3240 break;
3241 }
3242
3243 /* Update EIP if no error occurred. */
3244 if (RT_SUCCESS(rc))
3245 pCtx->rip += cbInstr;
3246
3247 if (rc == VINF_SUCCESS)
3248 {
3249 /* Only resume if successful. */
3250 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3251 goto ResumeExecution;
3252 }
3253 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3254 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3255 break;
3256 }
3257
3258 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3259 {
3260 if (!DBGFIsStepping(pVCpu))
3261 {
3262 /* Disable drx move intercepts. */
3263 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3264 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3265 AssertRC(rc);
3266
3267 /* Save the host and load the guest debug state. */
3268 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3269 AssertRC(rc);
3270
3271#ifdef VBOX_WITH_STATISTICS
3272 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3273 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3274 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3275 else
3276 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3277#endif
3278
3279 goto ResumeExecution;
3280 }
3281
3282 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3283 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3284 {
3285 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3286 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3287 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3288 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3289 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3290 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3291 Log2(("DR7=%08x\n", pCtx->dr[7]));
3292 }
3293 else
3294 {
3295 Log2(("VMX: mov x, drx\n"));
3296 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3297 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3298 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3299 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3300 }
3301 /* Update EIP if no error occurred. */
3302 if (RT_SUCCESS(rc))
3303 pCtx->rip += cbInstr;
3304
3305 if (rc == VINF_SUCCESS)
3306 {
3307 /* Only resume if successful. */
3308 goto ResumeExecution;
3309 }
3310 Assert(rc == VERR_EM_INTERPRETER);
3311 break;
3312 }
3313
3314 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3315 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3316 {
3317 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3318 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3319 uint32_t uPort;
3320 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3321
3322 /** @todo necessary to make the distinction? */
3323 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3324 {
3325 uPort = pCtx->edx & 0xffff;
3326 }
3327 else
3328 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3329
3330 /* paranoia */
3331 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3332 {
3333 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3334 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3335 break;
3336 }
3337
3338 uint32_t cbSize = g_aIOSize[uIOWidth];
3339
3340 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3341 {
3342 /* ins/outs */
3343 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
3344
3345 /* Disassemble manually to deal with segment prefixes. */
3346 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3347 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3348 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
3349 if (rc == VINF_SUCCESS)
3350 {
3351 if (fIOWrite)
3352 {
3353 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3354 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3355 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3356 }
3357 else
3358 {
3359 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3360 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3361 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3362 }
3363 }
3364 else
3365 rc = VINF_EM_RAW_EMULATE_INSTR;
3366 }
3367 else
3368 {
3369 /* normal in/out */
3370 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3371
3372 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3373
3374 if (fIOWrite)
3375 {
3376 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3377 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3378 }
3379 else
3380 {
3381 uint32_t u32Val = 0;
3382
3383 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3384 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3385 if (IOM_SUCCESS(rc))
3386 {
3387 /* Write back to the EAX register. */
3388 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3389 }
3390 }
3391 }
3392 /*
3393 * Handled the I/O return codes.
3394 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3395 */
3396 if (IOM_SUCCESS(rc))
3397 {
3398 /* Update EIP and continue execution. */
3399 pCtx->rip += cbInstr;
3400 if (RT_LIKELY(rc == VINF_SUCCESS))
3401 {
3402 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3403 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3404 {
3405 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3406 for (unsigned i=0;i<4;i++)
3407 {
3408 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3409
3410 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3411 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3412 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3413 {
3414 uint64_t uDR6;
3415
3416 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3417
3418 uDR6 = ASMGetDR6();
3419
3420 /* Clear all breakpoint status flags and set the one we just hit. */
3421 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3422 uDR6 |= (uint64_t)RT_BIT(i);
3423
3424 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3425 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3426 * the contents have been read.
3427 */
3428 ASMSetDR6(uDR6);
3429
3430 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3431 pCtx->dr[7] &= ~X86_DR7_GD;
3432
3433 /* Paranoia. */
3434 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3435 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3436 pCtx->dr[7] |= 0x400; /* must be one */
3437
3438 /* Resync DR7 */
3439 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3440 AssertRC(rc);
3441
3442 /* Construct inject info. */
3443 intInfo = X86_XCPT_DB;
3444 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3445 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3446
3447 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3448 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3449 AssertRC(rc);
3450
3451 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3452 goto ResumeExecution;
3453 }
3454 }
3455 }
3456
3457 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3458 goto ResumeExecution;
3459 }
3460 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3461 break;
3462 }
3463
3464#ifdef VBOX_STRICT
3465 if (rc == VINF_IOM_HC_IOPORT_READ)
3466 Assert(!fIOWrite);
3467 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3468 Assert(fIOWrite);
3469 else
3470 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3471#endif
3472 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3473 break;
3474 }
3475
3476 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3477 LogFlow(("VMX_EXIT_TPR\n"));
3478 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3479 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3480 goto ResumeExecution;
3481
3482 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3483 {
3484 LogFlow(("VMX_EXIT_APIC_ACCESS\n"));
3485 unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
3486
3487 switch(uAccessType)
3488 {
3489 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
3490 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
3491 {
3492 RTGCPHYS GCPhys;
3493 PDMApicGetBase(pVM, &GCPhys);
3494 GCPhys &= PAGE_BASE_GC_MASK;
3495 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
3496
3497 LogFlow(("Apic access at %RGp\n", GCPhys));
3498 rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
3499 if (rc == VINF_SUCCESS)
3500 {
3501 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3502 goto ResumeExecution; /* rip already updated */
3503 }
3504 break;
3505 }
3506
3507 default:
3508 rc = VINF_EM_RAW_EMULATE_INSTR;
3509 break;
3510 }
3511 break;
3512 }
3513
3514 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3515 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3516 goto ResumeExecution;
3517
3518 default:
3519 /* The rest is handled after syncing the entire CPU state. */
3520 break;
3521 }
3522
3523 /* Note: the guest state isn't entirely synced back at this stage. */
3524
3525 /* Investigate why there was a VM-exit. (part 2) */
3526 switch (exitReason)
3527 {
3528 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3529 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3530 case VMX_EXIT_EPT_VIOLATION:
3531 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3532 /* Already handled above. */
3533 break;
3534
3535 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3536 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3537 break;
3538
3539 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3540 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3541 rc = VINF_EM_RAW_INTERRUPT;
3542 AssertFailed(); /* Can't happen. Yet. */
3543 break;
3544
3545 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3546 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3547 rc = VINF_EM_RAW_INTERRUPT;
3548 AssertFailed(); /* Can't happen afaik. */
3549 break;
3550
3551 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3552 rc = VERR_EM_INTERPRETER;
3553 break;
3554
3555 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3556 /** Check if external interrupts are pending; if so, don't switch back. */
3557 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
3558 pCtx->rip++; /* skip hlt */
3559 if ( pCtx->eflags.Bits.u1IF
3560 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3561 goto ResumeExecution;
3562
3563 rc = VINF_EM_HALT;
3564 break;
3565
3566 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3567 Log2(("VMX: mwait\n"));
3568 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
3569 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3570 if ( rc == VINF_EM_HALT
3571 || rc == VINF_SUCCESS)
3572 {
3573 /* Update EIP and continue execution. */
3574 pCtx->rip += cbInstr;
3575
3576 /** Check if external interrupts are pending; if so, don't switch back. */
3577 if ( rc == VINF_SUCCESS
3578 || ( rc == VINF_EM_HALT
3579 && pCtx->eflags.Bits.u1IF
3580 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3581 )
3582 goto ResumeExecution;
3583 }
3584 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
3585 break;
3586
3587 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3588 AssertFailed(); /* can't happen. */
3589 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3590 break;
3591
3592 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3593 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3594 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3595 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3596 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3597 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3598 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3599 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3600 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3601 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3602 /** @todo inject #UD immediately */
3603 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3604 break;
3605
3606 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3607 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3608 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3609 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3610 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3611 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3612 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3613 /* already handled above */
3614 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3615 || rc == VINF_EM_RAW_INTERRUPT
3616 || rc == VERR_EM_INTERPRETER
3617 || rc == VINF_EM_RAW_EMULATE_INSTR
3618 || rc == VINF_PGM_SYNC_CR3
3619 || rc == VINF_IOM_HC_IOPORT_READ
3620 || rc == VINF_IOM_HC_IOPORT_WRITE
3621 || rc == VINF_EM_RAW_GUEST_TRAP
3622 || rc == VINF_TRPM_XCPT_DISPATCHED
3623 || rc == VINF_EM_RESCHEDULE_REM,
3624 ("rc = %d\n", rc));
3625 break;
3626
3627 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3628 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3629 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3630 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3631 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3632 rc = VERR_EM_INTERPRETER;
3633 break;
3634
3635 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3636 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3637 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3638 break;
3639
3640 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3641 Assert(rc == VINF_EM_RAW_INTERRUPT);
3642 break;
3643
3644 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3645 {
3646#ifdef VBOX_STRICT
3647 RTCCUINTREG val = 0;
3648
3649 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3650
3651 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3652 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3653
3654 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3655 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3656
3657 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3658 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3659
3660 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3661 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3662
3663 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3664 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3665
3666 VMX_LOG_SELREG(CS, "CS");
3667 VMX_LOG_SELREG(DS, "DS");
3668 VMX_LOG_SELREG(ES, "ES");
3669 VMX_LOG_SELREG(FS, "FS");
3670 VMX_LOG_SELREG(GS, "GS");
3671 VMX_LOG_SELREG(SS, "SS");
3672 VMX_LOG_SELREG(TR, "TR");
3673 VMX_LOG_SELREG(LDTR, "LDTR");
3674
3675 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3676 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3677 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3678 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3679#endif /* VBOX_STRICT */
3680 rc = VERR_VMX_INVALID_GUEST_STATE;
3681 break;
3682 }
3683
3684 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3685 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3686 default:
3687 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3688 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3689 break;
3690
3691 }
3692end:
3693
3694 /* Signal changes for the recompiler. */
3695 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3696
3697 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3698 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3699 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3700 {
3701 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3702 /* On the next entry we'll only sync the host context. */
3703 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3704 }
3705 else
3706 {
3707 /* On the next entry we'll sync everything. */
3708 /** @todo we can do better than this */
3709 /* Not in the VINF_PGM_CHANGE_MODE though! */
3710 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3711 }
3712
3713 /* translate into a less severe return code */
3714 if (rc == VERR_EM_INTERPRETER)
3715 rc = VINF_EM_RAW_EMULATE_INSTR;
3716 else
3717 /* Try to extract more information about what might have gone wrong here. */
3718 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3719 {
3720 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3721 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3722 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3723 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3724 }
3725
3726 /* Just set the correct state here instead of trying to catch every goto above. */
3727 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
3728
3729#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
3730 /* Restore interrupts if we exitted after disabling them. */
3731 if (uOldEFlags != ~(RTCCUINTREG)0)
3732 ASMSetFlags(uOldEFlags);
3733#endif
3734
3735 STAM_STATS({
3736 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3737 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3738 });
3739 Log2(("X"));
3740 return rc;
3741}
3742
3743
3744/**
3745 * Enters the VT-x session
3746 *
3747 * @returns VBox status code.
3748 * @param pVM The VM to operate on.
3749 * @param pVCpu The VMCPU to operate on.
3750 * @param pCpu CPU info struct
3751 */
3752VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3753{
3754 Assert(pVM->hwaccm.s.vmx.fSupported);
3755
3756 unsigned cr4 = ASMGetCR4();
3757 if (!(cr4 & X86_CR4_VMXE))
3758 {
3759 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3760 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3761 }
3762
3763 /* Activate the VM Control Structure. */
3764 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3765 if (RT_FAILURE(rc))
3766 return rc;
3767
3768 pVCpu->hwaccm.s.fResumeVM = false;
3769 return VINF_SUCCESS;
3770}
3771
3772
3773/**
3774 * Leaves the VT-x session
3775 *
3776 * @returns VBox status code.
3777 * @param pVM The VM to operate on.
3778 * @param pVCpu The VMCPU to operate on.
3779 * @param pCtx CPU context
3780 */
3781VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3782{
3783 Assert(pVM->hwaccm.s.vmx.fSupported);
3784
3785 /* Save the guest debug state if necessary. */
3786 if (CPUMIsGuestDebugStateActive(pVCpu))
3787 {
3788 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3789
3790 /* Enable drx move intercepts again. */
3791 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3792 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3793 AssertRC(rc);
3794
3795 /* Resync the debug registers the next time. */
3796 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3797 }
3798 else
3799 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3800
3801 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3802 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3803 AssertRC(rc);
3804
3805 return VINF_SUCCESS;
3806}
3807
3808/**
3809 * Flush the TLB (EPT)
3810 *
3811 * @returns VBox status code.
3812 * @param pVM The VM to operate on.
3813 * @param pVCpu The VM CPU to operate on.
3814 * @param enmFlush Type of flush
3815 * @param GCPhys Physical address of the page to flush
3816 */
3817static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3818{
3819 uint64_t descriptor[2];
3820
3821 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3822 Assert(pVM->hwaccm.s.fNestedPaging);
3823 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3824 descriptor[1] = GCPhys;
3825 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3826 AssertRC(rc);
3827}
3828
3829#ifdef HWACCM_VTX_WITH_VPID
3830/**
3831 * Flush the TLB (EPT)
3832 *
3833 * @returns VBox status code.
3834 * @param pVM The VM to operate on.
3835 * @param pVCpu The VM CPU to operate on.
3836 * @param enmFlush Type of flush
3837 * @param GCPtr Virtual address of the page to flush
3838 */
3839static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3840{
3841#if HC_ARCH_BITS == 32
3842 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3843 if ( CPUMIsGuestInLongMode(pVCpu)
3844 && !VMX_IS_64BIT_HOST_MODE())
3845 {
3846 pVCpu->hwaccm.s.fForceTLBFlush = true;
3847 }
3848 else
3849#endif
3850 {
3851 uint64_t descriptor[2];
3852
3853 Assert(pVM->hwaccm.s.vmx.fVPID);
3854 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3855 descriptor[1] = GCPtr;
3856 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3857 AssertRC(rc);
3858 }
3859}
3860#endif /* HWACCM_VTX_WITH_VPID */
3861
3862/**
3863 * Invalidates a guest page
3864 *
3865 * @returns VBox status code.
3866 * @param pVM The VM to operate on.
3867 * @param pVCpu The VM CPU to operate on.
3868 * @param GCVirt Page to invalidate
3869 */
3870VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3871{
3872 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3873
3874 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3875
3876 /* Only relevant if we want to use VPID.
3877 * In the nested paging case we still see such calls, but
3878 * can safely ignore them. (e.g. after cr3 updates)
3879 */
3880#ifdef HWACCM_VTX_WITH_VPID
3881 /* Skip it if a TLB flush is already pending. */
3882 if ( !fFlushPending
3883 && pVM->hwaccm.s.vmx.fVPID)
3884 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3885#endif /* HWACCM_VTX_WITH_VPID */
3886
3887 return VINF_SUCCESS;
3888}
3889
3890/**
3891 * Invalidates a guest page by physical address
3892 *
3893 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3894 *
3895 * @returns VBox status code.
3896 * @param pVM The VM to operate on.
3897 * @param pVCpu The VM CPU to operate on.
3898 * @param GCPhys Page to invalidate
3899 */
3900VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3901{
3902 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3903
3904 Assert(pVM->hwaccm.s.fNestedPaging);
3905
3906 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3907
3908 /* Skip it if a TLB flush is already pending. */
3909 if (!fFlushPending)
3910 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3911
3912 return VINF_SUCCESS;
3913}
3914
3915/**
3916 * Report world switch error and dump some useful debug info
3917 *
3918 * @param pVM The VM to operate on.
3919 * @param pVCpu The VMCPU to operate on.
3920 * @param rc Return code
3921 * @param pCtx Current CPU context (not updated)
3922 */
3923static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3924{
3925 switch (rc)
3926 {
3927 case VERR_VMX_INVALID_VMXON_PTR:
3928 AssertFailed();
3929 break;
3930
3931 case VERR_VMX_UNABLE_TO_START_VM:
3932 case VERR_VMX_UNABLE_TO_RESUME_VM:
3933 {
3934 int rc;
3935 RTCCUINTREG exitReason, instrError;
3936
3937 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3938 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3939 AssertRC(rc);
3940 if (rc == VINF_SUCCESS)
3941 {
3942 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3943 Log(("Current stack %08x\n", &rc));
3944
3945 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3946 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3947
3948#ifdef VBOX_STRICT
3949 RTGDTR gdtr;
3950 PX86DESCHC pDesc;
3951 RTCCUINTREG val;
3952
3953 ASMGetGDTR(&gdtr);
3954
3955 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3956 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3957 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3958 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3959 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3960 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3961 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3962 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3963 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3964 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3965
3966 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3967 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3968
3969 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3970 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3971
3972 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3973 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3974
3975 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3976 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3977
3978 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3979 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3980
3981 if (val < gdtr.cbGdt)
3982 {
3983 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3984 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3985 }
3986
3987 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3988 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3989 if (val < gdtr.cbGdt)
3990 {
3991 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3992 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3993 }
3994
3995 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
3996 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3997 if (val < gdtr.cbGdt)
3998 {
3999 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4000 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
4001 }
4002
4003 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
4004 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
4005 if (val < gdtr.cbGdt)
4006 {
4007 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4008 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
4009 }
4010
4011 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
4012 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
4013 if (val < gdtr.cbGdt)
4014 {
4015 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4016 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
4017 }
4018
4019 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
4020 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
4021 if (val < gdtr.cbGdt)
4022 {
4023 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4024 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
4025 }
4026
4027 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
4028 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
4029 if (val < gdtr.cbGdt)
4030 {
4031 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4032 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
4033 }
4034
4035 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
4036 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
4037
4038 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
4039 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
4040 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
4041 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
4042
4043 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
4044 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
4045
4046 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
4047 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
4048
4049 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
4050 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
4051
4052 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
4053 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
4054 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
4055 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
4056
4057# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4058 if (VMX_IS_64BIT_HOST_MODE())
4059 {
4060 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
4061 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
4062 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
4063 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
4064 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
4065 }
4066# endif
4067#endif /* VBOX_STRICT */
4068 }
4069 break;
4070 }
4071
4072 default:
4073 /* impossible */
4074 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
4075 break;
4076 }
4077}
4078
4079#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4080/**
4081 * Prepares for and executes VMLAUNCH (64 bits guest mode)
4082 *
4083 * @returns VBox status code
4084 * @param fResume vmlauch/vmresume
4085 * @param pCtx Guest context
4086 * @param pCache VMCS cache
4087 * @param pVM The VM to operate on.
4088 * @param pVCpu The VMCPU to operate on.
4089 */
4090DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
4091{
4092 uint32_t aParam[6];
4093 PHWACCM_CPUINFO pCpu;
4094 RTHCPHYS pPageCpuPhys;
4095 int rc;
4096
4097 pCpu = HWACCMR0GetCurrentCpu();
4098 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4099
4100#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4101 pCache->uPos = 1;
4102 pCache->interPD = PGMGetInterPaeCR3(pVM);
4103 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
4104#endif
4105
4106#ifdef DEBUG
4107 pCache->TestIn.pPageCpuPhys = 0;
4108 pCache->TestIn.pVMCSPhys = 0;
4109 pCache->TestIn.pCache = 0;
4110 pCache->TestOut.pVMCSPhys = 0;
4111 pCache->TestOut.pCache = 0;
4112 pCache->TestOut.pCtx = 0;
4113 pCache->TestOut.eflags = 0;
4114#endif
4115
4116 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
4117 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
4118 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
4119 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
4120 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
4121 aParam[5] = 0;
4122
4123#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4124 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
4125 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
4126#endif
4127 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
4128
4129#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4130 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
4131 Assert(pCtx->dr[4] == 10);
4132 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
4133#endif
4134
4135#ifdef DEBUG
4136 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
4137 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
4138 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
4139 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
4140 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
4141 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
4142 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
4143#endif
4144 return rc;
4145}
4146
4147/**
4148 * Executes the specified handler in 64 mode
4149 *
4150 * @returns VBox status code.
4151 * @param pVM The VM to operate on.
4152 * @param pVCpu The VMCPU to operate on.
4153 * @param pCtx Guest context
4154 * @param pfnHandler RC handler
4155 * @param cbParam Number of parameters
4156 * @param paParam Array of 32 bits parameters
4157 */
4158VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
4159{
4160 int rc, rc2;
4161 PHWACCM_CPUINFO pCpu;
4162 RTHCPHYS pPageCpuPhys;
4163
4164 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
4165 AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
4166 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
4167 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
4168 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
4169
4170#ifdef VBOX_STRICT
4171 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
4172 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
4173
4174 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
4175 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
4176#endif
4177
4178 pCpu = HWACCMR0GetCurrentCpu();
4179 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4180
4181 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4182 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4183
4184 /* Leave VMX Root Mode. */
4185 VMXDisable();
4186
4187 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4188
4189 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
4190 CPUMSetHyperEIP(pVCpu, pfnHandler);
4191 for (int i=(int)cbParam-1;i>=0;i--)
4192 CPUMPushHyper(pVCpu, paParam[i]);
4193
4194 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4195 /* Call switcher. */
4196 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
4197 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4198
4199 /* Make sure the VMX instructions don't cause #UD faults. */
4200 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
4201
4202 /* Enter VMX Root Mode */
4203 rc2 = VMXEnable(pPageCpuPhys);
4204 if (RT_FAILURE(rc2))
4205 {
4206 if (pVM)
4207 VMXR0CheckError(pVM, pVCpu, rc2);
4208 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4209 return VERR_VMX_VMXON_FAILED;
4210 }
4211
4212 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4213 AssertRCReturn(rc2, rc2);
4214 Assert(!(ASMGetFlags() & X86_EFL_IF));
4215 return rc;
4216}
4217
4218#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4219
4220
4221#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4222/**
4223 * Executes VMWRITE
4224 *
4225 * @returns VBox status code
4226 * @param pVCpu The VMCPU to operate on.
4227 * @param idxField VMCS index
4228 * @param u64Val 16, 32 or 64 bits value
4229 */
4230VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4231{
4232 int rc;
4233
4234 switch (idxField)
4235 {
4236 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4237 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4238 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4239 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4240 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4241 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4242 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4243 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4244 case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
4245 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4246 case VMX_VMCS_GUEST_PDPTR0_FULL:
4247 case VMX_VMCS_GUEST_PDPTR1_FULL:
4248 case VMX_VMCS_GUEST_PDPTR2_FULL:
4249 case VMX_VMCS_GUEST_PDPTR3_FULL:
4250 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4251 case VMX_VMCS_GUEST_EFER_FULL:
4252 case VMX_VMCS_CTRL_EPTP_FULL:
4253 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4254 rc = VMXWriteVMCS32(idxField, u64Val);
4255 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4256 AssertRC(rc);
4257 return rc;
4258
4259 case VMX_VMCS64_GUEST_LDTR_BASE:
4260 case VMX_VMCS64_GUEST_TR_BASE:
4261 case VMX_VMCS64_GUEST_GDTR_BASE:
4262 case VMX_VMCS64_GUEST_IDTR_BASE:
4263 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4264 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4265 case VMX_VMCS64_GUEST_CR0:
4266 case VMX_VMCS64_GUEST_CR4:
4267 case VMX_VMCS64_GUEST_CR3:
4268 case VMX_VMCS64_GUEST_DR7:
4269 case VMX_VMCS64_GUEST_RIP:
4270 case VMX_VMCS64_GUEST_RSP:
4271 case VMX_VMCS64_GUEST_CS_BASE:
4272 case VMX_VMCS64_GUEST_DS_BASE:
4273 case VMX_VMCS64_GUEST_ES_BASE:
4274 case VMX_VMCS64_GUEST_FS_BASE:
4275 case VMX_VMCS64_GUEST_GS_BASE:
4276 case VMX_VMCS64_GUEST_SS_BASE:
4277 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4278 if (u64Val >> 32ULL)
4279 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4280 else
4281 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4282
4283 return rc;
4284
4285 default:
4286 AssertMsgFailed(("Unexpected field %x\n", idxField));
4287 return VERR_INVALID_PARAMETER;
4288 }
4289}
4290
4291/**
4292 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4293 *
4294 * @param pVCpu The VMCPU to operate on.
4295 * @param idxField VMCS field
4296 * @param u64Val Value
4297 */
4298VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4299{
4300 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4301
4302 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4303
4304 /* Make sure there are no duplicates. */
4305 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4306 {
4307 if (pCache->Write.aField[i] == idxField)
4308 {
4309 pCache->Write.aFieldVal[i] = u64Val;
4310 return VINF_SUCCESS;
4311 }
4312 }
4313
4314 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4315 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4316 pCache->Write.cValidEntries++;
4317 return VINF_SUCCESS;
4318}
4319
4320#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4321
4322#ifdef VBOX_STRICT
4323static bool vmxR0IsValidReadField(uint32_t idxField)
4324{
4325 switch(idxField)
4326 {
4327 case VMX_VMCS64_GUEST_RIP:
4328 case VMX_VMCS64_GUEST_RSP:
4329 case VMX_VMCS_GUEST_RFLAGS:
4330 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4331 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4332 case VMX_VMCS64_GUEST_CR0:
4333 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4334 case VMX_VMCS64_GUEST_CR4:
4335 case VMX_VMCS64_GUEST_DR7:
4336 case VMX_VMCS32_GUEST_SYSENTER_CS:
4337 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4338 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4339 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4340 case VMX_VMCS64_GUEST_GDTR_BASE:
4341 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4342 case VMX_VMCS64_GUEST_IDTR_BASE:
4343 case VMX_VMCS16_GUEST_FIELD_CS:
4344 case VMX_VMCS32_GUEST_CS_LIMIT:
4345 case VMX_VMCS64_GUEST_CS_BASE:
4346 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4347 case VMX_VMCS16_GUEST_FIELD_DS:
4348 case VMX_VMCS32_GUEST_DS_LIMIT:
4349 case VMX_VMCS64_GUEST_DS_BASE:
4350 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4351 case VMX_VMCS16_GUEST_FIELD_ES:
4352 case VMX_VMCS32_GUEST_ES_LIMIT:
4353 case VMX_VMCS64_GUEST_ES_BASE:
4354 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4355 case VMX_VMCS16_GUEST_FIELD_FS:
4356 case VMX_VMCS32_GUEST_FS_LIMIT:
4357 case VMX_VMCS64_GUEST_FS_BASE:
4358 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4359 case VMX_VMCS16_GUEST_FIELD_GS:
4360 case VMX_VMCS32_GUEST_GS_LIMIT:
4361 case VMX_VMCS64_GUEST_GS_BASE:
4362 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4363 case VMX_VMCS16_GUEST_FIELD_SS:
4364 case VMX_VMCS32_GUEST_SS_LIMIT:
4365 case VMX_VMCS64_GUEST_SS_BASE:
4366 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4367 case VMX_VMCS16_GUEST_FIELD_LDTR:
4368 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4369 case VMX_VMCS64_GUEST_LDTR_BASE:
4370 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4371 case VMX_VMCS16_GUEST_FIELD_TR:
4372 case VMX_VMCS32_GUEST_TR_LIMIT:
4373 case VMX_VMCS64_GUEST_TR_BASE:
4374 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4375 case VMX_VMCS32_RO_EXIT_REASON:
4376 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4377 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4378 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4379 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4380 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4381 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4382 case VMX_VMCS32_RO_IDT_INFO:
4383 case VMX_VMCS32_RO_IDT_ERRCODE:
4384 case VMX_VMCS64_GUEST_CR3:
4385 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4386 return true;
4387 }
4388 return false;
4389}
4390
4391static bool vmxR0IsValidWriteField(uint32_t idxField)
4392{
4393 switch(idxField)
4394 {
4395 case VMX_VMCS64_GUEST_LDTR_BASE:
4396 case VMX_VMCS64_GUEST_TR_BASE:
4397 case VMX_VMCS64_GUEST_GDTR_BASE:
4398 case VMX_VMCS64_GUEST_IDTR_BASE:
4399 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4400 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4401 case VMX_VMCS64_GUEST_CR0:
4402 case VMX_VMCS64_GUEST_CR4:
4403 case VMX_VMCS64_GUEST_CR3:
4404 case VMX_VMCS64_GUEST_DR7:
4405 case VMX_VMCS64_GUEST_RIP:
4406 case VMX_VMCS64_GUEST_RSP:
4407 case VMX_VMCS64_GUEST_CS_BASE:
4408 case VMX_VMCS64_GUEST_DS_BASE:
4409 case VMX_VMCS64_GUEST_ES_BASE:
4410 case VMX_VMCS64_GUEST_FS_BASE:
4411 case VMX_VMCS64_GUEST_GS_BASE:
4412 case VMX_VMCS64_GUEST_SS_BASE:
4413 return true;
4414 }
4415 return false;
4416}
4417
4418#endif
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette