VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 20838

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1/* $Id: HWVMXR0.cpp 20838 2009-06-23 14:15:46Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/param.h>
41#include <iprt/string.h>
42#include <iprt/time.h>
43#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
44# include <iprt/thread.h>
45#endif
46#include "HWVMXR0.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51#if defined(RT_ARCH_AMD64)
52# define VMX_IS_64BIT_HOST_MODE() (true)
53#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
54# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
55#else
56# define VMX_IS_64BIT_HOST_MODE() (false)
57#endif
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62/* IO operation lookup arrays. */
63static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
65
66#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
67/** See HWACCMR0A.asm. */
68extern "C" uint32_t g_fVMXIs64bitHost;
69#endif
70
71/*******************************************************************************
72* Local Functions *
73*******************************************************************************/
74static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
75static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
76static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
77static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
78static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
79static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
80static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
81#ifdef VBOX_STRICT
82static bool vmxR0IsValidReadField(uint32_t idxField);
83static bool vmxR0IsValidWriteField(uint32_t idxField);
84#endif
85
86static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
87{
88 if (rc == VERR_VMX_GENERIC)
89 {
90 RTCCUINTREG instrError;
91
92 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
93 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
94 }
95 pVM->hwaccm.s.lLastError = rc;
96}
97
98/**
99 * Sets up and activates VT-x on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pVM The VM to operate on. (can be NULL after a resume!!)
104 * @param pvPageCpu Pointer to the global cpu page
105 * @param pPageCpuPhys Physical address of the global cpu page
106 */
107VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
108{
109 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
110 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
111
112#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
113 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
114#endif
115 if (pVM)
116 {
117 /* Set revision dword at the beginning of the VMXON structure. */
118 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
119 }
120
121 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
122 * (which can have very bad consequences!!!)
123 */
124
125 /* Make sure the VMX instructions don't cause #UD faults. */
126 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
127
128 /* Enter VMX Root Mode */
129 int rc = VMXEnable(pPageCpuPhys);
130 if (RT_FAILURE(rc))
131 {
132 if (pVM)
133 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
134 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
135 return VERR_VMX_VMXON_FAILED;
136 }
137 return VINF_SUCCESS;
138}
139
140/**
141 * Deactivates VT-x on the current CPU
142 *
143 * @returns VBox status code.
144 * @param pCpu CPU info struct
145 * @param pvPageCpu Pointer to the global cpu page
146 * @param pPageCpuPhys Physical address of the global cpu page
147 */
148VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
149{
150 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
151 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
152
153 /* Leave VMX Root Mode. */
154 VMXDisable();
155
156 /* And clear the X86_CR4_VMXE bit */
157 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
158
159#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
160 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
161#endif
162 return VINF_SUCCESS;
163}
164
165/**
166 * Does Ring-0 per VM VT-x init.
167 *
168 * @returns VBox status code.
169 * @param pVM The VM to operate on.
170 */
171VMMR0DECL(int) VMXR0InitVM(PVM pVM)
172{
173 int rc;
174
175#ifdef LOG_ENABLED
176 SUPR0Printf("VMXR0InitVM %x\n", pVM);
177#endif
178
179 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
180
181 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
182 {
183 /* Allocate one page for the APIC physical page (serves for filtering accesses). */
184 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185 AssertRC(rc);
186 if (RT_FAILURE(rc))
187 return rc;
188
189 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
190 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
191 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
192 }
193 else
194 {
195 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
196 pVM->hwaccm.s.vmx.pAPIC = 0;
197 pVM->hwaccm.s.vmx.pAPICPhys = 0;
198 }
199
200 /* Allocate the MSR bitmap if this feature is supported. */
201 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
202 {
203 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
204 AssertRC(rc);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
209 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
210 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
211 }
212
213#ifdef VBOX_WITH_CRASHDUMP_MAGIC
214 {
215 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
216 AssertRC(rc);
217 if (RT_FAILURE(rc))
218 return rc;
219
220 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
221 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
222
223 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
224 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
225 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
226 }
227#endif
228
229 /* Allocate VMCBs for all guest CPUs. */
230 for (unsigned i=0;i<pVM->cCPUs;i++)
231 {
232 PVMCPU pVCpu = &pVM->aCpus[i];
233
234 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
235
236 /* Allocate one page for the VM control structure (VMCS). */
237 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
238 AssertRC(rc);
239 if (RT_FAILURE(rc))
240 return rc;
241
242 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
243 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
244 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
245
246 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
247 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
248
249 /* Allocate one page for the virtual APIC page for TPR caching. */
250 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
251 AssertRC(rc);
252 if (RT_FAILURE(rc))
253 return rc;
254
255 pVCpu->hwaccm.s.vmx.pVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
256 pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
257 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
258
259 /* Current guest paging mode. */
260 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
261
262#ifdef LOG_ENABLED
263 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
264#endif
265 }
266
267 return VINF_SUCCESS;
268}
269
270/**
271 * Does Ring-0 per VM VT-x termination.
272 *
273 * @returns VBox status code.
274 * @param pVM The VM to operate on.
275 */
276VMMR0DECL(int) VMXR0TermVM(PVM pVM)
277{
278 for (unsigned i=0;i<pVM->cCPUs;i++)
279 {
280 PVMCPU pVCpu = &pVM->aCpus[i];
281
282 if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
283 {
284 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
285 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
286 pVCpu->hwaccm.s.vmx.pVMCS = 0;
287 pVCpu->hwaccm.s.vmx.pVMCSPhys = 0;
288 }
289 if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
290 {
291 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
292 pVCpu->hwaccm.s.vmx.pMemObjVAPIC = NIL_RTR0MEMOBJ;
293 pVCpu->hwaccm.s.vmx.pVAPIC = 0;
294 pVCpu->hwaccm.s.vmx.pVAPICPhys = 0;
295 }
296 }
297 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
298 {
299 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
300 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
301 pVM->hwaccm.s.vmx.pAPIC = 0;
302 pVM->hwaccm.s.vmx.pAPICPhys = 0;
303 }
304 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
305 {
306 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
307 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
308 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
309 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
310 }
311#ifdef VBOX_WITH_CRASHDUMP_MAGIC
312 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
313 {
314 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
315 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
316 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
317 pVM->hwaccm.s.vmx.pScratch = 0;
318 pVM->hwaccm.s.vmx.pScratchPhys = 0;
319 }
320#endif
321 return VINF_SUCCESS;
322}
323
324/**
325 * Sets up VT-x for the specified VM
326 *
327 * @returns VBox status code.
328 * @param pVM The VM to operate on.
329 */
330VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
331{
332 int rc = VINF_SUCCESS;
333 uint32_t val;
334
335 AssertReturn(pVM, VERR_INVALID_PARAMETER);
336
337 for (unsigned i=0;i<pVM->cCPUs;i++)
338 {
339 PVMCPU pVCpu = &pVM->aCpus[i];
340
341 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
342
343 /* Set revision dword at the beginning of the VMCS structure. */
344 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
345
346 /* Clear VM Control Structure. */
347 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
348 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
349 if (RT_FAILURE(rc))
350 goto vmx_end;
351
352 /* Activate the VM Control Structure. */
353 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
354 if (RT_FAILURE(rc))
355 goto vmx_end;
356
357 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
358 * Set required bits to one and zero according to the MSR capabilities.
359 */
360 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
361 /* External and non-maskable interrupts cause VM-exits. */
362 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
363 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
364
365 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
366 AssertRC(rc);
367
368 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
369 * Set required bits to one and zero according to the MSR capabilities.
370 */
371 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
372 /* Program which event cause VM-exits and which features we want to use. */
373 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
374 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
375 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
376 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
377 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
378 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
379
380 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
381 if (!pVM->hwaccm.s.fNestedPaging)
382 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
383 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
384 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
385
386 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
387 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
388 {
389 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
390 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
391 Assert(pVM->hwaccm.s.vmx.pAPIC);
392 }
393 else
394 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
395 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
396
397#ifdef VBOX_WITH_VTX_MSR_BITMAPS
398 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
399 {
400 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
401 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
402 }
403#endif
404
405 /* We will use the secondary control if it's present. */
406 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
407
408 /* Mask away the bits that the CPU doesn't support */
409 /** @todo make sure they don't conflict with the above requirements. */
410 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
411 pVCpu->hwaccm.s.vmx.proc_ctls = val;
412
413 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
414 AssertRC(rc);
415
416 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
417 {
418 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
419 * Set required bits to one and zero according to the MSR capabilities.
420 */
421 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
422 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
423
424#ifdef HWACCM_VTX_WITH_EPT
425 if (pVM->hwaccm.s.fNestedPaging)
426 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
427#endif /* HWACCM_VTX_WITH_EPT */
428#ifdef HWACCM_VTX_WITH_VPID
429 else
430 if (pVM->hwaccm.s.vmx.fVPID)
431 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
432#endif /* HWACCM_VTX_WITH_VPID */
433
434 if (pVM->hwaccm.s.fHasIoApic)
435 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC;
436
437 /* Mask away the bits that the CPU doesn't support */
438 /** @todo make sure they don't conflict with the above requirements. */
439 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
440 pVCpu->hwaccm.s.vmx.proc_ctls2 = val;
441 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
442 AssertRC(rc);
443 }
444
445 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
446 * Set required bits to one and zero according to the MSR capabilities.
447 */
448 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
449 AssertRC(rc);
450
451 /* Forward all exception except #NM & #PF to the guest.
452 * We always need to check pagefaults since our shadow page table can be out of sync.
453 * And we always lazily sync the FPU & XMM state.
454 */
455
456 /** @todo Possible optimization:
457 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
458 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
459 * registers ourselves of course.
460 *
461 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
462 */
463
464 /* Don't filter page faults; all of them should cause a switch. */
465 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
467 AssertRC(rc);
468
469 /* Init TSC offset to zero. */
470 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
471 AssertRC(rc);
472
473 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
474 AssertRC(rc);
475
476 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
477 AssertRC(rc);
478
479 /* Set the MSR bitmap address. */
480 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
481 {
482 /* Optional */
483 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
484 AssertRC(rc);
485 }
486
487 /* Clear MSR controls. */
488 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
489 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
490 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
491 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
492 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
493 AssertRC(rc);
494
495 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
496 {
497 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
498 /* Optional */
499 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
500 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
501
502 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
503 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
504
505 AssertRC(rc);
506 }
507
508 /* Set link pointer to -1. Not currently used. */
509 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
510 AssertRC(rc);
511
512 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
513 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
514 AssertRC(rc);
515
516 /* Configure the VMCS read cache. */
517 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
518
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
525 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
526 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
527 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
530 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
531 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
532 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
533 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
534 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
535
536 VMX_SETUP_SELREG(ES, pCache);
537 VMX_SETUP_SELREG(SS, pCache);
538 VMX_SETUP_SELREG(CS, pCache);
539 VMX_SETUP_SELREG(DS, pCache);
540 VMX_SETUP_SELREG(FS, pCache);
541 VMX_SETUP_SELREG(GS, pCache);
542 VMX_SETUP_SELREG(LDTR, pCache);
543 VMX_SETUP_SELREG(TR, pCache);
544
545 /* Status code VMCS reads. */
546 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
547 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
548 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
549 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
550 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
551 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
552 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
553 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
554 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
555
556 if (pVM->hwaccm.s.fNestedPaging)
557 {
558 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
559 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
560 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
561 }
562 else
563 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
564 } /* for each VMCPU */
565
566 /* Choose the right TLB setup function. */
567 if (pVM->hwaccm.s.fNestedPaging)
568 {
569 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
570
571 /* Default values for flushing. */
572 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
574
575 /* If the capabilities specify we can do more, then make use of it. */
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
577 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
578 else
579 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
580 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
581
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
583 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
584 }
585#ifdef HWACCM_VTX_WITH_VPID
586 else
587 if (pVM->hwaccm.s.vmx.fVPID)
588 {
589 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
590
591 /* Default values for flushing. */
592 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
593 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
594
595 /* If the capabilities specify we can do more, then make use of it. */
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
597 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
598 else
599 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
600 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
601
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
603 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
604 }
605#endif /* HWACCM_VTX_WITH_VPID */
606 else
607 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
608
609vmx_end:
610 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
611 return rc;
612}
613
614
615/**
616 * Injects an event (trap or external interrupt)
617 *
618 * @returns VBox status code.
619 * @param pVM The VM to operate on.
620 * @param pVCpu The VMCPU to operate on.
621 * @param pCtx CPU Context
622 * @param intInfo VMX interrupt info
623 * @param cbInstr Opcode length of faulting instruction
624 * @param errCode Error code (optional)
625 */
626static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
627{
628 int rc;
629 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
630
631#ifdef VBOX_WITH_STATISTICS
632 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
633#endif
634
635#ifdef VBOX_STRICT
636 if (iGate == 0xE)
637 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
638 else
639 if (iGate < 0x20)
640 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
641 else
642 {
643 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
644 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
645 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
646 }
647#endif
648
649#ifdef HWACCM_VMX_EMULATE_REALMODE
650 if (CPUMIsGuestInRealModeEx(pCtx))
651 {
652 RTGCPHYS GCPhysHandler;
653 uint16_t offset, ip;
654 RTSEL sel;
655
656 /* Injecting events doesn't work right with real mode emulation.
657 * (#GP if we try to inject external hardware interrupts)
658 * Inject the interrupt or trap directly instead.
659 *
660 * ASSUMES no access handlers for the bits we read or write below (should be safe).
661 */
662 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
663
664 /* Check if the interrupt handler is present. */
665 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
666 {
667 Log(("IDT cbIdt violation\n"));
668 if (iGate != X86_XCPT_DF)
669 {
670 RTGCUINTPTR intInfo;
671
672 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
673 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
674 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
675 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
676
677 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
678 }
679 Log(("Triple fault -> reset the VM!\n"));
680 return VINF_EM_RESET;
681 }
682 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
683 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
684 || iGate == 4)
685 {
686 ip = pCtx->ip + cbInstr;
687 }
688 else
689 ip = pCtx->ip;
690
691 /* Read the selector:offset pair of the interrupt handler. */
692 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
693 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
694 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
695
696 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
697
698 /* Construct the stack frame. */
699 /** @todo should check stack limit. */
700 pCtx->sp -= 2;
701 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
702 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
703 pCtx->sp -= 2;
704 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
705 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
706 pCtx->sp -= 2;
707 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
708 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
709
710 /* Update the CPU state for executing the handler. */
711 pCtx->rip = offset;
712 pCtx->cs = sel;
713 pCtx->csHid.u64Base = sel << 4;
714 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
715
716 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
717 return VINF_SUCCESS;
718 }
719#endif /* HWACCM_VMX_EMULATE_REALMODE */
720
721 /* Set event injection state. */
722 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
723
724 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
725 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
726
727 AssertRC(rc);
728 return rc;
729}
730
731
732/**
733 * Checks for pending guest interrupts and injects them
734 *
735 * @returns VBox status code.
736 * @param pVM The VM to operate on.
737 * @param pVCpu The VMCPU to operate on.
738 * @param pCtx CPU Context
739 */
740static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
741{
742 int rc;
743
744 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
745 if (pVCpu->hwaccm.s.Event.fPending)
746 {
747 Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
748 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
749 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
750 AssertRC(rc);
751
752 pVCpu->hwaccm.s.Event.fPending = false;
753 return VINF_SUCCESS;
754 }
755
756 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI_BIT))
757 {
758 RTGCUINTPTR intInfo;
759
760 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
761
762 intInfo = X86_XCPT_NMI;
763 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
764 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
765
766 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
767 AssertRC(rc);
768
769 return VINF_SUCCESS;
770 }
771
772 /* @todo SMI interrupts. */
773
774 /* When external interrupts are pending, we should exit the VM when IF is set. */
775 if ( !TRPMHasTrap(pVCpu)
776 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
777 {
778 if (!(pCtx->eflags.u32 & X86_EFL_IF))
779 {
780 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
781 {
782 LogFlow(("Enable irq window exit!\n"));
783 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
784 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
785 AssertRC(rc);
786 }
787 /* else nothing to do but wait */
788 }
789 else
790 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
791 {
792 uint8_t u8Interrupt;
793
794 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
795 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
796 if (RT_SUCCESS(rc))
797 {
798 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
799 AssertRC(rc);
800 }
801 else
802 {
803 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
804 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
805 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
806 /* Just continue */
807 }
808 }
809 else
810 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
811 }
812
813#ifdef VBOX_STRICT
814 if (TRPMHasTrap(pVCpu))
815 {
816 uint8_t u8Vector;
817 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
818 AssertRC(rc);
819 }
820#endif
821
822 if ( (pCtx->eflags.u32 & X86_EFL_IF)
823 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
824 && TRPMHasTrap(pVCpu)
825 )
826 {
827 uint8_t u8Vector;
828 int rc;
829 TRPMEVENT enmType;
830 RTGCUINTPTR intInfo;
831 RTGCUINT errCode;
832
833 /* If a new event is pending, then dispatch it now. */
834 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
835 AssertRC(rc);
836 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
837 Assert(enmType != TRPM_SOFTWARE_INT);
838
839 /* Clear the pending trap. */
840 rc = TRPMResetTrap(pVCpu);
841 AssertRC(rc);
842
843 intInfo = u8Vector;
844 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
845
846 if (enmType == TRPM_TRAP)
847 {
848 switch (u8Vector) {
849 case 8:
850 case 10:
851 case 11:
852 case 12:
853 case 13:
854 case 14:
855 case 17:
856 /* Valid error codes. */
857 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
858 break;
859 default:
860 break;
861 }
862 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
863 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
864 else
865 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
866 }
867 else
868 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
869
870 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
871 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
872 AssertRC(rc);
873 } /* if (interrupts can be dispatched) */
874
875 return VINF_SUCCESS;
876}
877
878/**
879 * Save the host state
880 *
881 * @returns VBox status code.
882 * @param pVM The VM to operate on.
883 * @param pVCpu The VMCPU to operate on.
884 */
885VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
886{
887 int rc = VINF_SUCCESS;
888
889 /*
890 * Host CPU Context
891 */
892 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
893 {
894 RTIDTR idtr;
895 RTGDTR gdtr;
896 RTSEL SelTR;
897 PX86DESCHC pDesc;
898 uintptr_t trBase;
899 RTSEL cs;
900 RTSEL ss;
901 uint64_t cr3;
902
903 /* Control registers */
904 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
905#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
906 if (VMX_IS_64BIT_HOST_MODE())
907 {
908 cr3 = hwaccmR0Get64bitCR3();
909 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
910 }
911 else
912#endif
913 {
914 cr3 = ASMGetCR3();
915 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
916 }
917 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
918 AssertRC(rc);
919 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
920 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
921 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
922
923 /* Selector registers. */
924#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
925 if (VMX_IS_64BIT_HOST_MODE())
926 {
927 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
928 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
929 }
930 else
931 {
932 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
933 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
934 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
935 }
936#else
937 cs = ASMGetCS();
938 ss = ASMGetSS();
939#endif
940 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
941 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
942 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
943 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
944 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
945 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
946#if HC_ARCH_BITS == 32
947 if (!VMX_IS_64BIT_HOST_MODE())
948 {
949 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
950 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
951 }
952#endif
953 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
954 SelTR = ASMGetTR();
955 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
956 AssertRC(rc);
957 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
958 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
959 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
960 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
961 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
962 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
963 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
964
965 /* GDTR & IDTR */
966#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
967 if (VMX_IS_64BIT_HOST_MODE())
968 {
969 X86XDTR64 gdtr64, idtr64;
970 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
971 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
972 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
973 AssertRC(rc);
974 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
975 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
976 gdtr.cbGdt = gdtr64.cb;
977 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
978 }
979 else
980#endif
981 {
982 ASMGetGDTR(&gdtr);
983 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
984 ASMGetIDTR(&idtr);
985 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
986 AssertRC(rc);
987 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
988 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
989 }
990
991
992 /* Save the base address of the TR selector. */
993 if (SelTR > gdtr.cbGdt)
994 {
995 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
996 return VERR_VMX_INVALID_HOST_STATE;
997 }
998
999#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1000 if (VMX_IS_64BIT_HOST_MODE())
1001 {
1002 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
1003 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
1004 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
1005 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
1006 AssertRC(rc);
1007 }
1008 else
1009#endif
1010 {
1011 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
1012#if HC_ARCH_BITS == 64
1013 trBase = X86DESC64_BASE(*pDesc);
1014#else
1015 trBase = X86DESC_BASE(*pDesc);
1016#endif
1017 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
1018 AssertRC(rc);
1019 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
1020 }
1021
1022 /* FS and GS base. */
1023#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1024 if (VMX_IS_64BIT_HOST_MODE())
1025 {
1026 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
1027 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
1028 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
1029 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
1030 }
1031#endif
1032 AssertRC(rc);
1033
1034 /* Sysenter MSRs. */
1035 /** @todo expensive!! */
1036 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1037 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1038#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1039 if (VMX_IS_64BIT_HOST_MODE())
1040 {
1041 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1042 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1043 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1044 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1045 }
1046 else
1047 {
1048 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1049 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1050 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1051 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1052 }
1053#elif HC_ARCH_BITS == 32
1054 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1055 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1056 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1057 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1058#else
1059 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1060 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1061 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1062 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1063#endif
1064 AssertRC(rc);
1065
1066#if 0 /* @todo deal with 32/64 */
1067 /* Restore the host EFER - on CPUs that support it. */
1068 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1069 {
1070 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1071 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1072 AssertRC(rc);
1073 }
1074#endif
1075 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1076 }
1077 return rc;
1078}
1079
1080/**
1081 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1082 *
1083 * @param pVM The VM to operate on.
1084 * @param pVCpu The VMCPU to operate on.
1085 * @param pCtx Guest context
1086 */
1087static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1088{
1089 if (CPUMIsGuestInPAEModeEx(pCtx))
1090 {
1091 X86PDPE Pdpe;
1092
1093 for (unsigned i=0;i<4;i++)
1094 {
1095 Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1096 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1097 AssertRC(rc);
1098 }
1099 }
1100}
1101
1102/**
1103 * Update the exception bitmap according to the current CPU state
1104 *
1105 * @param pVM The VM to operate on.
1106 * @param pVCpu The VMCPU to operate on.
1107 * @param pCtx Guest context
1108 */
1109static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1110{
1111 uint32_t u32TrapMask;
1112 Assert(pCtx);
1113
1114 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1115#ifndef DEBUG
1116 if (pVM->hwaccm.s.fNestedPaging)
1117 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1118#endif
1119
1120 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1121 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1122 && !(pCtx->cr0 & X86_CR0_NE)
1123 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1124 {
1125 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1126 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1127 }
1128
1129#ifdef DEBUG /* till after branching, enable it by default then. */
1130 /* Intercept X86_XCPT_DB if stepping is enabled */
1131 if (DBGFIsStepping(pVCpu))
1132 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1133 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1134 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1135#endif
1136
1137#ifdef VBOX_STRICT
1138 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1139#endif
1140
1141# ifdef HWACCM_VMX_EMULATE_REALMODE
1142 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1143 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1144 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1145# endif /* HWACCM_VMX_EMULATE_REALMODE */
1146
1147 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1148 AssertRC(rc);
1149}
1150
1151/**
1152 * Loads the guest state
1153 *
1154 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1155 *
1156 * @returns VBox status code.
1157 * @param pVM The VM to operate on.
1158 * @param pVCpu The VMCPU to operate on.
1159 * @param pCtx Guest context
1160 */
1161VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1162{
1163 int rc = VINF_SUCCESS;
1164 RTGCUINTPTR val;
1165 X86EFLAGS eflags;
1166
1167 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1168 * Set required bits to one and zero according to the MSR capabilities.
1169 */
1170 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1171 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1172 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1173#if 0 /* @todo deal with 32/64 */
1174 /* Required for the EFER write below, not supported on all CPUs. */
1175 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1176#endif
1177 /* 64 bits guest mode? */
1178 if (CPUMIsGuestInLongModeEx(pCtx))
1179 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1180 /* else Must be zero when AMD64 is not available. */
1181
1182 /* Mask away the bits that the CPU doesn't support */
1183 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1184 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1185 AssertRC(rc);
1186
1187 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1188 * Set required bits to one and zero according to the MSR capabilities.
1189 */
1190 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1191
1192 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1193#if 0 /* @todo deal with 32/64 */
1194 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1195#else
1196 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1197#endif
1198
1199#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1200 if (VMX_IS_64BIT_HOST_MODE())
1201 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1202 /* else: Must be zero when AMD64 is not available. */
1203#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1204 if (CPUMIsGuestInLongModeEx(pCtx))
1205 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1206 else
1207 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1208#endif
1209 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1210 /* Don't acknowledge external interrupts on VM-exit. */
1211 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1212 AssertRC(rc);
1213
1214 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1215 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1216 {
1217#ifdef HWACCM_VMX_EMULATE_REALMODE
1218 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1219 {
1220 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1221 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1222 {
1223 /* Correct weird requirements for switching to protected mode. */
1224 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1225 && enmGuestMode >= PGMMODE_PROTECTED)
1226 {
1227 /* Flush the recompiler code cache as it's not unlikely
1228 * the guest will rewrite code it will later execute in real
1229 * mode (OpenBSD 4.0 is one such example)
1230 */
1231 REMFlushTBs(pVM);
1232
1233 /* DPL of all hidden selector registers must match the current CPL (0). */
1234 pCtx->csHid.Attr.n.u2Dpl = 0;
1235 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1236
1237 pCtx->dsHid.Attr.n.u2Dpl = 0;
1238 pCtx->esHid.Attr.n.u2Dpl = 0;
1239 pCtx->fsHid.Attr.n.u2Dpl = 0;
1240 pCtx->gsHid.Attr.n.u2Dpl = 0;
1241 pCtx->ssHid.Attr.n.u2Dpl = 0;
1242
1243 /* The limit must correspond to the granularity bit. */
1244 if (!pCtx->csHid.Attr.n.u1Granularity)
1245 pCtx->csHid.u32Limit &= 0xffff;
1246 if (!pCtx->dsHid.Attr.n.u1Granularity)
1247 pCtx->dsHid.u32Limit &= 0xffff;
1248 if (!pCtx->esHid.Attr.n.u1Granularity)
1249 pCtx->esHid.u32Limit &= 0xffff;
1250 if (!pCtx->fsHid.Attr.n.u1Granularity)
1251 pCtx->fsHid.u32Limit &= 0xffff;
1252 if (!pCtx->gsHid.Attr.n.u1Granularity)
1253 pCtx->gsHid.u32Limit &= 0xffff;
1254 if (!pCtx->ssHid.Attr.n.u1Granularity)
1255 pCtx->ssHid.u32Limit &= 0xffff;
1256 }
1257 else
1258 /* Switching from protected mode to real mode. */
1259 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1260 && enmGuestMode == PGMMODE_REAL)
1261 {
1262 /* The limit must also be set to 0xffff. */
1263 pCtx->csHid.u32Limit = 0xffff;
1264 pCtx->dsHid.u32Limit = 0xffff;
1265 pCtx->esHid.u32Limit = 0xffff;
1266 pCtx->fsHid.u32Limit = 0xffff;
1267 pCtx->gsHid.u32Limit = 0xffff;
1268 pCtx->ssHid.u32Limit = 0xffff;
1269
1270 Assert(pCtx->csHid.u64Base <= 0xfffff);
1271 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1272 Assert(pCtx->esHid.u64Base <= 0xfffff);
1273 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1274 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1275 }
1276 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1277 }
1278 else
1279 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1280 if ( CPUMIsGuestInRealModeEx(pCtx)
1281 && pCtx->csHid.u64Base == 0xffff0000)
1282 {
1283 pCtx->csHid.u64Base = 0xf0000;
1284 pCtx->cs = 0xf000;
1285 }
1286 }
1287#endif /* HWACCM_VMX_EMULATE_REALMODE */
1288
1289 VMX_WRITE_SELREG(ES, es);
1290 AssertRC(rc);
1291
1292 VMX_WRITE_SELREG(CS, cs);
1293 AssertRC(rc);
1294
1295 VMX_WRITE_SELREG(SS, ss);
1296 AssertRC(rc);
1297
1298 VMX_WRITE_SELREG(DS, ds);
1299 AssertRC(rc);
1300
1301 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1302 VMX_WRITE_SELREG(FS, fs);
1303 AssertRC(rc);
1304
1305 VMX_WRITE_SELREG(GS, gs);
1306 AssertRC(rc);
1307 }
1308
1309 /* Guest CPU context: LDTR. */
1310 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1311 {
1312 if (pCtx->ldtr == 0)
1313 {
1314 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1315 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1316 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1317 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1318 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1319 }
1320 else
1321 {
1322 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1323 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1324 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1325 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1326 }
1327 AssertRC(rc);
1328 }
1329 /* Guest CPU context: TR. */
1330 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1331 {
1332#ifdef HWACCM_VMX_EMULATE_REALMODE
1333 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1334 if (CPUMIsGuestInRealModeEx(pCtx))
1335 {
1336 RTGCPHYS GCPhys;
1337
1338 /* We convert it here every time as pci regions could be reconfigured. */
1339 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1340 AssertRC(rc);
1341
1342 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1343 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1344 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1345
1346 X86DESCATTR attr;
1347
1348 attr.u = 0;
1349 attr.n.u1Present = 1;
1350 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1351 val = attr.u;
1352 }
1353 else
1354#endif /* HWACCM_VMX_EMULATE_REALMODE */
1355 {
1356 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1357 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1358 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1359
1360 val = pCtx->trHid.Attr.u;
1361
1362 /* The TSS selector must be busy. */
1363 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1364 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1365 else
1366 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1367 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1368
1369 }
1370 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1371 AssertRC(rc);
1372 }
1373 /* Guest CPU context: GDTR. */
1374 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1375 {
1376 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1377 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1378 AssertRC(rc);
1379 }
1380 /* Guest CPU context: IDTR. */
1381 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1382 {
1383 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1384 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1385 AssertRC(rc);
1386 }
1387
1388 /*
1389 * Sysenter MSRs (unconditional)
1390 */
1391 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1392 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1393 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1394 AssertRC(rc);
1395
1396 /* Control registers */
1397 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1398 {
1399 val = pCtx->cr0;
1400 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1401 Log2(("Guest CR0-shadow %08x\n", val));
1402 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1403 {
1404 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1405 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1406 }
1407 else
1408 {
1409 /** @todo check if we support the old style mess correctly. */
1410 if (!(val & X86_CR0_NE))
1411 Log(("Forcing X86_CR0_NE!!!\n"));
1412
1413 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1414 }
1415 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1416 val |= X86_CR0_PE | X86_CR0_PG;
1417 if (pVM->hwaccm.s.fNestedPaging)
1418 {
1419 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1420 {
1421 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1422 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1423 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1424 }
1425 else
1426 {
1427 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1428 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1429 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1430 }
1431 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1432 AssertRC(rc);
1433 }
1434 else
1435 {
1436 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1437 val |= X86_CR0_WP;
1438 }
1439
1440 /* Always enable caching. */
1441 val &= ~(X86_CR0_CD|X86_CR0_NW);
1442
1443 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1444 Log2(("Guest CR0 %08x\n", val));
1445 /* CR0 flags owned by the host; if the guests attempts to change them, then
1446 * the VM will exit.
1447 */
1448 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1449 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1450 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1451 | X86_CR0_TS
1452 | X86_CR0_ET /* Bit not restored during VM-exit! */
1453 | X86_CR0_CD /* Bit not restored during VM-exit! */
1454 | X86_CR0_NW /* Bit not restored during VM-exit! */
1455 | X86_CR0_NE
1456 | X86_CR0_MP;
1457 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1458
1459 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1460 Log2(("Guest CR0-mask %08x\n", val));
1461 AssertRC(rc);
1462 }
1463 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1464 {
1465 /* CR4 */
1466 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1467 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1468 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1469 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1470
1471 if (!pVM->hwaccm.s.fNestedPaging)
1472 {
1473 switch(pVCpu->hwaccm.s.enmShadowMode)
1474 {
1475 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1476 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1477 case PGMMODE_32_BIT: /* 32-bit paging. */
1478 val &= ~X86_CR4_PAE;
1479 break;
1480
1481 case PGMMODE_PAE: /* PAE paging. */
1482 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1483 /** @todo use normal 32 bits paging */
1484 val |= X86_CR4_PAE;
1485 break;
1486
1487 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1488 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1489#ifdef VBOX_ENABLE_64_BITS_GUESTS
1490 break;
1491#else
1492 AssertFailed();
1493 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1494#endif
1495 default: /* shut up gcc */
1496 AssertFailed();
1497 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1498 }
1499 }
1500 else
1501 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1502 {
1503 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1504 val |= X86_CR4_PSE;
1505 /* Our identity mapping is a 32 bits page directory. */
1506 val &= ~X86_CR4_PAE;
1507 }
1508
1509 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1510 Log2(("Guest CR4 %08x\n", val));
1511 /* CR4 flags owned by the host; if the guests attempts to change them, then
1512 * the VM will exit.
1513 */
1514 val = 0
1515 | X86_CR4_PAE
1516 | X86_CR4_PGE
1517 | X86_CR4_PSE
1518 | X86_CR4_VMXE;
1519 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1520
1521 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1522 Log2(("Guest CR4-mask %08x\n", val));
1523 AssertRC(rc);
1524 }
1525
1526 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1527 {
1528 if (pVM->hwaccm.s.fNestedPaging)
1529 {
1530 Assert(PGMGetHyperCR3(pVCpu));
1531 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1532
1533 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1534 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1535 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1536 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1537
1538 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1539 AssertRC(rc);
1540
1541 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1542 {
1543 RTGCPHYS GCPhys;
1544
1545 /* We convert it here every time as pci regions could be reconfigured. */
1546 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1547 AssertRC(rc);
1548
1549 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1550 * take care of the translation to host physical addresses.
1551 */
1552 val = GCPhys;
1553 }
1554 else
1555 {
1556 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1557 val = pCtx->cr3;
1558 /* Prefetch the four PDPT entries in PAE mode. */
1559 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1560 }
1561 }
1562 else
1563 {
1564 val = PGMGetHyperCR3(pVCpu);
1565 Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1566 }
1567
1568 /* Save our shadow CR3 register. */
1569 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1570 AssertRC(rc);
1571 }
1572
1573 /* Debug registers. */
1574 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1575 {
1576 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1577 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1578
1579 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1580 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1581 pCtx->dr[7] |= 0x400; /* must be one */
1582
1583 /* Resync DR7 */
1584 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1585 AssertRC(rc);
1586
1587 /* Sync the debug state now if any breakpoint is armed. */
1588 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1589 && !CPUMIsGuestDebugStateActive(pVCpu)
1590 && !DBGFIsStepping(pVCpu))
1591 {
1592 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1593
1594 /* Disable drx move intercepts. */
1595 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1596 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1597 AssertRC(rc);
1598
1599 /* Save the host and load the guest debug state. */
1600 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1601 AssertRC(rc);
1602 }
1603
1604 /* IA32_DEBUGCTL MSR. */
1605 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1606 AssertRC(rc);
1607
1608 /** @todo do we really ever need this? */
1609 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1610 AssertRC(rc);
1611 }
1612
1613 /* EIP, ESP and EFLAGS */
1614 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1615 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1616 AssertRC(rc);
1617
1618 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1619 eflags = pCtx->eflags;
1620 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1621 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1622
1623#ifdef HWACCM_VMX_EMULATE_REALMODE
1624 /* Real mode emulation using v86 mode. */
1625 if (CPUMIsGuestInRealModeEx(pCtx))
1626 {
1627 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1628
1629 eflags.Bits.u1VM = 1;
1630 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1631 }
1632#endif /* HWACCM_VMX_EMULATE_REALMODE */
1633 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1634 AssertRC(rc);
1635
1636 /* TSC offset. */
1637 uint64_t u64TSCOffset;
1638
1639 if (TMCpuTickCanUseRealTSC(pVCpu, &u64TSCOffset))
1640 {
1641 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1642 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1643 AssertRC(rc);
1644
1645 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1646 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1647 AssertRC(rc);
1648 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1649 }
1650 else
1651 {
1652 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1653 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1654 AssertRC(rc);
1655 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1656 }
1657
1658 /* 64 bits guest mode? */
1659 if (CPUMIsGuestInLongModeEx(pCtx))
1660 {
1661#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1662 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1663#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1664 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1665#else
1666# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1667 if (!pVM->hwaccm.s.fAllow64BitGuests)
1668 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1669# endif
1670 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1671#endif
1672 /* Unconditionally update these as wrmsr might have changed them. */
1673 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1674 AssertRC(rc);
1675 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1676 AssertRC(rc);
1677 }
1678 else
1679 {
1680 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1681 }
1682
1683#if 0 /* @todo deal with 32/64 */
1684 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1685 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1686 {
1687 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1688 AssertRC(rc);
1689 }
1690#endif
1691
1692 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1693
1694 /* Done. */
1695 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1696
1697 return rc;
1698}
1699
1700/**
1701 * Syncs back the guest state
1702 *
1703 * @returns VBox status code.
1704 * @param pVM The VM to operate on.
1705 * @param pVCpu The VMCPU to operate on.
1706 * @param pCtx Guest context
1707 */
1708DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1709{
1710 RTGCUINTREG val, valShadow;
1711 RTGCUINTPTR uInterruptState;
1712 int rc;
1713
1714 /* Let's first sync back eip, esp, and eflags. */
1715 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1716 AssertRC(rc);
1717 pCtx->rip = val;
1718 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1719 AssertRC(rc);
1720 pCtx->rsp = val;
1721 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1722 AssertRC(rc);
1723 pCtx->eflags.u32 = val;
1724
1725 /* Take care of instruction fusing (sti, mov ss) */
1726 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1727 uInterruptState = val;
1728 if (uInterruptState != 0)
1729 {
1730 Assert(uInterruptState <= 2); /* only sti & mov ss */
1731 Log(("uInterruptState %x eip=%RGv\n", (uint32_t)uInterruptState, pCtx->rip));
1732 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1733 }
1734 else
1735 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1736
1737 /* Control registers. */
1738 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1739 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1740 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1741 CPUMSetGuestCR0(pVCpu, val);
1742
1743 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1744 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1745 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1746 CPUMSetGuestCR4(pVCpu, val);
1747
1748 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1749 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1750 if ( pVM->hwaccm.s.fNestedPaging
1751 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1752 {
1753 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1754
1755 /* Can be updated behind our back in the nested paging case. */
1756 CPUMSetGuestCR2(pVCpu, pCache->cr2);
1757
1758 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1759
1760 if (val != pCtx->cr3)
1761 {
1762 CPUMSetGuestCR3(pVCpu, val);
1763 PGMUpdateCR3(pVCpu, val);
1764 }
1765 /* Prefetch the four PDPT entries in PAE mode. */
1766 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1767 }
1768
1769 /* Sync back DR7 here. */
1770 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1771 pCtx->dr[7] = val;
1772
1773 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1774 VMX_READ_SELREG(ES, es);
1775 VMX_READ_SELREG(SS, ss);
1776 VMX_READ_SELREG(CS, cs);
1777 VMX_READ_SELREG(DS, ds);
1778 VMX_READ_SELREG(FS, fs);
1779 VMX_READ_SELREG(GS, gs);
1780
1781 /*
1782 * System MSRs
1783 */
1784 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1785 pCtx->SysEnter.cs = val;
1786 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1787 pCtx->SysEnter.eip = val;
1788 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1789 pCtx->SysEnter.esp = val;
1790
1791 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1792 VMX_READ_SELREG(LDTR, ldtr);
1793
1794 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1795 pCtx->gdtr.cbGdt = val;
1796 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1797 pCtx->gdtr.pGdt = val;
1798
1799 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1800 pCtx->idtr.cbIdt = val;
1801 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1802 pCtx->idtr.pIdt = val;
1803
1804#ifdef HWACCM_VMX_EMULATE_REALMODE
1805 /* Real mode emulation using v86 mode. */
1806 if (CPUMIsGuestInRealModeEx(pCtx))
1807 {
1808 /* Hide our emulation flags */
1809 pCtx->eflags.Bits.u1VM = 0;
1810
1811 /* Restore original IOPL setting as we always use 0. */
1812 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1813
1814 /* Force a TR resync every time in case we switch modes. */
1815 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1816 }
1817 else
1818#endif /* HWACCM_VMX_EMULATE_REALMODE */
1819 {
1820 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1821 VMX_READ_SELREG(TR, tr);
1822 }
1823 return VINF_SUCCESS;
1824}
1825
1826/**
1827 * Dummy placeholder
1828 *
1829 * @param pVM The VM to operate on.
1830 * @param pVCpu The VMCPU to operate on.
1831 */
1832static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1833{
1834 NOREF(pVM);
1835 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1836 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1837 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1838 return;
1839}
1840
1841/**
1842 * Setup the tagged TLB for EPT
1843 *
1844 * @returns VBox status code.
1845 * @param pVM The VM to operate on.
1846 * @param pVCpu The VMCPU to operate on.
1847 */
1848static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1849{
1850 PHWACCM_CPUINFO pCpu;
1851
1852 Assert(pVM->hwaccm.s.fNestedPaging);
1853 Assert(!pVM->hwaccm.s.vmx.fVPID);
1854
1855 /* Deal with tagged TLBs if VPID or EPT is supported. */
1856 pCpu = HWACCMR0GetCurrentCpu();
1857 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1858 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1859 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1860 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1861 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1862 {
1863 /* Force a TLB flush on VM entry. */
1864 pVCpu->hwaccm.s.fForceTLBFlush = true;
1865 }
1866 else
1867 Assert(!pCpu->fFlushTLB);
1868
1869 /* Check for tlb shootdown flushes. */
1870 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1871 pVCpu->hwaccm.s.fForceTLBFlush = true;
1872
1873 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1874 pCpu->fFlushTLB = false;
1875
1876 if (pVCpu->hwaccm.s.fForceTLBFlush)
1877 {
1878 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1879 }
1880 else
1881 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1882 {
1883 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1884 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1885
1886 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1887 {
1888 /* aTlbShootdownPages contains physical addresses in this case. */
1889 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1890 }
1891 }
1892 pVCpu->hwaccm.s.TlbShootdown.cPages= 0;
1893 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1894
1895#ifdef VBOX_WITH_STATISTICS
1896 if (pVCpu->hwaccm.s.fForceTLBFlush)
1897 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1898 else
1899 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1900#endif
1901}
1902
1903#ifdef HWACCM_VTX_WITH_VPID
1904/**
1905 * Setup the tagged TLB for VPID
1906 *
1907 * @returns VBox status code.
1908 * @param pVM The VM to operate on.
1909 * @param pVCpu The VMCPU to operate on.
1910 */
1911static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1912{
1913 PHWACCM_CPUINFO pCpu;
1914
1915 Assert(pVM->hwaccm.s.vmx.fVPID);
1916 Assert(!pVM->hwaccm.s.fNestedPaging);
1917
1918 /* Deal with tagged TLBs if VPID or EPT is supported. */
1919 pCpu = HWACCMR0GetCurrentCpu();
1920 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1921 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1922 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1923 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1924 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1925 {
1926 /* Force a TLB flush on VM entry. */
1927 pVCpu->hwaccm.s.fForceTLBFlush = true;
1928 }
1929 else
1930 Assert(!pCpu->fFlushTLB);
1931
1932 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1933
1934 /* Check for tlb shootdown flushes. */
1935 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1936 pVCpu->hwaccm.s.fForceTLBFlush = true;
1937
1938 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1939 if (pVCpu->hwaccm.s.fForceTLBFlush)
1940 {
1941 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1942 || pCpu->fFlushTLB)
1943 {
1944 pCpu->fFlushTLB = false;
1945 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1946 pCpu->cTLBFlushes++;
1947 }
1948 else
1949 {
1950 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1951 pVCpu->hwaccm.s.fForceTLBFlush = false;
1952 }
1953
1954 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1955 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1956 }
1957 else
1958 {
1959 Assert(!pCpu->fFlushTLB);
1960 Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
1961
1962 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1963 {
1964 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1965 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1966 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1967 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1968 }
1969 }
1970 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1971 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1972
1973 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1974 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1975 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1976
1977 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1978 AssertRC(rc);
1979
1980 if (pVCpu->hwaccm.s.fForceTLBFlush)
1981 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1982
1983#ifdef VBOX_WITH_STATISTICS
1984 if (pVCpu->hwaccm.s.fForceTLBFlush)
1985 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1986 else
1987 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1988#endif
1989}
1990#endif /* HWACCM_VTX_WITH_VPID */
1991
1992/**
1993 * Runs guest code in a VT-x VM.
1994 *
1995 * @returns VBox status code.
1996 * @param pVM The VM to operate on.
1997 * @param pVCpu The VMCPU to operate on.
1998 * @param pCtx Guest context
1999 */
2000VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2001{
2002 int rc = VINF_SUCCESS;
2003 RTGCUINTREG val;
2004 RTGCUINTREG exitReason = VMX_EXIT_INVALID;
2005 RTGCUINTREG instrError, cbInstr;
2006 RTGCUINTPTR exitQualification = 0;
2007 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
2008 RTGCUINTPTR errCode, instrInfo;
2009 bool fSetupTPRCaching = false;
2010 uint8_t u8LastTPR = 0;
2011 PHWACCM_CPUINFO pCpu = 0;
2012 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
2013 unsigned cResume = 0;
2014#ifdef VBOX_STRICT
2015 RTCPUID idCpuCheck;
2016#endif
2017#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2018 uint64_t u64LastTime = RTTimeMilliTS();
2019#endif
2020#ifdef VBOX_WITH_STATISTICS
2021 bool fStatEntryStarted = true;
2022 bool fStatExit2Started = false;
2023#endif
2024
2025 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
2026
2027 /* Check if we need to use TPR shadowing. */
2028 if ( CPUMIsGuestInLongModeEx(pCtx)
2029 || ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2030 && pVM->hwaccm.s.fHasIoApic)
2031 )
2032 {
2033 fSetupTPRCaching = true;
2034 }
2035
2036 Log2(("\nE"));
2037
2038 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
2039
2040#ifdef VBOX_STRICT
2041 {
2042 RTCCUINTREG val;
2043
2044 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
2045 AssertRC(rc);
2046 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
2047
2048 /* allowed zero */
2049 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
2050 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
2051
2052 /* allowed one */
2053 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
2054 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
2055
2056 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
2057 AssertRC(rc);
2058 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
2059
2060 /* Must be set according to the MSR, but can be cleared in case of EPT. */
2061 if (pVM->hwaccm.s.fNestedPaging)
2062 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
2063 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2064 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2065
2066 /* allowed zero */
2067 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2068 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2069
2070 /* allowed one */
2071 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2072 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2073
2074 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2075 AssertRC(rc);
2076 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2077
2078 /* allowed zero */
2079 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2080 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2081
2082 /* allowed one */
2083 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2084 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2085
2086 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2087 AssertRC(rc);
2088 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2089
2090 /* allowed zero */
2091 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2092 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2093
2094 /* allowed one */
2095 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2096 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2097 }
2098#endif
2099
2100#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2101 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2102#endif
2103
2104 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2105 */
2106ResumeExecution:
2107 STAM_STATS({
2108 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2109 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2110 });
2111 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2112 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2113 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2114 Assert(!HWACCMR0SuspendPending());
2115
2116 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2117 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
2118 {
2119 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2120 rc = VINF_EM_RAW_INTERRUPT;
2121 goto end;
2122 }
2123
2124 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2125 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2126 {
2127 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2128 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2129 {
2130 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2131 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2132 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2133 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2134 */
2135 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2136 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2137 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2138 AssertRC(rc);
2139 }
2140 }
2141 else
2142 {
2143 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2144 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2145 AssertRC(rc);
2146 }
2147
2148#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2149 if (RT_UNLIKELY(cResume & 0xf) == 0)
2150 {
2151 uint64_t u64CurTime = RTTimeMilliTS();
2152
2153 if (RT_UNLIKELY(u64CurTime > u64LastTime))
2154 {
2155 u64LastTime = u64CurTime;
2156 TMTimerPollVoid(pVM, pVCpu);
2157 }
2158 }
2159#endif
2160
2161 /* Check for pending actions that force us to go back to ring 3. */
2162#ifdef DEBUG
2163 /* Intercept X86_XCPT_DB if stepping is enabled */
2164 if (!DBGFIsStepping(pVCpu))
2165#endif
2166 {
2167 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2168 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2169 {
2170 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2171 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2172 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2173 goto end;
2174 }
2175 }
2176
2177 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2178 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2179 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2180 {
2181 rc = VINF_EM_PENDING_REQUEST;
2182 goto end;
2183 }
2184
2185#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2186 /*
2187 * Exit to ring-3 preemption/work is pending.
2188 *
2189 * Interrupts are disabled before the call to make sure we don't miss any interrupt
2190 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
2191 * further down, but VMXR0CheckPendingInterrupt makes that impossible.)
2192 *
2193 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
2194 * shootdowns rely on this.
2195 */
2196 uOldEFlags = ASMIntDisableFlags();
2197 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2198 {
2199 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
2200 rc = VINF_EM_RAW_INTERRUPT;
2201 goto end;
2202 }
2203 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2204#endif
2205
2206 /* When external interrupts are pending, we should exit the VM when IF is set. */
2207 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2208 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2209 if (RT_FAILURE(rc))
2210 goto end;
2211
2212 /** @todo check timers?? */
2213
2214 /* TPR caching using CR8 is only available in 64 bits mode */
2215 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2216 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2217 /**
2218 * @todo query and update the TPR only when it could have been changed (mmio access & wrmsr (x2apic))
2219 */
2220 if (fSetupTPRCaching)
2221 {
2222 /* TPR caching in CR8 */
2223 bool fPending;
2224
2225 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
2226 AssertRC(rc);
2227 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2228 pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8LastTPR;
2229
2230 /* Two options here:
2231 * - external interrupt pending, but masked by the TPR value.
2232 * -> a CR8 update that lower the current TPR value should cause an exit
2233 * - no pending interrupts
2234 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2235 */
2236 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
2237 AssertRC(rc);
2238 }
2239
2240#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2241 if ( pVM->hwaccm.s.fNestedPaging
2242# ifdef HWACCM_VTX_WITH_VPID
2243 || pVM->hwaccm.s.vmx.fVPID
2244# endif /* HWACCM_VTX_WITH_VPID */
2245 )
2246 {
2247 pCpu = HWACCMR0GetCurrentCpu();
2248 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2249 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2250 {
2251 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2252 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2253 else
2254 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2255 }
2256 if (pCpu->fFlushTLB)
2257 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2258 else
2259 if (pVCpu->hwaccm.s.fForceTLBFlush)
2260 LogFlow(("Manual TLB flush\n"));
2261 }
2262#endif
2263#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2264 PGMDynMapFlushAutoSet(pVCpu);
2265#endif
2266
2267 /*
2268 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2269 * (until the actual world switch)
2270 */
2271#ifdef VBOX_STRICT
2272 idCpuCheck = RTMpCpuId();
2273#endif
2274#ifdef LOG_ENABLED
2275 VMMR0LogFlushDisable(pVCpu);
2276#endif
2277 /* Save the host state first. */
2278 rc = VMXR0SaveHostState(pVM, pVCpu);
2279 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2280 {
2281 VMMR0LogFlushEnable(pVCpu);
2282 goto end;
2283 }
2284 /* Load the guest state */
2285 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2286 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2287 {
2288 VMMR0LogFlushEnable(pVCpu);
2289 goto end;
2290 }
2291
2292#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2293 /* Disable interrupts to make sure a poke will interrupt execution.
2294 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
2295 */
2296 uOldEFlags = ASMIntDisableFlags();
2297 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2298#endif
2299
2300 /* Deal with tagged TLB setup and invalidation. */
2301 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2302
2303 /* Non-register state Guest Context */
2304 /** @todo change me according to cpu state */
2305 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2306 AssertRC(rc);
2307
2308 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2309
2310 /* Manual save and restore:
2311 * - General purpose registers except RIP, RSP
2312 *
2313 * Trashed:
2314 * - CR2 (we don't care)
2315 * - LDTR (reset to 0)
2316 * - DRx (presumably not changed at all)
2317 * - DR7 (reset to 0x400)
2318 * - EFLAGS (reset to RT_BIT(1); not relevant)
2319 *
2320 */
2321
2322
2323 /* All done! Let's start VM execution. */
2324 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2325 Assert(idCpuCheck == RTMpCpuId());
2326
2327#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2328 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2329 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2330#endif
2331
2332 TMNotifyStartOfExecution(pVCpu);
2333 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2334 TMNotifyEndOfExecution(pVCpu);
2335 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2336 Assert(!(ASMGetFlags() & X86_EFL_IF));
2337 ASMSetFlags(uOldEFlags);
2338#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2339 uOldEFlags = ~(RTCCUINTREG)0;
2340#endif
2341
2342 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2343
2344 /* In case we execute a goto ResumeExecution later on. */
2345 pVCpu->hwaccm.s.fResumeVM = true;
2346 pVCpu->hwaccm.s.fForceTLBFlush = false;
2347
2348 /*
2349 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2350 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2351 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2352 */
2353 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2354 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2355
2356 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2357 {
2358 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2359 VMMR0LogFlushEnable(pVCpu);
2360 goto end;
2361 }
2362
2363 /* Success. Query the guest state and figure out what has happened. */
2364
2365 /* Investigate why there was a VM-exit. */
2366 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2367 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2368
2369 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2370 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2371 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2372 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2373 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2374 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2375 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2376 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2377 AssertRC(rc);
2378
2379 /* Sync back the guest state */
2380 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2381 AssertRC(rc);
2382
2383 /* Note! NOW IT'S SAFE FOR LOGGING! */
2384 VMMR0LogFlushEnable(pVCpu);
2385 Log2(("Raw exit reason %08x\n", exitReason));
2386
2387 /* Check if an injected event was interrupted prematurely. */
2388 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2389 AssertRC(rc);
2390 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2391 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2392 /* Ignore 'int xx' as they'll be restarted anyway. */
2393 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2394 /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
2395 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2396 {
2397 Assert(!pVCpu->hwaccm.s.Event.fPending);
2398 pVCpu->hwaccm.s.Event.fPending = true;
2399 /* Error code present? */
2400 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2401 {
2402 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2403 AssertRC(rc);
2404 pVCpu->hwaccm.s.Event.errCode = val;
2405 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2406 }
2407 else
2408 {
2409 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2410 pVCpu->hwaccm.s.Event.errCode = 0;
2411 }
2412 }
2413#ifdef VBOX_STRICT
2414 else
2415 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2416 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2417 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2418 {
2419 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2420 }
2421
2422 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2423 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2424#endif
2425
2426 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2427 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2428 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2429 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2430 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2431
2432 /* Sync back the TPR if it was changed. */
2433 if ( fSetupTPRCaching
2434 && u8LastTPR != pVCpu->hwaccm.s.vmx.pVAPIC[0x80])
2435 {
2436 rc = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);
2437 AssertRC(rc);
2438 }
2439
2440 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2441 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2442
2443 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2444 switch (exitReason)
2445 {
2446 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2447 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2448 {
2449 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2450
2451 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2452 {
2453 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2454 /* External interrupt; leave to allow it to be dispatched again. */
2455 rc = VINF_EM_RAW_INTERRUPT;
2456 break;
2457 }
2458 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2459 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2460 {
2461 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2462 /* External interrupt; leave to allow it to be dispatched again. */
2463 rc = VINF_EM_RAW_INTERRUPT;
2464 break;
2465
2466 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2467 AssertFailed(); /* can't come here; fails the first check. */
2468 break;
2469
2470 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2471 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2472 Assert(vector == 1 || vector == 3 || vector == 4);
2473 /* no break */
2474 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2475 Log2(("Hardware/software interrupt %d\n", vector));
2476 switch (vector)
2477 {
2478 case X86_XCPT_NM:
2479 {
2480 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2481
2482 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2483 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2484 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2485 if (rc == VINF_SUCCESS)
2486 {
2487 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2488
2489 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2490
2491 /* Continue execution. */
2492 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2493
2494 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2495 goto ResumeExecution;
2496 }
2497
2498 Log(("Forward #NM fault to the guest\n"));
2499 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2500 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2501 AssertRC(rc);
2502 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2503 goto ResumeExecution;
2504 }
2505
2506 case X86_XCPT_PF: /* Page fault */
2507 {
2508#ifdef DEBUG
2509 if (pVM->hwaccm.s.fNestedPaging)
2510 { /* A genuine pagefault.
2511 * Forward the trap to the guest by injecting the exception and resuming execution.
2512 */
2513 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2514
2515 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2516
2517 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2518
2519 /* Now we must update CR2. */
2520 pCtx->cr2 = exitQualification;
2521 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2522 AssertRC(rc);
2523
2524 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2525 goto ResumeExecution;
2526 }
2527#endif
2528 Assert(!pVM->hwaccm.s.fNestedPaging);
2529
2530 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2531 /* Exit qualification contains the linear address of the page fault. */
2532 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2533 TRPMSetErrorCode(pVCpu, errCode);
2534 TRPMSetFaultAddress(pVCpu, exitQualification);
2535
2536 /* Shortcut for APIC TPR reads and writes. */
2537 if ( (exitQualification & 0xfff) == 0x080
2538 && !(errCode & X86_TRAP_PF_P) /* not present */
2539 && fSetupTPRCaching
2540 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
2541 {
2542 RTGCPHYS GCPhysApicBase, GCPhys;
2543 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
2544 GCPhysApicBase &= PAGE_BASE_GC_MASK;
2545
2546 rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
2547 if ( rc == VINF_SUCCESS
2548 && GCPhys == GCPhysApicBase)
2549 {
2550 Log(("Enable VT-x virtual APIC access filtering\n"));
2551 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
2552 AssertRC(rc);
2553 }
2554 }
2555
2556 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2557 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2558 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2559 if (rc == VINF_SUCCESS)
2560 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2561 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2562 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2563
2564 TRPMResetTrap(pVCpu);
2565
2566 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2567 goto ResumeExecution;
2568 }
2569 else
2570 if (rc == VINF_EM_RAW_GUEST_TRAP)
2571 { /* A genuine pagefault.
2572 * Forward the trap to the guest by injecting the exception and resuming execution.
2573 */
2574 Log2(("Forward page fault to the guest\n"));
2575
2576 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2577 /* The error code might have been changed. */
2578 errCode = TRPMGetErrorCode(pVCpu);
2579
2580 TRPMResetTrap(pVCpu);
2581
2582 /* Now we must update CR2. */
2583 pCtx->cr2 = exitQualification;
2584 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2585 AssertRC(rc);
2586
2587 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2588 goto ResumeExecution;
2589 }
2590#ifdef VBOX_STRICT
2591 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2592 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2593#endif
2594 /* Need to go back to the recompiler to emulate the instruction. */
2595 TRPMResetTrap(pVCpu);
2596 break;
2597 }
2598
2599 case X86_XCPT_MF: /* Floating point exception. */
2600 {
2601 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2602 if (!(pCtx->cr0 & X86_CR0_NE))
2603 {
2604 /* old style FPU error reporting needs some extra work. */
2605 /** @todo don't fall back to the recompiler, but do it manually. */
2606 rc = VINF_EM_RAW_EMULATE_INSTR;
2607 break;
2608 }
2609 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2610 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2611 AssertRC(rc);
2612
2613 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2614 goto ResumeExecution;
2615 }
2616
2617 case X86_XCPT_DB: /* Debug exception. */
2618 {
2619 uint64_t uDR6;
2620
2621 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2622 *
2623 * Exit qualification bits:
2624 * 3:0 B0-B3 which breakpoint condition was met
2625 * 12:4 Reserved (0)
2626 * 13 BD - debug register access detected
2627 * 14 BS - single step execution or branch taken
2628 * 63:15 Reserved (0)
2629 */
2630 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2631
2632 /* Note that we don't support guest and host-initiated debugging at the same time. */
2633 Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx));
2634
2635 uDR6 = X86_DR6_INIT_VAL;
2636 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2637 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
2638 if (rc == VINF_EM_RAW_GUEST_TRAP)
2639 {
2640 /** @todo this isn't working, but we'll never get here normally. */
2641
2642 /* Update DR6 here. */
2643 pCtx->dr[6] = uDR6;
2644
2645 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2646 pCtx->dr[7] &= ~X86_DR7_GD;
2647
2648 /* Paranoia. */
2649 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2650 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2651 pCtx->dr[7] |= 0x400; /* must be one */
2652
2653 /* Resync DR7 */
2654 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2655 AssertRC(rc);
2656
2657 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2658 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2659 AssertRC(rc);
2660
2661 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2662 goto ResumeExecution;
2663 }
2664 /* Return to ring 3 to deal with the debug exit code. */
2665 break;
2666 }
2667
2668 case X86_XCPT_BP: /* Breakpoint. */
2669 {
2670 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2671 if (rc == VINF_EM_RAW_GUEST_TRAP)
2672 {
2673 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2674 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2675 AssertRC(rc);
2676 goto ResumeExecution;
2677 }
2678 if (rc == VINF_SUCCESS)
2679 goto ResumeExecution;
2680 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2681 break;
2682 }
2683
2684 case X86_XCPT_GP: /* General protection failure exception.*/
2685 {
2686 uint32_t cbOp;
2687 uint32_t cbSize;
2688 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2689
2690 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2691#ifdef VBOX_STRICT
2692 if (!CPUMIsGuestInRealModeEx(pCtx))
2693 {
2694 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2695 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2696 AssertRC(rc);
2697 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2698 goto ResumeExecution;
2699 }
2700#endif
2701 Assert(CPUMIsGuestInRealModeEx(pCtx));
2702
2703 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2704
2705 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2706 if (RT_SUCCESS(rc))
2707 {
2708 bool fUpdateRIP = true;
2709
2710 Assert(cbOp == pDis->opsize);
2711 switch (pDis->pCurInstr->opcode)
2712 {
2713 case OP_CLI:
2714 pCtx->eflags.Bits.u1IF = 0;
2715 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2716 break;
2717
2718 case OP_STI:
2719 pCtx->eflags.Bits.u1IF = 1;
2720 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2721 break;
2722
2723 case OP_HLT:
2724 fUpdateRIP = false;
2725 rc = VINF_EM_HALT;
2726 pCtx->rip += pDis->opsize;
2727 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2728 break;
2729
2730 case OP_POPF:
2731 {
2732 RTGCPTR GCPtrStack;
2733 uint32_t cbParm;
2734 uint32_t uMask;
2735 X86EFLAGS eflags;
2736
2737 if (pDis->prefix & PREFIX_OPSIZE)
2738 {
2739 cbParm = 4;
2740 uMask = 0xffffffff;
2741 }
2742 else
2743 {
2744 cbParm = 2;
2745 uMask = 0xffff;
2746 }
2747
2748 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2749 if (RT_FAILURE(rc))
2750 {
2751 rc = VERR_EM_INTERPRETER;
2752 break;
2753 }
2754 eflags.u = 0;
2755 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2756 if (RT_FAILURE(rc))
2757 {
2758 rc = VERR_EM_INTERPRETER;
2759 break;
2760 }
2761 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2762 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
2763 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
2764 pCtx->eflags.Bits.u1RF = 0;
2765 pCtx->esp += cbParm;
2766 pCtx->esp &= uMask;
2767
2768 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2769 break;
2770 }
2771
2772 case OP_PUSHF:
2773 {
2774 RTGCPTR GCPtrStack;
2775 uint32_t cbParm;
2776 uint32_t uMask;
2777 X86EFLAGS eflags;
2778
2779 if (pDis->prefix & PREFIX_OPSIZE)
2780 {
2781 cbParm = 4;
2782 uMask = 0xffffffff;
2783 }
2784 else
2785 {
2786 cbParm = 2;
2787 uMask = 0xffff;
2788 }
2789
2790 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2791 if (RT_FAILURE(rc))
2792 {
2793 rc = VERR_EM_INTERPRETER;
2794 break;
2795 }
2796 eflags = pCtx->eflags;
2797 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2798 eflags.Bits.u1RF = 0;
2799 eflags.Bits.u1VM = 0;
2800
2801 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2802 if (RT_FAILURE(rc))
2803 {
2804 rc = VERR_EM_INTERPRETER;
2805 break;
2806 }
2807 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2808 pCtx->esp -= cbParm;
2809 pCtx->esp &= uMask;
2810 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2811 break;
2812 }
2813
2814 case OP_IRET:
2815 {
2816 RTGCPTR GCPtrStack;
2817 uint32_t uMask = 0xffff;
2818 uint16_t aIretFrame[3];
2819
2820 if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
2821 {
2822 rc = VERR_EM_INTERPRETER;
2823 break;
2824 }
2825
2826 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2827 if (RT_FAILURE(rc))
2828 {
2829 rc = VERR_EM_INTERPRETER;
2830 break;
2831 }
2832 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2833 if (RT_FAILURE(rc))
2834 {
2835 rc = VERR_EM_INTERPRETER;
2836 break;
2837 }
2838 pCtx->ip = aIretFrame[0];
2839 pCtx->cs = aIretFrame[1];
2840 pCtx->csHid.u64Base = pCtx->cs << 4;
2841 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2842 pCtx->sp += sizeof(aIretFrame);
2843
2844 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2845 fUpdateRIP = false;
2846 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2847 break;
2848 }
2849
2850 case OP_INT:
2851 {
2852 RTGCUINTPTR intInfo;
2853
2854 LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
2855 intInfo = pDis->param1.parval & 0xff;
2856 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2857 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2858
2859 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2860 AssertRC(rc);
2861 fUpdateRIP = false;
2862 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2863 break;
2864 }
2865
2866 case OP_INTO:
2867 {
2868 if (pCtx->eflags.Bits.u1OF)
2869 {
2870 RTGCUINTPTR intInfo;
2871
2872 LogFlow(("Realmode: INTO\n"));
2873 intInfo = X86_XCPT_OF;
2874 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2875 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2876
2877 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2878 AssertRC(rc);
2879 fUpdateRIP = false;
2880 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2881 }
2882 break;
2883 }
2884
2885 case OP_INT3:
2886 {
2887 RTGCUINTPTR intInfo;
2888
2889 LogFlow(("Realmode: INT 3\n"));
2890 intInfo = 3;
2891 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2892 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2893
2894 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2895 AssertRC(rc);
2896 fUpdateRIP = false;
2897 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2898 break;
2899 }
2900
2901 default:
2902 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
2903 break;
2904 }
2905
2906 if (rc == VINF_SUCCESS)
2907 {
2908 if (fUpdateRIP)
2909 pCtx->rip += cbOp; /* Move on to the next instruction. */
2910
2911 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2912 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2913
2914 /* Only resume if successful. */
2915 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2916 goto ResumeExecution;
2917 }
2918 }
2919 else
2920 rc = VERR_EM_INTERPRETER;
2921
2922 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2923 break;
2924 }
2925
2926#ifdef VBOX_STRICT
2927 case X86_XCPT_DE: /* Divide error. */
2928 case X86_XCPT_UD: /* Unknown opcode exception. */
2929 case X86_XCPT_SS: /* Stack segment exception. */
2930 case X86_XCPT_NP: /* Segment not present exception. */
2931 {
2932 switch(vector)
2933 {
2934 case X86_XCPT_DE:
2935 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2936 break;
2937 case X86_XCPT_UD:
2938 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2939 break;
2940 case X86_XCPT_SS:
2941 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2942 break;
2943 case X86_XCPT_NP:
2944 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2945 break;
2946 }
2947
2948 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2949 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2950 AssertRC(rc);
2951
2952 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2953 goto ResumeExecution;
2954 }
2955#endif
2956 default:
2957#ifdef HWACCM_VMX_EMULATE_REALMODE
2958 if (CPUMIsGuestInRealModeEx(pCtx))
2959 {
2960 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2961 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2962 AssertRC(rc);
2963
2964 /* Go back to ring 3 in case of a triple fault. */
2965 if ( vector == X86_XCPT_DF
2966 && rc == VINF_EM_RESET)
2967 break;
2968
2969 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2970 goto ResumeExecution;
2971 }
2972#endif
2973 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2974 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2975 break;
2976 } /* switch (vector) */
2977
2978 break;
2979
2980 default:
2981 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2982 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2983 break;
2984 }
2985
2986 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2987 break;
2988 }
2989
2990 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2991 {
2992 RTGCPHYS GCPhys;
2993
2994 Assert(pVM->hwaccm.s.fNestedPaging);
2995
2996 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2997 AssertRC(rc);
2998 Assert(((exitQualification >> 7) & 3) != 2);
2999
3000 /* Determine the kind of violation. */
3001 errCode = 0;
3002 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
3003 errCode |= X86_TRAP_PF_ID;
3004
3005 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
3006 errCode |= X86_TRAP_PF_RW;
3007
3008 /* If the page is present, then it's a page level protection fault. */
3009 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
3010 {
3011 errCode |= X86_TRAP_PF_P;
3012 }
3013 else {
3014 /* Shortcut for APIC TPR reads and writes. */
3015 if ( (GCPhys & 0xfff) == 0x080
3016 && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
3017 && fSetupTPRCaching
3018 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
3019 {
3020 RTGCPHYS GCPhysApicBase;
3021 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
3022 GCPhysApicBase &= PAGE_BASE_GC_MASK;
3023 if (GCPhys == GCPhysApicBase + 0x80)
3024 {
3025 Log(("Enable VT-x virtual APIC access filtering\n"));
3026 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
3027 AssertRC(rc);
3028 }
3029 }
3030 }
3031 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
3032
3033 /* GCPhys contains the guest physical address of the page fault. */
3034 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
3035 TRPMSetErrorCode(pVCpu, errCode);
3036 TRPMSetFaultAddress(pVCpu, GCPhys);
3037
3038 /* Handle the pagefault trap for the nested shadow table. */
3039 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
3040 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
3041 if (rc == VINF_SUCCESS)
3042 { /* We've successfully synced our shadow pages, so let's just continue execution. */
3043 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
3044 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
3045
3046 TRPMResetTrap(pVCpu);
3047
3048 goto ResumeExecution;
3049 }
3050
3051#ifdef VBOX_STRICT
3052 if (rc != VINF_EM_RAW_EMULATE_INSTR)
3053 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
3054#endif
3055 /* Need to go back to the recompiler to emulate the instruction. */
3056 TRPMResetTrap(pVCpu);
3057 break;
3058 }
3059
3060 case VMX_EXIT_EPT_MISCONFIG:
3061 {
3062 RTGCPHYS GCPhys;
3063
3064 Assert(pVM->hwaccm.s.fNestedPaging);
3065
3066 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3067 AssertRC(rc);
3068
3069 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
3070 break;
3071 }
3072
3073 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3074 /* Clear VM-exit on IF=1 change. */
3075 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
3076 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
3077 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3078 AssertRC(rc);
3079 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
3080 goto ResumeExecution; /* we check for pending guest interrupts there */
3081
3082 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
3083 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
3084 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
3085 /* Skip instruction and continue directly. */
3086 pCtx->rip += cbInstr;
3087 /* Continue execution.*/
3088 goto ResumeExecution;
3089
3090 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3091 {
3092 Log2(("VMX: Cpuid %x\n", pCtx->eax));
3093 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
3094 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3095 if (rc == VINF_SUCCESS)
3096 {
3097 /* Update EIP and continue execution. */
3098 Assert(cbInstr == 2);
3099 pCtx->rip += cbInstr;
3100 goto ResumeExecution;
3101 }
3102 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
3103 rc = VINF_EM_RAW_EMULATE_INSTR;
3104 break;
3105 }
3106
3107 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3108 {
3109 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
3110 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
3111 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3112 if (rc == VINF_SUCCESS)
3113 {
3114 /* Update EIP and continue execution. */
3115 Assert(cbInstr == 2);
3116 pCtx->rip += cbInstr;
3117 goto ResumeExecution;
3118 }
3119 rc = VINF_EM_RAW_EMULATE_INSTR;
3120 break;
3121 }
3122
3123 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3124 {
3125 Log2(("VMX: Rdtsc\n"));
3126 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
3127 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3128 if (rc == VINF_SUCCESS)
3129 {
3130 /* Update EIP and continue execution. */
3131 Assert(cbInstr == 2);
3132 pCtx->rip += cbInstr;
3133 goto ResumeExecution;
3134 }
3135 rc = VINF_EM_RAW_EMULATE_INSTR;
3136 break;
3137 }
3138
3139 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3140 {
3141 Log2(("VMX: invlpg\n"));
3142 Assert(!pVM->hwaccm.s.fNestedPaging);
3143
3144 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
3145 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
3146 if (rc == VINF_SUCCESS)
3147 {
3148 /* Update EIP and continue execution. */
3149 pCtx->rip += cbInstr;
3150 goto ResumeExecution;
3151 }
3152 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
3153 break;
3154 }
3155
3156 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3157 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3158 {
3159 uint32_t cbSize;
3160
3161 STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
3162
3163 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3164 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3165 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3166 if (rc == VINF_SUCCESS)
3167 {
3168 /* EIP has been updated already. */
3169
3170 /* Only resume if successful. */
3171 goto ResumeExecution;
3172 }
3173 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
3174 break;
3175 }
3176
3177 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3178 {
3179 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3180
3181 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3182 {
3183 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3184 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3185 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3186 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3187 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3188 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3189
3190 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3191 {
3192 case 0:
3193 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3194 break;
3195 case 2:
3196 break;
3197 case 3:
3198 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3199 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3200 break;
3201 case 4:
3202 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3203 break;
3204 case 8:
3205 /* CR8 contains the APIC TPR */
3206 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3207 break;
3208
3209 default:
3210 AssertFailed();
3211 break;
3212 }
3213 /* Check if a sync operation is pending. */
3214 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3215 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3216 {
3217 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3218 AssertRC(rc);
3219 }
3220 break;
3221
3222 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3223 Log2(("VMX: mov x, crx\n"));
3224 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3225
3226 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3227
3228 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3229 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3230
3231 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3232 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3233 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3234 break;
3235
3236 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3237 Log2(("VMX: clts\n"));
3238 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3239 rc = EMInterpretCLTS(pVM, pVCpu);
3240 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3241 break;
3242
3243 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3244 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3245 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3246 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3247 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3248 break;
3249 }
3250
3251 /* Update EIP if no error occurred. */
3252 if (RT_SUCCESS(rc))
3253 pCtx->rip += cbInstr;
3254
3255 if (rc == VINF_SUCCESS)
3256 {
3257 /* Only resume if successful. */
3258 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3259 goto ResumeExecution;
3260 }
3261 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3262 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3263 break;
3264 }
3265
3266 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3267 {
3268 if (!DBGFIsStepping(pVCpu))
3269 {
3270 /* Disable drx move intercepts. */
3271 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3272 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3273 AssertRC(rc);
3274
3275 /* Save the host and load the guest debug state. */
3276 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3277 AssertRC(rc);
3278
3279#ifdef VBOX_WITH_STATISTICS
3280 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3281 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3282 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3283 else
3284 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3285#endif
3286
3287 goto ResumeExecution;
3288 }
3289
3290 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3291 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3292 {
3293 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3294 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3295 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3296 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3297 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3298 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3299 Log2(("DR7=%08x\n", pCtx->dr[7]));
3300 }
3301 else
3302 {
3303 Log2(("VMX: mov x, drx\n"));
3304 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3305 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3306 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3307 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3308 }
3309 /* Update EIP if no error occurred. */
3310 if (RT_SUCCESS(rc))
3311 pCtx->rip += cbInstr;
3312
3313 if (rc == VINF_SUCCESS)
3314 {
3315 /* Only resume if successful. */
3316 goto ResumeExecution;
3317 }
3318 Assert(rc == VERR_EM_INTERPRETER);
3319 break;
3320 }
3321
3322 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3323 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3324 {
3325 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3326 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3327 uint32_t uPort;
3328 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3329
3330 /** @todo necessary to make the distinction? */
3331 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3332 {
3333 uPort = pCtx->edx & 0xffff;
3334 }
3335 else
3336 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3337
3338 /* paranoia */
3339 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3340 {
3341 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3342 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3343 break;
3344 }
3345
3346 uint32_t cbSize = g_aIOSize[uIOWidth];
3347
3348 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3349 {
3350 /* ins/outs */
3351 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
3352
3353 /* Disassemble manually to deal with segment prefixes. */
3354 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3355 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3356 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
3357 if (rc == VINF_SUCCESS)
3358 {
3359 if (fIOWrite)
3360 {
3361 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3362 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3363 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3364 }
3365 else
3366 {
3367 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3368 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3369 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3370 }
3371 }
3372 else
3373 rc = VINF_EM_RAW_EMULATE_INSTR;
3374 }
3375 else
3376 {
3377 /* normal in/out */
3378 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3379
3380 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3381
3382 if (fIOWrite)
3383 {
3384 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3385 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3386 }
3387 else
3388 {
3389 uint32_t u32Val = 0;
3390
3391 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3392 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3393 if (IOM_SUCCESS(rc))
3394 {
3395 /* Write back to the EAX register. */
3396 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3397 }
3398 }
3399 }
3400 /*
3401 * Handled the I/O return codes.
3402 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3403 */
3404 if (IOM_SUCCESS(rc))
3405 {
3406 /* Update EIP and continue execution. */
3407 pCtx->rip += cbInstr;
3408 if (RT_LIKELY(rc == VINF_SUCCESS))
3409 {
3410 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3411 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3412 {
3413 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3414 for (unsigned i=0;i<4;i++)
3415 {
3416 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3417
3418 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3419 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3420 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3421 {
3422 uint64_t uDR6;
3423
3424 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3425
3426 uDR6 = ASMGetDR6();
3427
3428 /* Clear all breakpoint status flags and set the one we just hit. */
3429 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3430 uDR6 |= (uint64_t)RT_BIT(i);
3431
3432 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3433 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3434 * the contents have been read.
3435 */
3436 ASMSetDR6(uDR6);
3437
3438 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3439 pCtx->dr[7] &= ~X86_DR7_GD;
3440
3441 /* Paranoia. */
3442 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3443 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3444 pCtx->dr[7] |= 0x400; /* must be one */
3445
3446 /* Resync DR7 */
3447 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3448 AssertRC(rc);
3449
3450 /* Construct inject info. */
3451 intInfo = X86_XCPT_DB;
3452 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3453 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3454
3455 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3456 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3457 AssertRC(rc);
3458
3459 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3460 goto ResumeExecution;
3461 }
3462 }
3463 }
3464
3465 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3466 goto ResumeExecution;
3467 }
3468 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3469 break;
3470 }
3471
3472#ifdef VBOX_STRICT
3473 if (rc == VINF_IOM_HC_IOPORT_READ)
3474 Assert(!fIOWrite);
3475 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3476 Assert(fIOWrite);
3477 else
3478 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3479#endif
3480 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3481 break;
3482 }
3483
3484 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3485 LogFlow(("VMX_EXIT_TPR\n"));
3486 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3487 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3488 goto ResumeExecution;
3489
3490 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3491 {
3492 LogFlow(("VMX_EXIT_APIC_ACCESS\n"));
3493 unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
3494
3495 switch(uAccessType)
3496 {
3497 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
3498 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
3499 {
3500 RTGCPHYS GCPhys;
3501 PDMApicGetBase(pVM, &GCPhys);
3502 GCPhys &= PAGE_BASE_GC_MASK;
3503 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
3504
3505 LogFlow(("Apic access at %RGp\n", GCPhys));
3506 rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
3507 if (rc == VINF_SUCCESS)
3508 {
3509 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3510 goto ResumeExecution; /* rip already updated */
3511 }
3512 break;
3513 }
3514
3515 default:
3516 rc = VINF_EM_RAW_EMULATE_INSTR;
3517 break;
3518 }
3519 break;
3520 }
3521
3522 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3523 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3524 goto ResumeExecution;
3525
3526 default:
3527 /* The rest is handled after syncing the entire CPU state. */
3528 break;
3529 }
3530
3531 /* Note: the guest state isn't entirely synced back at this stage. */
3532
3533 /* Investigate why there was a VM-exit. (part 2) */
3534 switch (exitReason)
3535 {
3536 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3537 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3538 case VMX_EXIT_EPT_VIOLATION:
3539 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3540 /* Already handled above. */
3541 break;
3542
3543 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3544 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3545 break;
3546
3547 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3548 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3549 rc = VINF_EM_RAW_INTERRUPT;
3550 AssertFailed(); /* Can't happen. Yet. */
3551 break;
3552
3553 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3554 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3555 rc = VINF_EM_RAW_INTERRUPT;
3556 AssertFailed(); /* Can't happen afaik. */
3557 break;
3558
3559 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3560 rc = VERR_EM_INTERPRETER;
3561 break;
3562
3563 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3564 /** Check if external interrupts are pending; if so, don't switch back. */
3565 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
3566 pCtx->rip++; /* skip hlt */
3567 if ( pCtx->eflags.Bits.u1IF
3568 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3569 goto ResumeExecution;
3570
3571 rc = VINF_EM_HALT;
3572 break;
3573
3574 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3575 Log2(("VMX: mwait\n"));
3576 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
3577 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3578 if ( rc == VINF_EM_HALT
3579 || rc == VINF_SUCCESS)
3580 {
3581 /* Update EIP and continue execution. */
3582 pCtx->rip += cbInstr;
3583
3584 /** Check if external interrupts are pending; if so, don't switch back. */
3585 if ( rc == VINF_SUCCESS
3586 || ( rc == VINF_EM_HALT
3587 && pCtx->eflags.Bits.u1IF
3588 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3589 )
3590 goto ResumeExecution;
3591 }
3592 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
3593 break;
3594
3595 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3596 AssertFailed(); /* can't happen. */
3597 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3598 break;
3599
3600 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3601 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3602 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3603 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3604 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3605 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3606 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3607 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3608 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3609 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3610 /** @todo inject #UD immediately */
3611 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3612 break;
3613
3614 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3615 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3616 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3617 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3618 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3619 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3620 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3621 /* already handled above */
3622 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3623 || rc == VINF_EM_RAW_INTERRUPT
3624 || rc == VERR_EM_INTERPRETER
3625 || rc == VINF_EM_RAW_EMULATE_INSTR
3626 || rc == VINF_PGM_SYNC_CR3
3627 || rc == VINF_IOM_HC_IOPORT_READ
3628 || rc == VINF_IOM_HC_IOPORT_WRITE
3629 || rc == VINF_EM_RAW_GUEST_TRAP
3630 || rc == VINF_TRPM_XCPT_DISPATCHED
3631 || rc == VINF_EM_RESCHEDULE_REM,
3632 ("rc = %d\n", rc));
3633 break;
3634
3635 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3636 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3637 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3638 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3639 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3640 rc = VERR_EM_INTERPRETER;
3641 break;
3642
3643 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3644 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3645 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3646 break;
3647
3648 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3649 Assert(rc == VINF_EM_RAW_INTERRUPT);
3650 break;
3651
3652 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3653 {
3654#ifdef VBOX_STRICT
3655 RTCCUINTREG val = 0;
3656
3657 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3658
3659 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3660 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3661
3662 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3663 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3664
3665 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3666 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3667
3668 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3669 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3670
3671 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3672 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3673
3674 VMX_LOG_SELREG(CS, "CS");
3675 VMX_LOG_SELREG(DS, "DS");
3676 VMX_LOG_SELREG(ES, "ES");
3677 VMX_LOG_SELREG(FS, "FS");
3678 VMX_LOG_SELREG(GS, "GS");
3679 VMX_LOG_SELREG(SS, "SS");
3680 VMX_LOG_SELREG(TR, "TR");
3681 VMX_LOG_SELREG(LDTR, "LDTR");
3682
3683 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3684 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3685 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3686 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3687#endif /* VBOX_STRICT */
3688 rc = VERR_VMX_INVALID_GUEST_STATE;
3689 break;
3690 }
3691
3692 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3693 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3694 default:
3695 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3696 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3697 break;
3698
3699 }
3700end:
3701
3702 /* Signal changes for the recompiler. */
3703 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3704
3705 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3706 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3707 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3708 {
3709 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3710 /* On the next entry we'll only sync the host context. */
3711 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3712 }
3713 else
3714 {
3715 /* On the next entry we'll sync everything. */
3716 /** @todo we can do better than this */
3717 /* Not in the VINF_PGM_CHANGE_MODE though! */
3718 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3719 }
3720
3721 /* translate into a less severe return code */
3722 if (rc == VERR_EM_INTERPRETER)
3723 rc = VINF_EM_RAW_EMULATE_INSTR;
3724 else
3725 /* Try to extract more information about what might have gone wrong here. */
3726 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3727 {
3728 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3729 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3730 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3731 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3732 }
3733
3734 /* Just set the correct state here instead of trying to catch every goto above. */
3735 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
3736
3737#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
3738 /* Restore interrupts if we exitted after disabling them. */
3739 if (uOldEFlags != ~(RTCCUINTREG)0)
3740 ASMSetFlags(uOldEFlags);
3741#endif
3742
3743 STAM_STATS({
3744 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3745 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3746 });
3747 Log2(("X"));
3748 return rc;
3749}
3750
3751
3752/**
3753 * Enters the VT-x session
3754 *
3755 * @returns VBox status code.
3756 * @param pVM The VM to operate on.
3757 * @param pVCpu The VMCPU to operate on.
3758 * @param pCpu CPU info struct
3759 */
3760VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3761{
3762 Assert(pVM->hwaccm.s.vmx.fSupported);
3763
3764 unsigned cr4 = ASMGetCR4();
3765 if (!(cr4 & X86_CR4_VMXE))
3766 {
3767 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3768 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3769 }
3770
3771 /* Activate the VM Control Structure. */
3772 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3773 if (RT_FAILURE(rc))
3774 return rc;
3775
3776 pVCpu->hwaccm.s.fResumeVM = false;
3777 return VINF_SUCCESS;
3778}
3779
3780
3781/**
3782 * Leaves the VT-x session
3783 *
3784 * @returns VBox status code.
3785 * @param pVM The VM to operate on.
3786 * @param pVCpu The VMCPU to operate on.
3787 * @param pCtx CPU context
3788 */
3789VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3790{
3791 Assert(pVM->hwaccm.s.vmx.fSupported);
3792
3793 /* Save the guest debug state if necessary. */
3794 if (CPUMIsGuestDebugStateActive(pVCpu))
3795 {
3796 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3797
3798 /* Enable drx move intercepts again. */
3799 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3800 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3801 AssertRC(rc);
3802
3803 /* Resync the debug registers the next time. */
3804 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3805 }
3806 else
3807 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3808
3809 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3810 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3811 AssertRC(rc);
3812
3813 return VINF_SUCCESS;
3814}
3815
3816/**
3817 * Flush the TLB (EPT)
3818 *
3819 * @returns VBox status code.
3820 * @param pVM The VM to operate on.
3821 * @param pVCpu The VM CPU to operate on.
3822 * @param enmFlush Type of flush
3823 * @param GCPhys Physical address of the page to flush
3824 */
3825static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3826{
3827 uint64_t descriptor[2];
3828
3829 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3830 Assert(pVM->hwaccm.s.fNestedPaging);
3831 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3832 descriptor[1] = GCPhys;
3833 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3834 AssertRC(rc);
3835}
3836
3837#ifdef HWACCM_VTX_WITH_VPID
3838/**
3839 * Flush the TLB (EPT)
3840 *
3841 * @returns VBox status code.
3842 * @param pVM The VM to operate on.
3843 * @param pVCpu The VM CPU to operate on.
3844 * @param enmFlush Type of flush
3845 * @param GCPtr Virtual address of the page to flush
3846 */
3847static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3848{
3849#if HC_ARCH_BITS == 32
3850 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3851 if ( CPUMIsGuestInLongMode(pVCpu)
3852 && !VMX_IS_64BIT_HOST_MODE())
3853 {
3854 pVCpu->hwaccm.s.fForceTLBFlush = true;
3855 }
3856 else
3857#endif
3858 {
3859 uint64_t descriptor[2];
3860
3861 Assert(pVM->hwaccm.s.vmx.fVPID);
3862 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3863 descriptor[1] = GCPtr;
3864 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3865 AssertRC(rc);
3866 }
3867}
3868#endif /* HWACCM_VTX_WITH_VPID */
3869
3870/**
3871 * Invalidates a guest page
3872 *
3873 * @returns VBox status code.
3874 * @param pVM The VM to operate on.
3875 * @param pVCpu The VM CPU to operate on.
3876 * @param GCVirt Page to invalidate
3877 */
3878VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3879{
3880 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3881
3882 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3883
3884 /* Only relevant if we want to use VPID.
3885 * In the nested paging case we still see such calls, but
3886 * can safely ignore them. (e.g. after cr3 updates)
3887 */
3888#ifdef HWACCM_VTX_WITH_VPID
3889 /* Skip it if a TLB flush is already pending. */
3890 if ( !fFlushPending
3891 && pVM->hwaccm.s.vmx.fVPID)
3892 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3893#endif /* HWACCM_VTX_WITH_VPID */
3894
3895 return VINF_SUCCESS;
3896}
3897
3898/**
3899 * Invalidates a guest page by physical address
3900 *
3901 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3902 *
3903 * @returns VBox status code.
3904 * @param pVM The VM to operate on.
3905 * @param pVCpu The VM CPU to operate on.
3906 * @param GCPhys Page to invalidate
3907 */
3908VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3909{
3910 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3911
3912 Assert(pVM->hwaccm.s.fNestedPaging);
3913
3914 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3915
3916 /* Skip it if a TLB flush is already pending. */
3917 if (!fFlushPending)
3918 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3919
3920 return VINF_SUCCESS;
3921}
3922
3923/**
3924 * Report world switch error and dump some useful debug info
3925 *
3926 * @param pVM The VM to operate on.
3927 * @param pVCpu The VMCPU to operate on.
3928 * @param rc Return code
3929 * @param pCtx Current CPU context (not updated)
3930 */
3931static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3932{
3933 switch (rc)
3934 {
3935 case VERR_VMX_INVALID_VMXON_PTR:
3936 AssertFailed();
3937 break;
3938
3939 case VERR_VMX_UNABLE_TO_START_VM:
3940 case VERR_VMX_UNABLE_TO_RESUME_VM:
3941 {
3942 int rc;
3943 RTCCUINTREG exitReason, instrError;
3944
3945 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3946 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3947 AssertRC(rc);
3948 if (rc == VINF_SUCCESS)
3949 {
3950 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3951 Log(("Current stack %08x\n", &rc));
3952
3953 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3954 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3955
3956#ifdef VBOX_STRICT
3957 RTGDTR gdtr;
3958 PX86DESCHC pDesc;
3959 RTCCUINTREG val;
3960
3961 ASMGetGDTR(&gdtr);
3962
3963 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3964 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3965 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3966 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3967 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3968 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3969 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3970 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3971 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3972 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3973
3974 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3975 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3976
3977 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3978 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3979
3980 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3981 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3982
3983 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3984 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3985
3986 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3987 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3988
3989 if (val < gdtr.cbGdt)
3990 {
3991 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3992 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3993 }
3994
3995 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3996 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3997 if (val < gdtr.cbGdt)
3998 {
3999 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4000 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
4001 }
4002
4003 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
4004 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
4005 if (val < gdtr.cbGdt)
4006 {
4007 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4008 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
4009 }
4010
4011 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
4012 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
4013 if (val < gdtr.cbGdt)
4014 {
4015 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4016 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
4017 }
4018
4019 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
4020 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
4021 if (val < gdtr.cbGdt)
4022 {
4023 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4024 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
4025 }
4026
4027 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
4028 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
4029 if (val < gdtr.cbGdt)
4030 {
4031 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4032 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
4033 }
4034
4035 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
4036 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
4037 if (val < gdtr.cbGdt)
4038 {
4039 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4040 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
4041 }
4042
4043 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
4044 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
4045
4046 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
4047 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
4048 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
4049 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
4050
4051 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
4052 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
4053
4054 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
4055 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
4056
4057 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
4058 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
4059
4060 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
4061 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
4062 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
4063 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
4064
4065# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4066 if (VMX_IS_64BIT_HOST_MODE())
4067 {
4068 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
4069 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
4070 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
4071 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
4072 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
4073 }
4074# endif
4075#endif /* VBOX_STRICT */
4076 }
4077 break;
4078 }
4079
4080 default:
4081 /* impossible */
4082 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
4083 break;
4084 }
4085}
4086
4087#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4088/**
4089 * Prepares for and executes VMLAUNCH (64 bits guest mode)
4090 *
4091 * @returns VBox status code
4092 * @param fResume vmlauch/vmresume
4093 * @param pCtx Guest context
4094 * @param pCache VMCS cache
4095 * @param pVM The VM to operate on.
4096 * @param pVCpu The VMCPU to operate on.
4097 */
4098DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
4099{
4100 uint32_t aParam[6];
4101 PHWACCM_CPUINFO pCpu;
4102 RTHCPHYS pPageCpuPhys;
4103 int rc;
4104
4105 pCpu = HWACCMR0GetCurrentCpu();
4106 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4107
4108#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4109 pCache->uPos = 1;
4110 pCache->interPD = PGMGetInterPaeCR3(pVM);
4111 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
4112#endif
4113
4114#ifdef DEBUG
4115 pCache->TestIn.pPageCpuPhys = 0;
4116 pCache->TestIn.pVMCSPhys = 0;
4117 pCache->TestIn.pCache = 0;
4118 pCache->TestOut.pVMCSPhys = 0;
4119 pCache->TestOut.pCache = 0;
4120 pCache->TestOut.pCtx = 0;
4121 pCache->TestOut.eflags = 0;
4122#endif
4123
4124 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
4125 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
4126 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
4127 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
4128 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
4129 aParam[5] = 0;
4130
4131#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4132 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
4133 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
4134#endif
4135 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
4136
4137#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4138 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
4139 Assert(pCtx->dr[4] == 10);
4140 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
4141#endif
4142
4143#ifdef DEBUG
4144 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
4145 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
4146 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
4147 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
4148 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
4149 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
4150 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
4151#endif
4152 return rc;
4153}
4154
4155/**
4156 * Executes the specified handler in 64 mode
4157 *
4158 * @returns VBox status code.
4159 * @param pVM The VM to operate on.
4160 * @param pVCpu The VMCPU to operate on.
4161 * @param pCtx Guest context
4162 * @param pfnHandler RC handler
4163 * @param cbParam Number of parameters
4164 * @param paParam Array of 32 bits parameters
4165 */
4166VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
4167{
4168 int rc, rc2;
4169 PHWACCM_CPUINFO pCpu;
4170 RTHCPHYS pPageCpuPhys;
4171
4172 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
4173 AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
4174 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
4175 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
4176 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
4177
4178#ifdef VBOX_STRICT
4179 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
4180 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
4181
4182 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
4183 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
4184#endif
4185
4186 pCpu = HWACCMR0GetCurrentCpu();
4187 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4188
4189 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4190 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4191
4192 /* Leave VMX Root Mode. */
4193 VMXDisable();
4194
4195 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4196
4197 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
4198 CPUMSetHyperEIP(pVCpu, pfnHandler);
4199 for (int i=(int)cbParam-1;i>=0;i--)
4200 CPUMPushHyper(pVCpu, paParam[i]);
4201
4202 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4203 /* Call switcher. */
4204 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
4205 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4206
4207 /* Make sure the VMX instructions don't cause #UD faults. */
4208 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
4209
4210 /* Enter VMX Root Mode */
4211 rc2 = VMXEnable(pPageCpuPhys);
4212 if (RT_FAILURE(rc2))
4213 {
4214 if (pVM)
4215 VMXR0CheckError(pVM, pVCpu, rc2);
4216 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4217 return VERR_VMX_VMXON_FAILED;
4218 }
4219
4220 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4221 AssertRCReturn(rc2, rc2);
4222 Assert(!(ASMGetFlags() & X86_EFL_IF));
4223 return rc;
4224}
4225
4226#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4227
4228
4229#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4230/**
4231 * Executes VMWRITE
4232 *
4233 * @returns VBox status code
4234 * @param pVCpu The VMCPU to operate on.
4235 * @param idxField VMCS index
4236 * @param u64Val 16, 32 or 64 bits value
4237 */
4238VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4239{
4240 int rc;
4241
4242 switch (idxField)
4243 {
4244 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4245 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4246 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4247 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4248 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4249 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4250 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4251 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4252 case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
4253 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4254 case VMX_VMCS_GUEST_PDPTR0_FULL:
4255 case VMX_VMCS_GUEST_PDPTR1_FULL:
4256 case VMX_VMCS_GUEST_PDPTR2_FULL:
4257 case VMX_VMCS_GUEST_PDPTR3_FULL:
4258 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4259 case VMX_VMCS_GUEST_EFER_FULL:
4260 case VMX_VMCS_CTRL_EPTP_FULL:
4261 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4262 rc = VMXWriteVMCS32(idxField, u64Val);
4263 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4264 AssertRC(rc);
4265 return rc;
4266
4267 case VMX_VMCS64_GUEST_LDTR_BASE:
4268 case VMX_VMCS64_GUEST_TR_BASE:
4269 case VMX_VMCS64_GUEST_GDTR_BASE:
4270 case VMX_VMCS64_GUEST_IDTR_BASE:
4271 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4272 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4273 case VMX_VMCS64_GUEST_CR0:
4274 case VMX_VMCS64_GUEST_CR4:
4275 case VMX_VMCS64_GUEST_CR3:
4276 case VMX_VMCS64_GUEST_DR7:
4277 case VMX_VMCS64_GUEST_RIP:
4278 case VMX_VMCS64_GUEST_RSP:
4279 case VMX_VMCS64_GUEST_CS_BASE:
4280 case VMX_VMCS64_GUEST_DS_BASE:
4281 case VMX_VMCS64_GUEST_ES_BASE:
4282 case VMX_VMCS64_GUEST_FS_BASE:
4283 case VMX_VMCS64_GUEST_GS_BASE:
4284 case VMX_VMCS64_GUEST_SS_BASE:
4285 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4286 if (u64Val >> 32ULL)
4287 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4288 else
4289 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4290
4291 return rc;
4292
4293 default:
4294 AssertMsgFailed(("Unexpected field %x\n", idxField));
4295 return VERR_INVALID_PARAMETER;
4296 }
4297}
4298
4299/**
4300 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4301 *
4302 * @param pVCpu The VMCPU to operate on.
4303 * @param idxField VMCS field
4304 * @param u64Val Value
4305 */
4306VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4307{
4308 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4309
4310 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4311
4312 /* Make sure there are no duplicates. */
4313 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4314 {
4315 if (pCache->Write.aField[i] == idxField)
4316 {
4317 pCache->Write.aFieldVal[i] = u64Val;
4318 return VINF_SUCCESS;
4319 }
4320 }
4321
4322 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4323 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4324 pCache->Write.cValidEntries++;
4325 return VINF_SUCCESS;
4326}
4327
4328#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4329
4330#ifdef VBOX_STRICT
4331static bool vmxR0IsValidReadField(uint32_t idxField)
4332{
4333 switch(idxField)
4334 {
4335 case VMX_VMCS64_GUEST_RIP:
4336 case VMX_VMCS64_GUEST_RSP:
4337 case VMX_VMCS_GUEST_RFLAGS:
4338 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4339 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4340 case VMX_VMCS64_GUEST_CR0:
4341 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4342 case VMX_VMCS64_GUEST_CR4:
4343 case VMX_VMCS64_GUEST_DR7:
4344 case VMX_VMCS32_GUEST_SYSENTER_CS:
4345 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4346 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4347 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4348 case VMX_VMCS64_GUEST_GDTR_BASE:
4349 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4350 case VMX_VMCS64_GUEST_IDTR_BASE:
4351 case VMX_VMCS16_GUEST_FIELD_CS:
4352 case VMX_VMCS32_GUEST_CS_LIMIT:
4353 case VMX_VMCS64_GUEST_CS_BASE:
4354 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4355 case VMX_VMCS16_GUEST_FIELD_DS:
4356 case VMX_VMCS32_GUEST_DS_LIMIT:
4357 case VMX_VMCS64_GUEST_DS_BASE:
4358 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4359 case VMX_VMCS16_GUEST_FIELD_ES:
4360 case VMX_VMCS32_GUEST_ES_LIMIT:
4361 case VMX_VMCS64_GUEST_ES_BASE:
4362 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4363 case VMX_VMCS16_GUEST_FIELD_FS:
4364 case VMX_VMCS32_GUEST_FS_LIMIT:
4365 case VMX_VMCS64_GUEST_FS_BASE:
4366 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4367 case VMX_VMCS16_GUEST_FIELD_GS:
4368 case VMX_VMCS32_GUEST_GS_LIMIT:
4369 case VMX_VMCS64_GUEST_GS_BASE:
4370 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4371 case VMX_VMCS16_GUEST_FIELD_SS:
4372 case VMX_VMCS32_GUEST_SS_LIMIT:
4373 case VMX_VMCS64_GUEST_SS_BASE:
4374 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4375 case VMX_VMCS16_GUEST_FIELD_LDTR:
4376 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4377 case VMX_VMCS64_GUEST_LDTR_BASE:
4378 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4379 case VMX_VMCS16_GUEST_FIELD_TR:
4380 case VMX_VMCS32_GUEST_TR_LIMIT:
4381 case VMX_VMCS64_GUEST_TR_BASE:
4382 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4383 case VMX_VMCS32_RO_EXIT_REASON:
4384 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4385 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4386 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4387 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4388 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4389 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4390 case VMX_VMCS32_RO_IDT_INFO:
4391 case VMX_VMCS32_RO_IDT_ERRCODE:
4392 case VMX_VMCS64_GUEST_CR3:
4393 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4394 return true;
4395 }
4396 return false;
4397}
4398
4399static bool vmxR0IsValidWriteField(uint32_t idxField)
4400{
4401 switch(idxField)
4402 {
4403 case VMX_VMCS64_GUEST_LDTR_BASE:
4404 case VMX_VMCS64_GUEST_TR_BASE:
4405 case VMX_VMCS64_GUEST_GDTR_BASE:
4406 case VMX_VMCS64_GUEST_IDTR_BASE:
4407 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4408 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4409 case VMX_VMCS64_GUEST_CR0:
4410 case VMX_VMCS64_GUEST_CR4:
4411 case VMX_VMCS64_GUEST_CR3:
4412 case VMX_VMCS64_GUEST_DR7:
4413 case VMX_VMCS64_GUEST_RIP:
4414 case VMX_VMCS64_GUEST_RSP:
4415 case VMX_VMCS64_GUEST_CS_BASE:
4416 case VMX_VMCS64_GUEST_DS_BASE:
4417 case VMX_VMCS64_GUEST_ES_BASE:
4418 case VMX_VMCS64_GUEST_FS_BASE:
4419 case VMX_VMCS64_GUEST_GS_BASE:
4420 case VMX_VMCS64_GUEST_SS_BASE:
4421 return true;
4422 }
4423 return false;
4424}
4425
4426#endif
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