VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 20979

Last change on this file since 20979 was 20979, checked in by vboxsync, 15 years ago

Cpu poke never worked in the VT-x/AMD-V case, because pVCpu->idHostCpu was never set.
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1/* $Id: HWVMXR0.cpp 20979 2009-06-26 14:56:03Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/param.h>
41#include <iprt/string.h>
42#include <iprt/time.h>
43#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
44# include <iprt/thread.h>
45#endif
46#include "HWVMXR0.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51#if defined(RT_ARCH_AMD64)
52# define VMX_IS_64BIT_HOST_MODE() (true)
53#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
54# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
55#else
56# define VMX_IS_64BIT_HOST_MODE() (false)
57#endif
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62/* IO operation lookup arrays. */
63static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
65
66#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
67/** See HWACCMR0A.asm. */
68extern "C" uint32_t g_fVMXIs64bitHost;
69#endif
70
71/*******************************************************************************
72* Local Functions *
73*******************************************************************************/
74static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
75static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
76static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
77static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
78static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
79static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
80static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
81#ifdef VBOX_STRICT
82static bool vmxR0IsValidReadField(uint32_t idxField);
83static bool vmxR0IsValidWriteField(uint32_t idxField);
84#endif
85
86static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
87{
88 if (rc == VERR_VMX_GENERIC)
89 {
90 RTCCUINTREG instrError;
91
92 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
93 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
94 }
95 pVM->hwaccm.s.lLastError = rc;
96}
97
98/**
99 * Sets up and activates VT-x on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pVM The VM to operate on. (can be NULL after a resume!!)
104 * @param pvPageCpu Pointer to the global cpu page
105 * @param pPageCpuPhys Physical address of the global cpu page
106 */
107VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
108{
109 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
110 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
111
112#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
113 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
114#endif
115 if (pVM)
116 {
117 /* Set revision dword at the beginning of the VMXON structure. */
118 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
119 }
120
121 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
122 * (which can have very bad consequences!!!)
123 */
124
125 /* Make sure the VMX instructions don't cause #UD faults. */
126 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
127
128 /* Enter VMX Root Mode */
129 int rc = VMXEnable(pPageCpuPhys);
130 if (RT_FAILURE(rc))
131 {
132 if (pVM)
133 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
134 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
135 return VERR_VMX_VMXON_FAILED;
136 }
137 return VINF_SUCCESS;
138}
139
140/**
141 * Deactivates VT-x on the current CPU
142 *
143 * @returns VBox status code.
144 * @param pCpu CPU info struct
145 * @param pvPageCpu Pointer to the global cpu page
146 * @param pPageCpuPhys Physical address of the global cpu page
147 */
148VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
149{
150 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
151 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
152
153 /* Leave VMX Root Mode. */
154 VMXDisable();
155
156 /* And clear the X86_CR4_VMXE bit */
157 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
158
159#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
160 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
161#endif
162 return VINF_SUCCESS;
163}
164
165/**
166 * Does Ring-0 per VM VT-x init.
167 *
168 * @returns VBox status code.
169 * @param pVM The VM to operate on.
170 */
171VMMR0DECL(int) VMXR0InitVM(PVM pVM)
172{
173 int rc;
174
175#ifdef LOG_ENABLED
176 SUPR0Printf("VMXR0InitVM %x\n", pVM);
177#endif
178
179 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
180
181 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
182 {
183 /* Allocate one page for the APIC physical page (serves for filtering accesses). */
184 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185 AssertRC(rc);
186 if (RT_FAILURE(rc))
187 return rc;
188
189 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
190 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
191 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
192 }
193 else
194 {
195 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
196 pVM->hwaccm.s.vmx.pAPIC = 0;
197 pVM->hwaccm.s.vmx.pAPICPhys = 0;
198 }
199
200 /* Allocate the MSR bitmap if this feature is supported. */
201 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
202 {
203 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
204 AssertRC(rc);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
209 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
210 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
211 }
212
213#ifdef VBOX_WITH_CRASHDUMP_MAGIC
214 {
215 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
216 AssertRC(rc);
217 if (RT_FAILURE(rc))
218 return rc;
219
220 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
221 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
222
223 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
224 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
225 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
226 }
227#endif
228
229 /* Allocate VMCBs for all guest CPUs. */
230 for (unsigned i=0;i<pVM->cCPUs;i++)
231 {
232 PVMCPU pVCpu = &pVM->aCpus[i];
233
234 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
235
236 /* Allocate one page for the VM control structure (VMCS). */
237 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
238 AssertRC(rc);
239 if (RT_FAILURE(rc))
240 return rc;
241
242 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
243 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
244 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
245
246 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
247 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
248
249 /* Allocate one page for the virtual APIC page for TPR caching. */
250 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
251 AssertRC(rc);
252 if (RT_FAILURE(rc))
253 return rc;
254
255 pVCpu->hwaccm.s.vmx.pVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
256 pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
257 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
258
259 /* Current guest paging mode. */
260 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
261
262#ifdef LOG_ENABLED
263 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
264#endif
265 }
266
267 return VINF_SUCCESS;
268}
269
270/**
271 * Does Ring-0 per VM VT-x termination.
272 *
273 * @returns VBox status code.
274 * @param pVM The VM to operate on.
275 */
276VMMR0DECL(int) VMXR0TermVM(PVM pVM)
277{
278 for (unsigned i=0;i<pVM->cCPUs;i++)
279 {
280 PVMCPU pVCpu = &pVM->aCpus[i];
281
282 if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
283 {
284 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
285 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
286 pVCpu->hwaccm.s.vmx.pVMCS = 0;
287 pVCpu->hwaccm.s.vmx.pVMCSPhys = 0;
288 }
289 if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
290 {
291 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
292 pVCpu->hwaccm.s.vmx.pMemObjVAPIC = NIL_RTR0MEMOBJ;
293 pVCpu->hwaccm.s.vmx.pVAPIC = 0;
294 pVCpu->hwaccm.s.vmx.pVAPICPhys = 0;
295 }
296 }
297 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
298 {
299 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
300 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
301 pVM->hwaccm.s.vmx.pAPIC = 0;
302 pVM->hwaccm.s.vmx.pAPICPhys = 0;
303 }
304 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
305 {
306 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
307 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
308 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
309 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
310 }
311#ifdef VBOX_WITH_CRASHDUMP_MAGIC
312 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
313 {
314 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
315 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
316 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
317 pVM->hwaccm.s.vmx.pScratch = 0;
318 pVM->hwaccm.s.vmx.pScratchPhys = 0;
319 }
320#endif
321 return VINF_SUCCESS;
322}
323
324/**
325 * Sets up VT-x for the specified VM
326 *
327 * @returns VBox status code.
328 * @param pVM The VM to operate on.
329 */
330VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
331{
332 int rc = VINF_SUCCESS;
333 uint32_t val;
334
335 AssertReturn(pVM, VERR_INVALID_PARAMETER);
336
337 for (unsigned i=0;i<pVM->cCPUs;i++)
338 {
339 PVMCPU pVCpu = &pVM->aCpus[i];
340
341 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
342
343 /* Set revision dword at the beginning of the VMCS structure. */
344 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
345
346 /* Clear VM Control Structure. */
347 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
348 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
349 if (RT_FAILURE(rc))
350 goto vmx_end;
351
352 /* Activate the VM Control Structure. */
353 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
354 if (RT_FAILURE(rc))
355 goto vmx_end;
356
357 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
358 * Set required bits to one and zero according to the MSR capabilities.
359 */
360 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
361 /* External and non-maskable interrupts cause VM-exits. */
362 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
363 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
364
365 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
366 AssertRC(rc);
367
368 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
369 * Set required bits to one and zero according to the MSR capabilities.
370 */
371 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
372 /* Program which event cause VM-exits and which features we want to use. */
373 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
374 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
375 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
376 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
377 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
378 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
379
380 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
381 if (!pVM->hwaccm.s.fNestedPaging)
382 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
383 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
384 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
385
386 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
387 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
388 {
389 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
390 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
391 Assert(pVM->hwaccm.s.vmx.pAPIC);
392 }
393 else
394 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
395 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
396
397#ifdef VBOX_WITH_VTX_MSR_BITMAPS
398 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
399 {
400 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
401 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
402 }
403#endif
404
405 /* We will use the secondary control if it's present. */
406 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
407
408 /* Mask away the bits that the CPU doesn't support */
409 /** @todo make sure they don't conflict with the above requirements. */
410 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
411 pVCpu->hwaccm.s.vmx.proc_ctls = val;
412
413 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
414 AssertRC(rc);
415
416 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
417 {
418 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
419 * Set required bits to one and zero according to the MSR capabilities.
420 */
421 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
422 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
423
424#ifdef HWACCM_VTX_WITH_EPT
425 if (pVM->hwaccm.s.fNestedPaging)
426 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
427#endif /* HWACCM_VTX_WITH_EPT */
428#ifdef HWACCM_VTX_WITH_VPID
429 else
430 if (pVM->hwaccm.s.vmx.fVPID)
431 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
432#endif /* HWACCM_VTX_WITH_VPID */
433
434 if (pVM->hwaccm.s.fHasIoApic)
435 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC;
436
437 /* Mask away the bits that the CPU doesn't support */
438 /** @todo make sure they don't conflict with the above requirements. */
439 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
440 pVCpu->hwaccm.s.vmx.proc_ctls2 = val;
441 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
442 AssertRC(rc);
443 }
444
445 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
446 * Set required bits to one and zero according to the MSR capabilities.
447 */
448 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
449 AssertRC(rc);
450
451 /* Forward all exception except #NM & #PF to the guest.
452 * We always need to check pagefaults since our shadow page table can be out of sync.
453 * And we always lazily sync the FPU & XMM state.
454 */
455
456 /** @todo Possible optimization:
457 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
458 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
459 * registers ourselves of course.
460 *
461 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
462 */
463
464 /* Don't filter page faults; all of them should cause a switch. */
465 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
467 AssertRC(rc);
468
469 /* Init TSC offset to zero. */
470 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
471 AssertRC(rc);
472
473 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
474 AssertRC(rc);
475
476 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
477 AssertRC(rc);
478
479 /* Set the MSR bitmap address. */
480 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
481 {
482 /* Optional */
483 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
484 AssertRC(rc);
485 }
486
487 /* Clear MSR controls. */
488 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
489 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
490 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
491 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
492 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
493 AssertRC(rc);
494
495 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
496 {
497 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
498 /* Optional */
499 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
500 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
501
502 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
503 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
504
505 AssertRC(rc);
506 }
507
508 /* Set link pointer to -1. Not currently used. */
509 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
510 AssertRC(rc);
511
512 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
513 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
514 AssertRC(rc);
515
516 /* Configure the VMCS read cache. */
517 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
518
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
525 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
526 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
527 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
530 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
531 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
532 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
533 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
534 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
535
536 VMX_SETUP_SELREG(ES, pCache);
537 VMX_SETUP_SELREG(SS, pCache);
538 VMX_SETUP_SELREG(CS, pCache);
539 VMX_SETUP_SELREG(DS, pCache);
540 VMX_SETUP_SELREG(FS, pCache);
541 VMX_SETUP_SELREG(GS, pCache);
542 VMX_SETUP_SELREG(LDTR, pCache);
543 VMX_SETUP_SELREG(TR, pCache);
544
545 /* Status code VMCS reads. */
546 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
547 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
548 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
549 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
550 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
551 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
552 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
553 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
554 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
555
556 if (pVM->hwaccm.s.fNestedPaging)
557 {
558 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
559 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
560 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
561 }
562 else
563 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
564 } /* for each VMCPU */
565
566 /* Choose the right TLB setup function. */
567 if (pVM->hwaccm.s.fNestedPaging)
568 {
569 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
570
571 /* Default values for flushing. */
572 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
574
575 /* If the capabilities specify we can do more, then make use of it. */
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
577 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
578 else
579 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
580 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
581
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
583 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
584 }
585#ifdef HWACCM_VTX_WITH_VPID
586 else
587 if (pVM->hwaccm.s.vmx.fVPID)
588 {
589 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
590
591 /* Default values for flushing. */
592 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
593 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
594
595 /* If the capabilities specify we can do more, then make use of it. */
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
597 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
598 else
599 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
600 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
601
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
603 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
604 }
605#endif /* HWACCM_VTX_WITH_VPID */
606 else
607 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
608
609vmx_end:
610 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
611 return rc;
612}
613
614
615/**
616 * Injects an event (trap or external interrupt)
617 *
618 * @returns VBox status code.
619 * @param pVM The VM to operate on.
620 * @param pVCpu The VMCPU to operate on.
621 * @param pCtx CPU Context
622 * @param intInfo VMX interrupt info
623 * @param cbInstr Opcode length of faulting instruction
624 * @param errCode Error code (optional)
625 */
626static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
627{
628 int rc;
629 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
630
631#ifdef VBOX_WITH_STATISTICS
632 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
633#endif
634
635#ifdef VBOX_STRICT
636 if (iGate == 0xE)
637 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
638 else
639 if (iGate < 0x20)
640 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
641 else
642 {
643 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
644 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
645 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
646 }
647#endif
648
649#ifdef HWACCM_VMX_EMULATE_REALMODE
650 if (CPUMIsGuestInRealModeEx(pCtx))
651 {
652 RTGCPHYS GCPhysHandler;
653 uint16_t offset, ip;
654 RTSEL sel;
655
656 /* Injecting events doesn't work right with real mode emulation.
657 * (#GP if we try to inject external hardware interrupts)
658 * Inject the interrupt or trap directly instead.
659 *
660 * ASSUMES no access handlers for the bits we read or write below (should be safe).
661 */
662 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
663
664 /* Check if the interrupt handler is present. */
665 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
666 {
667 Log(("IDT cbIdt violation\n"));
668 if (iGate != X86_XCPT_DF)
669 {
670 RTGCUINTPTR intInfo;
671
672 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
673 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
674 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
675 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
676
677 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
678 }
679 Log(("Triple fault -> reset the VM!\n"));
680 return VINF_EM_RESET;
681 }
682 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
683 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
684 || iGate == 4)
685 {
686 ip = pCtx->ip + cbInstr;
687 }
688 else
689 ip = pCtx->ip;
690
691 /* Read the selector:offset pair of the interrupt handler. */
692 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
693 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
694 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
695
696 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
697
698 /* Construct the stack frame. */
699 /** @todo should check stack limit. */
700 pCtx->sp -= 2;
701 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
702 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
703 pCtx->sp -= 2;
704 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
705 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
706 pCtx->sp -= 2;
707 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
708 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
709
710 /* Update the CPU state for executing the handler. */
711 pCtx->rip = offset;
712 pCtx->cs = sel;
713 pCtx->csHid.u64Base = sel << 4;
714 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
715
716 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
717 return VINF_SUCCESS;
718 }
719#endif /* HWACCM_VMX_EMULATE_REALMODE */
720
721 /* Set event injection state. */
722 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
723
724 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
725 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
726
727 AssertRC(rc);
728 return rc;
729}
730
731
732/**
733 * Checks for pending guest interrupts and injects them
734 *
735 * @returns VBox status code.
736 * @param pVM The VM to operate on.
737 * @param pVCpu The VMCPU to operate on.
738 * @param pCtx CPU Context
739 */
740static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
741{
742 int rc;
743
744 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
745 if (pVCpu->hwaccm.s.Event.fPending)
746 {
747 Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
748 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
749 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
750 AssertRC(rc);
751
752 pVCpu->hwaccm.s.Event.fPending = false;
753 return VINF_SUCCESS;
754 }
755
756 /* If an active trap is already pending, then we must forward it first! */
757 if (!TRPMHasTrap(pVCpu))
758 {
759 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI_BIT))
760 {
761 RTGCUINTPTR intInfo;
762
763 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
764
765 intInfo = X86_XCPT_NMI;
766 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
767 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
768
769 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
770 AssertRC(rc);
771
772 return VINF_SUCCESS;
773 }
774
775 /* @todo SMI interrupts. */
776
777 /* When external interrupts are pending, we should exit the VM when IF is set. */
778 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
779 {
780 if (!(pCtx->eflags.u32 & X86_EFL_IF))
781 {
782 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
783 {
784 LogFlow(("Enable irq window exit!\n"));
785 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
786 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
787 AssertRC(rc);
788 }
789 /* else nothing to do but wait */
790 }
791 else
792 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
793 {
794 uint8_t u8Interrupt;
795
796 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
797 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
798 if (RT_SUCCESS(rc))
799 {
800 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
801 AssertRC(rc);
802 }
803 else
804 {
805 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
806 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
807 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
808 /* Just continue */
809 }
810 }
811 else
812 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
813 }
814 }
815
816#ifdef VBOX_STRICT
817 if (TRPMHasTrap(pVCpu))
818 {
819 uint8_t u8Vector;
820 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
821 AssertRC(rc);
822 }
823#endif
824
825 if ( (pCtx->eflags.u32 & X86_EFL_IF)
826 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
827 && TRPMHasTrap(pVCpu)
828 )
829 {
830 uint8_t u8Vector;
831 int rc;
832 TRPMEVENT enmType;
833 RTGCUINTPTR intInfo;
834 RTGCUINT errCode;
835
836 /* If a new event is pending, then dispatch it now. */
837 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
838 AssertRC(rc);
839 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
840 Assert(enmType != TRPM_SOFTWARE_INT);
841
842 /* Clear the pending trap. */
843 rc = TRPMResetTrap(pVCpu);
844 AssertRC(rc);
845
846 intInfo = u8Vector;
847 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
848
849 if (enmType == TRPM_TRAP)
850 {
851 switch (u8Vector) {
852 case 8:
853 case 10:
854 case 11:
855 case 12:
856 case 13:
857 case 14:
858 case 17:
859 /* Valid error codes. */
860 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
861 break;
862 default:
863 break;
864 }
865 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
866 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
867 else
868 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
869 }
870 else
871 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
872
873 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
874 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
875 AssertRC(rc);
876 } /* if (interrupts can be dispatched) */
877
878 return VINF_SUCCESS;
879}
880
881/**
882 * Save the host state
883 *
884 * @returns VBox status code.
885 * @param pVM The VM to operate on.
886 * @param pVCpu The VMCPU to operate on.
887 */
888VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
889{
890 int rc = VINF_SUCCESS;
891
892 /*
893 * Host CPU Context
894 */
895 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
896 {
897 RTIDTR idtr;
898 RTGDTR gdtr;
899 RTSEL SelTR;
900 PX86DESCHC pDesc;
901 uintptr_t trBase;
902 RTSEL cs;
903 RTSEL ss;
904 uint64_t cr3;
905
906 /* Control registers */
907 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
908#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
909 if (VMX_IS_64BIT_HOST_MODE())
910 {
911 cr3 = hwaccmR0Get64bitCR3();
912 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
913 }
914 else
915#endif
916 {
917 cr3 = ASMGetCR3();
918 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
919 }
920 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
921 AssertRC(rc);
922 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
923 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
924 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
925
926 /* Selector registers. */
927#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
928 if (VMX_IS_64BIT_HOST_MODE())
929 {
930 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
931 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
932 }
933 else
934 {
935 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
936 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
937 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
938 }
939#else
940 cs = ASMGetCS();
941 ss = ASMGetSS();
942#endif
943 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
944 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
945 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
946 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
947 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
948 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
949#if HC_ARCH_BITS == 32
950 if (!VMX_IS_64BIT_HOST_MODE())
951 {
952 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
953 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
954 }
955#endif
956 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
957 SelTR = ASMGetTR();
958 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
959 AssertRC(rc);
960 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
961 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
962 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
963 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
964 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
965 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
966 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
967
968 /* GDTR & IDTR */
969#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
970 if (VMX_IS_64BIT_HOST_MODE())
971 {
972 X86XDTR64 gdtr64, idtr64;
973 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
974 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
975 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
976 AssertRC(rc);
977 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
978 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
979 gdtr.cbGdt = gdtr64.cb;
980 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
981 }
982 else
983#endif
984 {
985 ASMGetGDTR(&gdtr);
986 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
987 ASMGetIDTR(&idtr);
988 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
989 AssertRC(rc);
990 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
991 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
992 }
993
994
995 /* Save the base address of the TR selector. */
996 if (SelTR > gdtr.cbGdt)
997 {
998 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
999 return VERR_VMX_INVALID_HOST_STATE;
1000 }
1001
1002#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1003 if (VMX_IS_64BIT_HOST_MODE())
1004 {
1005 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
1006 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
1007 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
1008 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
1009 AssertRC(rc);
1010 }
1011 else
1012#endif
1013 {
1014 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
1015#if HC_ARCH_BITS == 64
1016 trBase = X86DESC64_BASE(*pDesc);
1017#else
1018 trBase = X86DESC_BASE(*pDesc);
1019#endif
1020 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
1021 AssertRC(rc);
1022 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
1023 }
1024
1025 /* FS and GS base. */
1026#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1027 if (VMX_IS_64BIT_HOST_MODE())
1028 {
1029 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
1030 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
1031 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
1032 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
1033 }
1034#endif
1035 AssertRC(rc);
1036
1037 /* Sysenter MSRs. */
1038 /** @todo expensive!! */
1039 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1040 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1041#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1042 if (VMX_IS_64BIT_HOST_MODE())
1043 {
1044 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1045 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1046 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1047 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1048 }
1049 else
1050 {
1051 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1052 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1053 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1054 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1055 }
1056#elif HC_ARCH_BITS == 32
1057 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1058 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1059 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1060 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1061#else
1062 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1063 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1064 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1065 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1066#endif
1067 AssertRC(rc);
1068
1069#if 0 /* @todo deal with 32/64 */
1070 /* Restore the host EFER - on CPUs that support it. */
1071 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1072 {
1073 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1074 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1075 AssertRC(rc);
1076 }
1077#endif
1078 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1079 }
1080 return rc;
1081}
1082
1083/**
1084 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1085 *
1086 * @param pVM The VM to operate on.
1087 * @param pVCpu The VMCPU to operate on.
1088 * @param pCtx Guest context
1089 */
1090static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1091{
1092 if (CPUMIsGuestInPAEModeEx(pCtx))
1093 {
1094 X86PDPE Pdpe;
1095
1096 for (unsigned i=0;i<4;i++)
1097 {
1098 Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1099 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1100 AssertRC(rc);
1101 }
1102 }
1103}
1104
1105/**
1106 * Update the exception bitmap according to the current CPU state
1107 *
1108 * @param pVM The VM to operate on.
1109 * @param pVCpu The VMCPU to operate on.
1110 * @param pCtx Guest context
1111 */
1112static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1113{
1114 uint32_t u32TrapMask;
1115 Assert(pCtx);
1116
1117 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1118#ifndef DEBUG
1119 if (pVM->hwaccm.s.fNestedPaging)
1120 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1121#endif
1122
1123 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1124 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1125 && !(pCtx->cr0 & X86_CR0_NE)
1126 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1127 {
1128 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1129 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1130 }
1131
1132#ifdef DEBUG /* till after branching, enable it by default then. */
1133 /* Intercept X86_XCPT_DB if stepping is enabled */
1134 if (DBGFIsStepping(pVCpu))
1135 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1136 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1137 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1138#endif
1139
1140#ifdef VBOX_STRICT
1141 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1142#endif
1143
1144# ifdef HWACCM_VMX_EMULATE_REALMODE
1145 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1146 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1147 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1148# endif /* HWACCM_VMX_EMULATE_REALMODE */
1149
1150 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1151 AssertRC(rc);
1152}
1153
1154/**
1155 * Loads the guest state
1156 *
1157 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1158 *
1159 * @returns VBox status code.
1160 * @param pVM The VM to operate on.
1161 * @param pVCpu The VMCPU to operate on.
1162 * @param pCtx Guest context
1163 */
1164VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1165{
1166 int rc = VINF_SUCCESS;
1167 RTGCUINTPTR val;
1168 X86EFLAGS eflags;
1169
1170 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1171 * Set required bits to one and zero according to the MSR capabilities.
1172 */
1173 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1174 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1175 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1176#if 0 /* @todo deal with 32/64 */
1177 /* Required for the EFER write below, not supported on all CPUs. */
1178 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1179#endif
1180 /* 64 bits guest mode? */
1181 if (CPUMIsGuestInLongModeEx(pCtx))
1182 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1183 /* else Must be zero when AMD64 is not available. */
1184
1185 /* Mask away the bits that the CPU doesn't support */
1186 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1187 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1188 AssertRC(rc);
1189
1190 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1191 * Set required bits to one and zero according to the MSR capabilities.
1192 */
1193 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1194
1195 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1196#if 0 /* @todo deal with 32/64 */
1197 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1198#else
1199 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1200#endif
1201
1202#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1203 if (VMX_IS_64BIT_HOST_MODE())
1204 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1205 /* else: Must be zero when AMD64 is not available. */
1206#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1207 if (CPUMIsGuestInLongModeEx(pCtx))
1208 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1209 else
1210 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1211#endif
1212 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1213 /* Don't acknowledge external interrupts on VM-exit. */
1214 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1215 AssertRC(rc);
1216
1217 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1218 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1219 {
1220#ifdef HWACCM_VMX_EMULATE_REALMODE
1221 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1222 {
1223 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1224 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1225 {
1226 /* Correct weird requirements for switching to protected mode. */
1227 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1228 && enmGuestMode >= PGMMODE_PROTECTED)
1229 {
1230 /* Flush the recompiler code cache as it's not unlikely
1231 * the guest will rewrite code it will later execute in real
1232 * mode (OpenBSD 4.0 is one such example)
1233 */
1234 REMFlushTBs(pVM);
1235
1236 /* DPL of all hidden selector registers must match the current CPL (0). */
1237 pCtx->csHid.Attr.n.u2Dpl = 0;
1238 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1239
1240 pCtx->dsHid.Attr.n.u2Dpl = 0;
1241 pCtx->esHid.Attr.n.u2Dpl = 0;
1242 pCtx->fsHid.Attr.n.u2Dpl = 0;
1243 pCtx->gsHid.Attr.n.u2Dpl = 0;
1244 pCtx->ssHid.Attr.n.u2Dpl = 0;
1245
1246 /* The limit must correspond to the granularity bit. */
1247 if (!pCtx->csHid.Attr.n.u1Granularity)
1248 pCtx->csHid.u32Limit &= 0xffff;
1249 if (!pCtx->dsHid.Attr.n.u1Granularity)
1250 pCtx->dsHid.u32Limit &= 0xffff;
1251 if (!pCtx->esHid.Attr.n.u1Granularity)
1252 pCtx->esHid.u32Limit &= 0xffff;
1253 if (!pCtx->fsHid.Attr.n.u1Granularity)
1254 pCtx->fsHid.u32Limit &= 0xffff;
1255 if (!pCtx->gsHid.Attr.n.u1Granularity)
1256 pCtx->gsHid.u32Limit &= 0xffff;
1257 if (!pCtx->ssHid.Attr.n.u1Granularity)
1258 pCtx->ssHid.u32Limit &= 0xffff;
1259 }
1260 else
1261 /* Switching from protected mode to real mode. */
1262 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1263 && enmGuestMode == PGMMODE_REAL)
1264 {
1265 /* The limit must also be set to 0xffff. */
1266 pCtx->csHid.u32Limit = 0xffff;
1267 pCtx->dsHid.u32Limit = 0xffff;
1268 pCtx->esHid.u32Limit = 0xffff;
1269 pCtx->fsHid.u32Limit = 0xffff;
1270 pCtx->gsHid.u32Limit = 0xffff;
1271 pCtx->ssHid.u32Limit = 0xffff;
1272
1273 Assert(pCtx->csHid.u64Base <= 0xfffff);
1274 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1275 Assert(pCtx->esHid.u64Base <= 0xfffff);
1276 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1277 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1278 }
1279 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1280 }
1281 else
1282 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1283 if ( CPUMIsGuestInRealModeEx(pCtx)
1284 && pCtx->csHid.u64Base == 0xffff0000)
1285 {
1286 pCtx->csHid.u64Base = 0xf0000;
1287 pCtx->cs = 0xf000;
1288 }
1289 }
1290#endif /* HWACCM_VMX_EMULATE_REALMODE */
1291
1292 VMX_WRITE_SELREG(ES, es);
1293 AssertRC(rc);
1294
1295 VMX_WRITE_SELREG(CS, cs);
1296 AssertRC(rc);
1297
1298 VMX_WRITE_SELREG(SS, ss);
1299 AssertRC(rc);
1300
1301 VMX_WRITE_SELREG(DS, ds);
1302 AssertRC(rc);
1303
1304 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1305 VMX_WRITE_SELREG(FS, fs);
1306 AssertRC(rc);
1307
1308 VMX_WRITE_SELREG(GS, gs);
1309 AssertRC(rc);
1310 }
1311
1312 /* Guest CPU context: LDTR. */
1313 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1314 {
1315 if (pCtx->ldtr == 0)
1316 {
1317 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1318 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1319 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1320 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1321 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1322 }
1323 else
1324 {
1325 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1326 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1327 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1328 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1329 }
1330 AssertRC(rc);
1331 }
1332 /* Guest CPU context: TR. */
1333 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1334 {
1335#ifdef HWACCM_VMX_EMULATE_REALMODE
1336 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1337 if (CPUMIsGuestInRealModeEx(pCtx))
1338 {
1339 RTGCPHYS GCPhys;
1340
1341 /* We convert it here every time as pci regions could be reconfigured. */
1342 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1343 AssertRC(rc);
1344
1345 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1346 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1347 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1348
1349 X86DESCATTR attr;
1350
1351 attr.u = 0;
1352 attr.n.u1Present = 1;
1353 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1354 val = attr.u;
1355 }
1356 else
1357#endif /* HWACCM_VMX_EMULATE_REALMODE */
1358 {
1359 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1360 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1361 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1362
1363 val = pCtx->trHid.Attr.u;
1364
1365 /* The TSS selector must be busy. */
1366 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1367 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1368 else
1369 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1370 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1371
1372 }
1373 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1374 AssertRC(rc);
1375 }
1376 /* Guest CPU context: GDTR. */
1377 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1378 {
1379 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1380 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1381 AssertRC(rc);
1382 }
1383 /* Guest CPU context: IDTR. */
1384 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1385 {
1386 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1387 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1388 AssertRC(rc);
1389 }
1390
1391 /*
1392 * Sysenter MSRs (unconditional)
1393 */
1394 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1395 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1396 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1397 AssertRC(rc);
1398
1399 /* Control registers */
1400 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1401 {
1402 val = pCtx->cr0;
1403 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1404 Log2(("Guest CR0-shadow %08x\n", val));
1405 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1406 {
1407 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1408 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1409 }
1410 else
1411 {
1412 /** @todo check if we support the old style mess correctly. */
1413 if (!(val & X86_CR0_NE))
1414 Log(("Forcing X86_CR0_NE!!!\n"));
1415
1416 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1417 }
1418 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1419 val |= X86_CR0_PE | X86_CR0_PG;
1420 if (pVM->hwaccm.s.fNestedPaging)
1421 {
1422 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1423 {
1424 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1425 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1426 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1427 }
1428 else
1429 {
1430 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1431 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1432 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1433 }
1434 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1435 AssertRC(rc);
1436 }
1437 else
1438 {
1439 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1440 val |= X86_CR0_WP;
1441 }
1442
1443 /* Always enable caching. */
1444 val &= ~(X86_CR0_CD|X86_CR0_NW);
1445
1446 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1447 Log2(("Guest CR0 %08x\n", val));
1448 /* CR0 flags owned by the host; if the guests attempts to change them, then
1449 * the VM will exit.
1450 */
1451 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1452 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1453 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1454 | X86_CR0_TS
1455 | X86_CR0_ET /* Bit not restored during VM-exit! */
1456 | X86_CR0_CD /* Bit not restored during VM-exit! */
1457 | X86_CR0_NW /* Bit not restored during VM-exit! */
1458 | X86_CR0_NE
1459 | X86_CR0_MP;
1460 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1461
1462 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1463 Log2(("Guest CR0-mask %08x\n", val));
1464 AssertRC(rc);
1465 }
1466 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1467 {
1468 /* CR4 */
1469 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1470 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1471 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1472 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1473
1474 if (!pVM->hwaccm.s.fNestedPaging)
1475 {
1476 switch(pVCpu->hwaccm.s.enmShadowMode)
1477 {
1478 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1479 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1480 case PGMMODE_32_BIT: /* 32-bit paging. */
1481 val &= ~X86_CR4_PAE;
1482 break;
1483
1484 case PGMMODE_PAE: /* PAE paging. */
1485 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1486 /** @todo use normal 32 bits paging */
1487 val |= X86_CR4_PAE;
1488 break;
1489
1490 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1491 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1492#ifdef VBOX_ENABLE_64_BITS_GUESTS
1493 break;
1494#else
1495 AssertFailed();
1496 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1497#endif
1498 default: /* shut up gcc */
1499 AssertFailed();
1500 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1501 }
1502 }
1503 else
1504 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1505 {
1506 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1507 val |= X86_CR4_PSE;
1508 /* Our identity mapping is a 32 bits page directory. */
1509 val &= ~X86_CR4_PAE;
1510 }
1511
1512 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1513 Log2(("Guest CR4 %08x\n", val));
1514 /* CR4 flags owned by the host; if the guests attempts to change them, then
1515 * the VM will exit.
1516 */
1517 val = 0
1518 | X86_CR4_PAE
1519 | X86_CR4_PGE
1520 | X86_CR4_PSE
1521 | X86_CR4_VMXE;
1522 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1523
1524 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1525 Log2(("Guest CR4-mask %08x\n", val));
1526 AssertRC(rc);
1527 }
1528
1529 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1530 {
1531 if (pVM->hwaccm.s.fNestedPaging)
1532 {
1533 Assert(PGMGetHyperCR3(pVCpu));
1534 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1535
1536 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1537 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1538 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1539 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1540
1541 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1542 AssertRC(rc);
1543
1544 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1545 {
1546 RTGCPHYS GCPhys;
1547
1548 /* We convert it here every time as pci regions could be reconfigured. */
1549 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1550 AssertRC(rc);
1551
1552 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1553 * take care of the translation to host physical addresses.
1554 */
1555 val = GCPhys;
1556 }
1557 else
1558 {
1559 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1560 val = pCtx->cr3;
1561 /* Prefetch the four PDPT entries in PAE mode. */
1562 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1563 }
1564 }
1565 else
1566 {
1567 val = PGMGetHyperCR3(pVCpu);
1568 Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1569 }
1570
1571 /* Save our shadow CR3 register. */
1572 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1573 AssertRC(rc);
1574 }
1575
1576 /* Debug registers. */
1577 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1578 {
1579 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1580 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1581
1582 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1583 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1584 pCtx->dr[7] |= 0x400; /* must be one */
1585
1586 /* Resync DR7 */
1587 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1588 AssertRC(rc);
1589
1590 /* Sync the debug state now if any breakpoint is armed. */
1591 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1592 && !CPUMIsGuestDebugStateActive(pVCpu)
1593 && !DBGFIsStepping(pVCpu))
1594 {
1595 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1596
1597 /* Disable drx move intercepts. */
1598 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1599 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1600 AssertRC(rc);
1601
1602 /* Save the host and load the guest debug state. */
1603 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1604 AssertRC(rc);
1605 }
1606
1607 /* IA32_DEBUGCTL MSR. */
1608 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1609 AssertRC(rc);
1610
1611 /** @todo do we really ever need this? */
1612 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1613 AssertRC(rc);
1614 }
1615
1616 /* EIP, ESP and EFLAGS */
1617 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1618 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1619 AssertRC(rc);
1620
1621 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1622 eflags = pCtx->eflags;
1623 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1624 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1625
1626#ifdef HWACCM_VMX_EMULATE_REALMODE
1627 /* Real mode emulation using v86 mode. */
1628 if (CPUMIsGuestInRealModeEx(pCtx))
1629 {
1630 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1631
1632 eflags.Bits.u1VM = 1;
1633 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1634 }
1635#endif /* HWACCM_VMX_EMULATE_REALMODE */
1636 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1637 AssertRC(rc);
1638
1639 /* TSC offset. */
1640 uint64_t u64TSCOffset;
1641
1642 if (TMCpuTickCanUseRealTSC(pVCpu, &u64TSCOffset))
1643 {
1644 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1645 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1646 AssertRC(rc);
1647
1648 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1649 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1650 AssertRC(rc);
1651 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1652 }
1653 else
1654 {
1655 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1656 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1657 AssertRC(rc);
1658 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1659 }
1660
1661 /* 64 bits guest mode? */
1662 if (CPUMIsGuestInLongModeEx(pCtx))
1663 {
1664#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1665 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1666#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1667 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1668#else
1669# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1670 if (!pVM->hwaccm.s.fAllow64BitGuests)
1671 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1672# endif
1673 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1674#endif
1675 /* Unconditionally update these as wrmsr might have changed them. */
1676 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1677 AssertRC(rc);
1678 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1679 AssertRC(rc);
1680 }
1681 else
1682 {
1683 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1684 }
1685
1686#if 0 /* @todo deal with 32/64 */
1687 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1688 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1689 {
1690 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1691 AssertRC(rc);
1692 }
1693#endif
1694
1695 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1696
1697 /* Done. */
1698 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1699
1700 return rc;
1701}
1702
1703/**
1704 * Syncs back the guest state
1705 *
1706 * @returns VBox status code.
1707 * @param pVM The VM to operate on.
1708 * @param pVCpu The VMCPU to operate on.
1709 * @param pCtx Guest context
1710 */
1711DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1712{
1713 RTGCUINTREG val, valShadow;
1714 RTGCUINTPTR uInterruptState;
1715 int rc;
1716
1717 /* Let's first sync back eip, esp, and eflags. */
1718 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1719 AssertRC(rc);
1720 pCtx->rip = val;
1721 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1722 AssertRC(rc);
1723 pCtx->rsp = val;
1724 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1725 AssertRC(rc);
1726 pCtx->eflags.u32 = val;
1727
1728 /* Take care of instruction fusing (sti, mov ss) */
1729 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1730 uInterruptState = val;
1731 if (uInterruptState != 0)
1732 {
1733 Assert(uInterruptState <= 2); /* only sti & mov ss */
1734 Log(("uInterruptState %x eip=%RGv\n", (uint32_t)uInterruptState, pCtx->rip));
1735 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1736 }
1737 else
1738 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1739
1740 /* Control registers. */
1741 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1742 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1743 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1744 CPUMSetGuestCR0(pVCpu, val);
1745
1746 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1747 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1748 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1749 CPUMSetGuestCR4(pVCpu, val);
1750
1751 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1752 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1753 if ( pVM->hwaccm.s.fNestedPaging
1754 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1755 {
1756 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1757
1758 /* Can be updated behind our back in the nested paging case. */
1759 CPUMSetGuestCR2(pVCpu, pCache->cr2);
1760
1761 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1762
1763 if (val != pCtx->cr3)
1764 {
1765 CPUMSetGuestCR3(pVCpu, val);
1766 PGMUpdateCR3(pVCpu, val);
1767 }
1768 /* Prefetch the four PDPT entries in PAE mode. */
1769 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1770 }
1771
1772 /* Sync back DR7 here. */
1773 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1774 pCtx->dr[7] = val;
1775
1776 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1777 VMX_READ_SELREG(ES, es);
1778 VMX_READ_SELREG(SS, ss);
1779 VMX_READ_SELREG(CS, cs);
1780 VMX_READ_SELREG(DS, ds);
1781 VMX_READ_SELREG(FS, fs);
1782 VMX_READ_SELREG(GS, gs);
1783
1784 /*
1785 * System MSRs
1786 */
1787 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1788 pCtx->SysEnter.cs = val;
1789 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1790 pCtx->SysEnter.eip = val;
1791 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1792 pCtx->SysEnter.esp = val;
1793
1794 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1795 VMX_READ_SELREG(LDTR, ldtr);
1796
1797 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1798 pCtx->gdtr.cbGdt = val;
1799 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1800 pCtx->gdtr.pGdt = val;
1801
1802 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1803 pCtx->idtr.cbIdt = val;
1804 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1805 pCtx->idtr.pIdt = val;
1806
1807#ifdef HWACCM_VMX_EMULATE_REALMODE
1808 /* Real mode emulation using v86 mode. */
1809 if (CPUMIsGuestInRealModeEx(pCtx))
1810 {
1811 /* Hide our emulation flags */
1812 pCtx->eflags.Bits.u1VM = 0;
1813
1814 /* Restore original IOPL setting as we always use 0. */
1815 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1816
1817 /* Force a TR resync every time in case we switch modes. */
1818 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1819 }
1820 else
1821#endif /* HWACCM_VMX_EMULATE_REALMODE */
1822 {
1823 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1824 VMX_READ_SELREG(TR, tr);
1825 }
1826 return VINF_SUCCESS;
1827}
1828
1829/**
1830 * Dummy placeholder
1831 *
1832 * @param pVM The VM to operate on.
1833 * @param pVCpu The VMCPU to operate on.
1834 */
1835static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1836{
1837 NOREF(pVM);
1838 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1839 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1840 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1841 return;
1842}
1843
1844/**
1845 * Setup the tagged TLB for EPT
1846 *
1847 * @returns VBox status code.
1848 * @param pVM The VM to operate on.
1849 * @param pVCpu The VMCPU to operate on.
1850 */
1851static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1852{
1853 PHWACCM_CPUINFO pCpu;
1854
1855 Assert(pVM->hwaccm.s.fNestedPaging);
1856 Assert(!pVM->hwaccm.s.vmx.fVPID);
1857
1858 /* Deal with tagged TLBs if VPID or EPT is supported. */
1859 pCpu = HWACCMR0GetCurrentCpu();
1860 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1861 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1862 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1863 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1864 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1865 {
1866 /* Force a TLB flush on VM entry. */
1867 pVCpu->hwaccm.s.fForceTLBFlush = true;
1868 }
1869 else
1870 Assert(!pCpu->fFlushTLB);
1871
1872 /* Check for tlb shootdown flushes. */
1873 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1874 pVCpu->hwaccm.s.fForceTLBFlush = true;
1875
1876 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1877 pCpu->fFlushTLB = false;
1878
1879 if (pVCpu->hwaccm.s.fForceTLBFlush)
1880 {
1881 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1882 }
1883 else
1884 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1885 {
1886 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1887 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1888
1889 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1890 {
1891 /* aTlbShootdownPages contains physical addresses in this case. */
1892 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1893 }
1894 }
1895 pVCpu->hwaccm.s.TlbShootdown.cPages= 0;
1896 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1897
1898#ifdef VBOX_WITH_STATISTICS
1899 if (pVCpu->hwaccm.s.fForceTLBFlush)
1900 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1901 else
1902 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1903#endif
1904}
1905
1906#ifdef HWACCM_VTX_WITH_VPID
1907/**
1908 * Setup the tagged TLB for VPID
1909 *
1910 * @returns VBox status code.
1911 * @param pVM The VM to operate on.
1912 * @param pVCpu The VMCPU to operate on.
1913 */
1914static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1915{
1916 PHWACCM_CPUINFO pCpu;
1917
1918 Assert(pVM->hwaccm.s.vmx.fVPID);
1919 Assert(!pVM->hwaccm.s.fNestedPaging);
1920
1921 /* Deal with tagged TLBs if VPID or EPT is supported. */
1922 pCpu = HWACCMR0GetCurrentCpu();
1923 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1924 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1925 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1926 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1927 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1928 {
1929 /* Force a TLB flush on VM entry. */
1930 pVCpu->hwaccm.s.fForceTLBFlush = true;
1931 }
1932 else
1933 Assert(!pCpu->fFlushTLB);
1934
1935 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1936
1937 /* Check for tlb shootdown flushes. */
1938 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1939 pVCpu->hwaccm.s.fForceTLBFlush = true;
1940
1941 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1942 if (pVCpu->hwaccm.s.fForceTLBFlush)
1943 {
1944 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1945 || pCpu->fFlushTLB)
1946 {
1947 pCpu->fFlushTLB = false;
1948 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1949 pCpu->cTLBFlushes++;
1950 }
1951 else
1952 {
1953 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1954 pVCpu->hwaccm.s.fForceTLBFlush = false;
1955 }
1956
1957 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1958 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1959 }
1960 else
1961 {
1962 Assert(!pCpu->fFlushTLB);
1963 Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
1964
1965 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1966 {
1967 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1968 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1969 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1970 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1971 }
1972 }
1973 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1974 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1975
1976 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1977 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1978 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1979
1980 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1981 AssertRC(rc);
1982
1983 if (pVCpu->hwaccm.s.fForceTLBFlush)
1984 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1985
1986#ifdef VBOX_WITH_STATISTICS
1987 if (pVCpu->hwaccm.s.fForceTLBFlush)
1988 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1989 else
1990 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1991#endif
1992}
1993#endif /* HWACCM_VTX_WITH_VPID */
1994
1995/**
1996 * Runs guest code in a VT-x VM.
1997 *
1998 * @returns VBox status code.
1999 * @param pVM The VM to operate on.
2000 * @param pVCpu The VMCPU to operate on.
2001 * @param pCtx Guest context
2002 */
2003VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2004{
2005 int rc = VINF_SUCCESS;
2006 RTGCUINTREG val;
2007 RTGCUINTREG exitReason = VMX_EXIT_INVALID;
2008 RTGCUINTREG instrError, cbInstr;
2009 RTGCUINTPTR exitQualification = 0;
2010 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
2011 RTGCUINTPTR errCode, instrInfo;
2012 bool fSetupTPRCaching = false;
2013 uint8_t u8LastTPR = 0;
2014 PHWACCM_CPUINFO pCpu = 0;
2015 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
2016 unsigned cResume = 0;
2017#ifdef VBOX_STRICT
2018 RTCPUID idCpuCheck;
2019#endif
2020#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2021 uint64_t u64LastTime = RTTimeMilliTS();
2022#endif
2023#ifdef VBOX_WITH_STATISTICS
2024 bool fStatEntryStarted = true;
2025 bool fStatExit2Started = false;
2026#endif
2027
2028 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
2029
2030 /* Check if we need to use TPR shadowing. */
2031 if ( CPUMIsGuestInLongModeEx(pCtx)
2032 || ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2033 && pVM->hwaccm.s.fHasIoApic)
2034 )
2035 {
2036 fSetupTPRCaching = true;
2037 }
2038
2039 Log2(("\nE"));
2040
2041 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
2042
2043#ifdef VBOX_STRICT
2044 {
2045 RTCCUINTREG val;
2046
2047 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
2048 AssertRC(rc);
2049 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
2050
2051 /* allowed zero */
2052 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
2053 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
2054
2055 /* allowed one */
2056 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
2057 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
2058
2059 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
2060 AssertRC(rc);
2061 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
2062
2063 /* Must be set according to the MSR, but can be cleared in case of EPT. */
2064 if (pVM->hwaccm.s.fNestedPaging)
2065 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
2066 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2067 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2068
2069 /* allowed zero */
2070 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2071 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2072
2073 /* allowed one */
2074 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2075 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2076
2077 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2078 AssertRC(rc);
2079 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2080
2081 /* allowed zero */
2082 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2083 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2084
2085 /* allowed one */
2086 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2087 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2088
2089 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2090 AssertRC(rc);
2091 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2092
2093 /* allowed zero */
2094 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2095 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2096
2097 /* allowed one */
2098 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2099 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2100 }
2101#endif
2102
2103#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2104 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2105#endif
2106
2107 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2108 */
2109ResumeExecution:
2110 STAM_STATS({
2111 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2112 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2113 });
2114 AssertMsg(pVCpu->idHostCpu == RTMpCpuId(),
2115 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2116 (int)pVCpu->idHostCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2117 Assert(!HWACCMR0SuspendPending());
2118
2119 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2120 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
2121 {
2122 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2123 rc = VINF_EM_RAW_INTERRUPT;
2124 goto end;
2125 }
2126
2127 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2128 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2129 {
2130 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2131 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2132 {
2133 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2134 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2135 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2136 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2137 */
2138 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2139 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2140 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2141 AssertRC(rc);
2142 }
2143 }
2144 else
2145 {
2146 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2147 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2148 AssertRC(rc);
2149 }
2150
2151#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2152 if (RT_UNLIKELY(cResume & 0xf) == 0)
2153 {
2154 uint64_t u64CurTime = RTTimeMilliTS();
2155
2156 if (RT_UNLIKELY(u64CurTime > u64LastTime))
2157 {
2158 u64LastTime = u64CurTime;
2159 TMTimerPollVoid(pVM, pVCpu);
2160 }
2161 }
2162#endif
2163
2164 /* Check for pending actions that force us to go back to ring 3. */
2165#ifdef DEBUG
2166 /* Intercept X86_XCPT_DB if stepping is enabled */
2167 if (!DBGFIsStepping(pVCpu))
2168#endif
2169 {
2170 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2171 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2172 {
2173 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2174 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2175 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2176 goto end;
2177 }
2178 }
2179
2180 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2181 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2182 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2183 {
2184 rc = VINF_EM_PENDING_REQUEST;
2185 goto end;
2186 }
2187
2188#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2189 /*
2190 * Exit to ring-3 preemption/work is pending.
2191 *
2192 * Interrupts are disabled before the call to make sure we don't miss any interrupt
2193 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
2194 * further down, but VMXR0CheckPendingInterrupt makes that impossible.)
2195 *
2196 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
2197 * shootdowns rely on this.
2198 */
2199 uOldEFlags = ASMIntDisableFlags();
2200 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2201 {
2202 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
2203 rc = VINF_EM_RAW_INTERRUPT;
2204 goto end;
2205 }
2206 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2207#endif
2208
2209 /* When external interrupts are pending, we should exit the VM when IF is set. */
2210 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2211 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2212 if (RT_FAILURE(rc))
2213 goto end;
2214
2215 /** @todo check timers?? */
2216
2217 /* TPR caching using CR8 is only available in 64 bits mode */
2218 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2219 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2220 /**
2221 * @todo query and update the TPR only when it could have been changed (mmio access & wrmsr (x2apic))
2222 */
2223 if (fSetupTPRCaching)
2224 {
2225 /* TPR caching in CR8 */
2226 bool fPending;
2227
2228 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
2229 AssertRC(rc);
2230 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2231 pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8LastTPR;
2232
2233 /* Two options here:
2234 * - external interrupt pending, but masked by the TPR value.
2235 * -> a CR8 update that lower the current TPR value should cause an exit
2236 * - no pending interrupts
2237 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2238 */
2239 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
2240 AssertRC(rc);
2241 }
2242
2243#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2244 if ( pVM->hwaccm.s.fNestedPaging
2245# ifdef HWACCM_VTX_WITH_VPID
2246 || pVM->hwaccm.s.vmx.fVPID
2247# endif /* HWACCM_VTX_WITH_VPID */
2248 )
2249 {
2250 pCpu = HWACCMR0GetCurrentCpu();
2251 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2252 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2253 {
2254 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2255 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2256 else
2257 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2258 }
2259 if (pCpu->fFlushTLB)
2260 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2261 else
2262 if (pVCpu->hwaccm.s.fForceTLBFlush)
2263 LogFlow(("Manual TLB flush\n"));
2264 }
2265#endif
2266#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2267 PGMDynMapFlushAutoSet(pVCpu);
2268#endif
2269
2270 /*
2271 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2272 * (until the actual world switch)
2273 */
2274#ifdef VBOX_STRICT
2275 idCpuCheck = RTMpCpuId();
2276#endif
2277#ifdef LOG_ENABLED
2278 VMMR0LogFlushDisable(pVCpu);
2279#endif
2280 /* Save the host state first. */
2281 rc = VMXR0SaveHostState(pVM, pVCpu);
2282 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2283 {
2284 VMMR0LogFlushEnable(pVCpu);
2285 goto end;
2286 }
2287 /* Load the guest state */
2288 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2289 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2290 {
2291 VMMR0LogFlushEnable(pVCpu);
2292 goto end;
2293 }
2294
2295#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2296 /* Disable interrupts to make sure a poke will interrupt execution.
2297 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
2298 */
2299 uOldEFlags = ASMIntDisableFlags();
2300 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2301#endif
2302
2303 /* Deal with tagged TLB setup and invalidation. */
2304 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2305
2306 /* Non-register state Guest Context */
2307 /** @todo change me according to cpu state */
2308 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2309 AssertRC(rc);
2310
2311 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2312
2313 /* Manual save and restore:
2314 * - General purpose registers except RIP, RSP
2315 *
2316 * Trashed:
2317 * - CR2 (we don't care)
2318 * - LDTR (reset to 0)
2319 * - DRx (presumably not changed at all)
2320 * - DR7 (reset to 0x400)
2321 * - EFLAGS (reset to RT_BIT(1); not relevant)
2322 *
2323 */
2324
2325
2326 /* All done! Let's start VM execution. */
2327 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2328 Assert(idCpuCheck == RTMpCpuId());
2329
2330#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2331 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2332 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2333#endif
2334
2335 TMNotifyStartOfExecution(pVCpu);
2336 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2337 TMNotifyEndOfExecution(pVCpu);
2338 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2339 Assert(!(ASMGetFlags() & X86_EFL_IF));
2340 ASMSetFlags(uOldEFlags);
2341#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2342 uOldEFlags = ~(RTCCUINTREG)0;
2343#endif
2344
2345 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2346
2347 /* In case we execute a goto ResumeExecution later on. */
2348 pVCpu->hwaccm.s.fResumeVM = true;
2349 pVCpu->hwaccm.s.fForceTLBFlush = false;
2350
2351 /*
2352 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2353 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2354 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2355 */
2356 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2357 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2358
2359 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2360 {
2361 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2362 VMMR0LogFlushEnable(pVCpu);
2363 goto end;
2364 }
2365
2366 /* Success. Query the guest state and figure out what has happened. */
2367
2368 /* Investigate why there was a VM-exit. */
2369 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2370 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2371
2372 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2373 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2374 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2375 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2376 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2377 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2378 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2379 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2380 AssertRC(rc);
2381
2382 /* Sync back the guest state */
2383 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2384 AssertRC(rc);
2385
2386 /* Note! NOW IT'S SAFE FOR LOGGING! */
2387 VMMR0LogFlushEnable(pVCpu);
2388 Log2(("Raw exit reason %08x\n", exitReason));
2389
2390 /* Check if an injected event was interrupted prematurely. */
2391 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2392 AssertRC(rc);
2393 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2394 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2395 /* Ignore 'int xx' as they'll be restarted anyway. */
2396 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2397 /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
2398 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2399 {
2400 Assert(!pVCpu->hwaccm.s.Event.fPending);
2401 pVCpu->hwaccm.s.Event.fPending = true;
2402 /* Error code present? */
2403 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2404 {
2405 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2406 AssertRC(rc);
2407 pVCpu->hwaccm.s.Event.errCode = val;
2408 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2409 }
2410 else
2411 {
2412 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2413 pVCpu->hwaccm.s.Event.errCode = 0;
2414 }
2415 }
2416#ifdef VBOX_STRICT
2417 else
2418 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2419 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2420 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2421 {
2422 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2423 }
2424
2425 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2426 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2427#endif
2428
2429 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2430 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2431 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2432 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2433 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2434
2435 /* Sync back the TPR if it was changed. */
2436 if ( fSetupTPRCaching
2437 && u8LastTPR != pVCpu->hwaccm.s.vmx.pVAPIC[0x80])
2438 {
2439 rc = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);
2440 AssertRC(rc);
2441 }
2442
2443 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2444 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2445
2446 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2447 switch (exitReason)
2448 {
2449 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2450 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2451 {
2452 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2453
2454 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2455 {
2456 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2457 /* External interrupt; leave to allow it to be dispatched again. */
2458 rc = VINF_EM_RAW_INTERRUPT;
2459 break;
2460 }
2461 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2462 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2463 {
2464 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2465 /* External interrupt; leave to allow it to be dispatched again. */
2466 rc = VINF_EM_RAW_INTERRUPT;
2467 break;
2468
2469 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2470 AssertFailed(); /* can't come here; fails the first check. */
2471 break;
2472
2473 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2474 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2475 Assert(vector == 1 || vector == 3 || vector == 4);
2476 /* no break */
2477 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2478 Log2(("Hardware/software interrupt %d\n", vector));
2479 switch (vector)
2480 {
2481 case X86_XCPT_NM:
2482 {
2483 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2484
2485 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2486 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2487 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2488 if (rc == VINF_SUCCESS)
2489 {
2490 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2491
2492 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2493
2494 /* Continue execution. */
2495 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2496
2497 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2498 goto ResumeExecution;
2499 }
2500
2501 Log(("Forward #NM fault to the guest\n"));
2502 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2503 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2504 AssertRC(rc);
2505 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2506 goto ResumeExecution;
2507 }
2508
2509 case X86_XCPT_PF: /* Page fault */
2510 {
2511#ifdef DEBUG
2512 if (pVM->hwaccm.s.fNestedPaging)
2513 { /* A genuine pagefault.
2514 * Forward the trap to the guest by injecting the exception and resuming execution.
2515 */
2516 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2517
2518 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2519
2520 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2521
2522 /* Now we must update CR2. */
2523 pCtx->cr2 = exitQualification;
2524 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2525 AssertRC(rc);
2526
2527 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2528 goto ResumeExecution;
2529 }
2530#endif
2531 Assert(!pVM->hwaccm.s.fNestedPaging);
2532
2533 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2534 /* Exit qualification contains the linear address of the page fault. */
2535 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2536 TRPMSetErrorCode(pVCpu, errCode);
2537 TRPMSetFaultAddress(pVCpu, exitQualification);
2538
2539 /* Shortcut for APIC TPR reads and writes. */
2540 if ( (exitQualification & 0xfff) == 0x080
2541 && !(errCode & X86_TRAP_PF_P) /* not present */
2542 && fSetupTPRCaching
2543 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
2544 {
2545 RTGCPHYS GCPhysApicBase, GCPhys;
2546 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
2547 GCPhysApicBase &= PAGE_BASE_GC_MASK;
2548
2549 rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
2550 if ( rc == VINF_SUCCESS
2551 && GCPhys == GCPhysApicBase)
2552 {
2553 Log(("Enable VT-x virtual APIC access filtering\n"));
2554 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
2555 AssertRC(rc);
2556 }
2557 }
2558
2559 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2560 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2561 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2562 if (rc == VINF_SUCCESS)
2563 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2564 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2565 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2566
2567 TRPMResetTrap(pVCpu);
2568
2569 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2570 goto ResumeExecution;
2571 }
2572 else
2573 if (rc == VINF_EM_RAW_GUEST_TRAP)
2574 { /* A genuine pagefault.
2575 * Forward the trap to the guest by injecting the exception and resuming execution.
2576 */
2577 Log2(("Forward page fault to the guest\n"));
2578
2579 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2580 /* The error code might have been changed. */
2581 errCode = TRPMGetErrorCode(pVCpu);
2582
2583 TRPMResetTrap(pVCpu);
2584
2585 /* Now we must update CR2. */
2586 pCtx->cr2 = exitQualification;
2587 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2588 AssertRC(rc);
2589
2590 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2591 goto ResumeExecution;
2592 }
2593#ifdef VBOX_STRICT
2594 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2595 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2596#endif
2597 /* Need to go back to the recompiler to emulate the instruction. */
2598 TRPMResetTrap(pVCpu);
2599 break;
2600 }
2601
2602 case X86_XCPT_MF: /* Floating point exception. */
2603 {
2604 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2605 if (!(pCtx->cr0 & X86_CR0_NE))
2606 {
2607 /* old style FPU error reporting needs some extra work. */
2608 /** @todo don't fall back to the recompiler, but do it manually. */
2609 rc = VINF_EM_RAW_EMULATE_INSTR;
2610 break;
2611 }
2612 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2613 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2614 AssertRC(rc);
2615
2616 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2617 goto ResumeExecution;
2618 }
2619
2620 case X86_XCPT_DB: /* Debug exception. */
2621 {
2622 uint64_t uDR6;
2623
2624 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2625 *
2626 * Exit qualification bits:
2627 * 3:0 B0-B3 which breakpoint condition was met
2628 * 12:4 Reserved (0)
2629 * 13 BD - debug register access detected
2630 * 14 BS - single step execution or branch taken
2631 * 63:15 Reserved (0)
2632 */
2633 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2634
2635 /* Note that we don't support guest and host-initiated debugging at the same time. */
2636 Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx));
2637
2638 uDR6 = X86_DR6_INIT_VAL;
2639 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2640 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
2641 if (rc == VINF_EM_RAW_GUEST_TRAP)
2642 {
2643 /** @todo this isn't working, but we'll never get here normally. */
2644
2645 /* Update DR6 here. */
2646 pCtx->dr[6] = uDR6;
2647
2648 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2649 pCtx->dr[7] &= ~X86_DR7_GD;
2650
2651 /* Paranoia. */
2652 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2653 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2654 pCtx->dr[7] |= 0x400; /* must be one */
2655
2656 /* Resync DR7 */
2657 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2658 AssertRC(rc);
2659
2660 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2661 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2662 AssertRC(rc);
2663
2664 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2665 goto ResumeExecution;
2666 }
2667 /* Return to ring 3 to deal with the debug exit code. */
2668 break;
2669 }
2670
2671 case X86_XCPT_BP: /* Breakpoint. */
2672 {
2673 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2674 if (rc == VINF_EM_RAW_GUEST_TRAP)
2675 {
2676 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2677 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2678 AssertRC(rc);
2679 goto ResumeExecution;
2680 }
2681 if (rc == VINF_SUCCESS)
2682 goto ResumeExecution;
2683 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2684 break;
2685 }
2686
2687 case X86_XCPT_GP: /* General protection failure exception.*/
2688 {
2689 uint32_t cbOp;
2690 uint32_t cbSize;
2691 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2692
2693 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2694#ifdef VBOX_STRICT
2695 if (!CPUMIsGuestInRealModeEx(pCtx))
2696 {
2697 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2698 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2699 AssertRC(rc);
2700 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2701 goto ResumeExecution;
2702 }
2703#endif
2704 Assert(CPUMIsGuestInRealModeEx(pCtx));
2705
2706 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2707
2708 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2709 if (RT_SUCCESS(rc))
2710 {
2711 bool fUpdateRIP = true;
2712
2713 Assert(cbOp == pDis->opsize);
2714 switch (pDis->pCurInstr->opcode)
2715 {
2716 case OP_CLI:
2717 pCtx->eflags.Bits.u1IF = 0;
2718 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2719 break;
2720
2721 case OP_STI:
2722 pCtx->eflags.Bits.u1IF = 1;
2723 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2724 break;
2725
2726 case OP_HLT:
2727 fUpdateRIP = false;
2728 rc = VINF_EM_HALT;
2729 pCtx->rip += pDis->opsize;
2730 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2731 break;
2732
2733 case OP_POPF:
2734 {
2735 RTGCPTR GCPtrStack;
2736 uint32_t cbParm;
2737 uint32_t uMask;
2738 X86EFLAGS eflags;
2739
2740 if (pDis->prefix & PREFIX_OPSIZE)
2741 {
2742 cbParm = 4;
2743 uMask = 0xffffffff;
2744 }
2745 else
2746 {
2747 cbParm = 2;
2748 uMask = 0xffff;
2749 }
2750
2751 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2752 if (RT_FAILURE(rc))
2753 {
2754 rc = VERR_EM_INTERPRETER;
2755 break;
2756 }
2757 eflags.u = 0;
2758 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2759 if (RT_FAILURE(rc))
2760 {
2761 rc = VERR_EM_INTERPRETER;
2762 break;
2763 }
2764 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2765 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
2766 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
2767 pCtx->eflags.Bits.u1RF = 0;
2768 pCtx->esp += cbParm;
2769 pCtx->esp &= uMask;
2770
2771 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2772 break;
2773 }
2774
2775 case OP_PUSHF:
2776 {
2777 RTGCPTR GCPtrStack;
2778 uint32_t cbParm;
2779 uint32_t uMask;
2780 X86EFLAGS eflags;
2781
2782 if (pDis->prefix & PREFIX_OPSIZE)
2783 {
2784 cbParm = 4;
2785 uMask = 0xffffffff;
2786 }
2787 else
2788 {
2789 cbParm = 2;
2790 uMask = 0xffff;
2791 }
2792
2793 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2794 if (RT_FAILURE(rc))
2795 {
2796 rc = VERR_EM_INTERPRETER;
2797 break;
2798 }
2799 eflags = pCtx->eflags;
2800 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2801 eflags.Bits.u1RF = 0;
2802 eflags.Bits.u1VM = 0;
2803
2804 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2805 if (RT_FAILURE(rc))
2806 {
2807 rc = VERR_EM_INTERPRETER;
2808 break;
2809 }
2810 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2811 pCtx->esp -= cbParm;
2812 pCtx->esp &= uMask;
2813 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2814 break;
2815 }
2816
2817 case OP_IRET:
2818 {
2819 RTGCPTR GCPtrStack;
2820 uint32_t uMask = 0xffff;
2821 uint16_t aIretFrame[3];
2822
2823 if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
2824 {
2825 rc = VERR_EM_INTERPRETER;
2826 break;
2827 }
2828
2829 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2830 if (RT_FAILURE(rc))
2831 {
2832 rc = VERR_EM_INTERPRETER;
2833 break;
2834 }
2835 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2836 if (RT_FAILURE(rc))
2837 {
2838 rc = VERR_EM_INTERPRETER;
2839 break;
2840 }
2841 pCtx->ip = aIretFrame[0];
2842 pCtx->cs = aIretFrame[1];
2843 pCtx->csHid.u64Base = pCtx->cs << 4;
2844 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2845 pCtx->sp += sizeof(aIretFrame);
2846
2847 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2848 fUpdateRIP = false;
2849 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2850 break;
2851 }
2852
2853 case OP_INT:
2854 {
2855 RTGCUINTPTR intInfo;
2856
2857 LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
2858 intInfo = pDis->param1.parval & 0xff;
2859 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2860 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2861
2862 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2863 AssertRC(rc);
2864 fUpdateRIP = false;
2865 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2866 break;
2867 }
2868
2869 case OP_INTO:
2870 {
2871 if (pCtx->eflags.Bits.u1OF)
2872 {
2873 RTGCUINTPTR intInfo;
2874
2875 LogFlow(("Realmode: INTO\n"));
2876 intInfo = X86_XCPT_OF;
2877 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2878 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2879
2880 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2881 AssertRC(rc);
2882 fUpdateRIP = false;
2883 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2884 }
2885 break;
2886 }
2887
2888 case OP_INT3:
2889 {
2890 RTGCUINTPTR intInfo;
2891
2892 LogFlow(("Realmode: INT 3\n"));
2893 intInfo = 3;
2894 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2895 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2896
2897 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2898 AssertRC(rc);
2899 fUpdateRIP = false;
2900 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2901 break;
2902 }
2903
2904 default:
2905 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
2906 break;
2907 }
2908
2909 if (rc == VINF_SUCCESS)
2910 {
2911 if (fUpdateRIP)
2912 pCtx->rip += cbOp; /* Move on to the next instruction. */
2913
2914 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2915 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2916
2917 /* Only resume if successful. */
2918 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2919 goto ResumeExecution;
2920 }
2921 }
2922 else
2923 rc = VERR_EM_INTERPRETER;
2924
2925 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2926 break;
2927 }
2928
2929#ifdef VBOX_STRICT
2930 case X86_XCPT_DE: /* Divide error. */
2931 case X86_XCPT_UD: /* Unknown opcode exception. */
2932 case X86_XCPT_SS: /* Stack segment exception. */
2933 case X86_XCPT_NP: /* Segment not present exception. */
2934 {
2935 switch(vector)
2936 {
2937 case X86_XCPT_DE:
2938 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2939 break;
2940 case X86_XCPT_UD:
2941 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2942 break;
2943 case X86_XCPT_SS:
2944 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2945 break;
2946 case X86_XCPT_NP:
2947 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2948 break;
2949 }
2950
2951 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2952 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2953 AssertRC(rc);
2954
2955 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2956 goto ResumeExecution;
2957 }
2958#endif
2959 default:
2960#ifdef HWACCM_VMX_EMULATE_REALMODE
2961 if (CPUMIsGuestInRealModeEx(pCtx))
2962 {
2963 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2964 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2965 AssertRC(rc);
2966
2967 /* Go back to ring 3 in case of a triple fault. */
2968 if ( vector == X86_XCPT_DF
2969 && rc == VINF_EM_RESET)
2970 break;
2971
2972 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2973 goto ResumeExecution;
2974 }
2975#endif
2976 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2977 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2978 break;
2979 } /* switch (vector) */
2980
2981 break;
2982
2983 default:
2984 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2985 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2986 break;
2987 }
2988
2989 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2990 break;
2991 }
2992
2993 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2994 {
2995 RTGCPHYS GCPhys;
2996
2997 Assert(pVM->hwaccm.s.fNestedPaging);
2998
2999 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3000 AssertRC(rc);
3001 Assert(((exitQualification >> 7) & 3) != 2);
3002
3003 /* Determine the kind of violation. */
3004 errCode = 0;
3005 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
3006 errCode |= X86_TRAP_PF_ID;
3007
3008 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
3009 errCode |= X86_TRAP_PF_RW;
3010
3011 /* If the page is present, then it's a page level protection fault. */
3012 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
3013 {
3014 errCode |= X86_TRAP_PF_P;
3015 }
3016 else {
3017 /* Shortcut for APIC TPR reads and writes. */
3018 if ( (GCPhys & 0xfff) == 0x080
3019 && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
3020 && fSetupTPRCaching
3021 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
3022 {
3023 RTGCPHYS GCPhysApicBase;
3024 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
3025 GCPhysApicBase &= PAGE_BASE_GC_MASK;
3026 if (GCPhys == GCPhysApicBase + 0x80)
3027 {
3028 Log(("Enable VT-x virtual APIC access filtering\n"));
3029 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
3030 AssertRC(rc);
3031 }
3032 }
3033 }
3034 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
3035
3036 /* GCPhys contains the guest physical address of the page fault. */
3037 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
3038 TRPMSetErrorCode(pVCpu, errCode);
3039 TRPMSetFaultAddress(pVCpu, GCPhys);
3040
3041 /* Handle the pagefault trap for the nested shadow table. */
3042 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
3043 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
3044 if (rc == VINF_SUCCESS)
3045 { /* We've successfully synced our shadow pages, so let's just continue execution. */
3046 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
3047 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
3048
3049 TRPMResetTrap(pVCpu);
3050
3051 goto ResumeExecution;
3052 }
3053
3054#ifdef VBOX_STRICT
3055 if (rc != VINF_EM_RAW_EMULATE_INSTR)
3056 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
3057#endif
3058 /* Need to go back to the recompiler to emulate the instruction. */
3059 TRPMResetTrap(pVCpu);
3060 break;
3061 }
3062
3063 case VMX_EXIT_EPT_MISCONFIG:
3064 {
3065 RTGCPHYS GCPhys;
3066
3067 Assert(pVM->hwaccm.s.fNestedPaging);
3068
3069 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3070 AssertRC(rc);
3071
3072 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
3073 break;
3074 }
3075
3076 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3077 /* Clear VM-exit on IF=1 change. */
3078 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
3079 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
3080 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3081 AssertRC(rc);
3082 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
3083 goto ResumeExecution; /* we check for pending guest interrupts there */
3084
3085 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
3086 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
3087 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
3088 /* Skip instruction and continue directly. */
3089 pCtx->rip += cbInstr;
3090 /* Continue execution.*/
3091 goto ResumeExecution;
3092
3093 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3094 {
3095 Log2(("VMX: Cpuid %x\n", pCtx->eax));
3096 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
3097 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3098 if (rc == VINF_SUCCESS)
3099 {
3100 /* Update EIP and continue execution. */
3101 Assert(cbInstr == 2);
3102 pCtx->rip += cbInstr;
3103 goto ResumeExecution;
3104 }
3105 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
3106 rc = VINF_EM_RAW_EMULATE_INSTR;
3107 break;
3108 }
3109
3110 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3111 {
3112 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
3113 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
3114 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3115 if (rc == VINF_SUCCESS)
3116 {
3117 /* Update EIP and continue execution. */
3118 Assert(cbInstr == 2);
3119 pCtx->rip += cbInstr;
3120 goto ResumeExecution;
3121 }
3122 rc = VINF_EM_RAW_EMULATE_INSTR;
3123 break;
3124 }
3125
3126 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3127 {
3128 Log2(("VMX: Rdtsc\n"));
3129 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
3130 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3131 if (rc == VINF_SUCCESS)
3132 {
3133 /* Update EIP and continue execution. */
3134 Assert(cbInstr == 2);
3135 pCtx->rip += cbInstr;
3136 goto ResumeExecution;
3137 }
3138 rc = VINF_EM_RAW_EMULATE_INSTR;
3139 break;
3140 }
3141
3142 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3143 {
3144 Log2(("VMX: invlpg\n"));
3145 Assert(!pVM->hwaccm.s.fNestedPaging);
3146
3147 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
3148 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
3149 if (rc == VINF_SUCCESS)
3150 {
3151 /* Update EIP and continue execution. */
3152 pCtx->rip += cbInstr;
3153 goto ResumeExecution;
3154 }
3155 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
3156 break;
3157 }
3158
3159 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3160 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3161 {
3162 uint32_t cbSize;
3163
3164 STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
3165
3166 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3167 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3168 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3169 if (rc == VINF_SUCCESS)
3170 {
3171 /* EIP has been updated already. */
3172
3173 /* Only resume if successful. */
3174 goto ResumeExecution;
3175 }
3176 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
3177 break;
3178 }
3179
3180 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3181 {
3182 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3183
3184 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3185 {
3186 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3187 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3188 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3189 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3190 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3191 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3192
3193 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3194 {
3195 case 0:
3196 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3197 break;
3198 case 2:
3199 break;
3200 case 3:
3201 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3202 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3203 break;
3204 case 4:
3205 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3206 break;
3207 case 8:
3208 /* CR8 contains the APIC TPR */
3209 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3210 break;
3211
3212 default:
3213 AssertFailed();
3214 break;
3215 }
3216 /* Check if a sync operation is pending. */
3217 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3218 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3219 {
3220 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3221 AssertRC(rc);
3222 }
3223 break;
3224
3225 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3226 Log2(("VMX: mov x, crx\n"));
3227 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3228
3229 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3230
3231 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3232 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3233
3234 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3235 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3236 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3237 break;
3238
3239 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3240 Log2(("VMX: clts\n"));
3241 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3242 rc = EMInterpretCLTS(pVM, pVCpu);
3243 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3244 break;
3245
3246 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3247 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3248 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3249 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3250 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3251 break;
3252 }
3253
3254 /* Update EIP if no error occurred. */
3255 if (RT_SUCCESS(rc))
3256 pCtx->rip += cbInstr;
3257
3258 if (rc == VINF_SUCCESS)
3259 {
3260 /* Only resume if successful. */
3261 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3262 goto ResumeExecution;
3263 }
3264 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3265 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3266 break;
3267 }
3268
3269 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3270 {
3271 if (!DBGFIsStepping(pVCpu))
3272 {
3273 /* Disable drx move intercepts. */
3274 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3275 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3276 AssertRC(rc);
3277
3278 /* Save the host and load the guest debug state. */
3279 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3280 AssertRC(rc);
3281
3282#ifdef VBOX_WITH_STATISTICS
3283 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3284 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3285 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3286 else
3287 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3288#endif
3289
3290 goto ResumeExecution;
3291 }
3292
3293 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3294 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3295 {
3296 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3297 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3298 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3299 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3300 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3301 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3302 Log2(("DR7=%08x\n", pCtx->dr[7]));
3303 }
3304 else
3305 {
3306 Log2(("VMX: mov x, drx\n"));
3307 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3308 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3309 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3310 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3311 }
3312 /* Update EIP if no error occurred. */
3313 if (RT_SUCCESS(rc))
3314 pCtx->rip += cbInstr;
3315
3316 if (rc == VINF_SUCCESS)
3317 {
3318 /* Only resume if successful. */
3319 goto ResumeExecution;
3320 }
3321 Assert(rc == VERR_EM_INTERPRETER);
3322 break;
3323 }
3324
3325 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3326 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3327 {
3328 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3329 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3330 uint32_t uPort;
3331 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3332
3333 /** @todo necessary to make the distinction? */
3334 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3335 {
3336 uPort = pCtx->edx & 0xffff;
3337 }
3338 else
3339 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3340
3341 /* paranoia */
3342 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3343 {
3344 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3345 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3346 break;
3347 }
3348
3349 uint32_t cbSize = g_aIOSize[uIOWidth];
3350
3351 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3352 {
3353 /* ins/outs */
3354 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
3355
3356 /* Disassemble manually to deal with segment prefixes. */
3357 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3358 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3359 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
3360 if (rc == VINF_SUCCESS)
3361 {
3362 if (fIOWrite)
3363 {
3364 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3365 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3366 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3367 }
3368 else
3369 {
3370 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3371 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3372 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3373 }
3374 }
3375 else
3376 rc = VINF_EM_RAW_EMULATE_INSTR;
3377 }
3378 else
3379 {
3380 /* normal in/out */
3381 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3382
3383 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3384
3385 if (fIOWrite)
3386 {
3387 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3388 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3389 }
3390 else
3391 {
3392 uint32_t u32Val = 0;
3393
3394 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3395 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3396 if (IOM_SUCCESS(rc))
3397 {
3398 /* Write back to the EAX register. */
3399 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3400 }
3401 }
3402 }
3403 /*
3404 * Handled the I/O return codes.
3405 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3406 */
3407 if (IOM_SUCCESS(rc))
3408 {
3409 /* Update EIP and continue execution. */
3410 pCtx->rip += cbInstr;
3411 if (RT_LIKELY(rc == VINF_SUCCESS))
3412 {
3413 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3414 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3415 {
3416 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3417 for (unsigned i=0;i<4;i++)
3418 {
3419 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3420
3421 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3422 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3423 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3424 {
3425 uint64_t uDR6;
3426
3427 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3428
3429 uDR6 = ASMGetDR6();
3430
3431 /* Clear all breakpoint status flags and set the one we just hit. */
3432 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3433 uDR6 |= (uint64_t)RT_BIT(i);
3434
3435 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3436 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3437 * the contents have been read.
3438 */
3439 ASMSetDR6(uDR6);
3440
3441 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3442 pCtx->dr[7] &= ~X86_DR7_GD;
3443
3444 /* Paranoia. */
3445 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3446 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3447 pCtx->dr[7] |= 0x400; /* must be one */
3448
3449 /* Resync DR7 */
3450 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3451 AssertRC(rc);
3452
3453 /* Construct inject info. */
3454 intInfo = X86_XCPT_DB;
3455 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3456 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3457
3458 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3459 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3460 AssertRC(rc);
3461
3462 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3463 goto ResumeExecution;
3464 }
3465 }
3466 }
3467
3468 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3469 goto ResumeExecution;
3470 }
3471 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3472 break;
3473 }
3474
3475#ifdef VBOX_STRICT
3476 if (rc == VINF_IOM_HC_IOPORT_READ)
3477 Assert(!fIOWrite);
3478 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3479 Assert(fIOWrite);
3480 else
3481 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3482#endif
3483 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3484 break;
3485 }
3486
3487 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3488 LogFlow(("VMX_EXIT_TPR\n"));
3489 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3490 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3491 goto ResumeExecution;
3492
3493 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3494 {
3495 LogFlow(("VMX_EXIT_APIC_ACCESS\n"));
3496 unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
3497
3498 switch(uAccessType)
3499 {
3500 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
3501 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
3502 {
3503 RTGCPHYS GCPhys;
3504 PDMApicGetBase(pVM, &GCPhys);
3505 GCPhys &= PAGE_BASE_GC_MASK;
3506 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
3507
3508 LogFlow(("Apic access at %RGp\n", GCPhys));
3509 rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
3510 if (rc == VINF_SUCCESS)
3511 {
3512 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3513 goto ResumeExecution; /* rip already updated */
3514 }
3515 break;
3516 }
3517
3518 default:
3519 rc = VINF_EM_RAW_EMULATE_INSTR;
3520 break;
3521 }
3522 break;
3523 }
3524
3525 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3526 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3527 goto ResumeExecution;
3528
3529 default:
3530 /* The rest is handled after syncing the entire CPU state. */
3531 break;
3532 }
3533
3534 /* Note: the guest state isn't entirely synced back at this stage. */
3535
3536 /* Investigate why there was a VM-exit. (part 2) */
3537 switch (exitReason)
3538 {
3539 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3540 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3541 case VMX_EXIT_EPT_VIOLATION:
3542 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3543 /* Already handled above. */
3544 break;
3545
3546 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3547 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3548 break;
3549
3550 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3551 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3552 rc = VINF_EM_RAW_INTERRUPT;
3553 AssertFailed(); /* Can't happen. Yet. */
3554 break;
3555
3556 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3557 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3558 rc = VINF_EM_RAW_INTERRUPT;
3559 AssertFailed(); /* Can't happen afaik. */
3560 break;
3561
3562 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3563 rc = VERR_EM_INTERPRETER;
3564 break;
3565
3566 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3567 /** Check if external interrupts are pending; if so, don't switch back. */
3568 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
3569 pCtx->rip++; /* skip hlt */
3570 if ( pCtx->eflags.Bits.u1IF
3571 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3572 goto ResumeExecution;
3573
3574 rc = VINF_EM_HALT;
3575 break;
3576
3577 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3578 Log2(("VMX: mwait\n"));
3579 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
3580 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3581 if ( rc == VINF_EM_HALT
3582 || rc == VINF_SUCCESS)
3583 {
3584 /* Update EIP and continue execution. */
3585 pCtx->rip += cbInstr;
3586
3587 /** Check if external interrupts are pending; if so, don't switch back. */
3588 if ( rc == VINF_SUCCESS
3589 || ( rc == VINF_EM_HALT
3590 && pCtx->eflags.Bits.u1IF
3591 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3592 )
3593 goto ResumeExecution;
3594 }
3595 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
3596 break;
3597
3598 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3599 AssertFailed(); /* can't happen. */
3600 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3601 break;
3602
3603 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3604 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3605 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3606 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3607 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3608 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3609 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3610 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3611 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3612 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3613 /** @todo inject #UD immediately */
3614 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3615 break;
3616
3617 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3618 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3619 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3620 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3621 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3622 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3623 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3624 /* already handled above */
3625 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3626 || rc == VINF_EM_RAW_INTERRUPT
3627 || rc == VERR_EM_INTERPRETER
3628 || rc == VINF_EM_RAW_EMULATE_INSTR
3629 || rc == VINF_PGM_SYNC_CR3
3630 || rc == VINF_IOM_HC_IOPORT_READ
3631 || rc == VINF_IOM_HC_IOPORT_WRITE
3632 || rc == VINF_EM_RAW_GUEST_TRAP
3633 || rc == VINF_TRPM_XCPT_DISPATCHED
3634 || rc == VINF_EM_RESCHEDULE_REM,
3635 ("rc = %d\n", rc));
3636 break;
3637
3638 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3639 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3640 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3641 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3642 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3643 rc = VERR_EM_INTERPRETER;
3644 break;
3645
3646 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3647 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3648 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3649 break;
3650
3651 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3652 Assert(rc == VINF_EM_RAW_INTERRUPT);
3653 break;
3654
3655 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3656 {
3657#ifdef VBOX_STRICT
3658 RTCCUINTREG val = 0;
3659
3660 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3661
3662 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3663 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3664
3665 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3666 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3667
3668 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3669 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3670
3671 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3672 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3673
3674 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3675 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3676
3677 VMX_LOG_SELREG(CS, "CS");
3678 VMX_LOG_SELREG(DS, "DS");
3679 VMX_LOG_SELREG(ES, "ES");
3680 VMX_LOG_SELREG(FS, "FS");
3681 VMX_LOG_SELREG(GS, "GS");
3682 VMX_LOG_SELREG(SS, "SS");
3683 VMX_LOG_SELREG(TR, "TR");
3684 VMX_LOG_SELREG(LDTR, "LDTR");
3685
3686 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3687 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3688 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3689 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3690#endif /* VBOX_STRICT */
3691 rc = VERR_VMX_INVALID_GUEST_STATE;
3692 break;
3693 }
3694
3695 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3696 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3697 default:
3698 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3699 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3700 break;
3701
3702 }
3703end:
3704
3705 /* Signal changes for the recompiler. */
3706 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3707
3708 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3709 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3710 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3711 {
3712 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3713 /* On the next entry we'll only sync the host context. */
3714 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3715 }
3716 else
3717 {
3718 /* On the next entry we'll sync everything. */
3719 /** @todo we can do better than this */
3720 /* Not in the VINF_PGM_CHANGE_MODE though! */
3721 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3722 }
3723
3724 /* translate into a less severe return code */
3725 if (rc == VERR_EM_INTERPRETER)
3726 rc = VINF_EM_RAW_EMULATE_INSTR;
3727 else
3728 /* Try to extract more information about what might have gone wrong here. */
3729 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3730 {
3731 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3732 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3733 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->idHostCpu;
3734 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3735 }
3736
3737 /* Just set the correct state here instead of trying to catch every goto above. */
3738 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
3739
3740#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
3741 /* Restore interrupts if we exitted after disabling them. */
3742 if (uOldEFlags != ~(RTCCUINTREG)0)
3743 ASMSetFlags(uOldEFlags);
3744#endif
3745
3746 STAM_STATS({
3747 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3748 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3749 });
3750 Log2(("X"));
3751 return rc;
3752}
3753
3754
3755/**
3756 * Enters the VT-x session
3757 *
3758 * @returns VBox status code.
3759 * @param pVM The VM to operate on.
3760 * @param pVCpu The VMCPU to operate on.
3761 * @param pCpu CPU info struct
3762 */
3763VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3764{
3765 Assert(pVM->hwaccm.s.vmx.fSupported);
3766
3767 unsigned cr4 = ASMGetCR4();
3768 if (!(cr4 & X86_CR4_VMXE))
3769 {
3770 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3771 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3772 }
3773
3774 /* Activate the VM Control Structure. */
3775 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3776 if (RT_FAILURE(rc))
3777 return rc;
3778
3779 pVCpu->hwaccm.s.fResumeVM = false;
3780 return VINF_SUCCESS;
3781}
3782
3783
3784/**
3785 * Leaves the VT-x session
3786 *
3787 * @returns VBox status code.
3788 * @param pVM The VM to operate on.
3789 * @param pVCpu The VMCPU to operate on.
3790 * @param pCtx CPU context
3791 */
3792VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3793{
3794 Assert(pVM->hwaccm.s.vmx.fSupported);
3795
3796 /* Save the guest debug state if necessary. */
3797 if (CPUMIsGuestDebugStateActive(pVCpu))
3798 {
3799 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3800
3801 /* Enable drx move intercepts again. */
3802 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3803 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3804 AssertRC(rc);
3805
3806 /* Resync the debug registers the next time. */
3807 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3808 }
3809 else
3810 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3811
3812 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3813 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3814 AssertRC(rc);
3815
3816 return VINF_SUCCESS;
3817}
3818
3819/**
3820 * Flush the TLB (EPT)
3821 *
3822 * @returns VBox status code.
3823 * @param pVM The VM to operate on.
3824 * @param pVCpu The VM CPU to operate on.
3825 * @param enmFlush Type of flush
3826 * @param GCPhys Physical address of the page to flush
3827 */
3828static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3829{
3830 uint64_t descriptor[2];
3831
3832 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3833 Assert(pVM->hwaccm.s.fNestedPaging);
3834 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3835 descriptor[1] = GCPhys;
3836 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3837 AssertRC(rc);
3838}
3839
3840#ifdef HWACCM_VTX_WITH_VPID
3841/**
3842 * Flush the TLB (EPT)
3843 *
3844 * @returns VBox status code.
3845 * @param pVM The VM to operate on.
3846 * @param pVCpu The VM CPU to operate on.
3847 * @param enmFlush Type of flush
3848 * @param GCPtr Virtual address of the page to flush
3849 */
3850static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3851{
3852#if HC_ARCH_BITS == 32
3853 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3854 if ( CPUMIsGuestInLongMode(pVCpu)
3855 && !VMX_IS_64BIT_HOST_MODE())
3856 {
3857 pVCpu->hwaccm.s.fForceTLBFlush = true;
3858 }
3859 else
3860#endif
3861 {
3862 uint64_t descriptor[2];
3863
3864 Assert(pVM->hwaccm.s.vmx.fVPID);
3865 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3866 descriptor[1] = GCPtr;
3867 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3868 AssertRC(rc);
3869 }
3870}
3871#endif /* HWACCM_VTX_WITH_VPID */
3872
3873/**
3874 * Invalidates a guest page
3875 *
3876 * @returns VBox status code.
3877 * @param pVM The VM to operate on.
3878 * @param pVCpu The VM CPU to operate on.
3879 * @param GCVirt Page to invalidate
3880 */
3881VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3882{
3883 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3884
3885 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3886
3887 /* Only relevant if we want to use VPID.
3888 * In the nested paging case we still see such calls, but
3889 * can safely ignore them. (e.g. after cr3 updates)
3890 */
3891#ifdef HWACCM_VTX_WITH_VPID
3892 /* Skip it if a TLB flush is already pending. */
3893 if ( !fFlushPending
3894 && pVM->hwaccm.s.vmx.fVPID)
3895 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3896#endif /* HWACCM_VTX_WITH_VPID */
3897
3898 return VINF_SUCCESS;
3899}
3900
3901/**
3902 * Invalidates a guest page by physical address
3903 *
3904 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3905 *
3906 * @returns VBox status code.
3907 * @param pVM The VM to operate on.
3908 * @param pVCpu The VM CPU to operate on.
3909 * @param GCPhys Page to invalidate
3910 */
3911VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3912{
3913 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3914
3915 Assert(pVM->hwaccm.s.fNestedPaging);
3916
3917 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3918
3919 /* Skip it if a TLB flush is already pending. */
3920 if (!fFlushPending)
3921 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3922
3923 return VINF_SUCCESS;
3924}
3925
3926/**
3927 * Report world switch error and dump some useful debug info
3928 *
3929 * @param pVM The VM to operate on.
3930 * @param pVCpu The VMCPU to operate on.
3931 * @param rc Return code
3932 * @param pCtx Current CPU context (not updated)
3933 */
3934static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3935{
3936 switch (rc)
3937 {
3938 case VERR_VMX_INVALID_VMXON_PTR:
3939 AssertFailed();
3940 break;
3941
3942 case VERR_VMX_UNABLE_TO_START_VM:
3943 case VERR_VMX_UNABLE_TO_RESUME_VM:
3944 {
3945 int rc;
3946 RTCCUINTREG exitReason, instrError;
3947
3948 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3949 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3950 AssertRC(rc);
3951 if (rc == VINF_SUCCESS)
3952 {
3953 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3954 Log(("Current stack %08x\n", &rc));
3955
3956 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3957 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3958
3959#ifdef VBOX_STRICT
3960 RTGDTR gdtr;
3961 PX86DESCHC pDesc;
3962 RTCCUINTREG val;
3963
3964 ASMGetGDTR(&gdtr);
3965
3966 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3967 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3968 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3969 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3970 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3971 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3972 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3973 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3974 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3975 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3976
3977 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3978 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3979
3980 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3981 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3982
3983 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3984 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3985
3986 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3987 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3988
3989 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3990 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3991
3992 if (val < gdtr.cbGdt)
3993 {
3994 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3995 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3996 }
3997
3998 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3999 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
4000 if (val < gdtr.cbGdt)
4001 {
4002 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4003 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
4004 }
4005
4006 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
4007 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
4008 if (val < gdtr.cbGdt)
4009 {
4010 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4011 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
4012 }
4013
4014 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
4015 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
4016 if (val < gdtr.cbGdt)
4017 {
4018 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4019 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
4020 }
4021
4022 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
4023 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
4024 if (val < gdtr.cbGdt)
4025 {
4026 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4027 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
4028 }
4029
4030 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
4031 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
4032 if (val < gdtr.cbGdt)
4033 {
4034 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4035 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
4036 }
4037
4038 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
4039 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
4040 if (val < gdtr.cbGdt)
4041 {
4042 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4043 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
4044 }
4045
4046 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
4047 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
4048
4049 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
4050 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
4051 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
4052 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
4053
4054 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
4055 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
4056
4057 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
4058 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
4059
4060 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
4061 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
4062
4063 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
4064 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
4065 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
4066 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
4067
4068# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4069 if (VMX_IS_64BIT_HOST_MODE())
4070 {
4071 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
4072 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
4073 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
4074 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
4075 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
4076 }
4077# endif
4078#endif /* VBOX_STRICT */
4079 }
4080 break;
4081 }
4082
4083 default:
4084 /* impossible */
4085 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
4086 break;
4087 }
4088}
4089
4090#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4091/**
4092 * Prepares for and executes VMLAUNCH (64 bits guest mode)
4093 *
4094 * @returns VBox status code
4095 * @param fResume vmlauch/vmresume
4096 * @param pCtx Guest context
4097 * @param pCache VMCS cache
4098 * @param pVM The VM to operate on.
4099 * @param pVCpu The VMCPU to operate on.
4100 */
4101DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
4102{
4103 uint32_t aParam[6];
4104 PHWACCM_CPUINFO pCpu;
4105 RTHCPHYS pPageCpuPhys;
4106 int rc;
4107
4108 pCpu = HWACCMR0GetCurrentCpu();
4109 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4110
4111#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4112 pCache->uPos = 1;
4113 pCache->interPD = PGMGetInterPaeCR3(pVM);
4114 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
4115#endif
4116
4117#ifdef DEBUG
4118 pCache->TestIn.pPageCpuPhys = 0;
4119 pCache->TestIn.pVMCSPhys = 0;
4120 pCache->TestIn.pCache = 0;
4121 pCache->TestOut.pVMCSPhys = 0;
4122 pCache->TestOut.pCache = 0;
4123 pCache->TestOut.pCtx = 0;
4124 pCache->TestOut.eflags = 0;
4125#endif
4126
4127 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
4128 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
4129 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
4130 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
4131 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
4132 aParam[5] = 0;
4133
4134#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4135 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
4136 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
4137#endif
4138 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
4139
4140#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4141 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
4142 Assert(pCtx->dr[4] == 10);
4143 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
4144#endif
4145
4146#ifdef DEBUG
4147 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
4148 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
4149 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
4150 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
4151 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
4152 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
4153 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
4154#endif
4155 return rc;
4156}
4157
4158/**
4159 * Executes the specified handler in 64 mode
4160 *
4161 * @returns VBox status code.
4162 * @param pVM The VM to operate on.
4163 * @param pVCpu The VMCPU to operate on.
4164 * @param pCtx Guest context
4165 * @param pfnHandler RC handler
4166 * @param cbParam Number of parameters
4167 * @param paParam Array of 32 bits parameters
4168 */
4169VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
4170{
4171 int rc, rc2;
4172 PHWACCM_CPUINFO pCpu;
4173 RTHCPHYS pPageCpuPhys;
4174
4175 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
4176 AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
4177 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
4178 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
4179 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
4180
4181#ifdef VBOX_STRICT
4182 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
4183 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
4184
4185 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
4186 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
4187#endif
4188
4189 pCpu = HWACCMR0GetCurrentCpu();
4190 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4191
4192 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4193 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4194
4195 /* Leave VMX Root Mode. */
4196 VMXDisable();
4197
4198 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4199
4200 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
4201 CPUMSetHyperEIP(pVCpu, pfnHandler);
4202 for (int i=(int)cbParam-1;i>=0;i--)
4203 CPUMPushHyper(pVCpu, paParam[i]);
4204
4205 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4206 /* Call switcher. */
4207 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
4208 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4209
4210 /* Make sure the VMX instructions don't cause #UD faults. */
4211 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
4212
4213 /* Enter VMX Root Mode */
4214 rc2 = VMXEnable(pPageCpuPhys);
4215 if (RT_FAILURE(rc2))
4216 {
4217 if (pVM)
4218 VMXR0CheckError(pVM, pVCpu, rc2);
4219 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4220 return VERR_VMX_VMXON_FAILED;
4221 }
4222
4223 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4224 AssertRCReturn(rc2, rc2);
4225 Assert(!(ASMGetFlags() & X86_EFL_IF));
4226 return rc;
4227}
4228
4229#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4230
4231
4232#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4233/**
4234 * Executes VMWRITE
4235 *
4236 * @returns VBox status code
4237 * @param pVCpu The VMCPU to operate on.
4238 * @param idxField VMCS index
4239 * @param u64Val 16, 32 or 64 bits value
4240 */
4241VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4242{
4243 int rc;
4244
4245 switch (idxField)
4246 {
4247 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4248 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4249 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4250 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4251 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4252 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4253 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4254 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4255 case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
4256 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4257 case VMX_VMCS_GUEST_PDPTR0_FULL:
4258 case VMX_VMCS_GUEST_PDPTR1_FULL:
4259 case VMX_VMCS_GUEST_PDPTR2_FULL:
4260 case VMX_VMCS_GUEST_PDPTR3_FULL:
4261 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4262 case VMX_VMCS_GUEST_EFER_FULL:
4263 case VMX_VMCS_CTRL_EPTP_FULL:
4264 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4265 rc = VMXWriteVMCS32(idxField, u64Val);
4266 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4267 AssertRC(rc);
4268 return rc;
4269
4270 case VMX_VMCS64_GUEST_LDTR_BASE:
4271 case VMX_VMCS64_GUEST_TR_BASE:
4272 case VMX_VMCS64_GUEST_GDTR_BASE:
4273 case VMX_VMCS64_GUEST_IDTR_BASE:
4274 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4275 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4276 case VMX_VMCS64_GUEST_CR0:
4277 case VMX_VMCS64_GUEST_CR4:
4278 case VMX_VMCS64_GUEST_CR3:
4279 case VMX_VMCS64_GUEST_DR7:
4280 case VMX_VMCS64_GUEST_RIP:
4281 case VMX_VMCS64_GUEST_RSP:
4282 case VMX_VMCS64_GUEST_CS_BASE:
4283 case VMX_VMCS64_GUEST_DS_BASE:
4284 case VMX_VMCS64_GUEST_ES_BASE:
4285 case VMX_VMCS64_GUEST_FS_BASE:
4286 case VMX_VMCS64_GUEST_GS_BASE:
4287 case VMX_VMCS64_GUEST_SS_BASE:
4288 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4289 if (u64Val >> 32ULL)
4290 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4291 else
4292 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4293
4294 return rc;
4295
4296 default:
4297 AssertMsgFailed(("Unexpected field %x\n", idxField));
4298 return VERR_INVALID_PARAMETER;
4299 }
4300}
4301
4302/**
4303 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4304 *
4305 * @param pVCpu The VMCPU to operate on.
4306 * @param idxField VMCS field
4307 * @param u64Val Value
4308 */
4309VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4310{
4311 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4312
4313 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4314
4315 /* Make sure there are no duplicates. */
4316 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4317 {
4318 if (pCache->Write.aField[i] == idxField)
4319 {
4320 pCache->Write.aFieldVal[i] = u64Val;
4321 return VINF_SUCCESS;
4322 }
4323 }
4324
4325 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4326 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4327 pCache->Write.cValidEntries++;
4328 return VINF_SUCCESS;
4329}
4330
4331#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4332
4333#ifdef VBOX_STRICT
4334static bool vmxR0IsValidReadField(uint32_t idxField)
4335{
4336 switch(idxField)
4337 {
4338 case VMX_VMCS64_GUEST_RIP:
4339 case VMX_VMCS64_GUEST_RSP:
4340 case VMX_VMCS_GUEST_RFLAGS:
4341 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4342 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4343 case VMX_VMCS64_GUEST_CR0:
4344 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4345 case VMX_VMCS64_GUEST_CR4:
4346 case VMX_VMCS64_GUEST_DR7:
4347 case VMX_VMCS32_GUEST_SYSENTER_CS:
4348 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4349 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4350 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4351 case VMX_VMCS64_GUEST_GDTR_BASE:
4352 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4353 case VMX_VMCS64_GUEST_IDTR_BASE:
4354 case VMX_VMCS16_GUEST_FIELD_CS:
4355 case VMX_VMCS32_GUEST_CS_LIMIT:
4356 case VMX_VMCS64_GUEST_CS_BASE:
4357 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4358 case VMX_VMCS16_GUEST_FIELD_DS:
4359 case VMX_VMCS32_GUEST_DS_LIMIT:
4360 case VMX_VMCS64_GUEST_DS_BASE:
4361 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4362 case VMX_VMCS16_GUEST_FIELD_ES:
4363 case VMX_VMCS32_GUEST_ES_LIMIT:
4364 case VMX_VMCS64_GUEST_ES_BASE:
4365 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4366 case VMX_VMCS16_GUEST_FIELD_FS:
4367 case VMX_VMCS32_GUEST_FS_LIMIT:
4368 case VMX_VMCS64_GUEST_FS_BASE:
4369 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4370 case VMX_VMCS16_GUEST_FIELD_GS:
4371 case VMX_VMCS32_GUEST_GS_LIMIT:
4372 case VMX_VMCS64_GUEST_GS_BASE:
4373 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4374 case VMX_VMCS16_GUEST_FIELD_SS:
4375 case VMX_VMCS32_GUEST_SS_LIMIT:
4376 case VMX_VMCS64_GUEST_SS_BASE:
4377 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4378 case VMX_VMCS16_GUEST_FIELD_LDTR:
4379 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4380 case VMX_VMCS64_GUEST_LDTR_BASE:
4381 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4382 case VMX_VMCS16_GUEST_FIELD_TR:
4383 case VMX_VMCS32_GUEST_TR_LIMIT:
4384 case VMX_VMCS64_GUEST_TR_BASE:
4385 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4386 case VMX_VMCS32_RO_EXIT_REASON:
4387 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4388 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4389 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4390 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4391 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4392 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4393 case VMX_VMCS32_RO_IDT_INFO:
4394 case VMX_VMCS32_RO_IDT_ERRCODE:
4395 case VMX_VMCS64_GUEST_CR3:
4396 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4397 return true;
4398 }
4399 return false;
4400}
4401
4402static bool vmxR0IsValidWriteField(uint32_t idxField)
4403{
4404 switch(idxField)
4405 {
4406 case VMX_VMCS64_GUEST_LDTR_BASE:
4407 case VMX_VMCS64_GUEST_TR_BASE:
4408 case VMX_VMCS64_GUEST_GDTR_BASE:
4409 case VMX_VMCS64_GUEST_IDTR_BASE:
4410 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4411 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4412 case VMX_VMCS64_GUEST_CR0:
4413 case VMX_VMCS64_GUEST_CR4:
4414 case VMX_VMCS64_GUEST_CR3:
4415 case VMX_VMCS64_GUEST_DR7:
4416 case VMX_VMCS64_GUEST_RIP:
4417 case VMX_VMCS64_GUEST_RSP:
4418 case VMX_VMCS64_GUEST_CS_BASE:
4419 case VMX_VMCS64_GUEST_DS_BASE:
4420 case VMX_VMCS64_GUEST_ES_BASE:
4421 case VMX_VMCS64_GUEST_FS_BASE:
4422 case VMX_VMCS64_GUEST_GS_BASE:
4423 case VMX_VMCS64_GUEST_SS_BASE:
4424 return true;
4425 }
4426 return false;
4427}
4428
4429#endif
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