VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 21134

Last change on this file since 21134 was 21001, checked in by vboxsync, 16 years ago

HWACCM: Untested AMD-V fix for the xmm register corruption on Windows/AMD64.
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1/* $Id: HWVMXR0.cpp 21001 2009-06-26 23:18:11Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/param.h>
41#include <iprt/string.h>
42#include <iprt/time.h>
43#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
44# include <iprt/thread.h>
45#endif
46#include "HWVMXR0.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51#if defined(RT_ARCH_AMD64)
52# define VMX_IS_64BIT_HOST_MODE() (true)
53#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
54# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
55#else
56# define VMX_IS_64BIT_HOST_MODE() (false)
57#endif
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62/* IO operation lookup arrays. */
63static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
65
66#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
67/** See HWACCMR0A.asm. */
68extern "C" uint32_t g_fVMXIs64bitHost;
69#endif
70
71/*******************************************************************************
72* Local Functions *
73*******************************************************************************/
74static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
75static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
76static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
77static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
78static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
79static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
80static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
81#ifdef VBOX_STRICT
82static bool vmxR0IsValidReadField(uint32_t idxField);
83static bool vmxR0IsValidWriteField(uint32_t idxField);
84#endif
85
86static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
87{
88 if (rc == VERR_VMX_GENERIC)
89 {
90 RTCCUINTREG instrError;
91
92 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
93 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
94 }
95 pVM->hwaccm.s.lLastError = rc;
96}
97
98/**
99 * Sets up and activates VT-x on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pVM The VM to operate on. (can be NULL after a resume!!)
104 * @param pvPageCpu Pointer to the global cpu page
105 * @param pPageCpuPhys Physical address of the global cpu page
106 */
107VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
108{
109 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
110 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
111
112#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
113 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
114#endif
115 if (pVM)
116 {
117 /* Set revision dword at the beginning of the VMXON structure. */
118 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
119 }
120
121 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
122 * (which can have very bad consequences!!!)
123 */
124
125 /* Make sure the VMX instructions don't cause #UD faults. */
126 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
127
128 /* Enter VMX Root Mode */
129 int rc = VMXEnable(pPageCpuPhys);
130 if (RT_FAILURE(rc))
131 {
132 if (pVM)
133 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
134 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
135 return VERR_VMX_VMXON_FAILED;
136 }
137 return VINF_SUCCESS;
138}
139
140/**
141 * Deactivates VT-x on the current CPU
142 *
143 * @returns VBox status code.
144 * @param pCpu CPU info struct
145 * @param pvPageCpu Pointer to the global cpu page
146 * @param pPageCpuPhys Physical address of the global cpu page
147 */
148VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
149{
150 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
151 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
152
153 /* Leave VMX Root Mode. */
154 VMXDisable();
155
156 /* And clear the X86_CR4_VMXE bit */
157 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
158
159#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
160 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
161#endif
162 return VINF_SUCCESS;
163}
164
165/**
166 * Does Ring-0 per VM VT-x init.
167 *
168 * @returns VBox status code.
169 * @param pVM The VM to operate on.
170 */
171VMMR0DECL(int) VMXR0InitVM(PVM pVM)
172{
173 int rc;
174
175#ifdef LOG_ENABLED
176 SUPR0Printf("VMXR0InitVM %x\n", pVM);
177#endif
178
179 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
180
181 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
182 {
183 /* Allocate one page for the APIC physical page (serves for filtering accesses). */
184 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185 AssertRC(rc);
186 if (RT_FAILURE(rc))
187 return rc;
188
189 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
190 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
191 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
192 }
193 else
194 {
195 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
196 pVM->hwaccm.s.vmx.pAPIC = 0;
197 pVM->hwaccm.s.vmx.pAPICPhys = 0;
198 }
199
200 /* Allocate the MSR bitmap if this feature is supported. */
201 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
202 {
203 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
204 AssertRC(rc);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
209 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
210 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
211 }
212
213#ifdef VBOX_WITH_CRASHDUMP_MAGIC
214 {
215 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
216 AssertRC(rc);
217 if (RT_FAILURE(rc))
218 return rc;
219
220 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
221 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
222
223 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
224 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
225 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
226 }
227#endif
228
229 /* Allocate VMCBs for all guest CPUs. */
230 for (unsigned i=0;i<pVM->cCPUs;i++)
231 {
232 PVMCPU pVCpu = &pVM->aCpus[i];
233
234 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
235
236 /* Allocate one page for the VM control structure (VMCS). */
237 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
238 AssertRC(rc);
239 if (RT_FAILURE(rc))
240 return rc;
241
242 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
243 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
244 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
245
246 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
247 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
248
249 /* Allocate one page for the virtual APIC page for TPR caching. */
250 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
251 AssertRC(rc);
252 if (RT_FAILURE(rc))
253 return rc;
254
255 pVCpu->hwaccm.s.vmx.pVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
256 pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
257 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
258
259 /* Current guest paging mode. */
260 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
261
262#ifdef LOG_ENABLED
263 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
264#endif
265 }
266
267 return VINF_SUCCESS;
268}
269
270/**
271 * Does Ring-0 per VM VT-x termination.
272 *
273 * @returns VBox status code.
274 * @param pVM The VM to operate on.
275 */
276VMMR0DECL(int) VMXR0TermVM(PVM pVM)
277{
278 for (unsigned i=0;i<pVM->cCPUs;i++)
279 {
280 PVMCPU pVCpu = &pVM->aCpus[i];
281
282 if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
283 {
284 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
285 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
286 pVCpu->hwaccm.s.vmx.pVMCS = 0;
287 pVCpu->hwaccm.s.vmx.pVMCSPhys = 0;
288 }
289 if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
290 {
291 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
292 pVCpu->hwaccm.s.vmx.pMemObjVAPIC = NIL_RTR0MEMOBJ;
293 pVCpu->hwaccm.s.vmx.pVAPIC = 0;
294 pVCpu->hwaccm.s.vmx.pVAPICPhys = 0;
295 }
296 }
297 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
298 {
299 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
300 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
301 pVM->hwaccm.s.vmx.pAPIC = 0;
302 pVM->hwaccm.s.vmx.pAPICPhys = 0;
303 }
304 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
305 {
306 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
307 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
308 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
309 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
310 }
311#ifdef VBOX_WITH_CRASHDUMP_MAGIC
312 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
313 {
314 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
315 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
316 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
317 pVM->hwaccm.s.vmx.pScratch = 0;
318 pVM->hwaccm.s.vmx.pScratchPhys = 0;
319 }
320#endif
321 return VINF_SUCCESS;
322}
323
324/**
325 * Sets up VT-x for the specified VM
326 *
327 * @returns VBox status code.
328 * @param pVM The VM to operate on.
329 */
330VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
331{
332 int rc = VINF_SUCCESS;
333 uint32_t val;
334
335 AssertReturn(pVM, VERR_INVALID_PARAMETER);
336
337 for (unsigned i=0;i<pVM->cCPUs;i++)
338 {
339 PVMCPU pVCpu = &pVM->aCpus[i];
340
341 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
342
343 /* Set revision dword at the beginning of the VMCS structure. */
344 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
345
346 /* Clear VM Control Structure. */
347 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
348 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
349 if (RT_FAILURE(rc))
350 goto vmx_end;
351
352 /* Activate the VM Control Structure. */
353 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
354 if (RT_FAILURE(rc))
355 goto vmx_end;
356
357 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
358 * Set required bits to one and zero according to the MSR capabilities.
359 */
360 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
361 /* External and non-maskable interrupts cause VM-exits. */
362 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
363 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
364
365 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
366 AssertRC(rc);
367
368 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
369 * Set required bits to one and zero according to the MSR capabilities.
370 */
371 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
372 /* Program which event cause VM-exits and which features we want to use. */
373 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
374 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
375 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
376 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
377 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
378 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
379
380 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
381 if (!pVM->hwaccm.s.fNestedPaging)
382 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
383 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
384 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
385
386 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
387 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
388 {
389 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
390 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
391 Assert(pVM->hwaccm.s.vmx.pAPIC);
392 }
393 else
394 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
395 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
396
397#ifdef VBOX_WITH_VTX_MSR_BITMAPS
398 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
399 {
400 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
401 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
402 }
403#endif
404
405 /* We will use the secondary control if it's present. */
406 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
407
408 /* Mask away the bits that the CPU doesn't support */
409 /** @todo make sure they don't conflict with the above requirements. */
410 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
411 pVCpu->hwaccm.s.vmx.proc_ctls = val;
412
413 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
414 AssertRC(rc);
415
416 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
417 {
418 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
419 * Set required bits to one and zero according to the MSR capabilities.
420 */
421 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
422 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
423
424#ifdef HWACCM_VTX_WITH_EPT
425 if (pVM->hwaccm.s.fNestedPaging)
426 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
427#endif /* HWACCM_VTX_WITH_EPT */
428#ifdef HWACCM_VTX_WITH_VPID
429 else
430 if (pVM->hwaccm.s.vmx.fVPID)
431 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
432#endif /* HWACCM_VTX_WITH_VPID */
433
434 if (pVM->hwaccm.s.fHasIoApic)
435 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC;
436
437 /* Mask away the bits that the CPU doesn't support */
438 /** @todo make sure they don't conflict with the above requirements. */
439 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
440 pVCpu->hwaccm.s.vmx.proc_ctls2 = val;
441 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
442 AssertRC(rc);
443 }
444
445 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
446 * Set required bits to one and zero according to the MSR capabilities.
447 */
448 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
449 AssertRC(rc);
450
451 /* Forward all exception except #NM & #PF to the guest.
452 * We always need to check pagefaults since our shadow page table can be out of sync.
453 * And we always lazily sync the FPU & XMM state.
454 */
455
456 /** @todo Possible optimization:
457 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
458 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
459 * registers ourselves of course.
460 *
461 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
462 */
463
464 /* Don't filter page faults; all of them should cause a switch. */
465 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
467 AssertRC(rc);
468
469 /* Init TSC offset to zero. */
470 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
471 AssertRC(rc);
472
473 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
474 AssertRC(rc);
475
476 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
477 AssertRC(rc);
478
479 /* Set the MSR bitmap address. */
480 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
481 {
482 /* Optional */
483 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
484 AssertRC(rc);
485 }
486
487 /* Clear MSR controls. */
488 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
489 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
490 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
491 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
492 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
493 AssertRC(rc);
494
495 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
496 {
497 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
498 /* Optional */
499 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
500 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
501
502 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
503 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
504
505 AssertRC(rc);
506 }
507
508 /* Set link pointer to -1. Not currently used. */
509 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
510 AssertRC(rc);
511
512 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
513 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
514 AssertRC(rc);
515
516 /* Configure the VMCS read cache. */
517 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
518
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
525 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
526 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
527 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
530 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
531 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
532 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
533 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
534 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
535
536 VMX_SETUP_SELREG(ES, pCache);
537 VMX_SETUP_SELREG(SS, pCache);
538 VMX_SETUP_SELREG(CS, pCache);
539 VMX_SETUP_SELREG(DS, pCache);
540 VMX_SETUP_SELREG(FS, pCache);
541 VMX_SETUP_SELREG(GS, pCache);
542 VMX_SETUP_SELREG(LDTR, pCache);
543 VMX_SETUP_SELREG(TR, pCache);
544
545 /* Status code VMCS reads. */
546 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
547 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
548 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
549 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
550 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
551 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
552 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
553 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
554 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
555
556 if (pVM->hwaccm.s.fNestedPaging)
557 {
558 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
559 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
560 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
561 }
562 else
563 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
564 } /* for each VMCPU */
565
566 /* Choose the right TLB setup function. */
567 if (pVM->hwaccm.s.fNestedPaging)
568 {
569 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
570
571 /* Default values for flushing. */
572 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
574
575 /* If the capabilities specify we can do more, then make use of it. */
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
577 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
578 else
579 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
580 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
581
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
583 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
584 }
585#ifdef HWACCM_VTX_WITH_VPID
586 else
587 if (pVM->hwaccm.s.vmx.fVPID)
588 {
589 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
590
591 /* Default values for flushing. */
592 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
593 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
594
595 /* If the capabilities specify we can do more, then make use of it. */
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
597 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
598 else
599 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
600 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
601
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
603 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
604 }
605#endif /* HWACCM_VTX_WITH_VPID */
606 else
607 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
608
609vmx_end:
610 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
611 return rc;
612}
613
614
615/**
616 * Injects an event (trap or external interrupt)
617 *
618 * @returns VBox status code.
619 * @param pVM The VM to operate on.
620 * @param pVCpu The VMCPU to operate on.
621 * @param pCtx CPU Context
622 * @param intInfo VMX interrupt info
623 * @param cbInstr Opcode length of faulting instruction
624 * @param errCode Error code (optional)
625 */
626static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
627{
628 int rc;
629 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
630
631#ifdef VBOX_WITH_STATISTICS
632 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
633#endif
634
635#ifdef VBOX_STRICT
636 if (iGate == 0xE)
637 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
638 else
639 if (iGate < 0x20)
640 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
641 else
642 {
643 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
644 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
645 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
646 }
647#endif
648
649#ifdef HWACCM_VMX_EMULATE_REALMODE
650 if (CPUMIsGuestInRealModeEx(pCtx))
651 {
652 RTGCPHYS GCPhysHandler;
653 uint16_t offset, ip;
654 RTSEL sel;
655
656 /* Injecting events doesn't work right with real mode emulation.
657 * (#GP if we try to inject external hardware interrupts)
658 * Inject the interrupt or trap directly instead.
659 *
660 * ASSUMES no access handlers for the bits we read or write below (should be safe).
661 */
662 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
663
664 /* Check if the interrupt handler is present. */
665 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
666 {
667 Log(("IDT cbIdt violation\n"));
668 if (iGate != X86_XCPT_DF)
669 {
670 RTGCUINTPTR intInfo;
671
672 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
673 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
674 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
675 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
676
677 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
678 }
679 Log(("Triple fault -> reset the VM!\n"));
680 return VINF_EM_RESET;
681 }
682 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
683 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
684 || iGate == 4)
685 {
686 ip = pCtx->ip + cbInstr;
687 }
688 else
689 ip = pCtx->ip;
690
691 /* Read the selector:offset pair of the interrupt handler. */
692 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
693 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
694 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
695
696 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
697
698 /* Construct the stack frame. */
699 /** @todo should check stack limit. */
700 pCtx->sp -= 2;
701 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
702 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
703 pCtx->sp -= 2;
704 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
705 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
706 pCtx->sp -= 2;
707 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
708 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
709
710 /* Update the CPU state for executing the handler. */
711 pCtx->rip = offset;
712 pCtx->cs = sel;
713 pCtx->csHid.u64Base = sel << 4;
714 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
715
716 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
717 return VINF_SUCCESS;
718 }
719#endif /* HWACCM_VMX_EMULATE_REALMODE */
720
721 /* Set event injection state. */
722 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
723
724 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
725 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
726
727 AssertRC(rc);
728 return rc;
729}
730
731
732/**
733 * Checks for pending guest interrupts and injects them
734 *
735 * @returns VBox status code.
736 * @param pVM The VM to operate on.
737 * @param pVCpu The VMCPU to operate on.
738 * @param pCtx CPU Context
739 */
740static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
741{
742 int rc;
743
744 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
745 if (pVCpu->hwaccm.s.Event.fPending)
746 {
747 Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
748 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
749 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
750 AssertRC(rc);
751
752 pVCpu->hwaccm.s.Event.fPending = false;
753 return VINF_SUCCESS;
754 }
755
756 /* If an active trap is already pending, then we must forward it first! */
757 if (!TRPMHasTrap(pVCpu))
758 {
759 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI_BIT))
760 {
761 RTGCUINTPTR intInfo;
762
763 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
764
765 intInfo = X86_XCPT_NMI;
766 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
767 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
768
769 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
770 AssertRC(rc);
771
772 return VINF_SUCCESS;
773 }
774
775 /* @todo SMI interrupts. */
776
777 /* When external interrupts are pending, we should exit the VM when IF is set. */
778 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
779 {
780 if (!(pCtx->eflags.u32 & X86_EFL_IF))
781 {
782 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
783 {
784 LogFlow(("Enable irq window exit!\n"));
785 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
786 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
787 AssertRC(rc);
788 }
789 /* else nothing to do but wait */
790 }
791 else
792 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
793 {
794 uint8_t u8Interrupt;
795
796 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
797 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
798 if (RT_SUCCESS(rc))
799 {
800 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
801 AssertRC(rc);
802 }
803 else
804 {
805 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
806 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
807 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
808 /* Just continue */
809 }
810 }
811 else
812 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
813 }
814 }
815
816#ifdef VBOX_STRICT
817 if (TRPMHasTrap(pVCpu))
818 {
819 uint8_t u8Vector;
820 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
821 AssertRC(rc);
822 }
823#endif
824
825 if ( (pCtx->eflags.u32 & X86_EFL_IF)
826 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
827 && TRPMHasTrap(pVCpu)
828 )
829 {
830 uint8_t u8Vector;
831 int rc;
832 TRPMEVENT enmType;
833 RTGCUINTPTR intInfo;
834 RTGCUINT errCode;
835
836 /* If a new event is pending, then dispatch it now. */
837 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
838 AssertRC(rc);
839 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
840 Assert(enmType != TRPM_SOFTWARE_INT);
841
842 /* Clear the pending trap. */
843 rc = TRPMResetTrap(pVCpu);
844 AssertRC(rc);
845
846 intInfo = u8Vector;
847 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
848
849 if (enmType == TRPM_TRAP)
850 {
851 switch (u8Vector) {
852 case 8:
853 case 10:
854 case 11:
855 case 12:
856 case 13:
857 case 14:
858 case 17:
859 /* Valid error codes. */
860 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
861 break;
862 default:
863 break;
864 }
865 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
866 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
867 else
868 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
869 }
870 else
871 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
872
873 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
874 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
875 AssertRC(rc);
876 } /* if (interrupts can be dispatched) */
877
878 return VINF_SUCCESS;
879}
880
881/**
882 * Save the host state
883 *
884 * @returns VBox status code.
885 * @param pVM The VM to operate on.
886 * @param pVCpu The VMCPU to operate on.
887 */
888VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
889{
890 int rc = VINF_SUCCESS;
891
892 /*
893 * Host CPU Context
894 */
895 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
896 {
897 RTIDTR idtr;
898 RTGDTR gdtr;
899 RTSEL SelTR;
900 PX86DESCHC pDesc;
901 uintptr_t trBase;
902 RTSEL cs;
903 RTSEL ss;
904 uint64_t cr3;
905
906 /* Control registers */
907 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
908#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
909 if (VMX_IS_64BIT_HOST_MODE())
910 {
911 cr3 = hwaccmR0Get64bitCR3();
912 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
913 }
914 else
915#endif
916 {
917 cr3 = ASMGetCR3();
918 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
919 }
920 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
921 AssertRC(rc);
922 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
923 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
924 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
925
926 /* Selector registers. */
927#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
928 if (VMX_IS_64BIT_HOST_MODE())
929 {
930 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
931 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
932 }
933 else
934 {
935 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
936 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
937 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
938 }
939#else
940 cs = ASMGetCS();
941 ss = ASMGetSS();
942#endif
943 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
944 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
945 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
946 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
947 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
948 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
949#if HC_ARCH_BITS == 32
950 if (!VMX_IS_64BIT_HOST_MODE())
951 {
952 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
953 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
954 }
955#endif
956 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
957 SelTR = ASMGetTR();
958 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
959 AssertRC(rc);
960 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
961 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
962 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
963 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
964 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
965 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
966 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
967
968 /* GDTR & IDTR */
969#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
970 if (VMX_IS_64BIT_HOST_MODE())
971 {
972 X86XDTR64 gdtr64, idtr64;
973 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
974 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
975 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
976 AssertRC(rc);
977 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
978 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
979 gdtr.cbGdt = gdtr64.cb;
980 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
981 }
982 else
983#endif
984 {
985 ASMGetGDTR(&gdtr);
986 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
987 ASMGetIDTR(&idtr);
988 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
989 AssertRC(rc);
990 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
991 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
992 }
993
994
995 /* Save the base address of the TR selector. */
996 if (SelTR > gdtr.cbGdt)
997 {
998 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
999 return VERR_VMX_INVALID_HOST_STATE;
1000 }
1001
1002#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1003 if (VMX_IS_64BIT_HOST_MODE())
1004 {
1005 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
1006 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
1007 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
1008 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
1009 AssertRC(rc);
1010 }
1011 else
1012#endif
1013 {
1014 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
1015#if HC_ARCH_BITS == 64
1016 trBase = X86DESC64_BASE(*pDesc);
1017#else
1018 trBase = X86DESC_BASE(*pDesc);
1019#endif
1020 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
1021 AssertRC(rc);
1022 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
1023 }
1024
1025 /* FS and GS base. */
1026#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1027 if (VMX_IS_64BIT_HOST_MODE())
1028 {
1029 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
1030 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
1031 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
1032 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
1033 }
1034#endif
1035 AssertRC(rc);
1036
1037 /* Sysenter MSRs. */
1038 /** @todo expensive!! */
1039 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1040 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1041#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1042 if (VMX_IS_64BIT_HOST_MODE())
1043 {
1044 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1045 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1046 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1047 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1048 }
1049 else
1050 {
1051 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1052 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1053 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1054 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1055 }
1056#elif HC_ARCH_BITS == 32
1057 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1058 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1059 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1060 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1061#else
1062 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1063 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1064 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1065 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1066#endif
1067 AssertRC(rc);
1068
1069#if 0 /* @todo deal with 32/64 */
1070 /* Restore the host EFER - on CPUs that support it. */
1071 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1072 {
1073 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1074 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1075 AssertRC(rc);
1076 }
1077#endif
1078 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1079 }
1080 return rc;
1081}
1082
1083/**
1084 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1085 *
1086 * @param pVM The VM to operate on.
1087 * @param pVCpu The VMCPU to operate on.
1088 * @param pCtx Guest context
1089 */
1090static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1091{
1092 if (CPUMIsGuestInPAEModeEx(pCtx))
1093 {
1094 X86PDPE Pdpe;
1095
1096 for (unsigned i=0;i<4;i++)
1097 {
1098 Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1099 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1100 AssertRC(rc);
1101 }
1102 }
1103}
1104
1105/**
1106 * Update the exception bitmap according to the current CPU state
1107 *
1108 * @param pVM The VM to operate on.
1109 * @param pVCpu The VMCPU to operate on.
1110 * @param pCtx Guest context
1111 */
1112static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1113{
1114 uint32_t u32TrapMask;
1115 Assert(pCtx);
1116
1117 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1118#ifndef DEBUG
1119 if (pVM->hwaccm.s.fNestedPaging)
1120 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1121#endif
1122
1123 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1124 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1125 && !(pCtx->cr0 & X86_CR0_NE)
1126 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1127 {
1128 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1129 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1130 }
1131
1132#ifdef DEBUG /* till after branching, enable it by default then. */
1133 /* Intercept X86_XCPT_DB if stepping is enabled */
1134 if (DBGFIsStepping(pVCpu))
1135 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1136 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1137 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1138#endif
1139
1140#ifdef VBOX_STRICT
1141 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1142#endif
1143
1144# ifdef HWACCM_VMX_EMULATE_REALMODE
1145 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1146 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1147 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1148# endif /* HWACCM_VMX_EMULATE_REALMODE */
1149
1150 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1151 AssertRC(rc);
1152}
1153
1154/**
1155 * Loads the guest state
1156 *
1157 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1158 *
1159 * @returns VBox status code.
1160 * @param pVM The VM to operate on.
1161 * @param pVCpu The VMCPU to operate on.
1162 * @param pCtx Guest context
1163 */
1164VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1165{
1166 int rc = VINF_SUCCESS;
1167 RTGCUINTPTR val;
1168 X86EFLAGS eflags;
1169
1170 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1171 * Set required bits to one and zero according to the MSR capabilities.
1172 */
1173 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1174 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1175 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1176#if 0 /* @todo deal with 32/64 */
1177 /* Required for the EFER write below, not supported on all CPUs. */
1178 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1179#endif
1180 /* 64 bits guest mode? */
1181 if (CPUMIsGuestInLongModeEx(pCtx))
1182 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1183 /* else Must be zero when AMD64 is not available. */
1184
1185 /* Mask away the bits that the CPU doesn't support */
1186 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1187 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1188 AssertRC(rc);
1189
1190 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1191 * Set required bits to one and zero according to the MSR capabilities.
1192 */
1193 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1194
1195 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1196#if 0 /* @todo deal with 32/64 */
1197 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1198#else
1199 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1200#endif
1201
1202#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1203 if (VMX_IS_64BIT_HOST_MODE())
1204 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1205 /* else: Must be zero when AMD64 is not available. */
1206#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1207 if (CPUMIsGuestInLongModeEx(pCtx))
1208 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1209 else
1210 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1211#endif
1212 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1213 /* Don't acknowledge external interrupts on VM-exit. */
1214 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1215 AssertRC(rc);
1216
1217 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1218 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1219 {
1220#ifdef HWACCM_VMX_EMULATE_REALMODE
1221 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1222 {
1223 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1224 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1225 {
1226 /* Correct weird requirements for switching to protected mode. */
1227 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1228 && enmGuestMode >= PGMMODE_PROTECTED)
1229 {
1230 /* Flush the recompiler code cache as it's not unlikely
1231 * the guest will rewrite code it will later execute in real
1232 * mode (OpenBSD 4.0 is one such example)
1233 */
1234 REMFlushTBs(pVM);
1235
1236 /* DPL of all hidden selector registers must match the current CPL (0). */
1237 pCtx->csHid.Attr.n.u2Dpl = 0;
1238 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1239
1240 pCtx->dsHid.Attr.n.u2Dpl = 0;
1241 pCtx->esHid.Attr.n.u2Dpl = 0;
1242 pCtx->fsHid.Attr.n.u2Dpl = 0;
1243 pCtx->gsHid.Attr.n.u2Dpl = 0;
1244 pCtx->ssHid.Attr.n.u2Dpl = 0;
1245
1246 /* The limit must correspond to the granularity bit. */
1247 if (!pCtx->csHid.Attr.n.u1Granularity)
1248 pCtx->csHid.u32Limit &= 0xffff;
1249 if (!pCtx->dsHid.Attr.n.u1Granularity)
1250 pCtx->dsHid.u32Limit &= 0xffff;
1251 if (!pCtx->esHid.Attr.n.u1Granularity)
1252 pCtx->esHid.u32Limit &= 0xffff;
1253 if (!pCtx->fsHid.Attr.n.u1Granularity)
1254 pCtx->fsHid.u32Limit &= 0xffff;
1255 if (!pCtx->gsHid.Attr.n.u1Granularity)
1256 pCtx->gsHid.u32Limit &= 0xffff;
1257 if (!pCtx->ssHid.Attr.n.u1Granularity)
1258 pCtx->ssHid.u32Limit &= 0xffff;
1259 }
1260 else
1261 /* Switching from protected mode to real mode. */
1262 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1263 && enmGuestMode == PGMMODE_REAL)
1264 {
1265 /* The limit must also be set to 0xffff. */
1266 pCtx->csHid.u32Limit = 0xffff;
1267 pCtx->dsHid.u32Limit = 0xffff;
1268 pCtx->esHid.u32Limit = 0xffff;
1269 pCtx->fsHid.u32Limit = 0xffff;
1270 pCtx->gsHid.u32Limit = 0xffff;
1271 pCtx->ssHid.u32Limit = 0xffff;
1272
1273 Assert(pCtx->csHid.u64Base <= 0xfffff);
1274 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1275 Assert(pCtx->esHid.u64Base <= 0xfffff);
1276 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1277 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1278 }
1279 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1280 }
1281 else
1282 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1283 if ( CPUMIsGuestInRealModeEx(pCtx)
1284 && pCtx->csHid.u64Base == 0xffff0000)
1285 {
1286 pCtx->csHid.u64Base = 0xf0000;
1287 pCtx->cs = 0xf000;
1288 }
1289 }
1290#endif /* HWACCM_VMX_EMULATE_REALMODE */
1291
1292 VMX_WRITE_SELREG(ES, es);
1293 AssertRC(rc);
1294
1295 VMX_WRITE_SELREG(CS, cs);
1296 AssertRC(rc);
1297
1298 VMX_WRITE_SELREG(SS, ss);
1299 AssertRC(rc);
1300
1301 VMX_WRITE_SELREG(DS, ds);
1302 AssertRC(rc);
1303
1304 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1305 VMX_WRITE_SELREG(FS, fs);
1306 AssertRC(rc);
1307
1308 VMX_WRITE_SELREG(GS, gs);
1309 AssertRC(rc);
1310 }
1311
1312 /* Guest CPU context: LDTR. */
1313 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1314 {
1315 if (pCtx->ldtr == 0)
1316 {
1317 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1318 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1319 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1320 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1321 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1322 }
1323 else
1324 {
1325 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1326 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1327 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1328 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1329 }
1330 AssertRC(rc);
1331 }
1332 /* Guest CPU context: TR. */
1333 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1334 {
1335#ifdef HWACCM_VMX_EMULATE_REALMODE
1336 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1337 if (CPUMIsGuestInRealModeEx(pCtx))
1338 {
1339 RTGCPHYS GCPhys;
1340
1341 /* We convert it here every time as pci regions could be reconfigured. */
1342 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1343 AssertRC(rc);
1344
1345 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1346 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1347 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1348
1349 X86DESCATTR attr;
1350
1351 attr.u = 0;
1352 attr.n.u1Present = 1;
1353 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1354 val = attr.u;
1355 }
1356 else
1357#endif /* HWACCM_VMX_EMULATE_REALMODE */
1358 {
1359 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1360 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1361 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1362
1363 val = pCtx->trHid.Attr.u;
1364
1365 /* The TSS selector must be busy. */
1366 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1367 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1368 else
1369 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1370 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1371
1372 }
1373 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1374 AssertRC(rc);
1375 }
1376 /* Guest CPU context: GDTR. */
1377 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1378 {
1379 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1380 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1381 AssertRC(rc);
1382 }
1383 /* Guest CPU context: IDTR. */
1384 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1385 {
1386 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1387 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1388 AssertRC(rc);
1389 }
1390
1391 /*
1392 * Sysenter MSRs (unconditional)
1393 */
1394 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1395 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1396 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1397 AssertRC(rc);
1398
1399 /* Control registers */
1400 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1401 {
1402 val = pCtx->cr0;
1403 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1404 Log2(("Guest CR0-shadow %08x\n", val));
1405 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1406 {
1407 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1408 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1409 }
1410 else
1411 {
1412 /** @todo check if we support the old style mess correctly. */
1413 if (!(val & X86_CR0_NE))
1414 Log(("Forcing X86_CR0_NE!!!\n"));
1415
1416 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1417 }
1418 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1419 val |= X86_CR0_PE | X86_CR0_PG;
1420 if (pVM->hwaccm.s.fNestedPaging)
1421 {
1422 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1423 {
1424 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1425 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1426 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1427 }
1428 else
1429 {
1430 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1431 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1432 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1433 }
1434 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1435 AssertRC(rc);
1436 }
1437 else
1438 {
1439 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1440 val |= X86_CR0_WP;
1441 }
1442
1443 /* Always enable caching. */
1444 val &= ~(X86_CR0_CD|X86_CR0_NW);
1445
1446 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1447 Log2(("Guest CR0 %08x\n", val));
1448 /* CR0 flags owned by the host; if the guests attempts to change them, then
1449 * the VM will exit.
1450 */
1451 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1452 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1453 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1454 | X86_CR0_TS
1455 | X86_CR0_ET /* Bit not restored during VM-exit! */
1456 | X86_CR0_CD /* Bit not restored during VM-exit! */
1457 | X86_CR0_NW /* Bit not restored during VM-exit! */
1458 | X86_CR0_NE
1459 | X86_CR0_MP;
1460 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1461
1462 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1463 Log2(("Guest CR0-mask %08x\n", val));
1464 AssertRC(rc);
1465 }
1466 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1467 {
1468 /* CR4 */
1469 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1470 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1471 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1472 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1473
1474 if (!pVM->hwaccm.s.fNestedPaging)
1475 {
1476 switch(pVCpu->hwaccm.s.enmShadowMode)
1477 {
1478 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1479 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1480 case PGMMODE_32_BIT: /* 32-bit paging. */
1481 val &= ~X86_CR4_PAE;
1482 break;
1483
1484 case PGMMODE_PAE: /* PAE paging. */
1485 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1486 /** @todo use normal 32 bits paging */
1487 val |= X86_CR4_PAE;
1488 break;
1489
1490 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1491 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1492#ifdef VBOX_ENABLE_64_BITS_GUESTS
1493 break;
1494#else
1495 AssertFailed();
1496 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1497#endif
1498 default: /* shut up gcc */
1499 AssertFailed();
1500 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1501 }
1502 }
1503 else
1504 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1505 {
1506 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1507 val |= X86_CR4_PSE;
1508 /* Our identity mapping is a 32 bits page directory. */
1509 val &= ~X86_CR4_PAE;
1510 }
1511
1512 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1513 Log2(("Guest CR4 %08x\n", val));
1514 /* CR4 flags owned by the host; if the guests attempts to change them, then
1515 * the VM will exit.
1516 */
1517 val = 0
1518 | X86_CR4_PAE
1519 | X86_CR4_PGE
1520 | X86_CR4_PSE
1521 | X86_CR4_VMXE;
1522 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1523
1524 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1525 Log2(("Guest CR4-mask %08x\n", val));
1526 AssertRC(rc);
1527 }
1528
1529 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1530 {
1531 if (pVM->hwaccm.s.fNestedPaging)
1532 {
1533 Assert(PGMGetHyperCR3(pVCpu));
1534 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1535
1536 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1537 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1538 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1539 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1540
1541 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1542 AssertRC(rc);
1543
1544 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1545 {
1546 RTGCPHYS GCPhys;
1547
1548 /* We convert it here every time as pci regions could be reconfigured. */
1549 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1550 AssertRC(rc);
1551
1552 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1553 * take care of the translation to host physical addresses.
1554 */
1555 val = GCPhys;
1556 }
1557 else
1558 {
1559 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1560 val = pCtx->cr3;
1561 /* Prefetch the four PDPT entries in PAE mode. */
1562 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1563 }
1564 }
1565 else
1566 {
1567 val = PGMGetHyperCR3(pVCpu);
1568 Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1569 }
1570
1571 /* Save our shadow CR3 register. */
1572 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1573 AssertRC(rc);
1574 }
1575
1576 /* Debug registers. */
1577 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1578 {
1579 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1580 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1581
1582 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1583 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1584 pCtx->dr[7] |= 0x400; /* must be one */
1585
1586 /* Resync DR7 */
1587 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1588 AssertRC(rc);
1589
1590 /* Sync the debug state now if any breakpoint is armed. */
1591 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1592 && !CPUMIsGuestDebugStateActive(pVCpu)
1593 && !DBGFIsStepping(pVCpu))
1594 {
1595 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1596
1597 /* Disable drx move intercepts. */
1598 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1599 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1600 AssertRC(rc);
1601
1602 /* Save the host and load the guest debug state. */
1603 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1604 AssertRC(rc);
1605 }
1606
1607 /* IA32_DEBUGCTL MSR. */
1608 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1609 AssertRC(rc);
1610
1611 /** @todo do we really ever need this? */
1612 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1613 AssertRC(rc);
1614 }
1615
1616 /* EIP, ESP and EFLAGS */
1617 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1618 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1619 AssertRC(rc);
1620
1621 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1622 eflags = pCtx->eflags;
1623 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1624 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1625
1626#ifdef HWACCM_VMX_EMULATE_REALMODE
1627 /* Real mode emulation using v86 mode. */
1628 if (CPUMIsGuestInRealModeEx(pCtx))
1629 {
1630 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1631
1632 eflags.Bits.u1VM = 1;
1633 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1634 }
1635#endif /* HWACCM_VMX_EMULATE_REALMODE */
1636 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1637 AssertRC(rc);
1638
1639 /* TSC offset. */
1640 uint64_t u64TSCOffset;
1641
1642 if (TMCpuTickCanUseRealTSC(pVCpu, &u64TSCOffset))
1643 {
1644 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1645 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1646 AssertRC(rc);
1647
1648 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1649 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1650 AssertRC(rc);
1651 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1652 }
1653 else
1654 {
1655 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1656 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1657 AssertRC(rc);
1658 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1659 }
1660
1661 /* 64 bits guest mode? */
1662 if (CPUMIsGuestInLongModeEx(pCtx))
1663 {
1664#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1665 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1666#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1667 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1668#else
1669# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1670 if (!pVM->hwaccm.s.fAllow64BitGuests)
1671 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1672# endif
1673 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1674#endif
1675 /* Unconditionally update these as wrmsr might have changed them. */
1676 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1677 AssertRC(rc);
1678 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1679 AssertRC(rc);
1680 }
1681 else
1682 {
1683 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1684 }
1685
1686#if 0 /* @todo deal with 32/64 */
1687 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1688 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1689 {
1690 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1691 AssertRC(rc);
1692 }
1693#endif
1694
1695 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1696
1697 /* Done. */
1698 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1699
1700 return rc;
1701}
1702
1703/**
1704 * Syncs back the guest state
1705 *
1706 * @returns VBox status code.
1707 * @param pVM The VM to operate on.
1708 * @param pVCpu The VMCPU to operate on.
1709 * @param pCtx Guest context
1710 */
1711DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1712{
1713 RTGCUINTREG val, valShadow;
1714 RTGCUINTPTR uInterruptState;
1715 int rc;
1716
1717 /* Let's first sync back eip, esp, and eflags. */
1718 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1719 AssertRC(rc);
1720 pCtx->rip = val;
1721 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1722 AssertRC(rc);
1723 pCtx->rsp = val;
1724 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1725 AssertRC(rc);
1726 pCtx->eflags.u32 = val;
1727
1728 /* Take care of instruction fusing (sti, mov ss) */
1729 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1730 uInterruptState = val;
1731 if (uInterruptState != 0)
1732 {
1733 Assert(uInterruptState <= 2); /* only sti & mov ss */
1734 Log(("uInterruptState %x eip=%RGv\n", (uint32_t)uInterruptState, pCtx->rip));
1735 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1736 }
1737 else
1738 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1739
1740 /* Control registers. */
1741 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1742 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1743 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1744 CPUMSetGuestCR0(pVCpu, val);
1745
1746 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1747 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1748 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1749 CPUMSetGuestCR4(pVCpu, val);
1750
1751 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1752 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1753 if ( pVM->hwaccm.s.fNestedPaging
1754 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1755 {
1756 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1757
1758 /* Can be updated behind our back in the nested paging case. */
1759 CPUMSetGuestCR2(pVCpu, pCache->cr2);
1760
1761 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1762
1763 if (val != pCtx->cr3)
1764 {
1765 CPUMSetGuestCR3(pVCpu, val);
1766 PGMUpdateCR3(pVCpu, val);
1767 }
1768 /* Prefetch the four PDPT entries in PAE mode. */
1769 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1770 }
1771
1772 /* Sync back DR7 here. */
1773 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1774 pCtx->dr[7] = val;
1775
1776 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1777 VMX_READ_SELREG(ES, es);
1778 VMX_READ_SELREG(SS, ss);
1779 VMX_READ_SELREG(CS, cs);
1780 VMX_READ_SELREG(DS, ds);
1781 VMX_READ_SELREG(FS, fs);
1782 VMX_READ_SELREG(GS, gs);
1783
1784 /*
1785 * System MSRs
1786 */
1787 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1788 pCtx->SysEnter.cs = val;
1789 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1790 pCtx->SysEnter.eip = val;
1791 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1792 pCtx->SysEnter.esp = val;
1793
1794 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1795 VMX_READ_SELREG(LDTR, ldtr);
1796
1797 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1798 pCtx->gdtr.cbGdt = val;
1799 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1800 pCtx->gdtr.pGdt = val;
1801
1802 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1803 pCtx->idtr.cbIdt = val;
1804 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1805 pCtx->idtr.pIdt = val;
1806
1807#ifdef HWACCM_VMX_EMULATE_REALMODE
1808 /* Real mode emulation using v86 mode. */
1809 if (CPUMIsGuestInRealModeEx(pCtx))
1810 {
1811 /* Hide our emulation flags */
1812 pCtx->eflags.Bits.u1VM = 0;
1813
1814 /* Restore original IOPL setting as we always use 0. */
1815 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1816
1817 /* Force a TR resync every time in case we switch modes. */
1818 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1819 }
1820 else
1821#endif /* HWACCM_VMX_EMULATE_REALMODE */
1822 {
1823 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1824 VMX_READ_SELREG(TR, tr);
1825 }
1826 return VINF_SUCCESS;
1827}
1828
1829/**
1830 * Dummy placeholder
1831 *
1832 * @param pVM The VM to operate on.
1833 * @param pVCpu The VMCPU to operate on.
1834 */
1835static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1836{
1837 NOREF(pVM);
1838 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1839 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1840 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1841 return;
1842}
1843
1844/**
1845 * Setup the tagged TLB for EPT
1846 *
1847 * @returns VBox status code.
1848 * @param pVM The VM to operate on.
1849 * @param pVCpu The VMCPU to operate on.
1850 */
1851static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1852{
1853 PHWACCM_CPUINFO pCpu;
1854
1855 Assert(pVM->hwaccm.s.fNestedPaging);
1856 Assert(!pVM->hwaccm.s.vmx.fVPID);
1857
1858 /* Deal with tagged TLBs if VPID or EPT is supported. */
1859 pCpu = HWACCMR0GetCurrentCpu();
1860 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1861 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1862 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1863 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1864 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1865 {
1866 /* Force a TLB flush on VM entry. */
1867 pVCpu->hwaccm.s.fForceTLBFlush = true;
1868 }
1869 else
1870 Assert(!pCpu->fFlushTLB);
1871
1872 /* Check for tlb shootdown flushes. */
1873 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1874 pVCpu->hwaccm.s.fForceTLBFlush = true;
1875
1876 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1877 pCpu->fFlushTLB = false;
1878
1879 if (pVCpu->hwaccm.s.fForceTLBFlush)
1880 {
1881 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1882 }
1883 else
1884 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1885 {
1886 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1887 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1888
1889 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1890 {
1891 /* aTlbShootdownPages contains physical addresses in this case. */
1892 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1893 }
1894 }
1895 pVCpu->hwaccm.s.TlbShootdown.cPages= 0;
1896 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1897
1898#ifdef VBOX_WITH_STATISTICS
1899 if (pVCpu->hwaccm.s.fForceTLBFlush)
1900 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1901 else
1902 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1903#endif
1904}
1905
1906#ifdef HWACCM_VTX_WITH_VPID
1907/**
1908 * Setup the tagged TLB for VPID
1909 *
1910 * @returns VBox status code.
1911 * @param pVM The VM to operate on.
1912 * @param pVCpu The VMCPU to operate on.
1913 */
1914static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1915{
1916 PHWACCM_CPUINFO pCpu;
1917
1918 Assert(pVM->hwaccm.s.vmx.fVPID);
1919 Assert(!pVM->hwaccm.s.fNestedPaging);
1920
1921 /* Deal with tagged TLBs if VPID or EPT is supported. */
1922 pCpu = HWACCMR0GetCurrentCpu();
1923 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1924 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1925 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1926 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1927 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1928 {
1929 /* Force a TLB flush on VM entry. */
1930 pVCpu->hwaccm.s.fForceTLBFlush = true;
1931 }
1932 else
1933 Assert(!pCpu->fFlushTLB);
1934
1935 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1936
1937 /* Check for tlb shootdown flushes. */
1938 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1939 pVCpu->hwaccm.s.fForceTLBFlush = true;
1940
1941 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1942 if (pVCpu->hwaccm.s.fForceTLBFlush)
1943 {
1944 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1945 || pCpu->fFlushTLB)
1946 {
1947 pCpu->fFlushTLB = false;
1948 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1949 pCpu->cTLBFlushes++;
1950 }
1951 else
1952 {
1953 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1954 pVCpu->hwaccm.s.fForceTLBFlush = false;
1955 }
1956
1957 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1958 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1959 }
1960 else
1961 {
1962 Assert(!pCpu->fFlushTLB);
1963 Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
1964
1965 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1966 {
1967 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1968 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1969 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1970 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1971 }
1972 }
1973 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1974 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1975
1976 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1977 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1978 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1979
1980 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1981 AssertRC(rc);
1982
1983 if (pVCpu->hwaccm.s.fForceTLBFlush)
1984 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1985
1986#ifdef VBOX_WITH_STATISTICS
1987 if (pVCpu->hwaccm.s.fForceTLBFlush)
1988 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1989 else
1990 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1991#endif
1992}
1993#endif /* HWACCM_VTX_WITH_VPID */
1994
1995/**
1996 * Runs guest code in a VT-x VM.
1997 *
1998 * @returns VBox status code.
1999 * @param pVM The VM to operate on.
2000 * @param pVCpu The VMCPU to operate on.
2001 * @param pCtx Guest context
2002 */
2003VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2004{
2005 int rc = VINF_SUCCESS;
2006 RTGCUINTREG val;
2007 RTGCUINTREG exitReason = VMX_EXIT_INVALID;
2008 RTGCUINTREG instrError, cbInstr;
2009 RTGCUINTPTR exitQualification = 0;
2010 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
2011 RTGCUINTPTR errCode, instrInfo;
2012 bool fSetupTPRCaching = false;
2013 uint8_t u8LastTPR = 0;
2014 PHWACCM_CPUINFO pCpu = 0;
2015 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
2016 unsigned cResume = 0;
2017#ifdef VBOX_STRICT
2018 RTCPUID idCpuCheck;
2019#endif
2020#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2021 uint64_t u64LastTime = RTTimeMilliTS();
2022#endif
2023#ifdef VBOX_WITH_STATISTICS
2024 bool fStatEntryStarted = true;
2025 bool fStatExit2Started = false;
2026#endif
2027
2028 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
2029
2030 /* Check if we need to use TPR shadowing. */
2031 if ( CPUMIsGuestInLongModeEx(pCtx)
2032 || ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2033 && pVM->hwaccm.s.fHasIoApic)
2034 )
2035 {
2036 fSetupTPRCaching = true;
2037 }
2038
2039 Log2(("\nE"));
2040
2041 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
2042
2043#ifdef VBOX_STRICT
2044 {
2045 RTCCUINTREG val;
2046
2047 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
2048 AssertRC(rc);
2049 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
2050
2051 /* allowed zero */
2052 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
2053 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
2054
2055 /* allowed one */
2056 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
2057 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
2058
2059 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
2060 AssertRC(rc);
2061 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
2062
2063 /* Must be set according to the MSR, but can be cleared in case of EPT. */
2064 if (pVM->hwaccm.s.fNestedPaging)
2065 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
2066 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2067 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2068
2069 /* allowed zero */
2070 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2071 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2072
2073 /* allowed one */
2074 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2075 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2076
2077 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2078 AssertRC(rc);
2079 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2080
2081 /* allowed zero */
2082 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2083 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2084
2085 /* allowed one */
2086 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2087 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2088
2089 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2090 AssertRC(rc);
2091 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2092
2093 /* allowed zero */
2094 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2095 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2096
2097 /* allowed one */
2098 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2099 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2100 }
2101#endif
2102
2103#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2104 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2105#endif
2106
2107 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2108 */
2109ResumeExecution:
2110 STAM_STATS({
2111 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2112 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2113 });
2114 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2115 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2116 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2117 Assert(!HWACCMR0SuspendPending());
2118
2119 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2120 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
2121 {
2122 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2123 rc = VINF_EM_RAW_INTERRUPT;
2124 goto end;
2125 }
2126
2127 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2128 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2129 {
2130 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2131 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2132 {
2133 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2134 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2135 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2136 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2137 */
2138 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2139 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2140 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2141 AssertRC(rc);
2142 }
2143 }
2144 else
2145 {
2146 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2147 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2148 AssertRC(rc);
2149 }
2150
2151#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2152 if (RT_UNLIKELY(cResume & 0xf) == 0)
2153 {
2154 uint64_t u64CurTime = RTTimeMilliTS();
2155
2156 if (RT_UNLIKELY(u64CurTime > u64LastTime))
2157 {
2158 u64LastTime = u64CurTime;
2159 TMTimerPollVoid(pVM, pVCpu);
2160 }
2161 }
2162#endif
2163
2164 /* Check for pending actions that force us to go back to ring 3. */
2165#ifdef DEBUG
2166 /* Intercept X86_XCPT_DB if stepping is enabled */
2167 if (!DBGFIsStepping(pVCpu))
2168#endif
2169 {
2170 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2171 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2172 {
2173 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2174 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2175 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2176 goto end;
2177 }
2178 }
2179
2180 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2181 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2182 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2183 {
2184 rc = VINF_EM_PENDING_REQUEST;
2185 goto end;
2186 }
2187
2188#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2189 /*
2190 * Exit to ring-3 preemption/work is pending.
2191 *
2192 * Interrupts are disabled before the call to make sure we don't miss any interrupt
2193 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
2194 * further down, but VMXR0CheckPendingInterrupt makes that impossible.)
2195 *
2196 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
2197 * shootdowns rely on this.
2198 */
2199 uOldEFlags = ASMIntDisableFlags();
2200 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2201 {
2202 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
2203 rc = VINF_EM_RAW_INTERRUPT;
2204 goto end;
2205 }
2206 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2207#endif
2208
2209 /* When external interrupts are pending, we should exit the VM when IF is set. */
2210 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2211 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2212 if (RT_FAILURE(rc))
2213 goto end;
2214
2215 /** @todo check timers?? */
2216
2217 /* TPR caching using CR8 is only available in 64 bits mode */
2218 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2219 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2220 /**
2221 * @todo query and update the TPR only when it could have been changed (mmio access & wrmsr (x2apic))
2222 */
2223 if (fSetupTPRCaching)
2224 {
2225 /* TPR caching in CR8 */
2226 bool fPending;
2227
2228 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
2229 AssertRC(rc);
2230 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2231 pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8LastTPR;
2232
2233 /* Two options here:
2234 * - external interrupt pending, but masked by the TPR value.
2235 * -> a CR8 update that lower the current TPR value should cause an exit
2236 * - no pending interrupts
2237 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2238 */
2239 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
2240 AssertRC(rc);
2241 }
2242
2243#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2244 if ( pVM->hwaccm.s.fNestedPaging
2245# ifdef HWACCM_VTX_WITH_VPID
2246 || pVM->hwaccm.s.vmx.fVPID
2247# endif /* HWACCM_VTX_WITH_VPID */
2248 )
2249 {
2250 pCpu = HWACCMR0GetCurrentCpu();
2251 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2252 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2253 {
2254 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2255 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2256 else
2257 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2258 }
2259 if (pCpu->fFlushTLB)
2260 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2261 else
2262 if (pVCpu->hwaccm.s.fForceTLBFlush)
2263 LogFlow(("Manual TLB flush\n"));
2264 }
2265#endif
2266#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2267 PGMDynMapFlushAutoSet(pVCpu);
2268#endif
2269
2270 /*
2271 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2272 * (until the actual world switch)
2273 */
2274#ifdef VBOX_STRICT
2275 idCpuCheck = RTMpCpuId();
2276#endif
2277#ifdef LOG_ENABLED
2278 VMMR0LogFlushDisable(pVCpu);
2279#endif
2280 /* Save the host state first. */
2281 rc = VMXR0SaveHostState(pVM, pVCpu);
2282 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2283 {
2284 VMMR0LogFlushEnable(pVCpu);
2285 goto end;
2286 }
2287 /* Load the guest state */
2288 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2289 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2290 {
2291 VMMR0LogFlushEnable(pVCpu);
2292 goto end;
2293 }
2294
2295#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2296 /* Disable interrupts to make sure a poke will interrupt execution.
2297 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
2298 */
2299 uOldEFlags = ASMIntDisableFlags();
2300 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2301#endif
2302
2303 /* Deal with tagged TLB setup and invalidation. */
2304 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2305
2306 /* Non-register state Guest Context */
2307 /** @todo change me according to cpu state */
2308 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2309 AssertRC(rc);
2310
2311 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2312
2313 /* Manual save and restore:
2314 * - General purpose registers except RIP, RSP
2315 *
2316 * Trashed:
2317 * - CR2 (we don't care)
2318 * - LDTR (reset to 0)
2319 * - DRx (presumably not changed at all)
2320 * - DR7 (reset to 0x400)
2321 * - EFLAGS (reset to RT_BIT(1); not relevant)
2322 *
2323 */
2324
2325
2326 /* All done! Let's start VM execution. */
2327 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2328 Assert(idCpuCheck == RTMpCpuId());
2329
2330#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2331 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2332 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2333#endif
2334
2335 TMNotifyStartOfExecution(pVCpu);
2336#ifdef VBOX_WITH_KERNEL_USING_XMM
2337 rc = hwaccmR0VMXStartVMWrapXMM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hwaccm.s.vmx.pfnStartVM);
2338#else
2339 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2340#endif
2341 TMNotifyEndOfExecution(pVCpu);
2342 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2343 Assert(!(ASMGetFlags() & X86_EFL_IF));
2344 ASMSetFlags(uOldEFlags);
2345#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2346 uOldEFlags = ~(RTCCUINTREG)0;
2347#endif
2348
2349 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2350
2351 /* In case we execute a goto ResumeExecution later on. */
2352 pVCpu->hwaccm.s.fResumeVM = true;
2353 pVCpu->hwaccm.s.fForceTLBFlush = false;
2354
2355 /*
2356 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2357 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2358 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2359 */
2360 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2361 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2362
2363 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2364 {
2365 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2366 VMMR0LogFlushEnable(pVCpu);
2367 goto end;
2368 }
2369
2370 /* Success. Query the guest state and figure out what has happened. */
2371
2372 /* Investigate why there was a VM-exit. */
2373 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2374 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2375
2376 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2377 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2378 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2379 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2380 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2381 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2382 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2383 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2384 AssertRC(rc);
2385
2386 /* Sync back the guest state */
2387 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2388 AssertRC(rc);
2389
2390 /* Note! NOW IT'S SAFE FOR LOGGING! */
2391 VMMR0LogFlushEnable(pVCpu);
2392 Log2(("Raw exit reason %08x\n", exitReason));
2393
2394 /* Check if an injected event was interrupted prematurely. */
2395 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2396 AssertRC(rc);
2397 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2398 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2399 /* Ignore 'int xx' as they'll be restarted anyway. */
2400 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2401 /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
2402 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2403 {
2404 Assert(!pVCpu->hwaccm.s.Event.fPending);
2405 pVCpu->hwaccm.s.Event.fPending = true;
2406 /* Error code present? */
2407 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2408 {
2409 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2410 AssertRC(rc);
2411 pVCpu->hwaccm.s.Event.errCode = val;
2412 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2413 }
2414 else
2415 {
2416 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2417 pVCpu->hwaccm.s.Event.errCode = 0;
2418 }
2419 }
2420#ifdef VBOX_STRICT
2421 else
2422 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2423 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2424 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2425 {
2426 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2427 }
2428
2429 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2430 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2431#endif
2432
2433 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2434 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2435 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2436 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2437 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2438
2439 /* Sync back the TPR if it was changed. */
2440 if ( fSetupTPRCaching
2441 && u8LastTPR != pVCpu->hwaccm.s.vmx.pVAPIC[0x80])
2442 {
2443 rc = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);
2444 AssertRC(rc);
2445 }
2446
2447 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2448 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2449
2450 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2451 switch (exitReason)
2452 {
2453 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2454 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2455 {
2456 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2457
2458 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2459 {
2460 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2461 /* External interrupt; leave to allow it to be dispatched again. */
2462 rc = VINF_EM_RAW_INTERRUPT;
2463 break;
2464 }
2465 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2466 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2467 {
2468 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2469 /* External interrupt; leave to allow it to be dispatched again. */
2470 rc = VINF_EM_RAW_INTERRUPT;
2471 break;
2472
2473 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2474 AssertFailed(); /* can't come here; fails the first check. */
2475 break;
2476
2477 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2478 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2479 Assert(vector == 1 || vector == 3 || vector == 4);
2480 /* no break */
2481 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2482 Log2(("Hardware/software interrupt %d\n", vector));
2483 switch (vector)
2484 {
2485 case X86_XCPT_NM:
2486 {
2487 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2488
2489 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2490 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2491 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2492 if (rc == VINF_SUCCESS)
2493 {
2494 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2495
2496 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2497
2498 /* Continue execution. */
2499 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2500
2501 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2502 goto ResumeExecution;
2503 }
2504
2505 Log(("Forward #NM fault to the guest\n"));
2506 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2507 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2508 AssertRC(rc);
2509 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2510 goto ResumeExecution;
2511 }
2512
2513 case X86_XCPT_PF: /* Page fault */
2514 {
2515#ifdef DEBUG
2516 if (pVM->hwaccm.s.fNestedPaging)
2517 { /* A genuine pagefault.
2518 * Forward the trap to the guest by injecting the exception and resuming execution.
2519 */
2520 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2521
2522 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2523
2524 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2525
2526 /* Now we must update CR2. */
2527 pCtx->cr2 = exitQualification;
2528 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2529 AssertRC(rc);
2530
2531 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2532 goto ResumeExecution;
2533 }
2534#endif
2535 Assert(!pVM->hwaccm.s.fNestedPaging);
2536
2537 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2538 /* Exit qualification contains the linear address of the page fault. */
2539 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2540 TRPMSetErrorCode(pVCpu, errCode);
2541 TRPMSetFaultAddress(pVCpu, exitQualification);
2542
2543 /* Shortcut for APIC TPR reads and writes. */
2544 if ( (exitQualification & 0xfff) == 0x080
2545 && !(errCode & X86_TRAP_PF_P) /* not present */
2546 && fSetupTPRCaching
2547 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
2548 {
2549 RTGCPHYS GCPhysApicBase, GCPhys;
2550 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
2551 GCPhysApicBase &= PAGE_BASE_GC_MASK;
2552
2553 rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
2554 if ( rc == VINF_SUCCESS
2555 && GCPhys == GCPhysApicBase)
2556 {
2557 Log(("Enable VT-x virtual APIC access filtering\n"));
2558 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
2559 AssertRC(rc);
2560 }
2561 }
2562
2563 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2564 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2565 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2566 if (rc == VINF_SUCCESS)
2567 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2568 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2569 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2570
2571 TRPMResetTrap(pVCpu);
2572
2573 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2574 goto ResumeExecution;
2575 }
2576 else
2577 if (rc == VINF_EM_RAW_GUEST_TRAP)
2578 { /* A genuine pagefault.
2579 * Forward the trap to the guest by injecting the exception and resuming execution.
2580 */
2581 Log2(("Forward page fault to the guest\n"));
2582
2583 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2584 /* The error code might have been changed. */
2585 errCode = TRPMGetErrorCode(pVCpu);
2586
2587 TRPMResetTrap(pVCpu);
2588
2589 /* Now we must update CR2. */
2590 pCtx->cr2 = exitQualification;
2591 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2592 AssertRC(rc);
2593
2594 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2595 goto ResumeExecution;
2596 }
2597#ifdef VBOX_STRICT
2598 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2599 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2600#endif
2601 /* Need to go back to the recompiler to emulate the instruction. */
2602 TRPMResetTrap(pVCpu);
2603 break;
2604 }
2605
2606 case X86_XCPT_MF: /* Floating point exception. */
2607 {
2608 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2609 if (!(pCtx->cr0 & X86_CR0_NE))
2610 {
2611 /* old style FPU error reporting needs some extra work. */
2612 /** @todo don't fall back to the recompiler, but do it manually. */
2613 rc = VINF_EM_RAW_EMULATE_INSTR;
2614 break;
2615 }
2616 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2617 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2618 AssertRC(rc);
2619
2620 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2621 goto ResumeExecution;
2622 }
2623
2624 case X86_XCPT_DB: /* Debug exception. */
2625 {
2626 uint64_t uDR6;
2627
2628 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2629 *
2630 * Exit qualification bits:
2631 * 3:0 B0-B3 which breakpoint condition was met
2632 * 12:4 Reserved (0)
2633 * 13 BD - debug register access detected
2634 * 14 BS - single step execution or branch taken
2635 * 63:15 Reserved (0)
2636 */
2637 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2638
2639 /* Note that we don't support guest and host-initiated debugging at the same time. */
2640 Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx));
2641
2642 uDR6 = X86_DR6_INIT_VAL;
2643 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2644 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
2645 if (rc == VINF_EM_RAW_GUEST_TRAP)
2646 {
2647 /** @todo this isn't working, but we'll never get here normally. */
2648
2649 /* Update DR6 here. */
2650 pCtx->dr[6] = uDR6;
2651
2652 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2653 pCtx->dr[7] &= ~X86_DR7_GD;
2654
2655 /* Paranoia. */
2656 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2657 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2658 pCtx->dr[7] |= 0x400; /* must be one */
2659
2660 /* Resync DR7 */
2661 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2662 AssertRC(rc);
2663
2664 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2665 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2666 AssertRC(rc);
2667
2668 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2669 goto ResumeExecution;
2670 }
2671 /* Return to ring 3 to deal with the debug exit code. */
2672 break;
2673 }
2674
2675 case X86_XCPT_BP: /* Breakpoint. */
2676 {
2677 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2678 if (rc == VINF_EM_RAW_GUEST_TRAP)
2679 {
2680 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2681 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2682 AssertRC(rc);
2683 goto ResumeExecution;
2684 }
2685 if (rc == VINF_SUCCESS)
2686 goto ResumeExecution;
2687 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2688 break;
2689 }
2690
2691 case X86_XCPT_GP: /* General protection failure exception.*/
2692 {
2693 uint32_t cbOp;
2694 uint32_t cbSize;
2695 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2696
2697 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2698#ifdef VBOX_STRICT
2699 if (!CPUMIsGuestInRealModeEx(pCtx))
2700 {
2701 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2702 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2703 AssertRC(rc);
2704 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2705 goto ResumeExecution;
2706 }
2707#endif
2708 Assert(CPUMIsGuestInRealModeEx(pCtx));
2709
2710 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2711
2712 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2713 if (RT_SUCCESS(rc))
2714 {
2715 bool fUpdateRIP = true;
2716
2717 Assert(cbOp == pDis->opsize);
2718 switch (pDis->pCurInstr->opcode)
2719 {
2720 case OP_CLI:
2721 pCtx->eflags.Bits.u1IF = 0;
2722 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2723 break;
2724
2725 case OP_STI:
2726 pCtx->eflags.Bits.u1IF = 1;
2727 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2728 break;
2729
2730 case OP_HLT:
2731 fUpdateRIP = false;
2732 rc = VINF_EM_HALT;
2733 pCtx->rip += pDis->opsize;
2734 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2735 break;
2736
2737 case OP_POPF:
2738 {
2739 RTGCPTR GCPtrStack;
2740 uint32_t cbParm;
2741 uint32_t uMask;
2742 X86EFLAGS eflags;
2743
2744 if (pDis->prefix & PREFIX_OPSIZE)
2745 {
2746 cbParm = 4;
2747 uMask = 0xffffffff;
2748 }
2749 else
2750 {
2751 cbParm = 2;
2752 uMask = 0xffff;
2753 }
2754
2755 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2756 if (RT_FAILURE(rc))
2757 {
2758 rc = VERR_EM_INTERPRETER;
2759 break;
2760 }
2761 eflags.u = 0;
2762 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2763 if (RT_FAILURE(rc))
2764 {
2765 rc = VERR_EM_INTERPRETER;
2766 break;
2767 }
2768 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2769 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
2770 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
2771 pCtx->eflags.Bits.u1RF = 0;
2772 pCtx->esp += cbParm;
2773 pCtx->esp &= uMask;
2774
2775 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2776 break;
2777 }
2778
2779 case OP_PUSHF:
2780 {
2781 RTGCPTR GCPtrStack;
2782 uint32_t cbParm;
2783 uint32_t uMask;
2784 X86EFLAGS eflags;
2785
2786 if (pDis->prefix & PREFIX_OPSIZE)
2787 {
2788 cbParm = 4;
2789 uMask = 0xffffffff;
2790 }
2791 else
2792 {
2793 cbParm = 2;
2794 uMask = 0xffff;
2795 }
2796
2797 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2798 if (RT_FAILURE(rc))
2799 {
2800 rc = VERR_EM_INTERPRETER;
2801 break;
2802 }
2803 eflags = pCtx->eflags;
2804 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2805 eflags.Bits.u1RF = 0;
2806 eflags.Bits.u1VM = 0;
2807
2808 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2809 if (RT_FAILURE(rc))
2810 {
2811 rc = VERR_EM_INTERPRETER;
2812 break;
2813 }
2814 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2815 pCtx->esp -= cbParm;
2816 pCtx->esp &= uMask;
2817 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2818 break;
2819 }
2820
2821 case OP_IRET:
2822 {
2823 RTGCPTR GCPtrStack;
2824 uint32_t uMask = 0xffff;
2825 uint16_t aIretFrame[3];
2826
2827 if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
2828 {
2829 rc = VERR_EM_INTERPRETER;
2830 break;
2831 }
2832
2833 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2834 if (RT_FAILURE(rc))
2835 {
2836 rc = VERR_EM_INTERPRETER;
2837 break;
2838 }
2839 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2840 if (RT_FAILURE(rc))
2841 {
2842 rc = VERR_EM_INTERPRETER;
2843 break;
2844 }
2845 pCtx->ip = aIretFrame[0];
2846 pCtx->cs = aIretFrame[1];
2847 pCtx->csHid.u64Base = pCtx->cs << 4;
2848 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2849 pCtx->sp += sizeof(aIretFrame);
2850
2851 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2852 fUpdateRIP = false;
2853 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2854 break;
2855 }
2856
2857 case OP_INT:
2858 {
2859 RTGCUINTPTR intInfo;
2860
2861 LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
2862 intInfo = pDis->param1.parval & 0xff;
2863 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2864 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2865
2866 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2867 AssertRC(rc);
2868 fUpdateRIP = false;
2869 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2870 break;
2871 }
2872
2873 case OP_INTO:
2874 {
2875 if (pCtx->eflags.Bits.u1OF)
2876 {
2877 RTGCUINTPTR intInfo;
2878
2879 LogFlow(("Realmode: INTO\n"));
2880 intInfo = X86_XCPT_OF;
2881 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2882 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2883
2884 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2885 AssertRC(rc);
2886 fUpdateRIP = false;
2887 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2888 }
2889 break;
2890 }
2891
2892 case OP_INT3:
2893 {
2894 RTGCUINTPTR intInfo;
2895
2896 LogFlow(("Realmode: INT 3\n"));
2897 intInfo = 3;
2898 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2899 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2900
2901 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2902 AssertRC(rc);
2903 fUpdateRIP = false;
2904 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2905 break;
2906 }
2907
2908 default:
2909 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
2910 break;
2911 }
2912
2913 if (rc == VINF_SUCCESS)
2914 {
2915 if (fUpdateRIP)
2916 pCtx->rip += cbOp; /* Move on to the next instruction. */
2917
2918 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2919 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2920
2921 /* Only resume if successful. */
2922 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2923 goto ResumeExecution;
2924 }
2925 }
2926 else
2927 rc = VERR_EM_INTERPRETER;
2928
2929 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2930 break;
2931 }
2932
2933#ifdef VBOX_STRICT
2934 case X86_XCPT_DE: /* Divide error. */
2935 case X86_XCPT_UD: /* Unknown opcode exception. */
2936 case X86_XCPT_SS: /* Stack segment exception. */
2937 case X86_XCPT_NP: /* Segment not present exception. */
2938 {
2939 switch(vector)
2940 {
2941 case X86_XCPT_DE:
2942 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2943 break;
2944 case X86_XCPT_UD:
2945 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2946 break;
2947 case X86_XCPT_SS:
2948 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2949 break;
2950 case X86_XCPT_NP:
2951 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2952 break;
2953 }
2954
2955 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2956 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2957 AssertRC(rc);
2958
2959 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2960 goto ResumeExecution;
2961 }
2962#endif
2963 default:
2964#ifdef HWACCM_VMX_EMULATE_REALMODE
2965 if (CPUMIsGuestInRealModeEx(pCtx))
2966 {
2967 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2968 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2969 AssertRC(rc);
2970
2971 /* Go back to ring 3 in case of a triple fault. */
2972 if ( vector == X86_XCPT_DF
2973 && rc == VINF_EM_RESET)
2974 break;
2975
2976 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2977 goto ResumeExecution;
2978 }
2979#endif
2980 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2981 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2982 break;
2983 } /* switch (vector) */
2984
2985 break;
2986
2987 default:
2988 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2989 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2990 break;
2991 }
2992
2993 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2994 break;
2995 }
2996
2997 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2998 {
2999 RTGCPHYS GCPhys;
3000
3001 Assert(pVM->hwaccm.s.fNestedPaging);
3002
3003 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3004 AssertRC(rc);
3005 Assert(((exitQualification >> 7) & 3) != 2);
3006
3007 /* Determine the kind of violation. */
3008 errCode = 0;
3009 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
3010 errCode |= X86_TRAP_PF_ID;
3011
3012 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
3013 errCode |= X86_TRAP_PF_RW;
3014
3015 /* If the page is present, then it's a page level protection fault. */
3016 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
3017 {
3018 errCode |= X86_TRAP_PF_P;
3019 }
3020 else {
3021 /* Shortcut for APIC TPR reads and writes. */
3022 if ( (GCPhys & 0xfff) == 0x080
3023 && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
3024 && fSetupTPRCaching
3025 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
3026 {
3027 RTGCPHYS GCPhysApicBase;
3028 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
3029 GCPhysApicBase &= PAGE_BASE_GC_MASK;
3030 if (GCPhys == GCPhysApicBase + 0x80)
3031 {
3032 Log(("Enable VT-x virtual APIC access filtering\n"));
3033 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
3034 AssertRC(rc);
3035 }
3036 }
3037 }
3038 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
3039
3040 /* GCPhys contains the guest physical address of the page fault. */
3041 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
3042 TRPMSetErrorCode(pVCpu, errCode);
3043 TRPMSetFaultAddress(pVCpu, GCPhys);
3044
3045 /* Handle the pagefault trap for the nested shadow table. */
3046 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
3047 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
3048 if (rc == VINF_SUCCESS)
3049 { /* We've successfully synced our shadow pages, so let's just continue execution. */
3050 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
3051 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
3052
3053 TRPMResetTrap(pVCpu);
3054
3055 goto ResumeExecution;
3056 }
3057
3058#ifdef VBOX_STRICT
3059 if (rc != VINF_EM_RAW_EMULATE_INSTR)
3060 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
3061#endif
3062 /* Need to go back to the recompiler to emulate the instruction. */
3063 TRPMResetTrap(pVCpu);
3064 break;
3065 }
3066
3067 case VMX_EXIT_EPT_MISCONFIG:
3068 {
3069 RTGCPHYS GCPhys;
3070
3071 Assert(pVM->hwaccm.s.fNestedPaging);
3072
3073 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3074 AssertRC(rc);
3075
3076 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
3077 break;
3078 }
3079
3080 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3081 /* Clear VM-exit on IF=1 change. */
3082 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
3083 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
3084 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3085 AssertRC(rc);
3086 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
3087 goto ResumeExecution; /* we check for pending guest interrupts there */
3088
3089 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
3090 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
3091 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
3092 /* Skip instruction and continue directly. */
3093 pCtx->rip += cbInstr;
3094 /* Continue execution.*/
3095 goto ResumeExecution;
3096
3097 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3098 {
3099 Log2(("VMX: Cpuid %x\n", pCtx->eax));
3100 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
3101 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3102 if (rc == VINF_SUCCESS)
3103 {
3104 /* Update EIP and continue execution. */
3105 Assert(cbInstr == 2);
3106 pCtx->rip += cbInstr;
3107 goto ResumeExecution;
3108 }
3109 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
3110 rc = VINF_EM_RAW_EMULATE_INSTR;
3111 break;
3112 }
3113
3114 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3115 {
3116 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
3117 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
3118 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3119 if (rc == VINF_SUCCESS)
3120 {
3121 /* Update EIP and continue execution. */
3122 Assert(cbInstr == 2);
3123 pCtx->rip += cbInstr;
3124 goto ResumeExecution;
3125 }
3126 rc = VINF_EM_RAW_EMULATE_INSTR;
3127 break;
3128 }
3129
3130 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3131 {
3132 Log2(("VMX: Rdtsc\n"));
3133 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
3134 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3135 if (rc == VINF_SUCCESS)
3136 {
3137 /* Update EIP and continue execution. */
3138 Assert(cbInstr == 2);
3139 pCtx->rip += cbInstr;
3140 goto ResumeExecution;
3141 }
3142 rc = VINF_EM_RAW_EMULATE_INSTR;
3143 break;
3144 }
3145
3146 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3147 {
3148 Log2(("VMX: invlpg\n"));
3149 Assert(!pVM->hwaccm.s.fNestedPaging);
3150
3151 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
3152 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
3153 if (rc == VINF_SUCCESS)
3154 {
3155 /* Update EIP and continue execution. */
3156 pCtx->rip += cbInstr;
3157 goto ResumeExecution;
3158 }
3159 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
3160 break;
3161 }
3162
3163 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3164 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3165 {
3166 uint32_t cbSize;
3167
3168 STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
3169
3170 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3171 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3172 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3173 if (rc == VINF_SUCCESS)
3174 {
3175 /* EIP has been updated already. */
3176
3177 /* Only resume if successful. */
3178 goto ResumeExecution;
3179 }
3180 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
3181 break;
3182 }
3183
3184 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3185 {
3186 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3187
3188 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3189 {
3190 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3191 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3192 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3193 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3194 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3195 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3196
3197 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3198 {
3199 case 0:
3200 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3201 break;
3202 case 2:
3203 break;
3204 case 3:
3205 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3206 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3207 break;
3208 case 4:
3209 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3210 break;
3211 case 8:
3212 /* CR8 contains the APIC TPR */
3213 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3214 break;
3215
3216 default:
3217 AssertFailed();
3218 break;
3219 }
3220 /* Check if a sync operation is pending. */
3221 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3222 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3223 {
3224 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3225 AssertRC(rc);
3226 }
3227 break;
3228
3229 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3230 Log2(("VMX: mov x, crx\n"));
3231 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3232
3233 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3234
3235 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3236 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3237
3238 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3239 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3240 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3241 break;
3242
3243 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3244 Log2(("VMX: clts\n"));
3245 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3246 rc = EMInterpretCLTS(pVM, pVCpu);
3247 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3248 break;
3249
3250 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3251 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3252 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3253 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3254 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3255 break;
3256 }
3257
3258 /* Update EIP if no error occurred. */
3259 if (RT_SUCCESS(rc))
3260 pCtx->rip += cbInstr;
3261
3262 if (rc == VINF_SUCCESS)
3263 {
3264 /* Only resume if successful. */
3265 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3266 goto ResumeExecution;
3267 }
3268 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3269 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3270 break;
3271 }
3272
3273 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3274 {
3275 if (!DBGFIsStepping(pVCpu))
3276 {
3277 /* Disable drx move intercepts. */
3278 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3279 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3280 AssertRC(rc);
3281
3282 /* Save the host and load the guest debug state. */
3283 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3284 AssertRC(rc);
3285
3286#ifdef VBOX_WITH_STATISTICS
3287 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3288 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3289 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3290 else
3291 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3292#endif
3293
3294 goto ResumeExecution;
3295 }
3296
3297 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3298 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3299 {
3300 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3301 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3302 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3303 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3304 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3305 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3306 Log2(("DR7=%08x\n", pCtx->dr[7]));
3307 }
3308 else
3309 {
3310 Log2(("VMX: mov x, drx\n"));
3311 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3312 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3313 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3314 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3315 }
3316 /* Update EIP if no error occurred. */
3317 if (RT_SUCCESS(rc))
3318 pCtx->rip += cbInstr;
3319
3320 if (rc == VINF_SUCCESS)
3321 {
3322 /* Only resume if successful. */
3323 goto ResumeExecution;
3324 }
3325 Assert(rc == VERR_EM_INTERPRETER);
3326 break;
3327 }
3328
3329 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3330 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3331 {
3332 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3333 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3334 uint32_t uPort;
3335 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3336
3337 /** @todo necessary to make the distinction? */
3338 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3339 {
3340 uPort = pCtx->edx & 0xffff;
3341 }
3342 else
3343 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3344
3345 /* paranoia */
3346 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3347 {
3348 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3349 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3350 break;
3351 }
3352
3353 uint32_t cbSize = g_aIOSize[uIOWidth];
3354
3355 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3356 {
3357 /* ins/outs */
3358 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
3359
3360 /* Disassemble manually to deal with segment prefixes. */
3361 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3362 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3363 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
3364 if (rc == VINF_SUCCESS)
3365 {
3366 if (fIOWrite)
3367 {
3368 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3369 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3370 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3371 }
3372 else
3373 {
3374 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3375 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3376 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3377 }
3378 }
3379 else
3380 rc = VINF_EM_RAW_EMULATE_INSTR;
3381 }
3382 else
3383 {
3384 /* normal in/out */
3385 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3386
3387 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3388
3389 if (fIOWrite)
3390 {
3391 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3392 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3393 }
3394 else
3395 {
3396 uint32_t u32Val = 0;
3397
3398 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3399 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3400 if (IOM_SUCCESS(rc))
3401 {
3402 /* Write back to the EAX register. */
3403 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3404 }
3405 }
3406 }
3407 /*
3408 * Handled the I/O return codes.
3409 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3410 */
3411 if (IOM_SUCCESS(rc))
3412 {
3413 /* Update EIP and continue execution. */
3414 pCtx->rip += cbInstr;
3415 if (RT_LIKELY(rc == VINF_SUCCESS))
3416 {
3417 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3418 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3419 {
3420 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3421 for (unsigned i=0;i<4;i++)
3422 {
3423 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3424
3425 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3426 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3427 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3428 {
3429 uint64_t uDR6;
3430
3431 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3432
3433 uDR6 = ASMGetDR6();
3434
3435 /* Clear all breakpoint status flags and set the one we just hit. */
3436 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3437 uDR6 |= (uint64_t)RT_BIT(i);
3438
3439 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3440 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3441 * the contents have been read.
3442 */
3443 ASMSetDR6(uDR6);
3444
3445 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3446 pCtx->dr[7] &= ~X86_DR7_GD;
3447
3448 /* Paranoia. */
3449 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3450 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3451 pCtx->dr[7] |= 0x400; /* must be one */
3452
3453 /* Resync DR7 */
3454 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3455 AssertRC(rc);
3456
3457 /* Construct inject info. */
3458 intInfo = X86_XCPT_DB;
3459 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3460 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3461
3462 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3463 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3464 AssertRC(rc);
3465
3466 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3467 goto ResumeExecution;
3468 }
3469 }
3470 }
3471
3472 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3473 goto ResumeExecution;
3474 }
3475 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3476 break;
3477 }
3478
3479#ifdef VBOX_STRICT
3480 if (rc == VINF_IOM_HC_IOPORT_READ)
3481 Assert(!fIOWrite);
3482 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3483 Assert(fIOWrite);
3484 else
3485 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3486#endif
3487 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3488 break;
3489 }
3490
3491 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3492 LogFlow(("VMX_EXIT_TPR\n"));
3493 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3494 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3495 goto ResumeExecution;
3496
3497 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3498 {
3499 LogFlow(("VMX_EXIT_APIC_ACCESS\n"));
3500 unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
3501
3502 switch(uAccessType)
3503 {
3504 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
3505 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
3506 {
3507 RTGCPHYS GCPhys;
3508 PDMApicGetBase(pVM, &GCPhys);
3509 GCPhys &= PAGE_BASE_GC_MASK;
3510 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
3511
3512 LogFlow(("Apic access at %RGp\n", GCPhys));
3513 rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
3514 if (rc == VINF_SUCCESS)
3515 {
3516 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3517 goto ResumeExecution; /* rip already updated */
3518 }
3519 break;
3520 }
3521
3522 default:
3523 rc = VINF_EM_RAW_EMULATE_INSTR;
3524 break;
3525 }
3526 break;
3527 }
3528
3529 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3530 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3531 goto ResumeExecution;
3532
3533 default:
3534 /* The rest is handled after syncing the entire CPU state. */
3535 break;
3536 }
3537
3538 /* Note: the guest state isn't entirely synced back at this stage. */
3539
3540 /* Investigate why there was a VM-exit. (part 2) */
3541 switch (exitReason)
3542 {
3543 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3544 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3545 case VMX_EXIT_EPT_VIOLATION:
3546 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3547 /* Already handled above. */
3548 break;
3549
3550 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3551 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3552 break;
3553
3554 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3555 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3556 rc = VINF_EM_RAW_INTERRUPT;
3557 AssertFailed(); /* Can't happen. Yet. */
3558 break;
3559
3560 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3561 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3562 rc = VINF_EM_RAW_INTERRUPT;
3563 AssertFailed(); /* Can't happen afaik. */
3564 break;
3565
3566 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3567 rc = VERR_EM_INTERPRETER;
3568 break;
3569
3570 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3571 /** Check if external interrupts are pending; if so, don't switch back. */
3572 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
3573 pCtx->rip++; /* skip hlt */
3574 if ( pCtx->eflags.Bits.u1IF
3575 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3576 goto ResumeExecution;
3577
3578 rc = VINF_EM_HALT;
3579 break;
3580
3581 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3582 Log2(("VMX: mwait\n"));
3583 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
3584 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3585 if ( rc == VINF_EM_HALT
3586 || rc == VINF_SUCCESS)
3587 {
3588 /* Update EIP and continue execution. */
3589 pCtx->rip += cbInstr;
3590
3591 /** Check if external interrupts are pending; if so, don't switch back. */
3592 if ( rc == VINF_SUCCESS
3593 || ( rc == VINF_EM_HALT
3594 && pCtx->eflags.Bits.u1IF
3595 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3596 )
3597 goto ResumeExecution;
3598 }
3599 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
3600 break;
3601
3602 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3603 AssertFailed(); /* can't happen. */
3604 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3605 break;
3606
3607 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3608 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3609 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3610 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3611 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3612 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3613 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3614 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3615 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3616 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3617 /** @todo inject #UD immediately */
3618 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3619 break;
3620
3621 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3622 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3623 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3624 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3625 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3626 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3627 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3628 /* already handled above */
3629 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3630 || rc == VINF_EM_RAW_INTERRUPT
3631 || rc == VERR_EM_INTERPRETER
3632 || rc == VINF_EM_RAW_EMULATE_INSTR
3633 || rc == VINF_PGM_SYNC_CR3
3634 || rc == VINF_IOM_HC_IOPORT_READ
3635 || rc == VINF_IOM_HC_IOPORT_WRITE
3636 || rc == VINF_EM_RAW_GUEST_TRAP
3637 || rc == VINF_TRPM_XCPT_DISPATCHED
3638 || rc == VINF_EM_RESCHEDULE_REM,
3639 ("rc = %d\n", rc));
3640 break;
3641
3642 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3643 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3644 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3645 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3646 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3647 rc = VERR_EM_INTERPRETER;
3648 break;
3649
3650 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3651 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3652 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3653 break;
3654
3655 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3656 Assert(rc == VINF_EM_RAW_INTERRUPT);
3657 break;
3658
3659 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3660 {
3661#ifdef VBOX_STRICT
3662 RTCCUINTREG val = 0;
3663
3664 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3665
3666 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3667 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3668
3669 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3670 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3671
3672 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3673 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3674
3675 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3676 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3677
3678 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3679 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3680
3681 VMX_LOG_SELREG(CS, "CS");
3682 VMX_LOG_SELREG(DS, "DS");
3683 VMX_LOG_SELREG(ES, "ES");
3684 VMX_LOG_SELREG(FS, "FS");
3685 VMX_LOG_SELREG(GS, "GS");
3686 VMX_LOG_SELREG(SS, "SS");
3687 VMX_LOG_SELREG(TR, "TR");
3688 VMX_LOG_SELREG(LDTR, "LDTR");
3689
3690 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3691 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3692 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3693 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3694#endif /* VBOX_STRICT */
3695 rc = VERR_VMX_INVALID_GUEST_STATE;
3696 break;
3697 }
3698
3699 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3700 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3701 default:
3702 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3703 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3704 break;
3705
3706 }
3707end:
3708
3709 /* Signal changes for the recompiler. */
3710 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3711
3712 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3713 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3714 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3715 {
3716 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3717 /* On the next entry we'll only sync the host context. */
3718 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3719 }
3720 else
3721 {
3722 /* On the next entry we'll sync everything. */
3723 /** @todo we can do better than this */
3724 /* Not in the VINF_PGM_CHANGE_MODE though! */
3725 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3726 }
3727
3728 /* translate into a less severe return code */
3729 if (rc == VERR_EM_INTERPRETER)
3730 rc = VINF_EM_RAW_EMULATE_INSTR;
3731 else
3732 /* Try to extract more information about what might have gone wrong here. */
3733 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3734 {
3735 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3736 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3737 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3738 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3739 }
3740
3741 /* Just set the correct state here instead of trying to catch every goto above. */
3742 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
3743
3744#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
3745 /* Restore interrupts if we exitted after disabling them. */
3746 if (uOldEFlags != ~(RTCCUINTREG)0)
3747 ASMSetFlags(uOldEFlags);
3748#endif
3749
3750 STAM_STATS({
3751 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3752 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3753 });
3754 Log2(("X"));
3755 return rc;
3756}
3757
3758
3759/**
3760 * Enters the VT-x session
3761 *
3762 * @returns VBox status code.
3763 * @param pVM The VM to operate on.
3764 * @param pVCpu The VMCPU to operate on.
3765 * @param pCpu CPU info struct
3766 */
3767VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3768{
3769 Assert(pVM->hwaccm.s.vmx.fSupported);
3770
3771 unsigned cr4 = ASMGetCR4();
3772 if (!(cr4 & X86_CR4_VMXE))
3773 {
3774 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3775 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3776 }
3777
3778 /* Activate the VM Control Structure. */
3779 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3780 if (RT_FAILURE(rc))
3781 return rc;
3782
3783 pVCpu->hwaccm.s.fResumeVM = false;
3784 return VINF_SUCCESS;
3785}
3786
3787
3788/**
3789 * Leaves the VT-x session
3790 *
3791 * @returns VBox status code.
3792 * @param pVM The VM to operate on.
3793 * @param pVCpu The VMCPU to operate on.
3794 * @param pCtx CPU context
3795 */
3796VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3797{
3798 Assert(pVM->hwaccm.s.vmx.fSupported);
3799
3800 /* Save the guest debug state if necessary. */
3801 if (CPUMIsGuestDebugStateActive(pVCpu))
3802 {
3803 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3804
3805 /* Enable drx move intercepts again. */
3806 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3807 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3808 AssertRC(rc);
3809
3810 /* Resync the debug registers the next time. */
3811 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3812 }
3813 else
3814 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3815
3816 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3817 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3818 AssertRC(rc);
3819
3820 return VINF_SUCCESS;
3821}
3822
3823/**
3824 * Flush the TLB (EPT)
3825 *
3826 * @returns VBox status code.
3827 * @param pVM The VM to operate on.
3828 * @param pVCpu The VM CPU to operate on.
3829 * @param enmFlush Type of flush
3830 * @param GCPhys Physical address of the page to flush
3831 */
3832static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3833{
3834 uint64_t descriptor[2];
3835
3836 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3837 Assert(pVM->hwaccm.s.fNestedPaging);
3838 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3839 descriptor[1] = GCPhys;
3840 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3841 AssertRC(rc);
3842}
3843
3844#ifdef HWACCM_VTX_WITH_VPID
3845/**
3846 * Flush the TLB (EPT)
3847 *
3848 * @returns VBox status code.
3849 * @param pVM The VM to operate on.
3850 * @param pVCpu The VM CPU to operate on.
3851 * @param enmFlush Type of flush
3852 * @param GCPtr Virtual address of the page to flush
3853 */
3854static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3855{
3856#if HC_ARCH_BITS == 32
3857 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3858 if ( CPUMIsGuestInLongMode(pVCpu)
3859 && !VMX_IS_64BIT_HOST_MODE())
3860 {
3861 pVCpu->hwaccm.s.fForceTLBFlush = true;
3862 }
3863 else
3864#endif
3865 {
3866 uint64_t descriptor[2];
3867
3868 Assert(pVM->hwaccm.s.vmx.fVPID);
3869 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3870 descriptor[1] = GCPtr;
3871 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3872 AssertRC(rc);
3873 }
3874}
3875#endif /* HWACCM_VTX_WITH_VPID */
3876
3877/**
3878 * Invalidates a guest page
3879 *
3880 * @returns VBox status code.
3881 * @param pVM The VM to operate on.
3882 * @param pVCpu The VM CPU to operate on.
3883 * @param GCVirt Page to invalidate
3884 */
3885VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3886{
3887 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3888
3889 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3890
3891 /* Only relevant if we want to use VPID.
3892 * In the nested paging case we still see such calls, but
3893 * can safely ignore them. (e.g. after cr3 updates)
3894 */
3895#ifdef HWACCM_VTX_WITH_VPID
3896 /* Skip it if a TLB flush is already pending. */
3897 if ( !fFlushPending
3898 && pVM->hwaccm.s.vmx.fVPID)
3899 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3900#endif /* HWACCM_VTX_WITH_VPID */
3901
3902 return VINF_SUCCESS;
3903}
3904
3905/**
3906 * Invalidates a guest page by physical address
3907 *
3908 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3909 *
3910 * @returns VBox status code.
3911 * @param pVM The VM to operate on.
3912 * @param pVCpu The VM CPU to operate on.
3913 * @param GCPhys Page to invalidate
3914 */
3915VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3916{
3917 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3918
3919 Assert(pVM->hwaccm.s.fNestedPaging);
3920
3921 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3922
3923 /* Skip it if a TLB flush is already pending. */
3924 if (!fFlushPending)
3925 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3926
3927 return VINF_SUCCESS;
3928}
3929
3930/**
3931 * Report world switch error and dump some useful debug info
3932 *
3933 * @param pVM The VM to operate on.
3934 * @param pVCpu The VMCPU to operate on.
3935 * @param rc Return code
3936 * @param pCtx Current CPU context (not updated)
3937 */
3938static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3939{
3940 switch (rc)
3941 {
3942 case VERR_VMX_INVALID_VMXON_PTR:
3943 AssertFailed();
3944 break;
3945
3946 case VERR_VMX_UNABLE_TO_START_VM:
3947 case VERR_VMX_UNABLE_TO_RESUME_VM:
3948 {
3949 int rc;
3950 RTCCUINTREG exitReason, instrError;
3951
3952 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3953 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3954 AssertRC(rc);
3955 if (rc == VINF_SUCCESS)
3956 {
3957 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3958 Log(("Current stack %08x\n", &rc));
3959
3960 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3961 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3962
3963#ifdef VBOX_STRICT
3964 RTGDTR gdtr;
3965 PX86DESCHC pDesc;
3966 RTCCUINTREG val;
3967
3968 ASMGetGDTR(&gdtr);
3969
3970 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3971 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3972 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3973 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3974 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3975 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3976 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3977 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3978 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3979 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3980
3981 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3982 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3983
3984 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3985 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3986
3987 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3988 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3989
3990 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3991 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3992
3993 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3994 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3995
3996 if (val < gdtr.cbGdt)
3997 {
3998 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3999 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
4000 }
4001
4002 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
4003 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
4004 if (val < gdtr.cbGdt)
4005 {
4006 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4007 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
4008 }
4009
4010 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
4011 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
4012 if (val < gdtr.cbGdt)
4013 {
4014 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4015 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
4016 }
4017
4018 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
4019 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
4020 if (val < gdtr.cbGdt)
4021 {
4022 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4023 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
4024 }
4025
4026 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
4027 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
4028 if (val < gdtr.cbGdt)
4029 {
4030 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4031 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
4032 }
4033
4034 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
4035 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
4036 if (val < gdtr.cbGdt)
4037 {
4038 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4039 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
4040 }
4041
4042 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
4043 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
4044 if (val < gdtr.cbGdt)
4045 {
4046 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4047 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
4048 }
4049
4050 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
4051 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
4052
4053 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
4054 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
4055 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
4056 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
4057
4058 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
4059 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
4060
4061 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
4062 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
4063
4064 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
4065 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
4066
4067 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
4068 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
4069 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
4070 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
4071
4072# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4073 if (VMX_IS_64BIT_HOST_MODE())
4074 {
4075 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
4076 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
4077 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
4078 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
4079 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
4080 }
4081# endif
4082#endif /* VBOX_STRICT */
4083 }
4084 break;
4085 }
4086
4087 default:
4088 /* impossible */
4089 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
4090 break;
4091 }
4092}
4093
4094#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4095/**
4096 * Prepares for and executes VMLAUNCH (64 bits guest mode)
4097 *
4098 * @returns VBox status code
4099 * @param fResume vmlauch/vmresume
4100 * @param pCtx Guest context
4101 * @param pCache VMCS cache
4102 * @param pVM The VM to operate on.
4103 * @param pVCpu The VMCPU to operate on.
4104 */
4105DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
4106{
4107 uint32_t aParam[6];
4108 PHWACCM_CPUINFO pCpu;
4109 RTHCPHYS pPageCpuPhys;
4110 int rc;
4111
4112 pCpu = HWACCMR0GetCurrentCpu();
4113 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4114
4115#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4116 pCache->uPos = 1;
4117 pCache->interPD = PGMGetInterPaeCR3(pVM);
4118 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
4119#endif
4120
4121#ifdef DEBUG
4122 pCache->TestIn.pPageCpuPhys = 0;
4123 pCache->TestIn.pVMCSPhys = 0;
4124 pCache->TestIn.pCache = 0;
4125 pCache->TestOut.pVMCSPhys = 0;
4126 pCache->TestOut.pCache = 0;
4127 pCache->TestOut.pCtx = 0;
4128 pCache->TestOut.eflags = 0;
4129#endif
4130
4131 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
4132 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
4133 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
4134 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
4135 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
4136 aParam[5] = 0;
4137
4138#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4139 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
4140 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
4141#endif
4142 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
4143
4144#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4145 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
4146 Assert(pCtx->dr[4] == 10);
4147 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
4148#endif
4149
4150#ifdef DEBUG
4151 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
4152 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
4153 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
4154 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
4155 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
4156 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
4157 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
4158#endif
4159 return rc;
4160}
4161
4162/**
4163 * Executes the specified handler in 64 mode
4164 *
4165 * @returns VBox status code.
4166 * @param pVM The VM to operate on.
4167 * @param pVCpu The VMCPU to operate on.
4168 * @param pCtx Guest context
4169 * @param pfnHandler RC handler
4170 * @param cbParam Number of parameters
4171 * @param paParam Array of 32 bits parameters
4172 */
4173VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
4174{
4175 int rc, rc2;
4176 PHWACCM_CPUINFO pCpu;
4177 RTHCPHYS pPageCpuPhys;
4178
4179 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
4180 AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
4181 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
4182 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
4183 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
4184
4185#ifdef VBOX_STRICT
4186 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
4187 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
4188
4189 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
4190 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
4191#endif
4192
4193 pCpu = HWACCMR0GetCurrentCpu();
4194 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4195
4196 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4197 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4198
4199 /* Leave VMX Root Mode. */
4200 VMXDisable();
4201
4202 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4203
4204 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
4205 CPUMSetHyperEIP(pVCpu, pfnHandler);
4206 for (int i=(int)cbParam-1;i>=0;i--)
4207 CPUMPushHyper(pVCpu, paParam[i]);
4208
4209 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4210 /* Call switcher. */
4211 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
4212 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4213
4214 /* Make sure the VMX instructions don't cause #UD faults. */
4215 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
4216
4217 /* Enter VMX Root Mode */
4218 rc2 = VMXEnable(pPageCpuPhys);
4219 if (RT_FAILURE(rc2))
4220 {
4221 if (pVM)
4222 VMXR0CheckError(pVM, pVCpu, rc2);
4223 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4224 return VERR_VMX_VMXON_FAILED;
4225 }
4226
4227 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4228 AssertRCReturn(rc2, rc2);
4229 Assert(!(ASMGetFlags() & X86_EFL_IF));
4230 return rc;
4231}
4232
4233#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4234
4235
4236#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4237/**
4238 * Executes VMWRITE
4239 *
4240 * @returns VBox status code
4241 * @param pVCpu The VMCPU to operate on.
4242 * @param idxField VMCS index
4243 * @param u64Val 16, 32 or 64 bits value
4244 */
4245VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4246{
4247 int rc;
4248
4249 switch (idxField)
4250 {
4251 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4252 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4253 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4254 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4255 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4256 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4257 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4258 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4259 case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
4260 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4261 case VMX_VMCS_GUEST_PDPTR0_FULL:
4262 case VMX_VMCS_GUEST_PDPTR1_FULL:
4263 case VMX_VMCS_GUEST_PDPTR2_FULL:
4264 case VMX_VMCS_GUEST_PDPTR3_FULL:
4265 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4266 case VMX_VMCS_GUEST_EFER_FULL:
4267 case VMX_VMCS_CTRL_EPTP_FULL:
4268 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4269 rc = VMXWriteVMCS32(idxField, u64Val);
4270 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4271 AssertRC(rc);
4272 return rc;
4273
4274 case VMX_VMCS64_GUEST_LDTR_BASE:
4275 case VMX_VMCS64_GUEST_TR_BASE:
4276 case VMX_VMCS64_GUEST_GDTR_BASE:
4277 case VMX_VMCS64_GUEST_IDTR_BASE:
4278 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4279 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4280 case VMX_VMCS64_GUEST_CR0:
4281 case VMX_VMCS64_GUEST_CR4:
4282 case VMX_VMCS64_GUEST_CR3:
4283 case VMX_VMCS64_GUEST_DR7:
4284 case VMX_VMCS64_GUEST_RIP:
4285 case VMX_VMCS64_GUEST_RSP:
4286 case VMX_VMCS64_GUEST_CS_BASE:
4287 case VMX_VMCS64_GUEST_DS_BASE:
4288 case VMX_VMCS64_GUEST_ES_BASE:
4289 case VMX_VMCS64_GUEST_FS_BASE:
4290 case VMX_VMCS64_GUEST_GS_BASE:
4291 case VMX_VMCS64_GUEST_SS_BASE:
4292 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4293 if (u64Val >> 32ULL)
4294 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4295 else
4296 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4297
4298 return rc;
4299
4300 default:
4301 AssertMsgFailed(("Unexpected field %x\n", idxField));
4302 return VERR_INVALID_PARAMETER;
4303 }
4304}
4305
4306/**
4307 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4308 *
4309 * @param pVCpu The VMCPU to operate on.
4310 * @param idxField VMCS field
4311 * @param u64Val Value
4312 */
4313VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4314{
4315 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4316
4317 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4318
4319 /* Make sure there are no duplicates. */
4320 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4321 {
4322 if (pCache->Write.aField[i] == idxField)
4323 {
4324 pCache->Write.aFieldVal[i] = u64Val;
4325 return VINF_SUCCESS;
4326 }
4327 }
4328
4329 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4330 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4331 pCache->Write.cValidEntries++;
4332 return VINF_SUCCESS;
4333}
4334
4335#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4336
4337#ifdef VBOX_STRICT
4338static bool vmxR0IsValidReadField(uint32_t idxField)
4339{
4340 switch(idxField)
4341 {
4342 case VMX_VMCS64_GUEST_RIP:
4343 case VMX_VMCS64_GUEST_RSP:
4344 case VMX_VMCS_GUEST_RFLAGS:
4345 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4346 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4347 case VMX_VMCS64_GUEST_CR0:
4348 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4349 case VMX_VMCS64_GUEST_CR4:
4350 case VMX_VMCS64_GUEST_DR7:
4351 case VMX_VMCS32_GUEST_SYSENTER_CS:
4352 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4353 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4354 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4355 case VMX_VMCS64_GUEST_GDTR_BASE:
4356 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4357 case VMX_VMCS64_GUEST_IDTR_BASE:
4358 case VMX_VMCS16_GUEST_FIELD_CS:
4359 case VMX_VMCS32_GUEST_CS_LIMIT:
4360 case VMX_VMCS64_GUEST_CS_BASE:
4361 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4362 case VMX_VMCS16_GUEST_FIELD_DS:
4363 case VMX_VMCS32_GUEST_DS_LIMIT:
4364 case VMX_VMCS64_GUEST_DS_BASE:
4365 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4366 case VMX_VMCS16_GUEST_FIELD_ES:
4367 case VMX_VMCS32_GUEST_ES_LIMIT:
4368 case VMX_VMCS64_GUEST_ES_BASE:
4369 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4370 case VMX_VMCS16_GUEST_FIELD_FS:
4371 case VMX_VMCS32_GUEST_FS_LIMIT:
4372 case VMX_VMCS64_GUEST_FS_BASE:
4373 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4374 case VMX_VMCS16_GUEST_FIELD_GS:
4375 case VMX_VMCS32_GUEST_GS_LIMIT:
4376 case VMX_VMCS64_GUEST_GS_BASE:
4377 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4378 case VMX_VMCS16_GUEST_FIELD_SS:
4379 case VMX_VMCS32_GUEST_SS_LIMIT:
4380 case VMX_VMCS64_GUEST_SS_BASE:
4381 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4382 case VMX_VMCS16_GUEST_FIELD_LDTR:
4383 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4384 case VMX_VMCS64_GUEST_LDTR_BASE:
4385 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4386 case VMX_VMCS16_GUEST_FIELD_TR:
4387 case VMX_VMCS32_GUEST_TR_LIMIT:
4388 case VMX_VMCS64_GUEST_TR_BASE:
4389 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4390 case VMX_VMCS32_RO_EXIT_REASON:
4391 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4392 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4393 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4394 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4395 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4396 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4397 case VMX_VMCS32_RO_IDT_INFO:
4398 case VMX_VMCS32_RO_IDT_ERRCODE:
4399 case VMX_VMCS64_GUEST_CR3:
4400 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4401 return true;
4402 }
4403 return false;
4404}
4405
4406static bool vmxR0IsValidWriteField(uint32_t idxField)
4407{
4408 switch(idxField)
4409 {
4410 case VMX_VMCS64_GUEST_LDTR_BASE:
4411 case VMX_VMCS64_GUEST_TR_BASE:
4412 case VMX_VMCS64_GUEST_GDTR_BASE:
4413 case VMX_VMCS64_GUEST_IDTR_BASE:
4414 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4415 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4416 case VMX_VMCS64_GUEST_CR0:
4417 case VMX_VMCS64_GUEST_CR4:
4418 case VMX_VMCS64_GUEST_CR3:
4419 case VMX_VMCS64_GUEST_DR7:
4420 case VMX_VMCS64_GUEST_RIP:
4421 case VMX_VMCS64_GUEST_RSP:
4422 case VMX_VMCS64_GUEST_CS_BASE:
4423 case VMX_VMCS64_GUEST_DS_BASE:
4424 case VMX_VMCS64_GUEST_ES_BASE:
4425 case VMX_VMCS64_GUEST_FS_BASE:
4426 case VMX_VMCS64_GUEST_GS_BASE:
4427 case VMX_VMCS64_GUEST_SS_BASE:
4428 return true;
4429 }
4430 return false;
4431}
4432
4433#endif
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