HWVMXR0.cpp@ 2121

Last change on this file since 2121 was 2076, checked in by vboxsync, 18 years ago
TMTimerGet is unsafe as it checks for expired timers each time.
Property svn:keywords set to `Id`
File size: 69.1 KB

Line
1	/* $Id: HWVMXR0.cpp 2076 2007-04-13 12:59:52Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include "HWVMXR0.h"
41
42
43	/* IO operation lookup arrays. */
44	static uint32_t aIOSize[4] = {1, 2, 0, 4};
45	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
46
47
48	/**
49	* Sets up and activates VMX
50	*
51	* @returns VBox status code.
52	* @param pVM The VM to operate on.
53	*/
54	HWACCMR0DECL(int) VMXR0Setup(PVM pVM)
55	{
56	int rc = VINF_SUCCESS;
57	uint32_t val;
58
59	if (pVM == NULL)
60	return VERR_INVALID_PARAMETER;
61
62	/* Setup Intel VMX. */
63	Assert(pVM->hwaccm.s.vmx.fSupported);
64
65	/* Set revision dword at the beginning of both structures. */
66	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
67	(uint32_t )pVM->hwaccm.s.vmx.pVMXON = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
68
69	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
70	* (which can have very bad consequences!!!)
71	*/
72
73	/* Make sure the VMX instructions don't cause #UD faults. */
74	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
75
76	/* Enter VMX Root Mode */
77	rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
78	if (VBOX_FAILURE(rc))
79	{
80	return rc;
81	}
82
83	/* Clear VM Control Structure. */
84	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
85	if (VBOX_FAILURE(rc))
86	goto vmx_end;
87
88	/* Activate the VM Control Structure. */
89	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
90	if (VBOX_FAILURE(rc))
91	goto vmx_end;
92
93	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
94	* Set required bits to one and zero according to the MSR capabilities.
95	*/
96	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
97	/* External and non-maskable interrupts cause VM-exits. */
98	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
99	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
100
101	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
102	AssertRC(rc);
103
104	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
105	* Set required bits to one and zero according to the MSR capabilities.
106	*/
107	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
108	/* Program which event cause VM-exits and which features we want to use. */
109	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
110	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
111	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
112	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
113	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
114	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
115
116	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
117
118	/*
119	if AMD64 guest mode
120	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
121	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
122	*/
123	/* Mask away the bits that the CPU doesn't support */
124	/** @todo make sure they don't conflict with the above requirements. */
125	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
126	pVM->hwaccm.s.vmx.proc_ctls = val;
127
128	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
129	AssertRC(rc);
130
131	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
132	* Set required bits to one and zero according to the MSR capabilities.
133	*/
134	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
135	AssertRC(rc);
136
137	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
138	* Set required bits to one and zero according to the MSR capabilities.
139	*/
140	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
141	if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
142	{
143	/** @todo 32 bits guest mode only for now. */
144	/* val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
145	}
146	/* Mask away the bits that the CPU doesn't support */
147	/** @todo make sure they don't conflict with the above requirements. */
148	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
149	/* else Must be zero when AMD64 is not available. */
150	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
151	AssertRC(rc);
152
153	/* VMX_VMCS_CTRL_EXIT_CONTROLS
154	* Set required bits to one and zero according to the MSR capabilities.
155	*/
156	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
157	#if HC_ARCH_BITS == 64
158	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
159	#else
160	/* else Must be zero when AMD64 is not available. */
161	#endif
162	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
163	/* Don't acknowledge external interrupts on VM-exit. */
164	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
165	AssertRC(rc);
166
167	/* Forward all exception except #NM & #PF to the guest.
168	* We always need to check pagefaults since our shadow page table can be out of sync.
169	* And we always lazily sync the FPU & XMM state.
170	*/
171
172	/*
173	* @todo Possible optimization:
174	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
175	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
176	* registers ourselves of course.
177	*
178	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
179	*/
180	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
181	AssertRC(rc);
182
183	/* Don't filter page faults; all of them should cause a switch. */
184	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
185	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
186	AssertRC(rc);
187
188	/* Init TSC offset to zero. */
189	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
190	#if HC_ARCH_BITS == 32
191	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
192	#endif
193	AssertRC(rc);
194
195	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
196	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
197	AssertRC(rc);
198
199	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
200	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
201	AssertRC(rc);
202
203	/* Clear MSR controls. */
204	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
205	{
206	/* Optional */
207	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
208	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
209	AssertRC(rc);
210	}
211	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
212	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
213	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
214	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
215	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
216	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH, 0);
217	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
218	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
219	AssertRC(rc);
220
221	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
222	{
223	/* Optional */
224	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
225	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
226	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
227	AssertRC(rc);
228	}
229
230	/* Set link pointer to -1. Not currently used. */
231	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
232	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
233	AssertRC(rc);
234
235	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
236	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
237	AssertRC(rc);
238
239	vmx_end:
240	/* Leave VMX Root Mode. */
241	VMXDisable();
242	return rc;
243	}
244
245
246	/**
247	* Injects an event (trap or external interrupt)
248	*
249	* @returns VBox status code.
250	* @param pVM The VM to operate on.
251	* @param pCtx CPU Context
252	* @param intInfo VMX interrupt info
253	* @param cbInstr Opcode length of faulting instruction
254	* @param errCode Error code (optional)
255	*/
256	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
257	{
258	int rc;
259
260	#ifdef VBOX_STRICT
261	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
262	if (iGate == 0xE)
263	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
264	else
265	if (iGate < 0x20)
266	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
267	else
268	{
269	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
270	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
271	Assert(pCtx->eflags.u32 & X86_EFL_IF);
272	}
273	#endif
274
275	/* Set event injection state. */
276	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
277	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
278	);
279
280	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
281	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
282
283	AssertRC(rc);
284	return rc;
285	}
286
287
288	/**
289	* Checks for pending guest interrupts and injects them
290	*
291	* @returns VBox status code.
292	* @param pVM The VM to operate on.
293	* @param pCtx CPU Context
294	*/
295	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
296	{
297	int rc;
298
299	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
300	if (pVM->hwaccm.s.Event.fPending)
301	{
302	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
303	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
304	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
305	AssertRC(rc);
306
307	pVM->hwaccm.s.Event.fPending = false;
308	return VINF_SUCCESS;
309	}
310
311	/* When external interrupts are pending, we should exit the VM when IF is set. */
312	if ( !TRPMHasTrap(pVM)
313	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
314	{
315	if (!(pCtx->eflags.u32 & X86_EFL_IF))
316	{
317	Log2(("Enable irq window exit!\n"));
318	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT);
319	AssertRC(rc);
320	}
321	else
322	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
323	{
324	uint8_t u8Interrupt;
325
326	rc = PDMGetInterrupt(pVM, &u8Interrupt);
327	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
328	if (VBOX_SUCCESS(rc))
329	{
330	rc = TRPMAssertTrap(pVM, u8Interrupt, false);
331	AssertRC(rc);
332	}
333	else
334	{
335	/* can't happen... */
336	AssertFailed();
337	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
338	return VINF_EM_RAW_INTERRUPT_PENDING;
339	}
340	}
341	else
342	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
343	}
344
345	#ifdef VBOX_STRICT
346	if (TRPMHasTrap(pVM))
347	{
348	uint8_t u8Vector;
349	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
350	AssertRC(rc);
351	Assert(u8Vector >= 0x20);
352	}
353	#endif
354
355	if ( pCtx->eflags.u32 & X86_EFL_IF
356	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
357	&& TRPMHasTrap(pVM)
358	)
359	{
360	uint8_t u8Vector;
361	int rc;
362	bool fSoftwareInt;
363	RTGCUINTPTR intInfo, errCode;
364
365	/* If a new event is pending, then dispatch it now. */
366	rc = TRPMQueryTrapAll(pVM, &u8Vector, &fSoftwareInt, &errCode, 0);
367	AssertRC(rc);
368	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| u8Vector < 0x20);
369	Assert(fSoftwareInt == false);
370
371	/* Clear the pending trap. */
372	rc = TRPMResetTrap(pVM);
373	AssertRC(rc);
374
375	intInfo = u8Vector;
376	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
377
378	switch (u8Vector) {
379	case 8:
380	case 10:
381	case 11:
382	case 12:
383	case 13:
384	case 14:
385	case 17:
386	/* Valid error codes. */
387	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
388	break;
389	default:
390	break;
391	}
392
393	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
394	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
395	else
396	if (u8Vector < 0x20)
397	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
398	else
399	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
400
401	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
402	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
403	AssertRC(rc);
404	} /* if (interrupts can be dispatched) */
405
406	return VINF_SUCCESS;
407	}
408
409	/**
410	* Save the host state
411	*
412	* @returns VBox status code.
413	* @param pVM The VM to operate on.
414	*/
415	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
416	{
417	int rc = VINF_SUCCESS;
418
419	/*
420	* Host CPU Context
421	*/
422	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
423	{
424	RTIDTR idtr;
425	RTGDTR gdtr;
426	RTSEL SelTR;
427	PVBOXDESC pDesc;
428	uintptr_t trBase;
429
430	/* Control registers */
431	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
432	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
433	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
434	AssertRC(rc);
435	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
436	Log2(("VMX_VMCS_HOST_CR3 %08x\n", ASMGetCR3()));
437	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
438
439	/* Selector registers. */
440	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
441	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
442	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
443	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
444	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
445	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
446	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
447	SelTR = ASMGetTR();
448	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
449	AssertRC(rc);
450	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
451	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
452	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
453	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
454	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
455	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
456	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
457
458	/* GDTR & IDTR */
459	ASMGetGDTR(&gdtr);
460	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
461	ASMGetIDTR(&idtr);
462	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
463	AssertRC(rc);
464	Log2(("VMX_VMCS_HOST_GDTR_BASE %VGv\n", gdtr.pGdt));
465	Log2(("VMX_VMCS_HOST_IDTR_BASE %VGv\n", idtr.pIdt));
466
467	/* Save the base address of the TR selector. */
468	if (SelTR > gdtr.cbGdt)
469	{
470	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
471	return VERR_VMX_INVALID_HOST_STATE;
472	}
473
474	pDesc = &((PVBOXDESC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT];
475	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16) \| (pDesc->Gen.u8BaseHigh2 << 24);
476	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
477	AssertRC(rc);
478	Log2(("VMX_VMCS_HOST_TR_BASE %VGv\n", trBase));
479
480	/* FS and GS base. */
481	#if HC_ARCH_BITS == 32
482	rc = VMXWriteVMCS(VMX_VMCS_HOST_FS_BASE, 0);
483	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_GS_BASE, 0);
484	#else
485	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
486	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
487	#endif
488	AssertRC(rc);
489
490	/* Sysenter MSRs. */
491	/** @todo expensive!! */
492	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
493	#if HC_ARCH_BITS == 32
494	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
495	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
496	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
497	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VGv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
498	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VGv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
499	#else
500	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
501	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
502	#endif
503	AssertRC(rc);
504
505	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
506	}
507	return rc;
508	}
509
510
511	/**
512	* Loads the guest state
513	*
514	* @returns VBox status code.
515	* @param pVM The VM to operate on.
516	* @param pCtx Guest context
517	*/
518	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
519	{
520	int rc = VINF_SUCCESS;
521	RTGCUINTPTR val;
522
523	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
524	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
525	{
526	VMX_WRITE_SELREG(ES, es);
527	AssertRC(rc);
528
529	VMX_WRITE_SELREG(CS, cs);
530	AssertRC(rc);
531
532	VMX_WRITE_SELREG(SS, ss);
533	AssertRC(rc);
534
535	VMX_WRITE_SELREG(DS, ds);
536	AssertRC(rc);
537
538	VMX_WRITE_SELREG(FS, fs);
539	AssertRC(rc);
540
541	VMX_WRITE_SELREG(GS, gs);
542	AssertRC(rc);
543	}
544
545	/* Guest CPU context: LDTR. */
546	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
547	{
548	if (pCtx->ldtr == 0)
549	{
550	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
551	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
552	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
553	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
554	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
555	}
556	else
557	{
558	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
559	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
560	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
561	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
562	}
563	AssertRC(rc);
564	}
565	/* Guest CPU context: TR. */
566	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
567	{
568	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
569	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
570	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
571	val = pCtx->trHid.Attr.u;
572
573	/* The TSS selector must be busy. */
574	if ((val & 0xF) == X86_SEL_TYPE_SYS_386_TSS_AVAIL)
575	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
576	else
577	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
578	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
579
580	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
581	AssertRC(rc);
582	}
583	/* Guest CPU context: GDTR. */
584	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
585	{
586	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
587	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
588	AssertRC(rc);
589	}
590	/* Guest CPU context: IDTR. */
591	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
592	{
593	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
594	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
595	AssertRC(rc);
596	}
597
598	/*
599	* Sysenter MSRs
600	*/
601	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
602	{
603	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
604	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
605	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
606	AssertRC(rc);
607	}
608
609	/* Control registers */
610	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
611	{
612	val = pCtx->cr0;
613	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
614	Log2(("Guest CR0-shadow %08x\n", val));
615	if (CPUMIsGuestFPUStateActive(pVM) == false)
616	{
617	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
618	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
619	}
620	else
621	{
622	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
623	/** @todo check if we support the old style mess correctly. */
624	if (!(val & X86_CR0_NE))
625	{
626	Log(("Forcing X86_CR0_NE!!!\n"));
627
628	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
629	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
630	{
631	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| BIT(16));
632	AssertRC(rc);
633	pVM->hwaccm.s.fFPUOldStyleOverride = true;
634	}
635	}
636
637	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
638	}
639	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
640	Log2(("Guest CR0 %08x\n", val));
641	/* CR0 flags owned by the host; if the guests attempts to change them, then
642	* the VM will exit.
643	*/
644	val = X86_CR0_PE
645	\| X86_CR0_WP /** @todo do we care? (we do if we start patching the guest) */
646	\| X86_CR0_PG
647	\| X86_CR0_TS
648	\| X86_CR0_ET
649	\| X86_CR0_NE
650	\| X86_CR0_MP;
651	pVM->hwaccm.s.vmx.cr0_mask = val;
652
653	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
654	Log2(("Guest CR0-mask %08x\n", val));
655	AssertRC(rc);
656	}
657	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
658	{
659	/* CR4 */
660	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
661	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
662	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
663	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
664	switch(pVM->hwaccm.s.enmShadowMode)
665	{
666	case PGMMODE_REAL:
667	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
668	AssertFailed();
669	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
670
671	case PGMMODE_32_BIT: /* 32-bit paging. */
672	break;
673
674	case PGMMODE_PAE: /* PAE paging. */
675	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
676	/** @todo use normal 32 bits paging */
677	val \|= X86_CR4_PAE;
678	break;
679
680	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
681	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
682	AssertFailed();
683	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
684
685	default: /* shut up gcc */
686	AssertFailed();
687	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
688	}
689	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
690	Log2(("Guest CR4 %08x\n", val));
691	/* CR4 flags owned by the host; if the guests attempts to change them, then
692	* the VM will exit.
693	*/
694	val = X86_CR4_PAE
695	\| X86_CR4_PGE
696	\| X86_CR4_PSE
697	\| X86_CR4_VMXE;
698	pVM->hwaccm.s.vmx.cr4_mask = val;
699
700	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
701	Log2(("Guest CR4-mask %08x\n", val));
702	AssertRC(rc);
703	}
704
705	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
706	{
707	/* Save our shadow CR3 register. */
708	val = PGMGetHyperCR3(pVM);
709	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
710	AssertRC(rc);
711	}
712
713	/* Debug registers. */
714	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
715	{
716	/** @todo DR0-6 */
717	val = pCtx->dr7;
718	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
719	val \|= 0x400; /* must be one */
720	#ifdef VBOX_STRICT
721	val = 0x400;
722	#endif
723	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
724	AssertRC(rc);
725
726	/* IA32_DEBUGCTL MSR. */
727	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
728	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
729	AssertRC(rc);
730
731	/** @todo */
732	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
733	AssertRC(rc);
734	}
735
736	/* EIP, ESP and EFLAGS */
737	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
738	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
739	AssertRC(rc);
740
741	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
742	val = pCtx->eflags.u32;
743	val &= VMX_EFLAGS_RESERVED_0;
744	val \|= VMX_EFLAGS_RESERVED_1;
745	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, val);
746	AssertRC(rc);
747
748	/** TSC offset. */
749	uint64_t u64TSCOffset = TMCpuTickGetOffset(pVM);
750
751	#if HC_ARCH_BITS == 64
752	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
753	#else
754	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
755	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
756	#endif
757	AssertRC(rc);
758
759
760	/* Done. */
761	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
762
763	return rc;
764	}
765
766	/**
767	* Runs guest code in a VMX VM.
768	*
769	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
770	*
771	* @returns VBox status code.
772	* @param pVM The VM to operate on.
773	* @param pCtx Guest context
774	*/
775	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
776	{
777	int rc = VINF_SUCCESS;
778	RTCCUINTREG val, valShadow;
779	RTCCUINTREG exitReason, instrError, cbInstr;
780	RTGCUINTPTR exitQualification;
781	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
782	RTGCUINTPTR errCode, instrInfo, uInterruptState;
783
784	Log2(("\nE"));
785
786	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
787
788	#ifdef VBOX_STRICT
789	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
790	AssertRC(rc);
791	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
792
793	/* allowed zero */
794	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
795	{
796	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
797	}
798	/* allowed one */
799	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
800	{
801	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
802	}
803
804	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
805	AssertRC(rc);
806	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
807
808	/* allowed zero */
809	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
810	{
811	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
812	}
813	/* allowed one */
814	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
815	{
816	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
817	}
818
819	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
820	AssertRC(rc);
821	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
822
823	/* allowed zero */
824	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
825	{
826	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
827	}
828	/* allowed one */
829	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
830	{
831	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
832	}
833
834	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
835	AssertRC(rc);
836	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
837
838	/* allowed zero */
839	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
840	{
841	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
842	}
843	/* allowed one */
844	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
845	{
846	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
847	}
848	#endif
849
850	#if 0
851	/*
852	* Check if debug registers are armed.
853	*/
854	uint32_t u32DR7 = ASMGetDR7();
855	if (u32DR7 & X86_DR7_ENABLED_MASK)
856	{
857	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
858	}
859	else
860	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
861	#endif
862
863	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
864	*/
865	ResumeExecution:
866
867	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
868	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
869	{
870	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
871	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
872	{
873	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
874	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
875	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
876	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
877	*/
878	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
879	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
880	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
881	AssertRC(rc);
882	}
883	}
884	else
885	{
886	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
887	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
888	AssertRC(rc);
889	}
890
891	/* Check for pending actions that force us to go back to ring 3. */
892	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
893	{
894	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
895	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
896	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
897	rc = VINF_EM_RAW_TO_R3;
898	goto end;
899	}
900	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
901	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
902	{
903	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
904	rc = VINF_EM_PENDING_REQUEST;
905	goto end;
906	}
907
908	/* When external interrupts are pending, we should exit the VM when IF is set. */
909	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
910	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
911	if (VBOX_FAILURE(rc))
912	{
913	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
914	goto end;
915	}
916
917	/** @todo check timers?? */
918
919	/* Save the host state first. */
920	rc = VMXR0SaveHostState(pVM);
921	if (rc != VINF_SUCCESS)
922	{
923	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
924	goto end;
925	}
926	/* Load the guest state */
927	rc = VMXR0LoadGuestState(pVM, pCtx);
928	if (rc != VINF_SUCCESS)
929	{
930	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
931	goto end;
932	}
933
934	/* Non-register state Guest Context */
935	/** @todo change me according to cpu state */
936	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
937	AssertRC(rc);
938
939	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
940
941	/* Manual save and restore:
942	* - General purpose registers except RIP, RSP
943	*
944	* Trashed:
945	* - CR2 (we don't care)
946	* - LDTR (reset to 0)
947	* - DRx (presumably not changed at all)
948	* - DR7 (reset to 0x400)
949	* - EFLAGS (reset to BIT(1); not relevant)
950	*
951	*/
952
953	/* All done! Let's start VM execution. */
954	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
955	if (pVM->hwaccm.s.vmx.fResumeVM == false)
956	{
957	rc = VMXStartVM(pCtx);
958	}
959	else
960	{
961	rc = VMXResumeVM(pCtx);
962	}
963
964	/* In case we execute a goto ResumeExecution later on. */
965	pVM->hwaccm.s.vmx.fResumeVM = true;
966
967	/**
968	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
969	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
970	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
971	*/
972
973	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
974	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
975
976	switch (rc)
977	{
978	case VINF_SUCCESS:
979	break;
980
981	case VERR_VMX_INVALID_VMXON_PTR:
982	AssertFailed();
983	goto end;
984
985	case VERR_VMX_UNABLE_TO_START_VM:
986	case VERR_VMX_UNABLE_TO_RESUME_VM:
987	{
988	#ifdef VBOX_STRICT
989	int rc1;
990
991	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
992	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
993	AssertRC(rc1);
994	if (rc1 == VINF_SUCCESS)
995	{
996	RTGDTR gdtr;
997	PVBOXDESC pDesc;
998
999	ASMGetGDTR(&gdtr);
1000	VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
1001
1002	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1003	Log(("Current stack %08x\n", &rc1));
1004
1005	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1006	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1007
1008	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1009	Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
1010
1011	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1012	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1013
1014	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1015	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1016	if (val < gdtr.cbGdt)
1017	{
1018	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1019	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1020	}
1021
1022	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1023	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1024	if (val < gdtr.cbGdt)
1025	{
1026	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1027	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1028	}
1029
1030	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1031	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1032	if (val < gdtr.cbGdt)
1033	{
1034	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1035	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1036	}
1037
1038	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1039	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1040	if (val < gdtr.cbGdt)
1041	{
1042	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1043	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1044	}
1045
1046	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1047	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1048	if (val < gdtr.cbGdt)
1049	{
1050	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1051	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1052	}
1053
1054	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1055	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1056	if (val < gdtr.cbGdt)
1057	{
1058	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1059	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1060	}
1061
1062	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1063	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1064	if (val < gdtr.cbGdt)
1065	{
1066	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1067	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1068	}
1069
1070	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1071	Log(("VMX_VMCS_HOST_TR_BASE %VGv\n", val));
1072
1073	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1074	Log(("VMX_VMCS_HOST_GDTR_BASE %VGv\n", val));
1075	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1076	Log(("VMX_VMCS_HOST_IDTR_BASE %VGv\n", val));
1077
1078	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1079	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1080
1081	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1082	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VGv\n", val));
1083
1084	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1085	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VGv\n", val));
1086
1087	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1088	Log(("VMX_VMCS_HOST_RSP %VGv\n", val));
1089	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1090	Log(("VMX_VMCS_HOST_RIP %VGv\n", val));
1091	}
1092	#endif /* VBOX_STRICT */
1093	goto end;
1094	}
1095
1096	default:
1097	/* impossible */
1098	AssertFailed();
1099	goto end;
1100	}
1101	/* Success. Query the guest state and figure out what has happened. */
1102
1103	/* Investigate why there was a VM-exit. */
1104	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1105	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReason[exitReason & MASK_EXITREASON_STAT]);
1106
1107	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1108	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1109	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1110	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1111	intInfo = val;
1112	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1113	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1114	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1115	instrInfo = val;
1116	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1117	exitQualification = val;
1118	AssertRC(rc);
1119
1120	/* Take care of instruction fusing (sti, mov ss) */
1121	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1122	uInterruptState = val;
1123	if (uInterruptState != 0)
1124	{
1125	Assert(uInterruptState <= 2); /* only sti & mov ss */
1126	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1127	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1128	}
1129	else
1130	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1131
1132	/* Let's first sync back eip, esp, and eflags. */
1133	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1134	AssertRC(rc);
1135	pCtx->eip = val;
1136	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1137	AssertRC(rc);
1138	pCtx->esp = val;
1139	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1140	AssertRC(rc);
1141	pCtx->eflags.u32 = val;
1142
1143	/* Control registers. */
1144	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1145	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1146	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1147	CPUMSetGuestCR0(pVM, val);
1148
1149	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1150	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1151	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1152	CPUMSetGuestCR4(pVM, val);
1153
1154	CPUMSetGuestCR2(pVM, ASMGetCR2());
1155
1156	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1157	CPUMSetGuestDR7(pVM, val);
1158
1159	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1160	VMX_READ_SELREG(ES, es);
1161	VMX_READ_SELREG(SS, ss);
1162	VMX_READ_SELREG(CS, cs);
1163	VMX_READ_SELREG(DS, ds);
1164	VMX_READ_SELREG(FS, fs);
1165	VMX_READ_SELREG(GS, gs);
1166
1167	/** @note NOW IT'S SAFE FOR LOGGING! */
1168	Log2(("Raw exit reason %08x\n", exitReason));
1169
1170	/* Check if an injected event was interrupted prematurely. */
1171	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1172	AssertRC(rc);
1173	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1174	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1175	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1176	{
1177	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1178	pVM->hwaccm.s.Event.fPending = true;
1179	/* Error code present? */
1180	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1181	{
1182	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1183	AssertRC(rc);
1184	pVM->hwaccm.s.Event.errCode = val;
1185	}
1186	else
1187	pVM->hwaccm.s.Event.errCode = 0;
1188	}
1189
1190	#ifdef VBOX_STRICT
1191	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1192	HWACCMDumpRegs(pCtx);
1193	#endif
1194
1195	Log2(("E%d", exitReason));
1196	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1197	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1198	Log2(("Interruption error code %d\n", errCode));
1199	Log2(("IntInfo = %08x\n", intInfo));
1200	Log2(("New EIP=%VGv\n", pCtx->eip));
1201
1202	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1203	switch (exitReason)
1204	{
1205	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1206	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1207	{
1208	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1209
1210	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1211	{
1212	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1213	/* External interrupt; leave to allow it to be dispatched again. */
1214	rc = VINF_EM_RAW_INTERRUPT;
1215	break;
1216	}
1217	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1218	{
1219	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1220	/* External interrupt; leave to allow it to be dispatched again. */
1221	rc = VINF_EM_RAW_INTERRUPT;
1222	break;
1223
1224	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1225	AssertFailed(); /* can't come here; fails the first check. */
1226	break;
1227
1228	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1229	Assert(vector == 3 \|\| vector == 4);
1230	/* no break */
1231	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1232	Log2(("Hardware/software interrupt %d\n", vector));
1233	switch (vector)
1234	{
1235	case X86_XCPT_NM:
1236	{
1237	uint32_t oldCR0;
1238
1239	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1240
1241	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1242	oldCR0 = ASMGetCR0();
1243	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1244	rc = CPUMHandleLazyFPU(pVM);
1245	if (rc == VINF_SUCCESS)
1246	{
1247	Assert(CPUMIsGuestFPUStateActive(pVM));
1248
1249	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1250	ASMSetCR0(oldCR0);
1251
1252	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1253
1254	/* Continue execution. */
1255	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1256	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1257
1258	goto ResumeExecution;
1259	}
1260
1261	Log(("Forward #NM fault to the guest\n"));
1262	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1263	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1264	AssertRC(rc);
1265	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1266	goto ResumeExecution;
1267	}
1268
1269	case X86_XCPT_PF: /* Page fault */
1270	{
1271	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1272	/* Exit qualification contains the linear address of the page fault. */
1273	TRPMAssertTrap(pVM, X86_XCPT_PF, false);
1274	TRPMSetErrorCode(pVM, errCode);
1275	TRPMSetFaultAddress(pVM, exitQualification);
1276
1277	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1278	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1279	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1280	if (rc == VINF_SUCCESS)
1281	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1282	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1283	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1284
1285	TRPMResetTrap(pVM);
1286
1287	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1288	goto ResumeExecution;
1289	}
1290	else
1291	if (rc == VINF_EM_RAW_GUEST_TRAP)
1292	{ /* A genuine pagefault.
1293	* Forward the trap to the guest by injecting the exception and resuming execution.
1294	*/
1295	Log2(("Forward page fault to the guest\n"));
1296	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1297	/* The error code might have been changed. */
1298	errCode = TRPMGetErrorCode(pVM);
1299
1300	TRPMResetTrap(pVM);
1301
1302	/* Now we must update CR2. */
1303	pCtx->cr2 = exitQualification;
1304	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1305	AssertRC(rc);
1306
1307	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1308	goto ResumeExecution;
1309	}
1310	#ifdef VBOX_STRICT
1311	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1312	Log(("PGMTrap0eHandler failed with %d\n", rc));
1313	#endif
1314	/* Need to go back to the recompiler to emulate the instruction. */
1315	TRPMResetTrap(pVM);
1316	break;
1317	}
1318
1319	case X86_XCPT_MF: /* Floating point exception. */
1320	{
1321	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1322	if (!(pCtx->cr0 & X86_CR0_NE))
1323	{
1324	/* old style FPU error reporting needs some extra work. */
1325	/** @todo don't fall back to the recompiler, but do it manually. */
1326	rc = VINF_EM_RAW_EMULATE_INSTR;
1327	break;
1328	}
1329	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1330	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1331	AssertRC(rc);
1332
1333	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1334	goto ResumeExecution;
1335	}
1336
1337	#ifdef VBOX_STRICT
1338	case X86_XCPT_GP: /* General protection failure exception.*/
1339	case X86_XCPT_UD: /* Unknown opcode exception. */
1340	case X86_XCPT_DE: /* Debug exception. */
1341	case X86_XCPT_SS: /* Stack segment exception. */
1342	case X86_XCPT_NP: /* Segment not present exception. */
1343	{
1344	switch(vector)
1345	{
1346	case X86_XCPT_DE:
1347	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1348	break;
1349	case X86_XCPT_UD:
1350	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1351	break;
1352	case X86_XCPT_SS:
1353	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1354	break;
1355	case X86_XCPT_NP:
1356	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1357	break;
1358	case X86_XCPT_GP:
1359	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1360	break;
1361	}
1362
1363	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1364	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1365	AssertRC(rc);
1366
1367	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1368	goto ResumeExecution;
1369	}
1370	#endif
1371	default:
1372	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1373	rc = VERR_EM_INTERNAL_ERROR;
1374	break;
1375	} /* switch (vector) */
1376
1377	break;
1378
1379	default:
1380	rc = VERR_EM_INTERNAL_ERROR;
1381	AssertFailed();
1382	break;
1383	}
1384
1385	break;
1386	}
1387
1388	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1389	/* Clear VM-exit on IF=1 change. */
1390	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1391	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1392	AssertRC(rc);
1393	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1394	goto ResumeExecution; /* we check for pending guest interrupts there */
1395
1396	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1397	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1398	/* Skip instruction and continue directly. */
1399	pCtx->eip += cbInstr;
1400	/* Continue execution.*/
1401	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1402	goto ResumeExecution;
1403
1404	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1405	{
1406	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1407	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1408	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1409	if (rc == VINF_SUCCESS)
1410	{
1411	/* Update EIP and continue execution. */
1412	pCtx->eip += cbInstr;
1413	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1414	goto ResumeExecution;
1415	}
1416	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1417	rc = VINF_EM_RAW_EMULATE_INSTR;
1418	break;
1419	}
1420
1421	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1422	{
1423	Log2(("VMX: invlpg\n"));
1424	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1425	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1426	if (rc == VINF_SUCCESS)
1427	{
1428	/* Update EIP and continue execution. */
1429	pCtx->eip += cbInstr;
1430	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1431	goto ResumeExecution;
1432	}
1433	AssertMsgFailed(("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1434	rc = VINF_EM_RAW_EMULATE_INSTR;
1435	break;
1436	}
1437
1438	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1439	{
1440	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1441	{
1442	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1443	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1444	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1445	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1446	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1447	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1448
1449	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1450	{
1451	case 0:
1452	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1453	break;
1454	case 2:
1455	break;
1456	case 3:
1457	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1458	break;
1459	case 4:
1460	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1461	break;
1462	default:
1463	AssertFailed();
1464	}
1465	/* Check if a sync operation is pending. */
1466	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1467	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1468	{
1469	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1470	AssertRC(rc);
1471	}
1472	break;
1473
1474	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1475	Log2(("VMX: mov x, crx\n"));
1476	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1477	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1478	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1479	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1480	break;
1481
1482	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1483	Log2(("VMX: clts\n"));
1484	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1485	rc = EMInterpretCLTS(pVM);
1486	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1487	break;
1488
1489	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1490	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1491	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1492	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1493	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1494	break;
1495	}
1496
1497	/* Update EIP if no error occurred. */
1498	if (VBOX_SUCCESS(rc))
1499	pCtx->eip += cbInstr;
1500
1501	if (rc == VINF_SUCCESS)
1502	{
1503	/* Only resume if successful. */
1504	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1505	goto ResumeExecution;
1506	}
1507	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1508	if (rc == VERR_EM_INTERPRETER)
1509	rc = VINF_EM_RAW_EMULATE_INSTR;
1510	break;
1511	}
1512
1513	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1514	{
1515	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1516	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1517	{
1518	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1519	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1520	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1521	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1522	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1523	Log2(("DR7=%08x\n", pCtx->dr7));
1524	}
1525	else
1526	{
1527	Log2(("VMX: mov x, drx\n"));
1528	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1529	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1530	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1531	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1532	}
1533	/* Update EIP if no error occurred. */
1534	if (VBOX_SUCCESS(rc))
1535	pCtx->eip += cbInstr;
1536
1537	if (rc == VINF_SUCCESS)
1538	{
1539	/* Only resume if successful. */
1540	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1541	goto ResumeExecution;
1542	}
1543	Assert(rc == VERR_EM_INTERPRETER);
1544	rc = VINF_EM_RAW_EMULATE_INSTR;
1545	break;
1546	}
1547
1548	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1549	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1550	{
1551	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1552	uint32_t uPort;
1553
1554	/** @todo necessary to make the distinction? */
1555	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1556	{
1557	uPort = pCtx->edx & 0xffff;
1558	}
1559	else
1560	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1561
1562	/* First simple in and out instructions. */
1563	/** @todo str & rep */
1564	if ( !VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification)
1565	&& !VMX_EXIT_QUALIFICATION_IO_REP(exitQualification)
1566	/* paranoid checks ahead */
1567	&& uIOWidth != 2
1568	&& uIOWidth < 4
1569	)
1570	{
1571	uint32_t cbSize = aIOSize[uIOWidth];
1572	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1573
1574	if (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT)
1575	{
1576	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1577	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1578	}
1579	else
1580	{
1581	uint32_t u32Val = 0;
1582
1583	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1584	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1585	if (rc == VINF_SUCCESS)
1586	{
1587	/* Write back to the EAX register. */
1588	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1589	}
1590	}
1591	if (rc == VINF_SUCCESS)
1592	{
1593	/* Update EIP and continue execution. */
1594	pCtx->eip += cbInstr;
1595	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1596	goto ResumeExecution;
1597	}
1598	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1599	rc = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT)
1600	? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1601	}
1602	else
1603	rc = VINF_IOM_HC_IOPORT_READWRITE;
1604
1605	break;
1606	}
1607
1608	default:
1609	/* The rest is handled after syncing the entire CPU state. */
1610	break;
1611	}
1612
1613	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1614	VMX_READ_SELREG(LDTR, ldtr);
1615	VMX_READ_SELREG(TR, tr);
1616
1617	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1618	pCtx->gdtr.cbGdt = val;
1619	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1620	pCtx->gdtr.pGdt = val;
1621
1622	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1623	pCtx->idtr.cbIdt = val;
1624	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1625	pCtx->idtr.pIdt = val;
1626
1627	/*
1628	* System MSRs
1629	*/
1630	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1631	pCtx->SysEnter.cs = val;
1632	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1633	pCtx->SysEnter.eip = val;
1634	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1635	pCtx->SysEnter.esp = val;
1636
1637	/* Signal changes for the recompiler. */
1638	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1639
1640	/* Investigate why there was a VM-exit. (part 2) */
1641	switch (exitReason)
1642	{
1643	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1644	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1645	/* Already handled above. */
1646	break;
1647
1648	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1649	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1650	break;
1651
1652	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1653	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1654	rc = VINF_EM_RAW_INTERRUPT;
1655	AssertFailed(); /* Can't happen. Yet. */
1656	break;
1657
1658	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1659	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1660	rc = VINF_EM_RAW_INTERRUPT;
1661	AssertFailed(); /* Can't happen afaik. */
1662	break;
1663
1664	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1665	rc = VINF_EM_RAW_RING_SWITCH_INT;
1666	break;
1667
1668	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1669	/** Check if external interrupts are pending; if so, don't switch back. */
1670	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1671	{
1672	pCtx->eip++; /* skip hlt */
1673	goto ResumeExecution;
1674	}
1675
1676	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1677	break;
1678
1679	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1680	rc = VERR_EM_INTERNAL_ERROR;
1681	AssertFailed(); /* we don't let it fault. */
1682	break;
1683
1684	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1685	AssertFailed(); /* can't happen. */
1686	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1687	break;
1688
1689	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1690	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1691	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1692	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1693	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1694	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1695	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1696	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1697	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1698	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1699	/** @todo inject #UD immediately */
1700	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1701	break;
1702
1703	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1704	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1705	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1706	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1707	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1708	/* already handled above */
1709	AssertMsg(rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_EM_RAW_INTERRUPT \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_PGM_SYNC_CR3 \|\| rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE \|\| rc == VINF_IOM_HC_IOPORT_READWRITE, ("rc = %d\n", rc));
1710	break;
1711
1712	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1713	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1714	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1715	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1716	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1717	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1718	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1719	break;
1720
1721	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1722	Assert(rc == VINF_EM_RAW_INTERRUPT);
1723	break;
1724
1725	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1726	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1727	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1728	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1729	default:
1730	rc = VERR_EM_INTERNAL_ERROR;
1731	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1732	break;
1733
1734	}
1735	end:
1736
1737	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
1738	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
1739	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1740	{
1741	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1742	/* On the next entry we'll only sync the host context. */
1743	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1744	}
1745	else
1746	{
1747	/* On the next entry we'll sync everything. */
1748	/** @todo we can do better than this */
1749	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1750	}
1751
1752	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1753	Log2(("X"));
1754	return rc;
1755	}
1756
1757
1758	/**
1759	* Enable VMX
1760	*
1761	* @returns VBox status code.
1762	* @param pVM The VM to operate on.
1763	*/
1764	HWACCMR0DECL(int) VMXR0Enable(PVM pVM)
1765	{
1766	Assert(pVM->hwaccm.s.vmx.fSupported);
1767
1768	/* Make sure the VMX instructions don't cause #UD faults. */
1769	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
1770
1771	/* Enter VMX Root Mode */
1772	int rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
1773	if (VBOX_FAILURE(rc))
1774	return rc;
1775
1776	/* Activate the VM Control Structure. */
1777	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1778	if (VBOX_FAILURE(rc))
1779	{
1780	/* Leave VMX Root Mode. */
1781	VMXDisable();
1782	return rc;
1783	}
1784	pVM->hwaccm.s.vmx.fResumeVM = false;
1785	return VINF_SUCCESS;
1786	}
1787
1788
1789	/**
1790	* Disable VMX
1791	*
1792	* @returns VBox status code.
1793	* @param pVM The VM to operate on.
1794	*/
1795	HWACCMR0DECL(int) VMXR0Disable(PVM pVM)
1796	{
1797	Assert(pVM->hwaccm.s.vmx.fSupported);
1798
1799	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
1800	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1801	AssertRC(rc);
1802
1803	/* Leave VMX Root Mode. */
1804	VMXDisable();
1805
1806	return VINF_SUCCESS;
1807	}
1808

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 2121

Download in other formats: