VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 21257

Last change on this file since 21257 was 21257, checked in by vboxsync, 16 years ago

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1/* $Id: HWVMXR0.cpp 21257 2009-07-06 15:11:09Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/param.h>
41#include <iprt/string.h>
42#include <iprt/time.h>
43#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
44# include <iprt/thread.h>
45#endif
46#include "HWVMXR0.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51#if defined(RT_ARCH_AMD64)
52# define VMX_IS_64BIT_HOST_MODE() (true)
53#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
54# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
55#else
56# define VMX_IS_64BIT_HOST_MODE() (false)
57#endif
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62/* IO operation lookup arrays. */
63static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
65
66#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
67/** See HWACCMR0A.asm. */
68extern "C" uint32_t g_fVMXIs64bitHost;
69#endif
70
71/*******************************************************************************
72* Local Functions *
73*******************************************************************************/
74static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
75static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
76static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
77static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
78static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
79static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
80static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
81#ifdef VBOX_STRICT
82static bool vmxR0IsValidReadField(uint32_t idxField);
83static bool vmxR0IsValidWriteField(uint32_t idxField);
84#endif
85
86static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
87{
88 if (rc == VERR_VMX_GENERIC)
89 {
90 RTCCUINTREG instrError;
91
92 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
93 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
94 }
95 pVM->hwaccm.s.lLastError = rc;
96}
97
98/**
99 * Sets up and activates VT-x on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pVM The VM to operate on. (can be NULL after a resume!!)
104 * @param pvPageCpu Pointer to the global cpu page
105 * @param pPageCpuPhys Physical address of the global cpu page
106 */
107VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
108{
109 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
110 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
111
112#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
113 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
114#endif
115 if (pVM)
116 {
117 /* Set revision dword at the beginning of the VMXON structure. */
118 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
119 }
120
121 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
122 * (which can have very bad consequences!!!)
123 */
124
125 /* Make sure the VMX instructions don't cause #UD faults. */
126 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
127
128 /* Enter VMX Root Mode */
129 int rc = VMXEnable(pPageCpuPhys);
130 if (RT_FAILURE(rc))
131 {
132 if (pVM)
133 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
134 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
135 return VERR_VMX_VMXON_FAILED;
136 }
137 return VINF_SUCCESS;
138}
139
140/**
141 * Deactivates VT-x on the current CPU
142 *
143 * @returns VBox status code.
144 * @param pCpu CPU info struct
145 * @param pvPageCpu Pointer to the global cpu page
146 * @param pPageCpuPhys Physical address of the global cpu page
147 */
148VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
149{
150 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
151 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
152
153 /* Leave VMX Root Mode. */
154 VMXDisable();
155
156 /* And clear the X86_CR4_VMXE bit */
157 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
158
159#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
160 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
161#endif
162 return VINF_SUCCESS;
163}
164
165/**
166 * Does Ring-0 per VM VT-x init.
167 *
168 * @returns VBox status code.
169 * @param pVM The VM to operate on.
170 */
171VMMR0DECL(int) VMXR0InitVM(PVM pVM)
172{
173 int rc;
174
175#ifdef LOG_ENABLED
176 SUPR0Printf("VMXR0InitVM %x\n", pVM);
177#endif
178
179 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
180
181 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
182 {
183 /* Allocate one page for the APIC physical page (serves for filtering accesses). */
184 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185 AssertRC(rc);
186 if (RT_FAILURE(rc))
187 return rc;
188
189 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
190 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
191 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
192 }
193 else
194 {
195 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
196 pVM->hwaccm.s.vmx.pAPIC = 0;
197 pVM->hwaccm.s.vmx.pAPICPhys = 0;
198 }
199
200 /* Allocate the MSR bitmap if this feature is supported. */
201 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
202 {
203 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
204 AssertRC(rc);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
209 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
210 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
211 }
212
213#ifdef VBOX_WITH_CRASHDUMP_MAGIC
214 {
215 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
216 AssertRC(rc);
217 if (RT_FAILURE(rc))
218 return rc;
219
220 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
221 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
222
223 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
224 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
225 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
226 }
227#endif
228
229 /* Allocate VMCBs for all guest CPUs. */
230 for (unsigned i=0;i<pVM->cCPUs;i++)
231 {
232 PVMCPU pVCpu = &pVM->aCpus[i];
233
234 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
235
236 /* Allocate one page for the VM control structure (VMCS). */
237 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
238 AssertRC(rc);
239 if (RT_FAILURE(rc))
240 return rc;
241
242 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
243 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
244 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
245
246 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
247 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
248
249 /* Allocate one page for the virtual APIC page for TPR caching. */
250 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
251 AssertRC(rc);
252 if (RT_FAILURE(rc))
253 return rc;
254
255 pVCpu->hwaccm.s.vmx.pVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
256 pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
257 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
258
259 /* Current guest paging mode. */
260 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
261
262#ifdef LOG_ENABLED
263 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
264#endif
265 }
266
267 return VINF_SUCCESS;
268}
269
270/**
271 * Does Ring-0 per VM VT-x termination.
272 *
273 * @returns VBox status code.
274 * @param pVM The VM to operate on.
275 */
276VMMR0DECL(int) VMXR0TermVM(PVM pVM)
277{
278 for (unsigned i=0;i<pVM->cCPUs;i++)
279 {
280 PVMCPU pVCpu = &pVM->aCpus[i];
281
282 if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
283 {
284 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
285 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
286 pVCpu->hwaccm.s.vmx.pVMCS = 0;
287 pVCpu->hwaccm.s.vmx.pVMCSPhys = 0;
288 }
289 if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
290 {
291 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
292 pVCpu->hwaccm.s.vmx.pMemObjVAPIC = NIL_RTR0MEMOBJ;
293 pVCpu->hwaccm.s.vmx.pVAPIC = 0;
294 pVCpu->hwaccm.s.vmx.pVAPICPhys = 0;
295 }
296 }
297 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
298 {
299 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
300 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
301 pVM->hwaccm.s.vmx.pAPIC = 0;
302 pVM->hwaccm.s.vmx.pAPICPhys = 0;
303 }
304 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
305 {
306 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
307 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
308 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
309 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
310 }
311#ifdef VBOX_WITH_CRASHDUMP_MAGIC
312 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
313 {
314 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
315 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
316 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
317 pVM->hwaccm.s.vmx.pScratch = 0;
318 pVM->hwaccm.s.vmx.pScratchPhys = 0;
319 }
320#endif
321 return VINF_SUCCESS;
322}
323
324/**
325 * Sets up VT-x for the specified VM
326 *
327 * @returns VBox status code.
328 * @param pVM The VM to operate on.
329 */
330VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
331{
332 int rc = VINF_SUCCESS;
333 uint32_t val;
334
335 AssertReturn(pVM, VERR_INVALID_PARAMETER);
336
337 for (unsigned i=0;i<pVM->cCPUs;i++)
338 {
339 PVMCPU pVCpu = &pVM->aCpus[i];
340
341 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
342
343 /* Set revision dword at the beginning of the VMCS structure. */
344 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
345
346 /* Clear VM Control Structure. */
347 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
348 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
349 if (RT_FAILURE(rc))
350 goto vmx_end;
351
352 /* Activate the VM Control Structure. */
353 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
354 if (RT_FAILURE(rc))
355 goto vmx_end;
356
357 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
358 * Set required bits to one and zero according to the MSR capabilities.
359 */
360 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
361 /* External and non-maskable interrupts cause VM-exits. */
362 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
363 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
364
365 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
366 AssertRC(rc);
367
368 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
369 * Set required bits to one and zero according to the MSR capabilities.
370 */
371 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
372 /* Program which event cause VM-exits and which features we want to use. */
373 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
374 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
375 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
376 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
377 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
378 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
379
380 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
381 if (!pVM->hwaccm.s.fNestedPaging)
382 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
383 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
384 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
385
386 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
387 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
388 {
389 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
390 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
391 Assert(pVM->hwaccm.s.vmx.pAPIC);
392 }
393 else
394 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
395 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
396
397#ifdef VBOX_WITH_VTX_MSR_BITMAPS
398 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
399 {
400 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
401 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
402 }
403#endif
404
405 /* We will use the secondary control if it's present. */
406 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
407
408 /* Mask away the bits that the CPU doesn't support */
409 /** @todo make sure they don't conflict with the above requirements. */
410 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
411 pVCpu->hwaccm.s.vmx.proc_ctls = val;
412
413 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
414 AssertRC(rc);
415
416 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
417 {
418 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
419 * Set required bits to one and zero according to the MSR capabilities.
420 */
421 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
422 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
423
424#ifdef HWACCM_VTX_WITH_EPT
425 if (pVM->hwaccm.s.fNestedPaging)
426 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
427#endif /* HWACCM_VTX_WITH_EPT */
428#ifdef HWACCM_VTX_WITH_VPID
429 else
430 if (pVM->hwaccm.s.vmx.fVPID)
431 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
432#endif /* HWACCM_VTX_WITH_VPID */
433
434 if (pVM->hwaccm.s.fHasIoApic)
435 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC;
436
437 /* Mask away the bits that the CPU doesn't support */
438 /** @todo make sure they don't conflict with the above requirements. */
439 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
440 pVCpu->hwaccm.s.vmx.proc_ctls2 = val;
441 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
442 AssertRC(rc);
443 }
444
445 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
446 * Set required bits to one and zero according to the MSR capabilities.
447 */
448 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
449 AssertRC(rc);
450
451 /* Forward all exception except #NM & #PF to the guest.
452 * We always need to check pagefaults since our shadow page table can be out of sync.
453 * And we always lazily sync the FPU & XMM state.
454 */
455
456 /** @todo Possible optimization:
457 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
458 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
459 * registers ourselves of course.
460 *
461 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
462 */
463
464 /* Don't filter page faults; all of them should cause a switch. */
465 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
467 AssertRC(rc);
468
469 /* Init TSC offset to zero. */
470 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
471 AssertRC(rc);
472
473 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
474 AssertRC(rc);
475
476 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
477 AssertRC(rc);
478
479 /* Set the MSR bitmap address. */
480 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
481 {
482 /* Optional */
483 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
484 AssertRC(rc);
485 }
486
487 /* Clear MSR controls. */
488 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
489 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
490 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
491 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
492 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
493 AssertRC(rc);
494
495 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
496 {
497 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
498 /* Optional */
499 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
500 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
501
502 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
503 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
504
505 AssertRC(rc);
506 }
507
508 /* Set link pointer to -1. Not currently used. */
509 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
510 AssertRC(rc);
511
512 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
513 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
514 AssertRC(rc);
515
516 /* Configure the VMCS read cache. */
517 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
518
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
525 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
526 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
527 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
530 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
531 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
532 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
533 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
534 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
535
536 VMX_SETUP_SELREG(ES, pCache);
537 VMX_SETUP_SELREG(SS, pCache);
538 VMX_SETUP_SELREG(CS, pCache);
539 VMX_SETUP_SELREG(DS, pCache);
540 VMX_SETUP_SELREG(FS, pCache);
541 VMX_SETUP_SELREG(GS, pCache);
542 VMX_SETUP_SELREG(LDTR, pCache);
543 VMX_SETUP_SELREG(TR, pCache);
544
545 /* Status code VMCS reads. */
546 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
547 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
548 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
549 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
550 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
551 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
552 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
553 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
554 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
555
556 if (pVM->hwaccm.s.fNestedPaging)
557 {
558 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
559 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
560 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
561 }
562 else
563 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
564 } /* for each VMCPU */
565
566 /* Choose the right TLB setup function. */
567 if (pVM->hwaccm.s.fNestedPaging)
568 {
569 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
570
571 /* Default values for flushing. */
572 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
574
575 /* If the capabilities specify we can do more, then make use of it. */
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
577 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
578 else
579 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
580 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
581
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
583 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
584 }
585#ifdef HWACCM_VTX_WITH_VPID
586 else
587 if (pVM->hwaccm.s.vmx.fVPID)
588 {
589 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
590
591 /* Default values for flushing. */
592 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
593 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
594
595 /* If the capabilities specify we can do more, then make use of it. */
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
597 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
598 else
599 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
600 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
601
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
603 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
604 }
605#endif /* HWACCM_VTX_WITH_VPID */
606 else
607 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
608
609vmx_end:
610 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
611 return rc;
612}
613
614
615/**
616 * Injects an event (trap or external interrupt)
617 *
618 * @returns VBox status code.
619 * @param pVM The VM to operate on.
620 * @param pVCpu The VMCPU to operate on.
621 * @param pCtx CPU Context
622 * @param intInfo VMX interrupt info
623 * @param cbInstr Opcode length of faulting instruction
624 * @param errCode Error code (optional)
625 */
626static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
627{
628 int rc;
629 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
630
631#ifdef VBOX_WITH_STATISTICS
632 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
633#endif
634
635#ifdef VBOX_STRICT
636 if (iGate == 0xE)
637 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
638 else
639 if (iGate < 0x20)
640 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
641 else
642 {
643 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
644 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
645 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
646 }
647#endif
648
649#ifdef HWACCM_VMX_EMULATE_REALMODE
650 if (CPUMIsGuestInRealModeEx(pCtx))
651 {
652 RTGCPHYS GCPhysHandler;
653 uint16_t offset, ip;
654 RTSEL sel;
655
656 /* Injecting events doesn't work right with real mode emulation.
657 * (#GP if we try to inject external hardware interrupts)
658 * Inject the interrupt or trap directly instead.
659 *
660 * ASSUMES no access handlers for the bits we read or write below (should be safe).
661 */
662 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
663
664 /* Check if the interrupt handler is present. */
665 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
666 {
667 Log(("IDT cbIdt violation\n"));
668 if (iGate != X86_XCPT_DF)
669 {
670 RTGCUINTPTR intInfo;
671
672 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
673 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
674 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
675 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
676
677 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
678 }
679 Log(("Triple fault -> reset the VM!\n"));
680 return VINF_EM_RESET;
681 }
682 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
683 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
684 || iGate == 4)
685 {
686 ip = pCtx->ip + cbInstr;
687 }
688 else
689 ip = pCtx->ip;
690
691 /* Read the selector:offset pair of the interrupt handler. */
692 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
693 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
694 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
695
696 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
697
698 /* Construct the stack frame. */
699 /** @todo should check stack limit. */
700 pCtx->sp -= 2;
701 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
702 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
703 pCtx->sp -= 2;
704 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
705 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
706 pCtx->sp -= 2;
707 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
708 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
709
710 /* Update the CPU state for executing the handler. */
711 pCtx->rip = offset;
712 pCtx->cs = sel;
713 pCtx->csHid.u64Base = sel << 4;
714 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
715
716 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
717 return VINF_SUCCESS;
718 }
719#endif /* HWACCM_VMX_EMULATE_REALMODE */
720
721 /* Set event injection state. */
722 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
723
724 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
725 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
726
727 AssertRC(rc);
728 return rc;
729}
730
731
732/**
733 * Checks for pending guest interrupts and injects them
734 *
735 * @returns VBox status code.
736 * @param pVM The VM to operate on.
737 * @param pVCpu The VMCPU to operate on.
738 * @param pCtx CPU Context
739 */
740static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
741{
742 int rc;
743
744 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
745 if (pVCpu->hwaccm.s.Event.fPending)
746 {
747 Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
748 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
749 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
750 AssertRC(rc);
751
752 pVCpu->hwaccm.s.Event.fPending = false;
753 return VINF_SUCCESS;
754 }
755
756 /* If an active trap is already pending, then we must forward it first! */
757 if (!TRPMHasTrap(pVCpu))
758 {
759 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
760 {
761 RTGCUINTPTR intInfo;
762
763 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
764
765 intInfo = X86_XCPT_NMI;
766 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
767 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
768
769 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
770 AssertRC(rc);
771
772 return VINF_SUCCESS;
773 }
774
775 /* @todo SMI interrupts. */
776
777 /* When external interrupts are pending, we should exit the VM when IF is set. */
778 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
779 {
780 if (!(pCtx->eflags.u32 & X86_EFL_IF))
781 {
782 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
783 {
784 LogFlow(("Enable irq window exit!\n"));
785 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
786 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
787 AssertRC(rc);
788 }
789 /* else nothing to do but wait */
790 }
791 else
792 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
793 {
794 uint8_t u8Interrupt;
795
796 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
797 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
798 if (RT_SUCCESS(rc))
799 {
800 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
801 AssertRC(rc);
802 }
803 else
804 {
805 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
806 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
807 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
808 /* Just continue */
809 }
810 }
811 else
812 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
813 }
814 }
815
816#ifdef VBOX_STRICT
817 if (TRPMHasTrap(pVCpu))
818 {
819 uint8_t u8Vector;
820 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
821 AssertRC(rc);
822 }
823#endif
824
825 if ( (pCtx->eflags.u32 & X86_EFL_IF)
826 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
827 && TRPMHasTrap(pVCpu)
828 )
829 {
830 uint8_t u8Vector;
831 int rc;
832 TRPMEVENT enmType;
833 RTGCUINTPTR intInfo;
834 RTGCUINT errCode;
835
836 /* If a new event is pending, then dispatch it now. */
837 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
838 AssertRC(rc);
839 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
840 Assert(enmType != TRPM_SOFTWARE_INT);
841
842 /* Clear the pending trap. */
843 rc = TRPMResetTrap(pVCpu);
844 AssertRC(rc);
845
846 intInfo = u8Vector;
847 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
848
849 if (enmType == TRPM_TRAP)
850 {
851 switch (u8Vector) {
852 case 8:
853 case 10:
854 case 11:
855 case 12:
856 case 13:
857 case 14:
858 case 17:
859 /* Valid error codes. */
860 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
861 break;
862 default:
863 break;
864 }
865 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
866 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
867 else
868 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
869 }
870 else
871 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
872
873 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
874 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
875 AssertRC(rc);
876 } /* if (interrupts can be dispatched) */
877
878 return VINF_SUCCESS;
879}
880
881/**
882 * Save the host state
883 *
884 * @returns VBox status code.
885 * @param pVM The VM to operate on.
886 * @param pVCpu The VMCPU to operate on.
887 */
888VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
889{
890 int rc = VINF_SUCCESS;
891
892 /*
893 * Host CPU Context
894 */
895 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
896 {
897 RTIDTR idtr;
898 RTGDTR gdtr;
899 RTSEL SelTR;
900 PX86DESCHC pDesc;
901 uintptr_t trBase;
902 RTSEL cs;
903 RTSEL ss;
904 uint64_t cr3;
905
906 /* Control registers */
907 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
908#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
909 if (VMX_IS_64BIT_HOST_MODE())
910 {
911 cr3 = hwaccmR0Get64bitCR3();
912 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
913 }
914 else
915#endif
916 {
917 cr3 = ASMGetCR3();
918 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
919 }
920 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
921 AssertRC(rc);
922 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
923 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
924 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
925
926 /* Selector registers. */
927#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
928 if (VMX_IS_64BIT_HOST_MODE())
929 {
930 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
931 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
932 }
933 else
934 {
935 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
936 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
937 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
938 }
939#else
940 cs = ASMGetCS();
941 ss = ASMGetSS();
942#endif
943 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
944 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
945 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
946 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
947 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
948 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
949#if HC_ARCH_BITS == 32
950 if (!VMX_IS_64BIT_HOST_MODE())
951 {
952 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
953 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
954 }
955#endif
956 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
957 SelTR = ASMGetTR();
958 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
959 AssertRC(rc);
960 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
961 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
962 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
963 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
964 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
965 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
966 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
967
968 /* GDTR & IDTR */
969#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
970 if (VMX_IS_64BIT_HOST_MODE())
971 {
972 X86XDTR64 gdtr64, idtr64;
973 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
974 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
975 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
976 AssertRC(rc);
977 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
978 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
979 gdtr.cbGdt = gdtr64.cb;
980 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
981 }
982 else
983#endif
984 {
985 ASMGetGDTR(&gdtr);
986 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
987 ASMGetIDTR(&idtr);
988 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
989 AssertRC(rc);
990 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
991 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
992 }
993
994
995 /* Save the base address of the TR selector. */
996 if (SelTR > gdtr.cbGdt)
997 {
998 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
999 return VERR_VMX_INVALID_HOST_STATE;
1000 }
1001
1002#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1003 if (VMX_IS_64BIT_HOST_MODE())
1004 {
1005 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
1006 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
1007 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
1008 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
1009 AssertRC(rc);
1010 }
1011 else
1012#endif
1013 {
1014 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
1015#if HC_ARCH_BITS == 64
1016 trBase = X86DESC64_BASE(*pDesc);
1017#else
1018 trBase = X86DESC_BASE(*pDesc);
1019#endif
1020 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
1021 AssertRC(rc);
1022 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
1023 }
1024
1025 /* FS and GS base. */
1026#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1027 if (VMX_IS_64BIT_HOST_MODE())
1028 {
1029 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
1030 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
1031 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
1032 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
1033 }
1034#endif
1035 AssertRC(rc);
1036
1037 /* Sysenter MSRs. */
1038 /** @todo expensive!! */
1039 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1040 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1041#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1042 if (VMX_IS_64BIT_HOST_MODE())
1043 {
1044 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1045 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1046 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1047 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1048 }
1049 else
1050 {
1051 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1052 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1053 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1054 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1055 }
1056#elif HC_ARCH_BITS == 32
1057 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1058 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1059 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1060 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1061#else
1062 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1063 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1064 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1065 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1066#endif
1067 AssertRC(rc);
1068
1069#if 0 /* @todo deal with 32/64 */
1070 /* Restore the host EFER - on CPUs that support it. */
1071 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1072 {
1073 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1074 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1075 AssertRC(rc);
1076 }
1077#endif
1078 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1079 }
1080 return rc;
1081}
1082
1083/**
1084 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1085 *
1086 * @param pVM The VM to operate on.
1087 * @param pVCpu The VMCPU to operate on.
1088 * @param pCtx Guest context
1089 */
1090static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1091{
1092 if (CPUMIsGuestInPAEModeEx(pCtx))
1093 {
1094 X86PDPE Pdpe;
1095
1096 for (unsigned i=0;i<4;i++)
1097 {
1098 Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1099 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1100 AssertRC(rc);
1101 }
1102 }
1103}
1104
1105/**
1106 * Update the exception bitmap according to the current CPU state
1107 *
1108 * @param pVM The VM to operate on.
1109 * @param pVCpu The VMCPU to operate on.
1110 * @param pCtx Guest context
1111 */
1112static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1113{
1114 uint32_t u32TrapMask;
1115 Assert(pCtx);
1116
1117 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1118#ifndef DEBUG
1119 if (pVM->hwaccm.s.fNestedPaging)
1120 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1121#endif
1122
1123 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1124 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1125 && !(pCtx->cr0 & X86_CR0_NE)
1126 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1127 {
1128 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1129 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1130 }
1131
1132#ifdef DEBUG /* till after branching, enable it by default then. */
1133 /* Intercept X86_XCPT_DB if stepping is enabled */
1134 if (DBGFIsStepping(pVCpu))
1135 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1136 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1137 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1138#endif
1139
1140#ifdef VBOX_STRICT
1141 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1142#endif
1143
1144# ifdef HWACCM_VMX_EMULATE_REALMODE
1145 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1146 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1147 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1148# endif /* HWACCM_VMX_EMULATE_REALMODE */
1149
1150 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1151 AssertRC(rc);
1152}
1153
1154/**
1155 * Loads the guest state
1156 *
1157 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1158 *
1159 * @returns VBox status code.
1160 * @param pVM The VM to operate on.
1161 * @param pVCpu The VMCPU to operate on.
1162 * @param pCtx Guest context
1163 */
1164VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1165{
1166 int rc = VINF_SUCCESS;
1167 RTGCUINTPTR val;
1168 X86EFLAGS eflags;
1169
1170 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1171 * Set required bits to one and zero according to the MSR capabilities.
1172 */
1173 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1174 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1175 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1176#if 0 /* @todo deal with 32/64 */
1177 /* Required for the EFER write below, not supported on all CPUs. */
1178 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1179#endif
1180 /* 64 bits guest mode? */
1181 if (CPUMIsGuestInLongModeEx(pCtx))
1182 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1183 /* else Must be zero when AMD64 is not available. */
1184
1185 /* Mask away the bits that the CPU doesn't support */
1186 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1187 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1188 AssertRC(rc);
1189
1190 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1191 * Set required bits to one and zero according to the MSR capabilities.
1192 */
1193 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1194
1195 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1196#if 0 /* @todo deal with 32/64 */
1197 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1198#else
1199 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1200#endif
1201
1202#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1203 if (VMX_IS_64BIT_HOST_MODE())
1204 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1205 /* else: Must be zero when AMD64 is not available. */
1206#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1207 if (CPUMIsGuestInLongModeEx(pCtx))
1208 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1209 else
1210 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1211#endif
1212 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1213 /* Don't acknowledge external interrupts on VM-exit. */
1214 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1215 AssertRC(rc);
1216
1217 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1218 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1219 {
1220#ifdef HWACCM_VMX_EMULATE_REALMODE
1221 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1222 {
1223 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1224 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1225 {
1226 /* Correct weird requirements for switching to protected mode. */
1227 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1228 && enmGuestMode >= PGMMODE_PROTECTED)
1229 {
1230 /* Flush the recompiler code cache as it's not unlikely
1231 * the guest will rewrite code it will later execute in real
1232 * mode (OpenBSD 4.0 is one such example)
1233 */
1234 REMFlushTBs(pVM);
1235
1236 /* DPL of all hidden selector registers must match the current CPL (0). */
1237 pCtx->csHid.Attr.n.u2Dpl = 0;
1238 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1239
1240 pCtx->dsHid.Attr.n.u2Dpl = 0;
1241 pCtx->esHid.Attr.n.u2Dpl = 0;
1242 pCtx->fsHid.Attr.n.u2Dpl = 0;
1243 pCtx->gsHid.Attr.n.u2Dpl = 0;
1244 pCtx->ssHid.Attr.n.u2Dpl = 0;
1245
1246 /* The limit must correspond to the granularity bit. */
1247 if (!pCtx->csHid.Attr.n.u1Granularity)
1248 pCtx->csHid.u32Limit &= 0xffff;
1249 if (!pCtx->dsHid.Attr.n.u1Granularity)
1250 pCtx->dsHid.u32Limit &= 0xffff;
1251 if (!pCtx->esHid.Attr.n.u1Granularity)
1252 pCtx->esHid.u32Limit &= 0xffff;
1253 if (!pCtx->fsHid.Attr.n.u1Granularity)
1254 pCtx->fsHid.u32Limit &= 0xffff;
1255 if (!pCtx->gsHid.Attr.n.u1Granularity)
1256 pCtx->gsHid.u32Limit &= 0xffff;
1257 if (!pCtx->ssHid.Attr.n.u1Granularity)
1258 pCtx->ssHid.u32Limit &= 0xffff;
1259 }
1260 else
1261 /* Switching from protected mode to real mode. */
1262 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1263 && enmGuestMode == PGMMODE_REAL)
1264 {
1265 /* The limit must also be set to 0xffff. */
1266 pCtx->csHid.u32Limit = 0xffff;
1267 pCtx->dsHid.u32Limit = 0xffff;
1268 pCtx->esHid.u32Limit = 0xffff;
1269 pCtx->fsHid.u32Limit = 0xffff;
1270 pCtx->gsHid.u32Limit = 0xffff;
1271 pCtx->ssHid.u32Limit = 0xffff;
1272
1273 Assert(pCtx->csHid.u64Base <= 0xfffff);
1274 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1275 Assert(pCtx->esHid.u64Base <= 0xfffff);
1276 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1277 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1278 }
1279 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1280 }
1281 else
1282 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1283 if ( CPUMIsGuestInRealModeEx(pCtx)
1284 && pCtx->csHid.u64Base == 0xffff0000)
1285 {
1286 pCtx->csHid.u64Base = 0xf0000;
1287 pCtx->cs = 0xf000;
1288 }
1289 }
1290#endif /* HWACCM_VMX_EMULATE_REALMODE */
1291
1292 VMX_WRITE_SELREG(ES, es);
1293 AssertRC(rc);
1294
1295 VMX_WRITE_SELREG(CS, cs);
1296 AssertRC(rc);
1297
1298 VMX_WRITE_SELREG(SS, ss);
1299 AssertRC(rc);
1300
1301 VMX_WRITE_SELREG(DS, ds);
1302 AssertRC(rc);
1303
1304 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1305 VMX_WRITE_SELREG(FS, fs);
1306 AssertRC(rc);
1307
1308 VMX_WRITE_SELREG(GS, gs);
1309 AssertRC(rc);
1310 }
1311
1312 /* Guest CPU context: LDTR. */
1313 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1314 {
1315 if (pCtx->ldtr == 0)
1316 {
1317 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1318 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1319 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1320 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1321 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1322 }
1323 else
1324 {
1325 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1326 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1327 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1328 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1329 }
1330 AssertRC(rc);
1331 }
1332 /* Guest CPU context: TR. */
1333 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1334 {
1335#ifdef HWACCM_VMX_EMULATE_REALMODE
1336 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1337 if (CPUMIsGuestInRealModeEx(pCtx))
1338 {
1339 RTGCPHYS GCPhys;
1340
1341 /* We convert it here every time as pci regions could be reconfigured. */
1342 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1343 AssertRC(rc);
1344
1345 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1346 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1347 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1348
1349 X86DESCATTR attr;
1350
1351 attr.u = 0;
1352 attr.n.u1Present = 1;
1353 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1354 val = attr.u;
1355 }
1356 else
1357#endif /* HWACCM_VMX_EMULATE_REALMODE */
1358 {
1359 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1360 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1361 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1362
1363 val = pCtx->trHid.Attr.u;
1364
1365 /* The TSS selector must be busy. */
1366 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1367 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1368 else
1369 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1370 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1371
1372 }
1373 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1374 AssertRC(rc);
1375 }
1376 /* Guest CPU context: GDTR. */
1377 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1378 {
1379 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1380 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1381 AssertRC(rc);
1382 }
1383 /* Guest CPU context: IDTR. */
1384 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1385 {
1386 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1387 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1388 AssertRC(rc);
1389 }
1390
1391 /*
1392 * Sysenter MSRs (unconditional)
1393 */
1394 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1395 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1396 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1397 AssertRC(rc);
1398
1399 /* Control registers */
1400 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1401 {
1402 val = pCtx->cr0;
1403 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1404 Log2(("Guest CR0-shadow %08x\n", val));
1405 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1406 {
1407 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1408 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1409 }
1410 else
1411 {
1412 /** @todo check if we support the old style mess correctly. */
1413 if (!(val & X86_CR0_NE))
1414 Log(("Forcing X86_CR0_NE!!!\n"));
1415
1416 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1417 }
1418 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1419 val |= X86_CR0_PE | X86_CR0_PG;
1420 if (pVM->hwaccm.s.fNestedPaging)
1421 {
1422 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1423 {
1424 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1425 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1426 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1427 }
1428 else
1429 {
1430 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1431 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1432 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1433 }
1434 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1435 AssertRC(rc);
1436 }
1437 else
1438 {
1439 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1440 val |= X86_CR0_WP;
1441 }
1442
1443 /* Always enable caching. */
1444 val &= ~(X86_CR0_CD|X86_CR0_NW);
1445
1446 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1447 Log2(("Guest CR0 %08x\n", val));
1448 /* CR0 flags owned by the host; if the guests attempts to change them, then
1449 * the VM will exit.
1450 */
1451 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1452 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1453 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1454 | X86_CR0_TS
1455 | X86_CR0_ET /* Bit not restored during VM-exit! */
1456 | X86_CR0_CD /* Bit not restored during VM-exit! */
1457 | X86_CR0_NW /* Bit not restored during VM-exit! */
1458 | X86_CR0_NE
1459 | X86_CR0_MP;
1460 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1461
1462 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1463 Log2(("Guest CR0-mask %08x\n", val));
1464 AssertRC(rc);
1465 }
1466 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1467 {
1468 /* CR4 */
1469 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1470 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1471 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1472 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1473
1474 if (!pVM->hwaccm.s.fNestedPaging)
1475 {
1476 switch(pVCpu->hwaccm.s.enmShadowMode)
1477 {
1478 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1479 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1480 case PGMMODE_32_BIT: /* 32-bit paging. */
1481 val &= ~X86_CR4_PAE;
1482 break;
1483
1484 case PGMMODE_PAE: /* PAE paging. */
1485 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1486 /** @todo use normal 32 bits paging */
1487 val |= X86_CR4_PAE;
1488 break;
1489
1490 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1491 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1492#ifdef VBOX_ENABLE_64_BITS_GUESTS
1493 break;
1494#else
1495 AssertFailed();
1496 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1497#endif
1498 default: /* shut up gcc */
1499 AssertFailed();
1500 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1501 }
1502 }
1503 else
1504 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1505 {
1506 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1507 val |= X86_CR4_PSE;
1508 /* Our identity mapping is a 32 bits page directory. */
1509 val &= ~X86_CR4_PAE;
1510 }
1511
1512 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1513 Log2(("Guest CR4 %08x\n", val));
1514 /* CR4 flags owned by the host; if the guests attempts to change them, then
1515 * the VM will exit.
1516 */
1517 val = 0
1518 | X86_CR4_PAE
1519 | X86_CR4_PGE
1520 | X86_CR4_PSE
1521 | X86_CR4_VMXE;
1522 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1523
1524 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1525 Log2(("Guest CR4-mask %08x\n", val));
1526 AssertRC(rc);
1527 }
1528
1529 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1530 {
1531 if (pVM->hwaccm.s.fNestedPaging)
1532 {
1533 Assert(PGMGetHyperCR3(pVCpu));
1534 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1535
1536 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1537 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1538 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1539 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1540
1541 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1542 AssertRC(rc);
1543
1544 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1545 {
1546 RTGCPHYS GCPhys;
1547
1548 /* We convert it here every time as pci regions could be reconfigured. */
1549 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1550 AssertRC(rc);
1551
1552 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1553 * take care of the translation to host physical addresses.
1554 */
1555 val = GCPhys;
1556 }
1557 else
1558 {
1559 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1560 val = pCtx->cr3;
1561 /* Prefetch the four PDPT entries in PAE mode. */
1562 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1563 }
1564 }
1565 else
1566 {
1567 val = PGMGetHyperCR3(pVCpu);
1568 Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1569 }
1570
1571 /* Save our shadow CR3 register. */
1572 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1573 AssertRC(rc);
1574 }
1575
1576 /* Debug registers. */
1577 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1578 {
1579 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1580 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1581
1582 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1583 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1584 pCtx->dr[7] |= 0x400; /* must be one */
1585
1586 /* Resync DR7 */
1587 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1588 AssertRC(rc);
1589
1590#ifdef DEBUG
1591 /* Sync the hypervisor debug state now if any breakpoint is armed. */
1592 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
1593 && !CPUMIsHyperDebugStateActive(pVCpu)
1594 && !DBGFIsStepping(pVCpu))
1595 {
1596 /* Save the host and load the hypervisor debug state. */
1597 rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1598 AssertRC(rc);
1599
1600 /* DRx intercepts remain enabled. */
1601
1602 /* Override dr7 with the hypervisor value. */
1603 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, CPUMGetHyperDR7(pVCpu));
1604 AssertRC(rc);
1605 }
1606 else
1607#endif
1608 /* Sync the debug state now if any breakpoint is armed. */
1609 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1610 && !CPUMIsGuestDebugStateActive(pVCpu)
1611 && !DBGFIsStepping(pVCpu))
1612 {
1613 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1614
1615 /* Disable drx move intercepts. */
1616 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1617 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1618 AssertRC(rc);
1619
1620 /* Save the host and load the guest debug state. */
1621 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1622 AssertRC(rc);
1623 }
1624
1625 /* IA32_DEBUGCTL MSR. */
1626 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1627 AssertRC(rc);
1628
1629 /** @todo do we really ever need this? */
1630 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1631 AssertRC(rc);
1632 }
1633
1634 /* EIP, ESP and EFLAGS */
1635 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1636 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1637 AssertRC(rc);
1638
1639 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1640 eflags = pCtx->eflags;
1641 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1642 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1643
1644#ifdef HWACCM_VMX_EMULATE_REALMODE
1645 /* Real mode emulation using v86 mode. */
1646 if (CPUMIsGuestInRealModeEx(pCtx))
1647 {
1648 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1649
1650 eflags.Bits.u1VM = 1;
1651 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1652 }
1653#endif /* HWACCM_VMX_EMULATE_REALMODE */
1654 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1655 AssertRC(rc);
1656
1657 /* TSC offset. */
1658 uint64_t u64TSCOffset;
1659
1660 if (TMCpuTickCanUseRealTSC(pVCpu, &u64TSCOffset))
1661 {
1662 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1663 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1664 AssertRC(rc);
1665
1666 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1667 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1668 AssertRC(rc);
1669 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1670 }
1671 else
1672 {
1673 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1674 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1675 AssertRC(rc);
1676 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1677 }
1678
1679 /* 64 bits guest mode? */
1680 if (CPUMIsGuestInLongModeEx(pCtx))
1681 {
1682#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1683 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1684#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1685 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1686#else
1687# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1688 if (!pVM->hwaccm.s.fAllow64BitGuests)
1689 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1690# endif
1691 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1692#endif
1693 /* Unconditionally update these as wrmsr might have changed them. */
1694 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1695 AssertRC(rc);
1696 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1697 AssertRC(rc);
1698 }
1699 else
1700 {
1701 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1702 }
1703
1704#if 0 /* @todo deal with 32/64 */
1705 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1706 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1707 {
1708 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1709 AssertRC(rc);
1710 }
1711#endif
1712
1713 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1714
1715 /* Done. */
1716 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1717
1718 return rc;
1719}
1720
1721/**
1722 * Syncs back the guest state
1723 *
1724 * @returns VBox status code.
1725 * @param pVM The VM to operate on.
1726 * @param pVCpu The VMCPU to operate on.
1727 * @param pCtx Guest context
1728 */
1729DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1730{
1731 RTGCUINTREG val, valShadow;
1732 RTGCUINTPTR uInterruptState;
1733 int rc;
1734
1735 /* Let's first sync back eip, esp, and eflags. */
1736 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1737 AssertRC(rc);
1738 pCtx->rip = val;
1739 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1740 AssertRC(rc);
1741 pCtx->rsp = val;
1742 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1743 AssertRC(rc);
1744 pCtx->eflags.u32 = val;
1745
1746 /* Take care of instruction fusing (sti, mov ss) */
1747 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1748 uInterruptState = val;
1749 if (uInterruptState != 0)
1750 {
1751 Assert(uInterruptState <= 2); /* only sti & mov ss */
1752 Log(("uInterruptState %x eip=%RGv\n", (uint32_t)uInterruptState, pCtx->rip));
1753 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1754 }
1755 else
1756 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1757
1758 /* Control registers. */
1759 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1760 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1761 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1762 CPUMSetGuestCR0(pVCpu, val);
1763
1764 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1765 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1766 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1767 CPUMSetGuestCR4(pVCpu, val);
1768
1769 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1770 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1771 if ( pVM->hwaccm.s.fNestedPaging
1772 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1773 {
1774 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1775
1776 /* Can be updated behind our back in the nested paging case. */
1777 CPUMSetGuestCR2(pVCpu, pCache->cr2);
1778
1779 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1780
1781 if (val != pCtx->cr3)
1782 {
1783 CPUMSetGuestCR3(pVCpu, val);
1784 PGMUpdateCR3(pVCpu, val);
1785 }
1786 /* Prefetch the four PDPT entries in PAE mode. */
1787 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1788 }
1789
1790 /* Sync back DR7 here. */
1791 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1792 pCtx->dr[7] = val;
1793
1794 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1795 VMX_READ_SELREG(ES, es);
1796 VMX_READ_SELREG(SS, ss);
1797 VMX_READ_SELREG(CS, cs);
1798 VMX_READ_SELREG(DS, ds);
1799 VMX_READ_SELREG(FS, fs);
1800 VMX_READ_SELREG(GS, gs);
1801
1802 /*
1803 * System MSRs
1804 */
1805 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1806 pCtx->SysEnter.cs = val;
1807 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1808 pCtx->SysEnter.eip = val;
1809 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1810 pCtx->SysEnter.esp = val;
1811
1812 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1813 VMX_READ_SELREG(LDTR, ldtr);
1814
1815 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1816 pCtx->gdtr.cbGdt = val;
1817 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1818 pCtx->gdtr.pGdt = val;
1819
1820 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1821 pCtx->idtr.cbIdt = val;
1822 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1823 pCtx->idtr.pIdt = val;
1824
1825#ifdef HWACCM_VMX_EMULATE_REALMODE
1826 /* Real mode emulation using v86 mode. */
1827 if (CPUMIsGuestInRealModeEx(pCtx))
1828 {
1829 /* Hide our emulation flags */
1830 pCtx->eflags.Bits.u1VM = 0;
1831
1832 /* Restore original IOPL setting as we always use 0. */
1833 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1834
1835 /* Force a TR resync every time in case we switch modes. */
1836 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1837 }
1838 else
1839#endif /* HWACCM_VMX_EMULATE_REALMODE */
1840 {
1841 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1842 VMX_READ_SELREG(TR, tr);
1843 }
1844 return VINF_SUCCESS;
1845}
1846
1847/**
1848 * Dummy placeholder
1849 *
1850 * @param pVM The VM to operate on.
1851 * @param pVCpu The VMCPU to operate on.
1852 */
1853static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1854{
1855 NOREF(pVM);
1856 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1857 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1858 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1859 return;
1860}
1861
1862/**
1863 * Setup the tagged TLB for EPT
1864 *
1865 * @returns VBox status code.
1866 * @param pVM The VM to operate on.
1867 * @param pVCpu The VMCPU to operate on.
1868 */
1869static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1870{
1871 PHWACCM_CPUINFO pCpu;
1872
1873 Assert(pVM->hwaccm.s.fNestedPaging);
1874 Assert(!pVM->hwaccm.s.vmx.fVPID);
1875
1876 /* Deal with tagged TLBs if VPID or EPT is supported. */
1877 pCpu = HWACCMR0GetCurrentCpu();
1878 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1879 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1880 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1881 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1882 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1883 {
1884 /* Force a TLB flush on VM entry. */
1885 pVCpu->hwaccm.s.fForceTLBFlush = true;
1886 }
1887 else
1888 Assert(!pCpu->fFlushTLB);
1889
1890 /* Check for tlb shootdown flushes. */
1891 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1892 pVCpu->hwaccm.s.fForceTLBFlush = true;
1893
1894 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1895 pCpu->fFlushTLB = false;
1896
1897 if (pVCpu->hwaccm.s.fForceTLBFlush)
1898 {
1899 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1900 }
1901 else
1902 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1903 {
1904 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1905 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1906
1907 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1908 {
1909 /* aTlbShootdownPages contains physical addresses in this case. */
1910 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1911 }
1912 }
1913 pVCpu->hwaccm.s.TlbShootdown.cPages= 0;
1914 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1915
1916#ifdef VBOX_WITH_STATISTICS
1917 if (pVCpu->hwaccm.s.fForceTLBFlush)
1918 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1919 else
1920 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1921#endif
1922}
1923
1924#ifdef HWACCM_VTX_WITH_VPID
1925/**
1926 * Setup the tagged TLB for VPID
1927 *
1928 * @returns VBox status code.
1929 * @param pVM The VM to operate on.
1930 * @param pVCpu The VMCPU to operate on.
1931 */
1932static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1933{
1934 PHWACCM_CPUINFO pCpu;
1935
1936 Assert(pVM->hwaccm.s.vmx.fVPID);
1937 Assert(!pVM->hwaccm.s.fNestedPaging);
1938
1939 /* Deal with tagged TLBs if VPID or EPT is supported. */
1940 pCpu = HWACCMR0GetCurrentCpu();
1941 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1942 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1943 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1944 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1945 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1946 {
1947 /* Force a TLB flush on VM entry. */
1948 pVCpu->hwaccm.s.fForceTLBFlush = true;
1949 }
1950 else
1951 Assert(!pCpu->fFlushTLB);
1952
1953 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1954
1955 /* Check for tlb shootdown flushes. */
1956 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1957 pVCpu->hwaccm.s.fForceTLBFlush = true;
1958
1959 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1960 if (pVCpu->hwaccm.s.fForceTLBFlush)
1961 {
1962 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1963 || pCpu->fFlushTLB)
1964 {
1965 pCpu->fFlushTLB = false;
1966 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1967 pCpu->cTLBFlushes++;
1968 }
1969 else
1970 {
1971 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1972 pVCpu->hwaccm.s.fForceTLBFlush = false;
1973 }
1974
1975 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1976 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1977 }
1978 else
1979 {
1980 Assert(!pCpu->fFlushTLB);
1981 Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
1982
1983 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1984 {
1985 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1986 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1987 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1988 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1989 }
1990 }
1991 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1992 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1993
1994 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1995 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1996 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1997
1998 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1999 AssertRC(rc);
2000
2001 if (pVCpu->hwaccm.s.fForceTLBFlush)
2002 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
2003
2004#ifdef VBOX_WITH_STATISTICS
2005 if (pVCpu->hwaccm.s.fForceTLBFlush)
2006 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
2007 else
2008 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
2009#endif
2010}
2011#endif /* HWACCM_VTX_WITH_VPID */
2012
2013/**
2014 * Runs guest code in a VT-x VM.
2015 *
2016 * @returns VBox status code.
2017 * @param pVM The VM to operate on.
2018 * @param pVCpu The VMCPU to operate on.
2019 * @param pCtx Guest context
2020 */
2021VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2022{
2023 int rc = VINF_SUCCESS;
2024 RTGCUINTREG val;
2025 RTGCUINTREG exitReason = VMX_EXIT_INVALID;
2026 RTGCUINTREG instrError, cbInstr;
2027 RTGCUINTPTR exitQualification = 0;
2028 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
2029 RTGCUINTPTR errCode, instrInfo;
2030 bool fSetupTPRCaching = false;
2031 uint8_t u8LastTPR = 0;
2032 PHWACCM_CPUINFO pCpu = 0;
2033 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
2034 unsigned cResume = 0;
2035#ifdef VBOX_STRICT
2036 RTCPUID idCpuCheck;
2037#endif
2038#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2039 uint64_t u64LastTime = RTTimeMilliTS();
2040#endif
2041#ifdef VBOX_WITH_STATISTICS
2042 bool fStatEntryStarted = true;
2043 bool fStatExit2Started = false;
2044#endif
2045
2046 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
2047
2048 /* Check if we need to use TPR shadowing. */
2049 if ( CPUMIsGuestInLongModeEx(pCtx)
2050 || ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2051 && pVM->hwaccm.s.fHasIoApic)
2052 )
2053 {
2054 fSetupTPRCaching = true;
2055 }
2056
2057 Log2(("\nE"));
2058
2059 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
2060
2061#ifdef VBOX_STRICT
2062 {
2063 RTCCUINTREG val;
2064
2065 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
2066 AssertRC(rc);
2067 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
2068
2069 /* allowed zero */
2070 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
2071 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
2072
2073 /* allowed one */
2074 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
2075 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
2076
2077 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
2078 AssertRC(rc);
2079 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
2080
2081 /* Must be set according to the MSR, but can be cleared in case of EPT. */
2082 if (pVM->hwaccm.s.fNestedPaging)
2083 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
2084 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2085 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2086
2087 /* allowed zero */
2088 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2089 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2090
2091 /* allowed one */
2092 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2093 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2094
2095 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2096 AssertRC(rc);
2097 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2098
2099 /* allowed zero */
2100 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2101 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2102
2103 /* allowed one */
2104 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2105 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2106
2107 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2108 AssertRC(rc);
2109 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2110
2111 /* allowed zero */
2112 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2113 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2114
2115 /* allowed one */
2116 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2117 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2118 }
2119#endif
2120
2121#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2122 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2123#endif
2124
2125 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2126 */
2127ResumeExecution:
2128 STAM_STATS({
2129 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2130 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2131 });
2132 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2133 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2134 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2135 Assert(!HWACCMR0SuspendPending());
2136
2137 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2138 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
2139 {
2140 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2141 rc = VINF_EM_RAW_INTERRUPT;
2142 goto end;
2143 }
2144
2145 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2146 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2147 {
2148 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2149 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2150 {
2151 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2152 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2153 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2154 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2155 */
2156 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2157 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2158 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2159 AssertRC(rc);
2160 }
2161 }
2162 else
2163 {
2164 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2165 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2166 AssertRC(rc);
2167 }
2168
2169#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2170 if (RT_UNLIKELY(cResume & 0xf) == 0)
2171 {
2172 uint64_t u64CurTime = RTTimeMilliTS();
2173
2174 if (RT_UNLIKELY(u64CurTime > u64LastTime))
2175 {
2176 u64LastTime = u64CurTime;
2177 TMTimerPollVoid(pVM, pVCpu);
2178 }
2179 }
2180#endif
2181
2182 /* Check for pending actions that force us to go back to ring 3. */
2183#ifdef DEBUG
2184 /* Intercept X86_XCPT_DB if stepping is enabled */
2185 if (!DBGFIsStepping(pVCpu))
2186#endif
2187 {
2188 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2189 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2190 {
2191 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2192 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2193 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2194 goto end;
2195 }
2196 }
2197
2198 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2199 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2200 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2201 {
2202 rc = VINF_EM_PENDING_REQUEST;
2203 goto end;
2204 }
2205
2206#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2207 /*
2208 * Exit to ring-3 preemption/work is pending.
2209 *
2210 * Interrupts are disabled before the call to make sure we don't miss any interrupt
2211 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
2212 * further down, but VMXR0CheckPendingInterrupt makes that impossible.)
2213 *
2214 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
2215 * shootdowns rely on this.
2216 */
2217 uOldEFlags = ASMIntDisableFlags();
2218 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2219 {
2220 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
2221 rc = VINF_EM_RAW_INTERRUPT;
2222 goto end;
2223 }
2224 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2225#endif
2226
2227 /* When external interrupts are pending, we should exit the VM when IF is set. */
2228 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2229 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2230 if (RT_FAILURE(rc))
2231 goto end;
2232
2233 /** @todo check timers?? */
2234
2235 /* TPR caching using CR8 is only available in 64 bits mode */
2236 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2237 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2238 /**
2239 * @todo query and update the TPR only when it could have been changed (mmio access & wrmsr (x2apic))
2240 */
2241 if (fSetupTPRCaching)
2242 {
2243 /* TPR caching in CR8 */
2244 bool fPending;
2245
2246 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
2247 AssertRC(rc);
2248 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2249 pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8LastTPR;
2250
2251 /* Two options here:
2252 * - external interrupt pending, but masked by the TPR value.
2253 * -> a CR8 update that lower the current TPR value should cause an exit
2254 * - no pending interrupts
2255 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2256 */
2257 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
2258 AssertRC(rc);
2259 }
2260
2261#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2262 if ( pVM->hwaccm.s.fNestedPaging
2263# ifdef HWACCM_VTX_WITH_VPID
2264 || pVM->hwaccm.s.vmx.fVPID
2265# endif /* HWACCM_VTX_WITH_VPID */
2266 )
2267 {
2268 pCpu = HWACCMR0GetCurrentCpu();
2269 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2270 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2271 {
2272 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2273 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2274 else
2275 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2276 }
2277 if (pCpu->fFlushTLB)
2278 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2279 else
2280 if (pVCpu->hwaccm.s.fForceTLBFlush)
2281 LogFlow(("Manual TLB flush\n"));
2282 }
2283#endif
2284#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2285 PGMDynMapFlushAutoSet(pVCpu);
2286#endif
2287
2288 /*
2289 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2290 * (until the actual world switch)
2291 */
2292#ifdef VBOX_STRICT
2293 idCpuCheck = RTMpCpuId();
2294#endif
2295#ifdef LOG_ENABLED
2296 VMMR0LogFlushDisable(pVCpu);
2297#endif
2298 /* Save the host state first. */
2299 rc = VMXR0SaveHostState(pVM, pVCpu);
2300 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2301 {
2302 VMMR0LogFlushEnable(pVCpu);
2303 goto end;
2304 }
2305 /* Load the guest state */
2306 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2307 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2308 {
2309 VMMR0LogFlushEnable(pVCpu);
2310 goto end;
2311 }
2312
2313#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2314 /* Disable interrupts to make sure a poke will interrupt execution.
2315 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
2316 */
2317 uOldEFlags = ASMIntDisableFlags();
2318 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2319#endif
2320
2321 /* Deal with tagged TLB setup and invalidation. */
2322 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2323
2324 /* Non-register state Guest Context */
2325 /** @todo change me according to cpu state */
2326 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2327 AssertRC(rc);
2328
2329 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2330
2331 /* Manual save and restore:
2332 * - General purpose registers except RIP, RSP
2333 *
2334 * Trashed:
2335 * - CR2 (we don't care)
2336 * - LDTR (reset to 0)
2337 * - DRx (presumably not changed at all)
2338 * - DR7 (reset to 0x400)
2339 * - EFLAGS (reset to RT_BIT(1); not relevant)
2340 *
2341 */
2342
2343
2344 /* All done! Let's start VM execution. */
2345 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2346 Assert(idCpuCheck == RTMpCpuId());
2347
2348#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2349 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2350 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2351#endif
2352
2353 TMNotifyStartOfExecution(pVCpu);
2354#ifdef VBOX_WITH_KERNEL_USING_XMM
2355 rc = hwaccmR0VMXStartVMWrapXMM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hwaccm.s.vmx.pfnStartVM);
2356#else
2357 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2358#endif
2359 TMNotifyEndOfExecution(pVCpu);
2360 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2361 Assert(!(ASMGetFlags() & X86_EFL_IF));
2362 ASMSetFlags(uOldEFlags);
2363#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2364 uOldEFlags = ~(RTCCUINTREG)0;
2365#endif
2366
2367 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2368
2369 /* In case we execute a goto ResumeExecution later on. */
2370 pVCpu->hwaccm.s.fResumeVM = true;
2371 pVCpu->hwaccm.s.fForceTLBFlush = false;
2372
2373 /*
2374 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2375 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2376 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2377 */
2378 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2379 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2380
2381 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2382 {
2383 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2384 VMMR0LogFlushEnable(pVCpu);
2385 goto end;
2386 }
2387
2388 /* Success. Query the guest state and figure out what has happened. */
2389
2390 /* Investigate why there was a VM-exit. */
2391 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2392 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2393
2394 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2395 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2396 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2397 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2398 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2399 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2400 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2401 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2402 AssertRC(rc);
2403
2404 /* Sync back the guest state */
2405 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2406 AssertRC(rc);
2407
2408 /* Note! NOW IT'S SAFE FOR LOGGING! */
2409 VMMR0LogFlushEnable(pVCpu);
2410 Log2(("Raw exit reason %08x\n", exitReason));
2411
2412 /* Check if an injected event was interrupted prematurely. */
2413 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2414 AssertRC(rc);
2415 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2416 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2417 /* Ignore 'int xx' as they'll be restarted anyway. */
2418 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2419 /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
2420 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2421 {
2422 Assert(!pVCpu->hwaccm.s.Event.fPending);
2423 pVCpu->hwaccm.s.Event.fPending = true;
2424 /* Error code present? */
2425 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2426 {
2427 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2428 AssertRC(rc);
2429 pVCpu->hwaccm.s.Event.errCode = val;
2430 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2431 }
2432 else
2433 {
2434 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2435 pVCpu->hwaccm.s.Event.errCode = 0;
2436 }
2437 }
2438#ifdef VBOX_STRICT
2439 else
2440 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2441 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2442 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2443 {
2444 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2445 }
2446
2447 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2448 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2449#endif
2450
2451 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2452 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2453 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2454 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2455 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2456
2457 /* Sync back the TPR if it was changed. */
2458 if ( fSetupTPRCaching
2459 && u8LastTPR != pVCpu->hwaccm.s.vmx.pVAPIC[0x80])
2460 {
2461 rc = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);
2462 AssertRC(rc);
2463 }
2464
2465 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2466 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2467
2468 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2469 switch (exitReason)
2470 {
2471 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2472 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2473 {
2474 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2475
2476 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2477 {
2478 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2479 /* External interrupt; leave to allow it to be dispatched again. */
2480 rc = VINF_EM_RAW_INTERRUPT;
2481 break;
2482 }
2483 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2484 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2485 {
2486 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2487 /* External interrupt; leave to allow it to be dispatched again. */
2488 rc = VINF_EM_RAW_INTERRUPT;
2489 break;
2490
2491 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2492 AssertFailed(); /* can't come here; fails the first check. */
2493 break;
2494
2495 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2496 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2497 Assert(vector == 1 || vector == 3 || vector == 4);
2498 /* no break */
2499 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2500 Log2(("Hardware/software interrupt %d\n", vector));
2501 switch (vector)
2502 {
2503 case X86_XCPT_NM:
2504 {
2505 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2506
2507 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2508 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2509 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2510 if (rc == VINF_SUCCESS)
2511 {
2512 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2513
2514 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2515
2516 /* Continue execution. */
2517 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2518
2519 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2520 goto ResumeExecution;
2521 }
2522
2523 Log(("Forward #NM fault to the guest\n"));
2524 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2525 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2526 AssertRC(rc);
2527 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2528 goto ResumeExecution;
2529 }
2530
2531 case X86_XCPT_PF: /* Page fault */
2532 {
2533#ifdef DEBUG
2534 if (pVM->hwaccm.s.fNestedPaging)
2535 { /* A genuine pagefault.
2536 * Forward the trap to the guest by injecting the exception and resuming execution.
2537 */
2538 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2539
2540 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2541
2542 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2543
2544 /* Now we must update CR2. */
2545 pCtx->cr2 = exitQualification;
2546 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2547 AssertRC(rc);
2548
2549 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2550 goto ResumeExecution;
2551 }
2552#endif
2553 Assert(!pVM->hwaccm.s.fNestedPaging);
2554
2555 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2556 /* Exit qualification contains the linear address of the page fault. */
2557 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2558 TRPMSetErrorCode(pVCpu, errCode);
2559 TRPMSetFaultAddress(pVCpu, exitQualification);
2560
2561 /* Shortcut for APIC TPR reads and writes. */
2562 if ( (exitQualification & 0xfff) == 0x080
2563 && !(errCode & X86_TRAP_PF_P) /* not present */
2564 && fSetupTPRCaching
2565 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
2566 {
2567 RTGCPHYS GCPhysApicBase, GCPhys;
2568 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
2569 GCPhysApicBase &= PAGE_BASE_GC_MASK;
2570
2571 rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
2572 if ( rc == VINF_SUCCESS
2573 && GCPhys == GCPhysApicBase)
2574 {
2575 Log(("Enable VT-x virtual APIC access filtering\n"));
2576 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
2577 AssertRC(rc);
2578 }
2579 }
2580
2581 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2582 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2583 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2584 if (rc == VINF_SUCCESS)
2585 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2586 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2587 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2588
2589 TRPMResetTrap(pVCpu);
2590
2591 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2592 goto ResumeExecution;
2593 }
2594 else
2595 if (rc == VINF_EM_RAW_GUEST_TRAP)
2596 { /* A genuine pagefault.
2597 * Forward the trap to the guest by injecting the exception and resuming execution.
2598 */
2599 Log2(("Forward page fault to the guest\n"));
2600
2601 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2602 /* The error code might have been changed. */
2603 errCode = TRPMGetErrorCode(pVCpu);
2604
2605 TRPMResetTrap(pVCpu);
2606
2607 /* Now we must update CR2. */
2608 pCtx->cr2 = exitQualification;
2609 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2610 AssertRC(rc);
2611
2612 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2613 goto ResumeExecution;
2614 }
2615#ifdef VBOX_STRICT
2616 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2617 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2618#endif
2619 /* Need to go back to the recompiler to emulate the instruction. */
2620 TRPMResetTrap(pVCpu);
2621 break;
2622 }
2623
2624 case X86_XCPT_MF: /* Floating point exception. */
2625 {
2626 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2627 if (!(pCtx->cr0 & X86_CR0_NE))
2628 {
2629 /* old style FPU error reporting needs some extra work. */
2630 /** @todo don't fall back to the recompiler, but do it manually. */
2631 rc = VINF_EM_RAW_EMULATE_INSTR;
2632 break;
2633 }
2634 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2635 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2636 AssertRC(rc);
2637
2638 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2639 goto ResumeExecution;
2640 }
2641
2642 case X86_XCPT_DB: /* Debug exception. */
2643 {
2644 uint64_t uDR6;
2645
2646 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2647 *
2648 * Exit qualification bits:
2649 * 3:0 B0-B3 which breakpoint condition was met
2650 * 12:4 Reserved (0)
2651 * 13 BD - debug register access detected
2652 * 14 BS - single step execution or branch taken
2653 * 63:15 Reserved (0)
2654 */
2655 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2656
2657 /* Note that we don't support guest and host-initiated debugging at the same time. */
2658 Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx));
2659
2660 uDR6 = X86_DR6_INIT_VAL;
2661 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2662 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
2663 if (rc == VINF_EM_RAW_GUEST_TRAP)
2664 {
2665 /** @todo this isn't working, but we'll never get here normally. */
2666
2667 /* Update DR6 here. */
2668 pCtx->dr[6] = uDR6;
2669
2670 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2671 pCtx->dr[7] &= ~X86_DR7_GD;
2672
2673 /* Paranoia. */
2674 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2675 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2676 pCtx->dr[7] |= 0x400; /* must be one */
2677
2678 /* Resync DR7 */
2679 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2680 AssertRC(rc);
2681
2682 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2683 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2684 AssertRC(rc);
2685
2686 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2687 goto ResumeExecution;
2688 }
2689 /* Return to ring 3 to deal with the debug exit code. */
2690 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2691 break;
2692 }
2693
2694 case X86_XCPT_BP: /* Breakpoint. */
2695 {
2696 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2697 if (rc == VINF_EM_RAW_GUEST_TRAP)
2698 {
2699 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2700 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2701 AssertRC(rc);
2702 goto ResumeExecution;
2703 }
2704 if (rc == VINF_SUCCESS)
2705 goto ResumeExecution;
2706 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2707 break;
2708 }
2709
2710 case X86_XCPT_GP: /* General protection failure exception.*/
2711 {
2712 uint32_t cbOp;
2713 uint32_t cbSize;
2714 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2715
2716 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2717#ifdef VBOX_STRICT
2718 if (!CPUMIsGuestInRealModeEx(pCtx))
2719 {
2720 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2721 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2722 AssertRC(rc);
2723 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2724 goto ResumeExecution;
2725 }
2726#endif
2727 Assert(CPUMIsGuestInRealModeEx(pCtx));
2728
2729 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2730
2731 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2732 if (RT_SUCCESS(rc))
2733 {
2734 bool fUpdateRIP = true;
2735
2736 Assert(cbOp == pDis->opsize);
2737 switch (pDis->pCurInstr->opcode)
2738 {
2739 case OP_CLI:
2740 pCtx->eflags.Bits.u1IF = 0;
2741 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2742 break;
2743
2744 case OP_STI:
2745 pCtx->eflags.Bits.u1IF = 1;
2746 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2747 break;
2748
2749 case OP_HLT:
2750 fUpdateRIP = false;
2751 rc = VINF_EM_HALT;
2752 pCtx->rip += pDis->opsize;
2753 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2754 break;
2755
2756 case OP_POPF:
2757 {
2758 RTGCPTR GCPtrStack;
2759 uint32_t cbParm;
2760 uint32_t uMask;
2761 X86EFLAGS eflags;
2762
2763 if (pDis->prefix & PREFIX_OPSIZE)
2764 {
2765 cbParm = 4;
2766 uMask = 0xffffffff;
2767 }
2768 else
2769 {
2770 cbParm = 2;
2771 uMask = 0xffff;
2772 }
2773
2774 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2775 if (RT_FAILURE(rc))
2776 {
2777 rc = VERR_EM_INTERPRETER;
2778 break;
2779 }
2780 eflags.u = 0;
2781 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2782 if (RT_FAILURE(rc))
2783 {
2784 rc = VERR_EM_INTERPRETER;
2785 break;
2786 }
2787 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2788 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
2789 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
2790 pCtx->eflags.Bits.u1RF = 0;
2791 pCtx->esp += cbParm;
2792 pCtx->esp &= uMask;
2793
2794 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2795 break;
2796 }
2797
2798 case OP_PUSHF:
2799 {
2800 RTGCPTR GCPtrStack;
2801 uint32_t cbParm;
2802 uint32_t uMask;
2803 X86EFLAGS eflags;
2804
2805 if (pDis->prefix & PREFIX_OPSIZE)
2806 {
2807 cbParm = 4;
2808 uMask = 0xffffffff;
2809 }
2810 else
2811 {
2812 cbParm = 2;
2813 uMask = 0xffff;
2814 }
2815
2816 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2817 if (RT_FAILURE(rc))
2818 {
2819 rc = VERR_EM_INTERPRETER;
2820 break;
2821 }
2822 eflags = pCtx->eflags;
2823 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2824 eflags.Bits.u1RF = 0;
2825 eflags.Bits.u1VM = 0;
2826
2827 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2828 if (RT_FAILURE(rc))
2829 {
2830 rc = VERR_EM_INTERPRETER;
2831 break;
2832 }
2833 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2834 pCtx->esp -= cbParm;
2835 pCtx->esp &= uMask;
2836 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2837 break;
2838 }
2839
2840 case OP_IRET:
2841 {
2842 RTGCPTR GCPtrStack;
2843 uint32_t uMask = 0xffff;
2844 uint16_t aIretFrame[3];
2845
2846 if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
2847 {
2848 rc = VERR_EM_INTERPRETER;
2849 break;
2850 }
2851
2852 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2853 if (RT_FAILURE(rc))
2854 {
2855 rc = VERR_EM_INTERPRETER;
2856 break;
2857 }
2858 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2859 if (RT_FAILURE(rc))
2860 {
2861 rc = VERR_EM_INTERPRETER;
2862 break;
2863 }
2864 pCtx->ip = aIretFrame[0];
2865 pCtx->cs = aIretFrame[1];
2866 pCtx->csHid.u64Base = pCtx->cs << 4;
2867 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2868 pCtx->sp += sizeof(aIretFrame);
2869
2870 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2871 fUpdateRIP = false;
2872 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2873 break;
2874 }
2875
2876 case OP_INT:
2877 {
2878 RTGCUINTPTR intInfo;
2879
2880 LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
2881 intInfo = pDis->param1.parval & 0xff;
2882 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2883 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2884
2885 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2886 AssertRC(rc);
2887 fUpdateRIP = false;
2888 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2889 break;
2890 }
2891
2892 case OP_INTO:
2893 {
2894 if (pCtx->eflags.Bits.u1OF)
2895 {
2896 RTGCUINTPTR intInfo;
2897
2898 LogFlow(("Realmode: INTO\n"));
2899 intInfo = X86_XCPT_OF;
2900 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2901 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2902
2903 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2904 AssertRC(rc);
2905 fUpdateRIP = false;
2906 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2907 }
2908 break;
2909 }
2910
2911 case OP_INT3:
2912 {
2913 RTGCUINTPTR intInfo;
2914
2915 LogFlow(("Realmode: INT 3\n"));
2916 intInfo = 3;
2917 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2918 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2919
2920 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2921 AssertRC(rc);
2922 fUpdateRIP = false;
2923 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2924 break;
2925 }
2926
2927 default:
2928 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
2929 break;
2930 }
2931
2932 if (rc == VINF_SUCCESS)
2933 {
2934 if (fUpdateRIP)
2935 pCtx->rip += cbOp; /* Move on to the next instruction. */
2936
2937 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2938 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2939
2940 /* Only resume if successful. */
2941 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2942 goto ResumeExecution;
2943 }
2944 }
2945 else
2946 rc = VERR_EM_INTERPRETER;
2947
2948 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2949 break;
2950 }
2951
2952#ifdef VBOX_STRICT
2953 case X86_XCPT_DE: /* Divide error. */
2954 case X86_XCPT_UD: /* Unknown opcode exception. */
2955 case X86_XCPT_SS: /* Stack segment exception. */
2956 case X86_XCPT_NP: /* Segment not present exception. */
2957 {
2958 switch(vector)
2959 {
2960 case X86_XCPT_DE:
2961 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2962 break;
2963 case X86_XCPT_UD:
2964 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2965 break;
2966 case X86_XCPT_SS:
2967 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2968 break;
2969 case X86_XCPT_NP:
2970 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2971 break;
2972 }
2973
2974 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2975 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2976 AssertRC(rc);
2977
2978 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2979 goto ResumeExecution;
2980 }
2981#endif
2982 default:
2983#ifdef HWACCM_VMX_EMULATE_REALMODE
2984 if (CPUMIsGuestInRealModeEx(pCtx))
2985 {
2986 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2987 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2988 AssertRC(rc);
2989
2990 /* Go back to ring 3 in case of a triple fault. */
2991 if ( vector == X86_XCPT_DF
2992 && rc == VINF_EM_RESET)
2993 break;
2994
2995 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2996 goto ResumeExecution;
2997 }
2998#endif
2999 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
3000 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
3001 break;
3002 } /* switch (vector) */
3003
3004 break;
3005
3006 default:
3007 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
3008 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
3009 break;
3010 }
3011
3012 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3013 break;
3014 }
3015
3016 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
3017 {
3018 RTGCPHYS GCPhys;
3019
3020 Assert(pVM->hwaccm.s.fNestedPaging);
3021
3022 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3023 AssertRC(rc);
3024 Assert(((exitQualification >> 7) & 3) != 2);
3025
3026 /* Determine the kind of violation. */
3027 errCode = 0;
3028 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
3029 errCode |= X86_TRAP_PF_ID;
3030
3031 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
3032 errCode |= X86_TRAP_PF_RW;
3033
3034 /* If the page is present, then it's a page level protection fault. */
3035 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
3036 {
3037 errCode |= X86_TRAP_PF_P;
3038 }
3039 else {
3040 /* Shortcut for APIC TPR reads and writes. */
3041 if ( (GCPhys & 0xfff) == 0x080
3042 && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
3043 && fSetupTPRCaching
3044 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
3045 {
3046 RTGCPHYS GCPhysApicBase;
3047 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
3048 GCPhysApicBase &= PAGE_BASE_GC_MASK;
3049 if (GCPhys == GCPhysApicBase + 0x80)
3050 {
3051 Log(("Enable VT-x virtual APIC access filtering\n"));
3052 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
3053 AssertRC(rc);
3054 }
3055 }
3056 }
3057 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
3058
3059 /* GCPhys contains the guest physical address of the page fault. */
3060 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
3061 TRPMSetErrorCode(pVCpu, errCode);
3062 TRPMSetFaultAddress(pVCpu, GCPhys);
3063
3064 /* Handle the pagefault trap for the nested shadow table. */
3065 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
3066 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
3067 if (rc == VINF_SUCCESS)
3068 { /* We've successfully synced our shadow pages, so let's just continue execution. */
3069 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
3070 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
3071
3072 TRPMResetTrap(pVCpu);
3073
3074 goto ResumeExecution;
3075 }
3076
3077#ifdef VBOX_STRICT
3078 if (rc != VINF_EM_RAW_EMULATE_INSTR)
3079 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
3080#endif
3081 /* Need to go back to the recompiler to emulate the instruction. */
3082 TRPMResetTrap(pVCpu);
3083 break;
3084 }
3085
3086 case VMX_EXIT_EPT_MISCONFIG:
3087 {
3088 RTGCPHYS GCPhys;
3089
3090 Assert(pVM->hwaccm.s.fNestedPaging);
3091
3092 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3093 AssertRC(rc);
3094
3095 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
3096 break;
3097 }
3098
3099 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3100 /* Clear VM-exit on IF=1 change. */
3101 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
3102 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
3103 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3104 AssertRC(rc);
3105 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
3106 goto ResumeExecution; /* we check for pending guest interrupts there */
3107
3108 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
3109 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
3110 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
3111 /* Skip instruction and continue directly. */
3112 pCtx->rip += cbInstr;
3113 /* Continue execution.*/
3114 goto ResumeExecution;
3115
3116 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3117 {
3118 Log2(("VMX: Cpuid %x\n", pCtx->eax));
3119 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
3120 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3121 if (rc == VINF_SUCCESS)
3122 {
3123 /* Update EIP and continue execution. */
3124 Assert(cbInstr == 2);
3125 pCtx->rip += cbInstr;
3126 goto ResumeExecution;
3127 }
3128 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
3129 rc = VINF_EM_RAW_EMULATE_INSTR;
3130 break;
3131 }
3132
3133 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3134 {
3135 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
3136 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
3137 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3138 if (rc == VINF_SUCCESS)
3139 {
3140 /* Update EIP and continue execution. */
3141 Assert(cbInstr == 2);
3142 pCtx->rip += cbInstr;
3143 goto ResumeExecution;
3144 }
3145 rc = VINF_EM_RAW_EMULATE_INSTR;
3146 break;
3147 }
3148
3149 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3150 {
3151 Log2(("VMX: Rdtsc\n"));
3152 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
3153 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3154 if (rc == VINF_SUCCESS)
3155 {
3156 /* Update EIP and continue execution. */
3157 Assert(cbInstr == 2);
3158 pCtx->rip += cbInstr;
3159 goto ResumeExecution;
3160 }
3161 rc = VINF_EM_RAW_EMULATE_INSTR;
3162 break;
3163 }
3164
3165 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3166 {
3167 Log2(("VMX: invlpg\n"));
3168 Assert(!pVM->hwaccm.s.fNestedPaging);
3169
3170 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
3171 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
3172 if (rc == VINF_SUCCESS)
3173 {
3174 /* Update EIP and continue execution. */
3175 pCtx->rip += cbInstr;
3176 goto ResumeExecution;
3177 }
3178 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
3179 break;
3180 }
3181
3182 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3183 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3184 {
3185 uint32_t cbSize;
3186
3187 STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
3188
3189 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3190 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3191 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3192 if (rc == VINF_SUCCESS)
3193 {
3194 /* EIP has been updated already. */
3195
3196 /* Only resume if successful. */
3197 goto ResumeExecution;
3198 }
3199 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
3200 break;
3201 }
3202
3203 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3204 {
3205 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3206
3207 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3208 {
3209 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3210 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3211 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3212 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3213 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3214 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3215
3216 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3217 {
3218 case 0:
3219 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3220 break;
3221 case 2:
3222 break;
3223 case 3:
3224 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3225 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3226 break;
3227 case 4:
3228 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3229 break;
3230 case 8:
3231 /* CR8 contains the APIC TPR */
3232 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3233 break;
3234
3235 default:
3236 AssertFailed();
3237 break;
3238 }
3239 /* Check if a sync operation is pending. */
3240 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3241 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3242 {
3243 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3244 AssertRC(rc);
3245 }
3246 break;
3247
3248 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3249 Log2(("VMX: mov x, crx\n"));
3250 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3251
3252 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3253
3254 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3255 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3256
3257 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3258 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3259 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3260 break;
3261
3262 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3263 Log2(("VMX: clts\n"));
3264 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3265 rc = EMInterpretCLTS(pVM, pVCpu);
3266 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3267 break;
3268
3269 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3270 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3271 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3272 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3273 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3274 break;
3275 }
3276
3277 /* Update EIP if no error occurred. */
3278 if (RT_SUCCESS(rc))
3279 pCtx->rip += cbInstr;
3280
3281 if (rc == VINF_SUCCESS)
3282 {
3283 /* Only resume if successful. */
3284 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3285 goto ResumeExecution;
3286 }
3287 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3288 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3289 break;
3290 }
3291
3292 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3293 {
3294 if ( !DBGFIsStepping(pVCpu)
3295 && !CPUMIsHyperDebugStateActive(pVCpu))
3296 {
3297 /* Disable drx move intercepts. */
3298 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3299 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3300 AssertRC(rc);
3301
3302 /* Save the host and load the guest debug state. */
3303 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3304 AssertRC(rc);
3305
3306#ifdef VBOX_WITH_STATISTICS
3307 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3308 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3309 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3310 else
3311 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3312#endif
3313
3314 goto ResumeExecution;
3315 }
3316
3317 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3318 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3319 {
3320 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3321 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3322 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3323 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3324 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3325 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3326 Log2(("DR7=%08x\n", pCtx->dr[7]));
3327 }
3328 else
3329 {
3330 Log2(("VMX: mov x, drx\n"));
3331 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3332 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3333 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3334 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3335 }
3336 /* Update EIP if no error occurred. */
3337 if (RT_SUCCESS(rc))
3338 pCtx->rip += cbInstr;
3339
3340 if (rc == VINF_SUCCESS)
3341 {
3342 /* Only resume if successful. */
3343 goto ResumeExecution;
3344 }
3345 Assert(rc == VERR_EM_INTERPRETER);
3346 break;
3347 }
3348
3349 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3350 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3351 {
3352 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3353 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3354 uint32_t uPort;
3355 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3356
3357 /** @todo necessary to make the distinction? */
3358 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3359 {
3360 uPort = pCtx->edx & 0xffff;
3361 }
3362 else
3363 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3364
3365 /* paranoia */
3366 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3367 {
3368 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3369 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3370 break;
3371 }
3372
3373 uint32_t cbSize = g_aIOSize[uIOWidth];
3374
3375 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3376 {
3377 /* ins/outs */
3378 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
3379
3380 /* Disassemble manually to deal with segment prefixes. */
3381 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3382 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3383 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
3384 if (rc == VINF_SUCCESS)
3385 {
3386 if (fIOWrite)
3387 {
3388 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3389 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3390 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3391 }
3392 else
3393 {
3394 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3395 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3396 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3397 }
3398 }
3399 else
3400 rc = VINF_EM_RAW_EMULATE_INSTR;
3401 }
3402 else
3403 {
3404 /* normal in/out */
3405 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3406
3407 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3408
3409 if (fIOWrite)
3410 {
3411 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3412 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3413 if (rc == VINF_IOM_HC_IOPORT_WRITE)
3414 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pCtx->rip + cbInstr, uPort, uAndVal, cbSize);
3415 }
3416 else
3417 {
3418 uint32_t u32Val = 0;
3419
3420 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3421 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3422 if (IOM_SUCCESS(rc))
3423 {
3424 /* Write back to the EAX register. */
3425 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3426 }
3427 else
3428 if (rc == VINF_IOM_HC_IOPORT_READ)
3429 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pCtx->rip + cbInstr, uPort, uAndVal, cbSize);
3430 }
3431 }
3432 /*
3433 * Handled the I/O return codes.
3434 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3435 */
3436 if (IOM_SUCCESS(rc))
3437 {
3438 /* Update EIP and continue execution. */
3439 pCtx->rip += cbInstr;
3440 if (RT_LIKELY(rc == VINF_SUCCESS))
3441 {
3442 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3443 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3444 {
3445 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3446 for (unsigned i=0;i<4;i++)
3447 {
3448 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3449
3450 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3451 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3452 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3453 {
3454 uint64_t uDR6;
3455
3456 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3457
3458 uDR6 = ASMGetDR6();
3459
3460 /* Clear all breakpoint status flags and set the one we just hit. */
3461 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3462 uDR6 |= (uint64_t)RT_BIT(i);
3463
3464 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3465 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3466 * the contents have been read.
3467 */
3468 ASMSetDR6(uDR6);
3469
3470 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3471 pCtx->dr[7] &= ~X86_DR7_GD;
3472
3473 /* Paranoia. */
3474 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3475 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3476 pCtx->dr[7] |= 0x400; /* must be one */
3477
3478 /* Resync DR7 */
3479 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3480 AssertRC(rc);
3481
3482 /* Construct inject info. */
3483 intInfo = X86_XCPT_DB;
3484 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3485 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3486
3487 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3488 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3489 AssertRC(rc);
3490
3491 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3492 goto ResumeExecution;
3493 }
3494 }
3495 }
3496
3497 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3498 goto ResumeExecution;
3499 }
3500 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3501 break;
3502 }
3503
3504#ifdef VBOX_STRICT
3505 if (rc == VINF_IOM_HC_IOPORT_READ)
3506 Assert(!fIOWrite);
3507 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3508 Assert(fIOWrite);
3509 else
3510 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3511#endif
3512 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3513 break;
3514 }
3515
3516 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3517 LogFlow(("VMX_EXIT_TPR\n"));
3518 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3519 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3520 goto ResumeExecution;
3521
3522 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3523 {
3524 LogFlow(("VMX_EXIT_APIC_ACCESS\n"));
3525 unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
3526
3527 switch(uAccessType)
3528 {
3529 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
3530 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
3531 {
3532 RTGCPHYS GCPhys;
3533 PDMApicGetBase(pVM, &GCPhys);
3534 GCPhys &= PAGE_BASE_GC_MASK;
3535 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
3536
3537 LogFlow(("Apic access at %RGp\n", GCPhys));
3538 rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
3539 if (rc == VINF_SUCCESS)
3540 {
3541 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3542 goto ResumeExecution; /* rip already updated */
3543 }
3544 break;
3545 }
3546
3547 default:
3548 rc = VINF_EM_RAW_EMULATE_INSTR;
3549 break;
3550 }
3551 break;
3552 }
3553
3554 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3555 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3556 goto ResumeExecution;
3557
3558 default:
3559 /* The rest is handled after syncing the entire CPU state. */
3560 break;
3561 }
3562
3563 /* Note: the guest state isn't entirely synced back at this stage. */
3564
3565 /* Investigate why there was a VM-exit. (part 2) */
3566 switch (exitReason)
3567 {
3568 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3569 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3570 case VMX_EXIT_EPT_VIOLATION:
3571 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3572 /* Already handled above. */
3573 break;
3574
3575 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3576 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3577 break;
3578
3579 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3580 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3581 rc = VINF_EM_RAW_INTERRUPT;
3582 AssertFailed(); /* Can't happen. Yet. */
3583 break;
3584
3585 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3586 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3587 rc = VINF_EM_RAW_INTERRUPT;
3588 AssertFailed(); /* Can't happen afaik. */
3589 break;
3590
3591 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3592 rc = VERR_EM_INTERPRETER;
3593 break;
3594
3595 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3596 /** Check if external interrupts are pending; if so, don't switch back. */
3597 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
3598 pCtx->rip++; /* skip hlt */
3599 if ( pCtx->eflags.Bits.u1IF
3600 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3601 goto ResumeExecution;
3602
3603 rc = VINF_EM_HALT;
3604 break;
3605
3606 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3607 Log2(("VMX: mwait\n"));
3608 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
3609 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3610 if ( rc == VINF_EM_HALT
3611 || rc == VINF_SUCCESS)
3612 {
3613 /* Update EIP and continue execution. */
3614 pCtx->rip += cbInstr;
3615
3616 /** Check if external interrupts are pending; if so, don't switch back. */
3617 if ( rc == VINF_SUCCESS
3618 || ( rc == VINF_EM_HALT
3619 && pCtx->eflags.Bits.u1IF
3620 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3621 )
3622 goto ResumeExecution;
3623 }
3624 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
3625 break;
3626
3627 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3628 AssertFailed(); /* can't happen. */
3629 rc = VERR_EM_INTERPRETER;
3630 break;
3631
3632 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3633 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3634 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3635 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3636 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3637 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3638 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3639 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3640 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3641 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3642 /** @todo inject #UD immediately */
3643 rc = VERR_EM_INTERPRETER;
3644 break;
3645
3646 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3647 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3648 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3649 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3650 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3651 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3652 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3653 /* already handled above */
3654 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3655 || rc == VINF_EM_RAW_INTERRUPT
3656 || rc == VERR_EM_INTERPRETER
3657 || rc == VINF_EM_RAW_EMULATE_INSTR
3658 || rc == VINF_PGM_SYNC_CR3
3659 || rc == VINF_IOM_HC_IOPORT_READ
3660 || rc == VINF_IOM_HC_IOPORT_WRITE
3661 || rc == VINF_EM_RAW_GUEST_TRAP
3662 || rc == VINF_TRPM_XCPT_DISPATCHED
3663 || rc == VINF_EM_RESCHEDULE_REM,
3664 ("rc = %d\n", rc));
3665 break;
3666
3667 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3668 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3669 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3670 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3671 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3672 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3673 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3674 rc = VERR_EM_INTERPRETER;
3675 break;
3676
3677 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3678 Assert(rc == VINF_EM_RAW_INTERRUPT);
3679 break;
3680
3681 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3682 {
3683#ifdef VBOX_STRICT
3684 RTCCUINTREG val = 0;
3685
3686 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3687
3688 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3689 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3690
3691 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3692 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3693
3694 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3695 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3696
3697 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3698 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3699
3700 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3701 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3702
3703 VMX_LOG_SELREG(CS, "CS");
3704 VMX_LOG_SELREG(DS, "DS");
3705 VMX_LOG_SELREG(ES, "ES");
3706 VMX_LOG_SELREG(FS, "FS");
3707 VMX_LOG_SELREG(GS, "GS");
3708 VMX_LOG_SELREG(SS, "SS");
3709 VMX_LOG_SELREG(TR, "TR");
3710 VMX_LOG_SELREG(LDTR, "LDTR");
3711
3712 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3713 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3714 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3715 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3716#endif /* VBOX_STRICT */
3717 rc = VERR_VMX_INVALID_GUEST_STATE;
3718 break;
3719 }
3720
3721 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3722 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3723 default:
3724 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3725 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3726 break;
3727
3728 }
3729end:
3730
3731 /* Signal changes for the recompiler. */
3732 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3733
3734 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3735 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3736 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3737 {
3738 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3739 /* On the next entry we'll only sync the host context. */
3740 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3741 }
3742 else
3743 {
3744 /* On the next entry we'll sync everything. */
3745 /** @todo we can do better than this */
3746 /* Not in the VINF_PGM_CHANGE_MODE though! */
3747 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3748 }
3749
3750 /* translate into a less severe return code */
3751 if (rc == VERR_EM_INTERPRETER)
3752 rc = VINF_EM_RAW_EMULATE_INSTR;
3753 else
3754 /* Try to extract more information about what might have gone wrong here. */
3755 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3756 {
3757 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3758 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3759 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3760 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3761 }
3762
3763 /* Just set the correct state here instead of trying to catch every goto above. */
3764 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
3765
3766#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
3767 /* Restore interrupts if we exitted after disabling them. */
3768 if (uOldEFlags != ~(RTCCUINTREG)0)
3769 ASMSetFlags(uOldEFlags);
3770#endif
3771
3772 STAM_STATS({
3773 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3774 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3775 });
3776 Log2(("X"));
3777 return rc;
3778}
3779
3780
3781/**
3782 * Enters the VT-x session
3783 *
3784 * @returns VBox status code.
3785 * @param pVM The VM to operate on.
3786 * @param pVCpu The VMCPU to operate on.
3787 * @param pCpu CPU info struct
3788 */
3789VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3790{
3791 Assert(pVM->hwaccm.s.vmx.fSupported);
3792
3793 unsigned cr4 = ASMGetCR4();
3794 if (!(cr4 & X86_CR4_VMXE))
3795 {
3796 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3797 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3798 }
3799
3800 /* Activate the VM Control Structure. */
3801 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3802 if (RT_FAILURE(rc))
3803 return rc;
3804
3805 pVCpu->hwaccm.s.fResumeVM = false;
3806 return VINF_SUCCESS;
3807}
3808
3809
3810/**
3811 * Leaves the VT-x session
3812 *
3813 * @returns VBox status code.
3814 * @param pVM The VM to operate on.
3815 * @param pVCpu The VMCPU to operate on.
3816 * @param pCtx CPU context
3817 */
3818VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3819{
3820 Assert(pVM->hwaccm.s.vmx.fSupported);
3821
3822#ifdef DEBUG
3823 if (CPUMIsHyperDebugStateActive(pVCpu))
3824 {
3825 CPUMR0LoadHostDebugState(pVM, pVCpu);
3826 }
3827 else
3828#endif
3829 /* Save the guest debug state if necessary. */
3830 if (CPUMIsGuestDebugStateActive(pVCpu))
3831 {
3832 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3833
3834 /* Enable drx move intercepts again. */
3835 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3836 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3837 AssertRC(rc);
3838
3839 /* Resync the debug registers the next time. */
3840 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3841 }
3842 else
3843 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3844
3845 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3846 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3847 AssertRC(rc);
3848
3849 return VINF_SUCCESS;
3850}
3851
3852/**
3853 * Flush the TLB (EPT)
3854 *
3855 * @returns VBox status code.
3856 * @param pVM The VM to operate on.
3857 * @param pVCpu The VM CPU to operate on.
3858 * @param enmFlush Type of flush
3859 * @param GCPhys Physical address of the page to flush
3860 */
3861static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3862{
3863 uint64_t descriptor[2];
3864
3865 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3866 Assert(pVM->hwaccm.s.fNestedPaging);
3867 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3868 descriptor[1] = GCPhys;
3869 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3870 AssertRC(rc);
3871}
3872
3873#ifdef HWACCM_VTX_WITH_VPID
3874/**
3875 * Flush the TLB (EPT)
3876 *
3877 * @returns VBox status code.
3878 * @param pVM The VM to operate on.
3879 * @param pVCpu The VM CPU to operate on.
3880 * @param enmFlush Type of flush
3881 * @param GCPtr Virtual address of the page to flush
3882 */
3883static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3884{
3885#if HC_ARCH_BITS == 32
3886 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3887 if ( CPUMIsGuestInLongMode(pVCpu)
3888 && !VMX_IS_64BIT_HOST_MODE())
3889 {
3890 pVCpu->hwaccm.s.fForceTLBFlush = true;
3891 }
3892 else
3893#endif
3894 {
3895 uint64_t descriptor[2];
3896
3897 Assert(pVM->hwaccm.s.vmx.fVPID);
3898 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3899 descriptor[1] = GCPtr;
3900 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3901 AssertRC(rc);
3902 }
3903}
3904#endif /* HWACCM_VTX_WITH_VPID */
3905
3906/**
3907 * Invalidates a guest page
3908 *
3909 * @returns VBox status code.
3910 * @param pVM The VM to operate on.
3911 * @param pVCpu The VM CPU to operate on.
3912 * @param GCVirt Page to invalidate
3913 */
3914VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3915{
3916 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3917
3918 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3919
3920 /* Only relevant if we want to use VPID.
3921 * In the nested paging case we still see such calls, but
3922 * can safely ignore them. (e.g. after cr3 updates)
3923 */
3924#ifdef HWACCM_VTX_WITH_VPID
3925 /* Skip it if a TLB flush is already pending. */
3926 if ( !fFlushPending
3927 && pVM->hwaccm.s.vmx.fVPID)
3928 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3929#endif /* HWACCM_VTX_WITH_VPID */
3930
3931 return VINF_SUCCESS;
3932}
3933
3934/**
3935 * Invalidates a guest page by physical address
3936 *
3937 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3938 *
3939 * @returns VBox status code.
3940 * @param pVM The VM to operate on.
3941 * @param pVCpu The VM CPU to operate on.
3942 * @param GCPhys Page to invalidate
3943 */
3944VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3945{
3946 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3947
3948 Assert(pVM->hwaccm.s.fNestedPaging);
3949
3950 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3951
3952 /* Skip it if a TLB flush is already pending. */
3953 if (!fFlushPending)
3954 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3955
3956 return VINF_SUCCESS;
3957}
3958
3959/**
3960 * Report world switch error and dump some useful debug info
3961 *
3962 * @param pVM The VM to operate on.
3963 * @param pVCpu The VMCPU to operate on.
3964 * @param rc Return code
3965 * @param pCtx Current CPU context (not updated)
3966 */
3967static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3968{
3969 switch (rc)
3970 {
3971 case VERR_VMX_INVALID_VMXON_PTR:
3972 AssertFailed();
3973 break;
3974
3975 case VERR_VMX_UNABLE_TO_START_VM:
3976 case VERR_VMX_UNABLE_TO_RESUME_VM:
3977 {
3978 int rc;
3979 RTCCUINTREG exitReason, instrError;
3980
3981 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3982 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3983 AssertRC(rc);
3984 if (rc == VINF_SUCCESS)
3985 {
3986 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3987 Log(("Current stack %08x\n", &rc));
3988
3989 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3990 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3991
3992#ifdef VBOX_STRICT
3993 RTGDTR gdtr;
3994 PX86DESCHC pDesc;
3995 RTCCUINTREG val;
3996
3997 ASMGetGDTR(&gdtr);
3998
3999 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
4000 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
4001 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
4002 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
4003 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
4004 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
4005 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
4006 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
4007 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
4008 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
4009
4010 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
4011 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
4012
4013 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
4014 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
4015
4016 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
4017 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
4018
4019 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
4020 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
4021
4022 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
4023 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
4024
4025 if (val < gdtr.cbGdt)
4026 {
4027 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4028 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
4029 }
4030
4031 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
4032 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
4033 if (val < gdtr.cbGdt)
4034 {
4035 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4036 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
4037 }
4038
4039 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
4040 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
4041 if (val < gdtr.cbGdt)
4042 {
4043 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4044 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
4045 }
4046
4047 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
4048 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
4049 if (val < gdtr.cbGdt)
4050 {
4051 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4052 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
4053 }
4054
4055 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
4056 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
4057 if (val < gdtr.cbGdt)
4058 {
4059 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4060 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
4061 }
4062
4063 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
4064 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
4065 if (val < gdtr.cbGdt)
4066 {
4067 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4068 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
4069 }
4070
4071 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
4072 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
4073 if (val < gdtr.cbGdt)
4074 {
4075 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4076 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
4077 }
4078
4079 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
4080 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
4081
4082 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
4083 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
4084 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
4085 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
4086
4087 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
4088 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
4089
4090 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
4091 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
4092
4093 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
4094 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
4095
4096 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
4097 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
4098 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
4099 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
4100
4101# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4102 if (VMX_IS_64BIT_HOST_MODE())
4103 {
4104 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
4105 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
4106 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
4107 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
4108 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
4109 }
4110# endif
4111#endif /* VBOX_STRICT */
4112 }
4113 break;
4114 }
4115
4116 default:
4117 /* impossible */
4118 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
4119 break;
4120 }
4121}
4122
4123#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4124/**
4125 * Prepares for and executes VMLAUNCH (64 bits guest mode)
4126 *
4127 * @returns VBox status code
4128 * @param fResume vmlauch/vmresume
4129 * @param pCtx Guest context
4130 * @param pCache VMCS cache
4131 * @param pVM The VM to operate on.
4132 * @param pVCpu The VMCPU to operate on.
4133 */
4134DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
4135{
4136 uint32_t aParam[6];
4137 PHWACCM_CPUINFO pCpu;
4138 RTHCPHYS pPageCpuPhys;
4139 int rc;
4140
4141 pCpu = HWACCMR0GetCurrentCpu();
4142 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4143
4144#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4145 pCache->uPos = 1;
4146 pCache->interPD = PGMGetInterPaeCR3(pVM);
4147 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
4148#endif
4149
4150#ifdef DEBUG
4151 pCache->TestIn.pPageCpuPhys = 0;
4152 pCache->TestIn.pVMCSPhys = 0;
4153 pCache->TestIn.pCache = 0;
4154 pCache->TestOut.pVMCSPhys = 0;
4155 pCache->TestOut.pCache = 0;
4156 pCache->TestOut.pCtx = 0;
4157 pCache->TestOut.eflags = 0;
4158#endif
4159
4160 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
4161 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
4162 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
4163 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
4164 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
4165 aParam[5] = 0;
4166
4167#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4168 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
4169 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
4170#endif
4171 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
4172
4173#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4174 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
4175 Assert(pCtx->dr[4] == 10);
4176 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
4177#endif
4178
4179#ifdef DEBUG
4180 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
4181 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
4182 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
4183 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
4184 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
4185 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
4186 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
4187#endif
4188 return rc;
4189}
4190
4191/**
4192 * Executes the specified handler in 64 mode
4193 *
4194 * @returns VBox status code.
4195 * @param pVM The VM to operate on.
4196 * @param pVCpu The VMCPU to operate on.
4197 * @param pCtx Guest context
4198 * @param pfnHandler RC handler
4199 * @param cbParam Number of parameters
4200 * @param paParam Array of 32 bits parameters
4201 */
4202VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
4203{
4204 int rc, rc2;
4205 PHWACCM_CPUINFO pCpu;
4206 RTHCPHYS pPageCpuPhys;
4207
4208 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
4209 AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
4210 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
4211 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
4212 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
4213
4214#ifdef VBOX_STRICT
4215 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
4216 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
4217
4218 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
4219 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
4220#endif
4221
4222 pCpu = HWACCMR0GetCurrentCpu();
4223 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4224
4225 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4226 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4227
4228 /* Leave VMX Root Mode. */
4229 VMXDisable();
4230
4231 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4232
4233 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
4234 CPUMSetHyperEIP(pVCpu, pfnHandler);
4235 for (int i=(int)cbParam-1;i>=0;i--)
4236 CPUMPushHyper(pVCpu, paParam[i]);
4237
4238 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4239 /* Call switcher. */
4240 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
4241 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4242
4243 /* Make sure the VMX instructions don't cause #UD faults. */
4244 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
4245
4246 /* Enter VMX Root Mode */
4247 rc2 = VMXEnable(pPageCpuPhys);
4248 if (RT_FAILURE(rc2))
4249 {
4250 if (pVM)
4251 VMXR0CheckError(pVM, pVCpu, rc2);
4252 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4253 return VERR_VMX_VMXON_FAILED;
4254 }
4255
4256 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4257 AssertRCReturn(rc2, rc2);
4258 Assert(!(ASMGetFlags() & X86_EFL_IF));
4259 return rc;
4260}
4261
4262#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4263
4264
4265#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4266/**
4267 * Executes VMWRITE
4268 *
4269 * @returns VBox status code
4270 * @param pVCpu The VMCPU to operate on.
4271 * @param idxField VMCS index
4272 * @param u64Val 16, 32 or 64 bits value
4273 */
4274VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4275{
4276 int rc;
4277
4278 switch (idxField)
4279 {
4280 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4281 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4282 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4283 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4284 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4285 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4286 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4287 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4288 case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
4289 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4290 case VMX_VMCS_GUEST_PDPTR0_FULL:
4291 case VMX_VMCS_GUEST_PDPTR1_FULL:
4292 case VMX_VMCS_GUEST_PDPTR2_FULL:
4293 case VMX_VMCS_GUEST_PDPTR3_FULL:
4294 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4295 case VMX_VMCS_GUEST_EFER_FULL:
4296 case VMX_VMCS_CTRL_EPTP_FULL:
4297 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4298 rc = VMXWriteVMCS32(idxField, u64Val);
4299 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4300 AssertRC(rc);
4301 return rc;
4302
4303 case VMX_VMCS64_GUEST_LDTR_BASE:
4304 case VMX_VMCS64_GUEST_TR_BASE:
4305 case VMX_VMCS64_GUEST_GDTR_BASE:
4306 case VMX_VMCS64_GUEST_IDTR_BASE:
4307 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4308 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4309 case VMX_VMCS64_GUEST_CR0:
4310 case VMX_VMCS64_GUEST_CR4:
4311 case VMX_VMCS64_GUEST_CR3:
4312 case VMX_VMCS64_GUEST_DR7:
4313 case VMX_VMCS64_GUEST_RIP:
4314 case VMX_VMCS64_GUEST_RSP:
4315 case VMX_VMCS64_GUEST_CS_BASE:
4316 case VMX_VMCS64_GUEST_DS_BASE:
4317 case VMX_VMCS64_GUEST_ES_BASE:
4318 case VMX_VMCS64_GUEST_FS_BASE:
4319 case VMX_VMCS64_GUEST_GS_BASE:
4320 case VMX_VMCS64_GUEST_SS_BASE:
4321 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4322 if (u64Val >> 32ULL)
4323 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4324 else
4325 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4326
4327 return rc;
4328
4329 default:
4330 AssertMsgFailed(("Unexpected field %x\n", idxField));
4331 return VERR_INVALID_PARAMETER;
4332 }
4333}
4334
4335/**
4336 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4337 *
4338 * @param pVCpu The VMCPU to operate on.
4339 * @param idxField VMCS field
4340 * @param u64Val Value
4341 */
4342VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4343{
4344 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4345
4346 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4347
4348 /* Make sure there are no duplicates. */
4349 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4350 {
4351 if (pCache->Write.aField[i] == idxField)
4352 {
4353 pCache->Write.aFieldVal[i] = u64Val;
4354 return VINF_SUCCESS;
4355 }
4356 }
4357
4358 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4359 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4360 pCache->Write.cValidEntries++;
4361 return VINF_SUCCESS;
4362}
4363
4364#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4365
4366#ifdef VBOX_STRICT
4367static bool vmxR0IsValidReadField(uint32_t idxField)
4368{
4369 switch(idxField)
4370 {
4371 case VMX_VMCS64_GUEST_RIP:
4372 case VMX_VMCS64_GUEST_RSP:
4373 case VMX_VMCS_GUEST_RFLAGS:
4374 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4375 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4376 case VMX_VMCS64_GUEST_CR0:
4377 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4378 case VMX_VMCS64_GUEST_CR4:
4379 case VMX_VMCS64_GUEST_DR7:
4380 case VMX_VMCS32_GUEST_SYSENTER_CS:
4381 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4382 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4383 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4384 case VMX_VMCS64_GUEST_GDTR_BASE:
4385 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4386 case VMX_VMCS64_GUEST_IDTR_BASE:
4387 case VMX_VMCS16_GUEST_FIELD_CS:
4388 case VMX_VMCS32_GUEST_CS_LIMIT:
4389 case VMX_VMCS64_GUEST_CS_BASE:
4390 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4391 case VMX_VMCS16_GUEST_FIELD_DS:
4392 case VMX_VMCS32_GUEST_DS_LIMIT:
4393 case VMX_VMCS64_GUEST_DS_BASE:
4394 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4395 case VMX_VMCS16_GUEST_FIELD_ES:
4396 case VMX_VMCS32_GUEST_ES_LIMIT:
4397 case VMX_VMCS64_GUEST_ES_BASE:
4398 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4399 case VMX_VMCS16_GUEST_FIELD_FS:
4400 case VMX_VMCS32_GUEST_FS_LIMIT:
4401 case VMX_VMCS64_GUEST_FS_BASE:
4402 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4403 case VMX_VMCS16_GUEST_FIELD_GS:
4404 case VMX_VMCS32_GUEST_GS_LIMIT:
4405 case VMX_VMCS64_GUEST_GS_BASE:
4406 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4407 case VMX_VMCS16_GUEST_FIELD_SS:
4408 case VMX_VMCS32_GUEST_SS_LIMIT:
4409 case VMX_VMCS64_GUEST_SS_BASE:
4410 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4411 case VMX_VMCS16_GUEST_FIELD_LDTR:
4412 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4413 case VMX_VMCS64_GUEST_LDTR_BASE:
4414 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4415 case VMX_VMCS16_GUEST_FIELD_TR:
4416 case VMX_VMCS32_GUEST_TR_LIMIT:
4417 case VMX_VMCS64_GUEST_TR_BASE:
4418 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4419 case VMX_VMCS32_RO_EXIT_REASON:
4420 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4421 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4422 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4423 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4424 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4425 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4426 case VMX_VMCS32_RO_IDT_INFO:
4427 case VMX_VMCS32_RO_IDT_ERRCODE:
4428 case VMX_VMCS64_GUEST_CR3:
4429 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4430 return true;
4431 }
4432 return false;
4433}
4434
4435static bool vmxR0IsValidWriteField(uint32_t idxField)
4436{
4437 switch(idxField)
4438 {
4439 case VMX_VMCS64_GUEST_LDTR_BASE:
4440 case VMX_VMCS64_GUEST_TR_BASE:
4441 case VMX_VMCS64_GUEST_GDTR_BASE:
4442 case VMX_VMCS64_GUEST_IDTR_BASE:
4443 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4444 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4445 case VMX_VMCS64_GUEST_CR0:
4446 case VMX_VMCS64_GUEST_CR4:
4447 case VMX_VMCS64_GUEST_CR3:
4448 case VMX_VMCS64_GUEST_DR7:
4449 case VMX_VMCS64_GUEST_RIP:
4450 case VMX_VMCS64_GUEST_RSP:
4451 case VMX_VMCS64_GUEST_CS_BASE:
4452 case VMX_VMCS64_GUEST_DS_BASE:
4453 case VMX_VMCS64_GUEST_ES_BASE:
4454 case VMX_VMCS64_GUEST_FS_BASE:
4455 case VMX_VMCS64_GUEST_GS_BASE:
4456 case VMX_VMCS64_GUEST_SS_BASE:
4457 return true;
4458 }
4459 return false;
4460}
4461
4462#endif
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