VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 21567

Last change on this file since 21567 was 21567, checked in by vboxsync, 15 years ago

Checked the wrong flush flag (excessive flushing)
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1/* $Id: HWVMXR0.cpp 21567 2009-07-14 10:08:27Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/param.h>
41#include <iprt/string.h>
42#include <iprt/time.h>
43#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
44# include <iprt/thread.h>
45#endif
46#include "HWVMXR0.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51#if defined(RT_ARCH_AMD64)
52# define VMX_IS_64BIT_HOST_MODE() (true)
53#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
54# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
55#else
56# define VMX_IS_64BIT_HOST_MODE() (false)
57#endif
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62/* IO operation lookup arrays. */
63static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
65
66#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
67/** See HWACCMR0A.asm. */
68extern "C" uint32_t g_fVMXIs64bitHost;
69#endif
70
71/*******************************************************************************
72* Local Functions *
73*******************************************************************************/
74static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
75static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
76static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
77static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
78static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
79static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
80static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
81#ifdef VBOX_STRICT
82static bool vmxR0IsValidReadField(uint32_t idxField);
83static bool vmxR0IsValidWriteField(uint32_t idxField);
84#endif
85
86static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
87{
88 if (rc == VERR_VMX_GENERIC)
89 {
90 RTCCUINTREG instrError;
91
92 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
93 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
94 }
95 pVM->hwaccm.s.lLastError = rc;
96}
97
98/**
99 * Sets up and activates VT-x on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pVM The VM to operate on. (can be NULL after a resume!!)
104 * @param pvPageCpu Pointer to the global cpu page
105 * @param pPageCpuPhys Physical address of the global cpu page
106 */
107VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
108{
109 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
110 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
111
112#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
113 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
114#endif
115 if (pVM)
116 {
117 /* Set revision dword at the beginning of the VMXON structure. */
118 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
119 }
120
121 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
122 * (which can have very bad consequences!!!)
123 */
124
125 /* Make sure the VMX instructions don't cause #UD faults. */
126 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
127
128 /* Enter VMX Root Mode */
129 int rc = VMXEnable(pPageCpuPhys);
130 if (RT_FAILURE(rc))
131 {
132 if (pVM)
133 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
134 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
135 return VERR_VMX_VMXON_FAILED;
136 }
137 return VINF_SUCCESS;
138}
139
140/**
141 * Deactivates VT-x on the current CPU
142 *
143 * @returns VBox status code.
144 * @param pCpu CPU info struct
145 * @param pvPageCpu Pointer to the global cpu page
146 * @param pPageCpuPhys Physical address of the global cpu page
147 */
148VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
149{
150 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
151 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
152
153 /* Leave VMX Root Mode. */
154 VMXDisable();
155
156 /* And clear the X86_CR4_VMXE bit */
157 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
158
159#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
160 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
161#endif
162 return VINF_SUCCESS;
163}
164
165/**
166 * Does Ring-0 per VM VT-x init.
167 *
168 * @returns VBox status code.
169 * @param pVM The VM to operate on.
170 */
171VMMR0DECL(int) VMXR0InitVM(PVM pVM)
172{
173 int rc;
174
175#ifdef LOG_ENABLED
176 SUPR0Printf("VMXR0InitVM %x\n", pVM);
177#endif
178
179 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
180
181 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
182 {
183 /* Allocate one page for the APIC physical page (serves for filtering accesses). */
184 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185 AssertRC(rc);
186 if (RT_FAILURE(rc))
187 return rc;
188
189 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
190 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
191 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
192 }
193 else
194 {
195 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
196 pVM->hwaccm.s.vmx.pAPIC = 0;
197 pVM->hwaccm.s.vmx.pAPICPhys = 0;
198 }
199
200 /* Allocate the MSR bitmap if this feature is supported. */
201 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
202 {
203 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
204 AssertRC(rc);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
209 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
210 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
211 }
212
213#ifdef VBOX_WITH_CRASHDUMP_MAGIC
214 {
215 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
216 AssertRC(rc);
217 if (RT_FAILURE(rc))
218 return rc;
219
220 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
221 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
222
223 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
224 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
225 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
226 }
227#endif
228
229 /* Allocate VMCBs for all guest CPUs. */
230 for (unsigned i=0;i<pVM->cCPUs;i++)
231 {
232 PVMCPU pVCpu = &pVM->aCpus[i];
233
234 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
235
236 /* Allocate one page for the VM control structure (VMCS). */
237 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
238 AssertRC(rc);
239 if (RT_FAILURE(rc))
240 return rc;
241
242 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
243 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
244 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
245
246 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
247 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
248
249 /* Allocate one page for the virtual APIC page for TPR caching. */
250 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
251 AssertRC(rc);
252 if (RT_FAILURE(rc))
253 return rc;
254
255 pVCpu->hwaccm.s.vmx.pVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
256 pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
257 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
258
259 /* Current guest paging mode. */
260 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
261
262#ifdef LOG_ENABLED
263 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
264#endif
265 }
266
267 return VINF_SUCCESS;
268}
269
270/**
271 * Does Ring-0 per VM VT-x termination.
272 *
273 * @returns VBox status code.
274 * @param pVM The VM to operate on.
275 */
276VMMR0DECL(int) VMXR0TermVM(PVM pVM)
277{
278 for (unsigned i=0;i<pVM->cCPUs;i++)
279 {
280 PVMCPU pVCpu = &pVM->aCpus[i];
281
282 if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
283 {
284 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
285 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
286 pVCpu->hwaccm.s.vmx.pVMCS = 0;
287 pVCpu->hwaccm.s.vmx.pVMCSPhys = 0;
288 }
289 if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
290 {
291 RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
292 pVCpu->hwaccm.s.vmx.pMemObjVAPIC = NIL_RTR0MEMOBJ;
293 pVCpu->hwaccm.s.vmx.pVAPIC = 0;
294 pVCpu->hwaccm.s.vmx.pVAPICPhys = 0;
295 }
296 }
297 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
298 {
299 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
300 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
301 pVM->hwaccm.s.vmx.pAPIC = 0;
302 pVM->hwaccm.s.vmx.pAPICPhys = 0;
303 }
304 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
305 {
306 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
307 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
308 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
309 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
310 }
311#ifdef VBOX_WITH_CRASHDUMP_MAGIC
312 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
313 {
314 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
315 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
316 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
317 pVM->hwaccm.s.vmx.pScratch = 0;
318 pVM->hwaccm.s.vmx.pScratchPhys = 0;
319 }
320#endif
321 return VINF_SUCCESS;
322}
323
324/**
325 * Sets up VT-x for the specified VM
326 *
327 * @returns VBox status code.
328 * @param pVM The VM to operate on.
329 */
330VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
331{
332 int rc = VINF_SUCCESS;
333 uint32_t val;
334
335 AssertReturn(pVM, VERR_INVALID_PARAMETER);
336
337 for (unsigned i=0;i<pVM->cCPUs;i++)
338 {
339 PVMCPU pVCpu = &pVM->aCpus[i];
340
341 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
342
343 /* Set revision dword at the beginning of the VMCS structure. */
344 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
345
346 /* Clear VM Control Structure. */
347 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
348 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
349 if (RT_FAILURE(rc))
350 goto vmx_end;
351
352 /* Activate the VM Control Structure. */
353 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
354 if (RT_FAILURE(rc))
355 goto vmx_end;
356
357 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
358 * Set required bits to one and zero according to the MSR capabilities.
359 */
360 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
361 /* External and non-maskable interrupts cause VM-exits. */
362 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
363 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
364
365 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
366 AssertRC(rc);
367
368 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
369 * Set required bits to one and zero according to the MSR capabilities.
370 */
371 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
372 /* Program which event cause VM-exits and which features we want to use. */
373 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
374 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
375 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
376 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
377 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
378 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
379
380 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
381 if (!pVM->hwaccm.s.fNestedPaging)
382 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
383 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
384 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
385
386 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
387 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
388 {
389 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
390 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
391 Assert(pVM->hwaccm.s.vmx.pAPIC);
392 }
393 else
394 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
395 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
396
397#ifdef VBOX_WITH_VTX_MSR_BITMAPS
398 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
399 {
400 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
401 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
402 }
403#endif
404
405 /* We will use the secondary control if it's present. */
406 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
407
408 /* Mask away the bits that the CPU doesn't support */
409 /** @todo make sure they don't conflict with the above requirements. */
410 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
411 pVCpu->hwaccm.s.vmx.proc_ctls = val;
412
413 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
414 AssertRC(rc);
415
416 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
417 {
418 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
419 * Set required bits to one and zero according to the MSR capabilities.
420 */
421 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
422 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
423
424#ifdef HWACCM_VTX_WITH_EPT
425 if (pVM->hwaccm.s.fNestedPaging)
426 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
427#endif /* HWACCM_VTX_WITH_EPT */
428#ifdef HWACCM_VTX_WITH_VPID
429 else
430 if (pVM->hwaccm.s.vmx.fVPID)
431 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
432#endif /* HWACCM_VTX_WITH_VPID */
433
434 if (pVM->hwaccm.s.fHasIoApic)
435 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC;
436
437 /* Mask away the bits that the CPU doesn't support */
438 /** @todo make sure they don't conflict with the above requirements. */
439 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
440 pVCpu->hwaccm.s.vmx.proc_ctls2 = val;
441 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
442 AssertRC(rc);
443 }
444
445 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
446 * Set required bits to one and zero according to the MSR capabilities.
447 */
448 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
449 AssertRC(rc);
450
451 /* Forward all exception except #NM & #PF to the guest.
452 * We always need to check pagefaults since our shadow page table can be out of sync.
453 * And we always lazily sync the FPU & XMM state.
454 */
455
456 /** @todo Possible optimization:
457 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
458 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
459 * registers ourselves of course.
460 *
461 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
462 */
463
464 /* Don't filter page faults; all of them should cause a switch. */
465 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
467 AssertRC(rc);
468
469 /* Init TSC offset to zero. */
470 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
471 AssertRC(rc);
472
473 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
474 AssertRC(rc);
475
476 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
477 AssertRC(rc);
478
479 /* Set the MSR bitmap address. */
480 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
481 {
482 /* Optional */
483 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
484 AssertRC(rc);
485 }
486
487 /* Clear MSR controls. */
488 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
489 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
490 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
491 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
492 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
493 AssertRC(rc);
494
495 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
496 {
497 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
498 /* Optional */
499 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
500 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
501
502 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
503 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
504
505 AssertRC(rc);
506 }
507
508 /* Set link pointer to -1. Not currently used. */
509 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
510 AssertRC(rc);
511
512 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
513 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
514 AssertRC(rc);
515
516 /* Configure the VMCS read cache. */
517 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
518
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
525 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
526 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
527 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
530 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
531 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
532 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
533 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
534 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
535
536 VMX_SETUP_SELREG(ES, pCache);
537 VMX_SETUP_SELREG(SS, pCache);
538 VMX_SETUP_SELREG(CS, pCache);
539 VMX_SETUP_SELREG(DS, pCache);
540 VMX_SETUP_SELREG(FS, pCache);
541 VMX_SETUP_SELREG(GS, pCache);
542 VMX_SETUP_SELREG(LDTR, pCache);
543 VMX_SETUP_SELREG(TR, pCache);
544
545 /* Status code VMCS reads. */
546 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
547 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
548 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
549 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
550 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
551 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
552 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
553 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
554 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
555
556 if (pVM->hwaccm.s.fNestedPaging)
557 {
558 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
559 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
560 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
561 }
562 else
563 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
564 } /* for each VMCPU */
565
566 /* Choose the right TLB setup function. */
567 if (pVM->hwaccm.s.fNestedPaging)
568 {
569 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
570
571 /* Default values for flushing. */
572 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
574
575 /* If the capabilities specify we can do more, then make use of it. */
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
577 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
578 else
579 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
580 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
581
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
583 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
584 }
585#ifdef HWACCM_VTX_WITH_VPID
586 else
587 if (pVM->hwaccm.s.vmx.fVPID)
588 {
589 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
590
591 /* Default values for flushing. */
592 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
593 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
594
595 /* If the capabilities specify we can do more, then make use of it. */
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
597 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
598 else
599 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
600 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
601
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
603 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
604 }
605#endif /* HWACCM_VTX_WITH_VPID */
606 else
607 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
608
609vmx_end:
610 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
611 return rc;
612}
613
614
615/**
616 * Injects an event (trap or external interrupt)
617 *
618 * @returns VBox status code.
619 * @param pVM The VM to operate on.
620 * @param pVCpu The VMCPU to operate on.
621 * @param pCtx CPU Context
622 * @param intInfo VMX interrupt info
623 * @param cbInstr Opcode length of faulting instruction
624 * @param errCode Error code (optional)
625 */
626static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
627{
628 int rc;
629 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
630
631#ifdef VBOX_WITH_STATISTICS
632 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
633#endif
634
635#ifdef VBOX_STRICT
636 if (iGate == 0xE)
637 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
638 else
639 if (iGate < 0x20)
640 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
641 else
642 {
643 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
644 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
645 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
646 }
647#endif
648
649#ifdef HWACCM_VMX_EMULATE_REALMODE
650 if (CPUMIsGuestInRealModeEx(pCtx))
651 {
652 RTGCPHYS GCPhysHandler;
653 uint16_t offset, ip;
654 RTSEL sel;
655
656 /* Injecting events doesn't work right with real mode emulation.
657 * (#GP if we try to inject external hardware interrupts)
658 * Inject the interrupt or trap directly instead.
659 *
660 * ASSUMES no access handlers for the bits we read or write below (should be safe).
661 */
662 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
663
664 /* Check if the interrupt handler is present. */
665 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
666 {
667 Log(("IDT cbIdt violation\n"));
668 if (iGate != X86_XCPT_DF)
669 {
670 RTGCUINTPTR intInfo;
671
672 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
673 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
674 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
675 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
676
677 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
678 }
679 Log(("Triple fault -> reset the VM!\n"));
680 return VINF_EM_RESET;
681 }
682 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
683 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
684 || iGate == 4)
685 {
686 ip = pCtx->ip + cbInstr;
687 }
688 else
689 ip = pCtx->ip;
690
691 /* Read the selector:offset pair of the interrupt handler. */
692 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
693 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
694 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
695
696 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
697
698 /* Construct the stack frame. */
699 /** @todo should check stack limit. */
700 pCtx->sp -= 2;
701 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
702 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
703 pCtx->sp -= 2;
704 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
705 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
706 pCtx->sp -= 2;
707 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
708 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
709
710 /* Update the CPU state for executing the handler. */
711 pCtx->rip = offset;
712 pCtx->cs = sel;
713 pCtx->csHid.u64Base = sel << 4;
714 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
715
716 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
717 return VINF_SUCCESS;
718 }
719#endif /* HWACCM_VMX_EMULATE_REALMODE */
720
721 /* Set event injection state. */
722 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
723
724 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
725 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
726
727 AssertRC(rc);
728 return rc;
729}
730
731
732/**
733 * Checks for pending guest interrupts and injects them
734 *
735 * @returns VBox status code.
736 * @param pVM The VM to operate on.
737 * @param pVCpu The VMCPU to operate on.
738 * @param pCtx CPU Context
739 */
740static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
741{
742 int rc;
743
744 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
745 if (pVCpu->hwaccm.s.Event.fPending)
746 {
747 Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
748 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
749 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
750 AssertRC(rc);
751
752 pVCpu->hwaccm.s.Event.fPending = false;
753 return VINF_SUCCESS;
754 }
755
756 /* If an active trap is already pending, then we must forward it first! */
757 if (!TRPMHasTrap(pVCpu))
758 {
759 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
760 {
761 RTGCUINTPTR intInfo;
762
763 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
764
765 intInfo = X86_XCPT_NMI;
766 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
767 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
768
769 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
770 AssertRC(rc);
771
772 return VINF_SUCCESS;
773 }
774
775 /* @todo SMI interrupts. */
776
777 /* When external interrupts are pending, we should exit the VM when IF is set. */
778 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
779 {
780 if (!(pCtx->eflags.u32 & X86_EFL_IF))
781 {
782 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
783 {
784 LogFlow(("Enable irq window exit!\n"));
785 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
786 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
787 AssertRC(rc);
788 }
789 /* else nothing to do but wait */
790 }
791 else
792 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
793 {
794 uint8_t u8Interrupt;
795
796 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
797 Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
798 if (RT_SUCCESS(rc))
799 {
800 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
801 AssertRC(rc);
802 }
803 else
804 {
805 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
806 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
807 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
808 /* Just continue */
809 }
810 }
811 else
812 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
813 }
814 }
815
816#ifdef VBOX_STRICT
817 if (TRPMHasTrap(pVCpu))
818 {
819 uint8_t u8Vector;
820 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
821 AssertRC(rc);
822 }
823#endif
824
825 if ( (pCtx->eflags.u32 & X86_EFL_IF)
826 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
827 && TRPMHasTrap(pVCpu)
828 )
829 {
830 uint8_t u8Vector;
831 int rc;
832 TRPMEVENT enmType;
833 RTGCUINTPTR intInfo;
834 RTGCUINT errCode;
835
836 /* If a new event is pending, then dispatch it now. */
837 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
838 AssertRC(rc);
839 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
840 Assert(enmType != TRPM_SOFTWARE_INT);
841
842 /* Clear the pending trap. */
843 rc = TRPMResetTrap(pVCpu);
844 AssertRC(rc);
845
846 intInfo = u8Vector;
847 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
848
849 if (enmType == TRPM_TRAP)
850 {
851 switch (u8Vector) {
852 case 8:
853 case 10:
854 case 11:
855 case 12:
856 case 13:
857 case 14:
858 case 17:
859 /* Valid error codes. */
860 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
861 break;
862 default:
863 break;
864 }
865 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
866 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
867 else
868 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
869 }
870 else
871 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
872
873 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
874 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
875 AssertRC(rc);
876 } /* if (interrupts can be dispatched) */
877
878 return VINF_SUCCESS;
879}
880
881/**
882 * Save the host state
883 *
884 * @returns VBox status code.
885 * @param pVM The VM to operate on.
886 * @param pVCpu The VMCPU to operate on.
887 */
888VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
889{
890 int rc = VINF_SUCCESS;
891
892 /*
893 * Host CPU Context
894 */
895 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
896 {
897 RTIDTR idtr;
898 RTGDTR gdtr;
899 RTSEL SelTR;
900 PX86DESCHC pDesc;
901 uintptr_t trBase;
902 RTSEL cs;
903 RTSEL ss;
904 uint64_t cr3;
905
906 /* Control registers */
907 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
908#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
909 if (VMX_IS_64BIT_HOST_MODE())
910 {
911 cr3 = hwaccmR0Get64bitCR3();
912 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
913 }
914 else
915#endif
916 {
917 cr3 = ASMGetCR3();
918 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
919 }
920 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
921 AssertRC(rc);
922 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
923 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
924 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
925
926 /* Selector registers. */
927#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
928 if (VMX_IS_64BIT_HOST_MODE())
929 {
930 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
931 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
932 }
933 else
934 {
935 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
936 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
937 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
938 }
939#else
940 cs = ASMGetCS();
941 ss = ASMGetSS();
942#endif
943 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
944 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
945 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
946 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
947 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
948 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
949#if HC_ARCH_BITS == 32
950 if (!VMX_IS_64BIT_HOST_MODE())
951 {
952 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
953 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
954 }
955#endif
956 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
957 SelTR = ASMGetTR();
958 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
959 AssertRC(rc);
960 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
961 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
962 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
963 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
964 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
965 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
966 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
967
968 /* GDTR & IDTR */
969#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
970 if (VMX_IS_64BIT_HOST_MODE())
971 {
972 X86XDTR64 gdtr64, idtr64;
973 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
974 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
975 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
976 AssertRC(rc);
977 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
978 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
979 gdtr.cbGdt = gdtr64.cb;
980 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
981 }
982 else
983#endif
984 {
985 ASMGetGDTR(&gdtr);
986 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
987 ASMGetIDTR(&idtr);
988 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
989 AssertRC(rc);
990 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
991 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
992 }
993
994
995 /* Save the base address of the TR selector. */
996 if (SelTR > gdtr.cbGdt)
997 {
998 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
999 return VERR_VMX_INVALID_HOST_STATE;
1000 }
1001
1002#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1003 if (VMX_IS_64BIT_HOST_MODE())
1004 {
1005 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
1006 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
1007 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
1008 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
1009 AssertRC(rc);
1010 }
1011 else
1012#endif
1013 {
1014 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
1015#if HC_ARCH_BITS == 64
1016 trBase = X86DESC64_BASE(*pDesc);
1017#else
1018 trBase = X86DESC_BASE(*pDesc);
1019#endif
1020 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
1021 AssertRC(rc);
1022 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
1023 }
1024
1025 /* FS and GS base. */
1026#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1027 if (VMX_IS_64BIT_HOST_MODE())
1028 {
1029 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
1030 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
1031 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
1032 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
1033 }
1034#endif
1035 AssertRC(rc);
1036
1037 /* Sysenter MSRs. */
1038 /** @todo expensive!! */
1039 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1040 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1041#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1042 if (VMX_IS_64BIT_HOST_MODE())
1043 {
1044 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1045 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1046 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1047 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1048 }
1049 else
1050 {
1051 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1052 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1053 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1054 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1055 }
1056#elif HC_ARCH_BITS == 32
1057 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1058 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1059 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1060 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1061#else
1062 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1063 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1064 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1065 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1066#endif
1067 AssertRC(rc);
1068
1069#if 0 /* @todo deal with 32/64 */
1070 /* Restore the host EFER - on CPUs that support it. */
1071 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1072 {
1073 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1074 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1075 AssertRC(rc);
1076 }
1077#endif
1078 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1079 }
1080 return rc;
1081}
1082
1083/**
1084 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1085 *
1086 * @param pVM The VM to operate on.
1087 * @param pVCpu The VMCPU to operate on.
1088 * @param pCtx Guest context
1089 */
1090static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1091{
1092 if (CPUMIsGuestInPAEModeEx(pCtx))
1093 {
1094 X86PDPE Pdpe;
1095
1096 for (unsigned i=0;i<4;i++)
1097 {
1098 Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1099 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1100 AssertRC(rc);
1101 }
1102 }
1103}
1104
1105/**
1106 * Update the exception bitmap according to the current CPU state
1107 *
1108 * @param pVM The VM to operate on.
1109 * @param pVCpu The VMCPU to operate on.
1110 * @param pCtx Guest context
1111 */
1112static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1113{
1114 uint32_t u32TrapMask;
1115 Assert(pCtx);
1116
1117 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1118#ifndef DEBUG
1119 if (pVM->hwaccm.s.fNestedPaging)
1120 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1121#endif
1122
1123 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1124 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1125 && !(pCtx->cr0 & X86_CR0_NE)
1126 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1127 {
1128 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1129 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1130 }
1131
1132#ifdef DEBUG /* till after branching, enable it by default then. */
1133 /* Intercept X86_XCPT_DB if stepping is enabled */
1134 if ( DBGFIsStepping(pVCpu)
1135 || CPUMIsHyperDebugStateActive(pVCpu))
1136 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1137 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1138 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1139#endif
1140
1141#ifdef VBOX_STRICT
1142 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1143#endif
1144
1145# ifdef HWACCM_VMX_EMULATE_REALMODE
1146 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1147 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1148 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1149# endif /* HWACCM_VMX_EMULATE_REALMODE */
1150
1151 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1152 AssertRC(rc);
1153}
1154
1155/**
1156 * Loads the guest state
1157 *
1158 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1159 *
1160 * @returns VBox status code.
1161 * @param pVM The VM to operate on.
1162 * @param pVCpu The VMCPU to operate on.
1163 * @param pCtx Guest context
1164 */
1165VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1166{
1167 int rc = VINF_SUCCESS;
1168 RTGCUINTPTR val;
1169 X86EFLAGS eflags;
1170
1171 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1172 * Set required bits to one and zero according to the MSR capabilities.
1173 */
1174 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1175 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1176 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1177#if 0 /* @todo deal with 32/64 */
1178 /* Required for the EFER write below, not supported on all CPUs. */
1179 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1180#endif
1181 /* 64 bits guest mode? */
1182 if (CPUMIsGuestInLongModeEx(pCtx))
1183 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1184 /* else Must be zero when AMD64 is not available. */
1185
1186 /* Mask away the bits that the CPU doesn't support */
1187 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1188 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1189 AssertRC(rc);
1190
1191 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1192 * Set required bits to one and zero according to the MSR capabilities.
1193 */
1194 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1195
1196 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1197#if 0 /* @todo deal with 32/64 */
1198 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1199#else
1200 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1201#endif
1202
1203#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1204 if (VMX_IS_64BIT_HOST_MODE())
1205 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1206 /* else: Must be zero when AMD64 is not available. */
1207#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1208 if (CPUMIsGuestInLongModeEx(pCtx))
1209 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1210 else
1211 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1212#endif
1213 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1214 /* Don't acknowledge external interrupts on VM-exit. */
1215 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1216 AssertRC(rc);
1217
1218 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1219 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1220 {
1221#ifdef HWACCM_VMX_EMULATE_REALMODE
1222 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1223 {
1224 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1225 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1226 {
1227 /* Correct weird requirements for switching to protected mode. */
1228 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1229 && enmGuestMode >= PGMMODE_PROTECTED)
1230 {
1231 /* Flush the recompiler code cache as it's not unlikely
1232 * the guest will rewrite code it will later execute in real
1233 * mode (OpenBSD 4.0 is one such example)
1234 */
1235 REMFlushTBs(pVM);
1236
1237 /* DPL of all hidden selector registers must match the current CPL (0). */
1238 pCtx->csHid.Attr.n.u2Dpl = 0;
1239 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1240
1241 pCtx->dsHid.Attr.n.u2Dpl = 0;
1242 pCtx->esHid.Attr.n.u2Dpl = 0;
1243 pCtx->fsHid.Attr.n.u2Dpl = 0;
1244 pCtx->gsHid.Attr.n.u2Dpl = 0;
1245 pCtx->ssHid.Attr.n.u2Dpl = 0;
1246
1247 /* The limit must correspond to the granularity bit. */
1248 if (!pCtx->csHid.Attr.n.u1Granularity)
1249 pCtx->csHid.u32Limit &= 0xffff;
1250 if (!pCtx->dsHid.Attr.n.u1Granularity)
1251 pCtx->dsHid.u32Limit &= 0xffff;
1252 if (!pCtx->esHid.Attr.n.u1Granularity)
1253 pCtx->esHid.u32Limit &= 0xffff;
1254 if (!pCtx->fsHid.Attr.n.u1Granularity)
1255 pCtx->fsHid.u32Limit &= 0xffff;
1256 if (!pCtx->gsHid.Attr.n.u1Granularity)
1257 pCtx->gsHid.u32Limit &= 0xffff;
1258 if (!pCtx->ssHid.Attr.n.u1Granularity)
1259 pCtx->ssHid.u32Limit &= 0xffff;
1260 }
1261 else
1262 /* Switching from protected mode to real mode. */
1263 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1264 && enmGuestMode == PGMMODE_REAL)
1265 {
1266 /* The limit must also be set to 0xffff. */
1267 pCtx->csHid.u32Limit = 0xffff;
1268 pCtx->dsHid.u32Limit = 0xffff;
1269 pCtx->esHid.u32Limit = 0xffff;
1270 pCtx->fsHid.u32Limit = 0xffff;
1271 pCtx->gsHid.u32Limit = 0xffff;
1272 pCtx->ssHid.u32Limit = 0xffff;
1273
1274 Assert(pCtx->csHid.u64Base <= 0xfffff);
1275 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1276 Assert(pCtx->esHid.u64Base <= 0xfffff);
1277 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1278 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1279 }
1280 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1281 }
1282 else
1283 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1284 if ( CPUMIsGuestInRealModeEx(pCtx)
1285 && pCtx->csHid.u64Base == 0xffff0000)
1286 {
1287 pCtx->csHid.u64Base = 0xf0000;
1288 pCtx->cs = 0xf000;
1289 }
1290 }
1291#endif /* HWACCM_VMX_EMULATE_REALMODE */
1292
1293 VMX_WRITE_SELREG(ES, es);
1294 AssertRC(rc);
1295
1296 VMX_WRITE_SELREG(CS, cs);
1297 AssertRC(rc);
1298
1299 VMX_WRITE_SELREG(SS, ss);
1300 AssertRC(rc);
1301
1302 VMX_WRITE_SELREG(DS, ds);
1303 AssertRC(rc);
1304
1305 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1306 VMX_WRITE_SELREG(FS, fs);
1307 AssertRC(rc);
1308
1309 VMX_WRITE_SELREG(GS, gs);
1310 AssertRC(rc);
1311 }
1312
1313 /* Guest CPU context: LDTR. */
1314 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1315 {
1316 if (pCtx->ldtr == 0)
1317 {
1318 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1319 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1320 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1321 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1322 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1323 }
1324 else
1325 {
1326 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1327 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1328 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1329 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1330 }
1331 AssertRC(rc);
1332 }
1333 /* Guest CPU context: TR. */
1334 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1335 {
1336#ifdef HWACCM_VMX_EMULATE_REALMODE
1337 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1338 if (CPUMIsGuestInRealModeEx(pCtx))
1339 {
1340 RTGCPHYS GCPhys;
1341
1342 /* We convert it here every time as pci regions could be reconfigured. */
1343 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1344 AssertRC(rc);
1345
1346 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1347 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1348 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1349
1350 X86DESCATTR attr;
1351
1352 attr.u = 0;
1353 attr.n.u1Present = 1;
1354 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1355 val = attr.u;
1356 }
1357 else
1358#endif /* HWACCM_VMX_EMULATE_REALMODE */
1359 {
1360 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1361 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1362 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1363
1364 val = pCtx->trHid.Attr.u;
1365
1366 /* The TSS selector must be busy. */
1367 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1368 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1369 else
1370 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1371 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1372
1373 }
1374 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1375 AssertRC(rc);
1376 }
1377 /* Guest CPU context: GDTR. */
1378 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1379 {
1380 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1381 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1382 AssertRC(rc);
1383 }
1384 /* Guest CPU context: IDTR. */
1385 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1386 {
1387 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1388 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1389 AssertRC(rc);
1390 }
1391
1392 /*
1393 * Sysenter MSRs (unconditional)
1394 */
1395 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1396 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1397 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1398 AssertRC(rc);
1399
1400 /* Control registers */
1401 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1402 {
1403 val = pCtx->cr0;
1404 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1405 Log2(("Guest CR0-shadow %08x\n", val));
1406 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1407 {
1408 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1409 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1410 }
1411 else
1412 {
1413 /** @todo check if we support the old style mess correctly. */
1414 if (!(val & X86_CR0_NE))
1415 Log(("Forcing X86_CR0_NE!!!\n"));
1416
1417 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1418 }
1419 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1420 val |= X86_CR0_PE | X86_CR0_PG;
1421 if (pVM->hwaccm.s.fNestedPaging)
1422 {
1423 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1424 {
1425 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1426 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1427 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1428 }
1429 else
1430 {
1431 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1432 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1433 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1434 }
1435 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1436 AssertRC(rc);
1437 }
1438 else
1439 {
1440 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1441 val |= X86_CR0_WP;
1442 }
1443
1444 /* Always enable caching. */
1445 val &= ~(X86_CR0_CD|X86_CR0_NW);
1446
1447 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1448 Log2(("Guest CR0 %08x\n", val));
1449 /* CR0 flags owned by the host; if the guests attempts to change them, then
1450 * the VM will exit.
1451 */
1452 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1453 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1454 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1455 | X86_CR0_TS
1456 | X86_CR0_ET /* Bit not restored during VM-exit! */
1457 | X86_CR0_CD /* Bit not restored during VM-exit! */
1458 | X86_CR0_NW /* Bit not restored during VM-exit! */
1459 | X86_CR0_NE
1460 | X86_CR0_MP;
1461 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1462
1463 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1464 Log2(("Guest CR0-mask %08x\n", val));
1465 AssertRC(rc);
1466 }
1467 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1468 {
1469 /* CR4 */
1470 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1471 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1472 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1473 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1474
1475 if (!pVM->hwaccm.s.fNestedPaging)
1476 {
1477 switch(pVCpu->hwaccm.s.enmShadowMode)
1478 {
1479 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1480 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1481 case PGMMODE_32_BIT: /* 32-bit paging. */
1482 val &= ~X86_CR4_PAE;
1483 break;
1484
1485 case PGMMODE_PAE: /* PAE paging. */
1486 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1487 /** @todo use normal 32 bits paging */
1488 val |= X86_CR4_PAE;
1489 break;
1490
1491 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1492 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1493#ifdef VBOX_ENABLE_64_BITS_GUESTS
1494 break;
1495#else
1496 AssertFailed();
1497 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1498#endif
1499 default: /* shut up gcc */
1500 AssertFailed();
1501 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1502 }
1503 }
1504 else
1505 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1506 {
1507 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1508 val |= X86_CR4_PSE;
1509 /* Our identity mapping is a 32 bits page directory. */
1510 val &= ~X86_CR4_PAE;
1511 }
1512
1513 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1514 Log2(("Guest CR4 %08x\n", val));
1515 /* CR4 flags owned by the host; if the guests attempts to change them, then
1516 * the VM will exit.
1517 */
1518 val = 0
1519 | X86_CR4_PAE
1520 | X86_CR4_PGE
1521 | X86_CR4_PSE
1522 | X86_CR4_VMXE;
1523 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1524
1525 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1526 Log2(("Guest CR4-mask %08x\n", val));
1527 AssertRC(rc);
1528 }
1529
1530 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1531 {
1532 if (pVM->hwaccm.s.fNestedPaging)
1533 {
1534 Assert(PGMGetHyperCR3(pVCpu));
1535 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1536
1537 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1538 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1539 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1540 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1541
1542 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1543 AssertRC(rc);
1544
1545 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1546 {
1547 RTGCPHYS GCPhys;
1548
1549 /* We convert it here every time as pci regions could be reconfigured. */
1550 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1551 AssertRC(rc);
1552
1553 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1554 * take care of the translation to host physical addresses.
1555 */
1556 val = GCPhys;
1557 }
1558 else
1559 {
1560 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1561 val = pCtx->cr3;
1562 /* Prefetch the four PDPT entries in PAE mode. */
1563 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1564 }
1565 }
1566 else
1567 {
1568 val = PGMGetHyperCR3(pVCpu);
1569 Assert(val || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1570 }
1571
1572 /* Save our shadow CR3 register. */
1573 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1574 AssertRC(rc);
1575 }
1576
1577 /* Debug registers. */
1578 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1579 {
1580 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1581 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1582
1583 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1584 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1585 pCtx->dr[7] |= 0x400; /* must be one */
1586
1587 /* Resync DR7 */
1588 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1589 AssertRC(rc);
1590
1591#ifdef DEBUG
1592 /* Sync the hypervisor debug state now if any breakpoint is armed. */
1593 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
1594 && !CPUMIsHyperDebugStateActive(pVCpu)
1595 && !DBGFIsStepping(pVCpu))
1596 {
1597 /* Save the host and load the hypervisor debug state. */
1598 rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1599 AssertRC(rc);
1600
1601 /* DRx intercepts remain enabled. */
1602
1603 /* Override dr7 with the hypervisor value. */
1604 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, CPUMGetHyperDR7(pVCpu));
1605 AssertRC(rc);
1606 }
1607 else
1608#endif
1609 /* Sync the debug state now if any breakpoint is armed. */
1610 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1611 && !CPUMIsGuestDebugStateActive(pVCpu)
1612 && !DBGFIsStepping(pVCpu))
1613 {
1614 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1615
1616 /* Disable drx move intercepts. */
1617 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1618 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1619 AssertRC(rc);
1620
1621 /* Save the host and load the guest debug state. */
1622 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1623 AssertRC(rc);
1624 }
1625
1626 /* IA32_DEBUGCTL MSR. */
1627 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1628 AssertRC(rc);
1629
1630 /** @todo do we really ever need this? */
1631 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1632 AssertRC(rc);
1633 }
1634
1635 /* EIP, ESP and EFLAGS */
1636 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1637 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1638 AssertRC(rc);
1639
1640 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1641 eflags = pCtx->eflags;
1642 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1643 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1644
1645#ifdef HWACCM_VMX_EMULATE_REALMODE
1646 /* Real mode emulation using v86 mode. */
1647 if (CPUMIsGuestInRealModeEx(pCtx))
1648 {
1649 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1650
1651 eflags.Bits.u1VM = 1;
1652 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1653 }
1654#endif /* HWACCM_VMX_EMULATE_REALMODE */
1655 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1656 AssertRC(rc);
1657
1658 /* TSC offset. */
1659 uint64_t u64TSCOffset;
1660
1661 if (TMCpuTickCanUseRealTSC(pVCpu, &u64TSCOffset))
1662 {
1663 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1664 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1665 AssertRC(rc);
1666
1667 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1668 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1669 AssertRC(rc);
1670 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1671 }
1672 else
1673 {
1674 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1675 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1676 AssertRC(rc);
1677 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1678 }
1679
1680 /* 64 bits guest mode? */
1681 if (CPUMIsGuestInLongModeEx(pCtx))
1682 {
1683#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1684 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1685#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1686 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1687#else
1688# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1689 if (!pVM->hwaccm.s.fAllow64BitGuests)
1690 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1691# endif
1692 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1693#endif
1694 /* Unconditionally update these as wrmsr might have changed them. */
1695 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1696 AssertRC(rc);
1697 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1698 AssertRC(rc);
1699 }
1700 else
1701 {
1702 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1703 }
1704
1705#if 0 /* @todo deal with 32/64 */
1706 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1707 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1708 {
1709 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1710 AssertRC(rc);
1711 }
1712#endif
1713
1714 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1715
1716 /* Done. */
1717 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1718
1719 return rc;
1720}
1721
1722/**
1723 * Syncs back the guest state
1724 *
1725 * @returns VBox status code.
1726 * @param pVM The VM to operate on.
1727 * @param pVCpu The VMCPU to operate on.
1728 * @param pCtx Guest context
1729 */
1730DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1731{
1732 RTGCUINTREG val, valShadow;
1733 RTGCUINTPTR uInterruptState;
1734 int rc;
1735
1736 /* Let's first sync back eip, esp, and eflags. */
1737 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1738 AssertRC(rc);
1739 pCtx->rip = val;
1740 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1741 AssertRC(rc);
1742 pCtx->rsp = val;
1743 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1744 AssertRC(rc);
1745 pCtx->eflags.u32 = val;
1746
1747 /* Take care of instruction fusing (sti, mov ss) */
1748 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1749 uInterruptState = val;
1750 if (uInterruptState != 0)
1751 {
1752 Assert(uInterruptState <= 2); /* only sti & mov ss */
1753 Log(("uInterruptState %x eip=%RGv\n", (uint32_t)uInterruptState, pCtx->rip));
1754 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1755 }
1756 else
1757 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1758
1759 /* Control registers. */
1760 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1761 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1762 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1763 CPUMSetGuestCR0(pVCpu, val);
1764
1765 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1766 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1767 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1768 CPUMSetGuestCR4(pVCpu, val);
1769
1770 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1771 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1772 if ( pVM->hwaccm.s.fNestedPaging
1773 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1774 {
1775 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1776
1777 /* Can be updated behind our back in the nested paging case. */
1778 CPUMSetGuestCR2(pVCpu, pCache->cr2);
1779
1780 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1781
1782 if (val != pCtx->cr3)
1783 {
1784 CPUMSetGuestCR3(pVCpu, val);
1785 PGMUpdateCR3(pVCpu, val);
1786 }
1787 /* Prefetch the four PDPT entries in PAE mode. */
1788 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1789 }
1790
1791 /* Sync back DR7 here. */
1792 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1793 pCtx->dr[7] = val;
1794
1795 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1796 VMX_READ_SELREG(ES, es);
1797 VMX_READ_SELREG(SS, ss);
1798 VMX_READ_SELREG(CS, cs);
1799 VMX_READ_SELREG(DS, ds);
1800 VMX_READ_SELREG(FS, fs);
1801 VMX_READ_SELREG(GS, gs);
1802
1803 /*
1804 * System MSRs
1805 */
1806 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1807 pCtx->SysEnter.cs = val;
1808 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1809 pCtx->SysEnter.eip = val;
1810 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1811 pCtx->SysEnter.esp = val;
1812
1813 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1814 VMX_READ_SELREG(LDTR, ldtr);
1815
1816 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1817 pCtx->gdtr.cbGdt = val;
1818 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1819 pCtx->gdtr.pGdt = val;
1820
1821 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1822 pCtx->idtr.cbIdt = val;
1823 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1824 pCtx->idtr.pIdt = val;
1825
1826#ifdef HWACCM_VMX_EMULATE_REALMODE
1827 /* Real mode emulation using v86 mode. */
1828 if (CPUMIsGuestInRealModeEx(pCtx))
1829 {
1830 /* Hide our emulation flags */
1831 pCtx->eflags.Bits.u1VM = 0;
1832
1833 /* Restore original IOPL setting as we always use 0. */
1834 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1835
1836 /* Force a TR resync every time in case we switch modes. */
1837 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1838 }
1839 else
1840#endif /* HWACCM_VMX_EMULATE_REALMODE */
1841 {
1842 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1843 VMX_READ_SELREG(TR, tr);
1844 }
1845 return VINF_SUCCESS;
1846}
1847
1848/**
1849 * Dummy placeholder
1850 *
1851 * @param pVM The VM to operate on.
1852 * @param pVCpu The VMCPU to operate on.
1853 */
1854static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1855{
1856 NOREF(pVM);
1857 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1858 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1859 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1860 return;
1861}
1862
1863/**
1864 * Setup the tagged TLB for EPT
1865 *
1866 * @returns VBox status code.
1867 * @param pVM The VM to operate on.
1868 * @param pVCpu The VMCPU to operate on.
1869 */
1870static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1871{
1872 PHWACCM_CPUINFO pCpu;
1873
1874 Assert(pVM->hwaccm.s.fNestedPaging);
1875 Assert(!pVM->hwaccm.s.vmx.fVPID);
1876
1877 /* Deal with tagged TLBs if VPID or EPT is supported. */
1878 pCpu = HWACCMR0GetCurrentCpu();
1879 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1880 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1881 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1882 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1883 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1884 {
1885 /* Force a TLB flush on VM entry. */
1886 pVCpu->hwaccm.s.fForceTLBFlush = true;
1887 }
1888 else
1889 Assert(!pCpu->fFlushTLB);
1890
1891 /* Check for tlb shootdown flushes. */
1892 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1893 pVCpu->hwaccm.s.fForceTLBFlush = true;
1894
1895 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1896 pCpu->fFlushTLB = false;
1897
1898 if (pVCpu->hwaccm.s.fForceTLBFlush)
1899 {
1900 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1901 }
1902 else
1903 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1904 {
1905 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1906 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1907
1908 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1909 {
1910 /* aTlbShootdownPages contains physical addresses in this case. */
1911 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1912 }
1913 }
1914 pVCpu->hwaccm.s.TlbShootdown.cPages= 0;
1915 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1916
1917#ifdef VBOX_WITH_STATISTICS
1918 if (pVCpu->hwaccm.s.fForceTLBFlush)
1919 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1920 else
1921 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1922#endif
1923}
1924
1925#ifdef HWACCM_VTX_WITH_VPID
1926/**
1927 * Setup the tagged TLB for VPID
1928 *
1929 * @returns VBox status code.
1930 * @param pVM The VM to operate on.
1931 * @param pVCpu The VMCPU to operate on.
1932 */
1933static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1934{
1935 PHWACCM_CPUINFO pCpu;
1936
1937 Assert(pVM->hwaccm.s.vmx.fVPID);
1938 Assert(!pVM->hwaccm.s.fNestedPaging);
1939
1940 /* Deal with tagged TLBs if VPID or EPT is supported. */
1941 pCpu = HWACCMR0GetCurrentCpu();
1942 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1943 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1944 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1945 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1946 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1947 {
1948 /* Force a TLB flush on VM entry. */
1949 pVCpu->hwaccm.s.fForceTLBFlush = true;
1950 }
1951 else
1952 Assert(!pCpu->fFlushTLB);
1953
1954 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1955
1956 /* Check for tlb shootdown flushes. */
1957 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1958 pVCpu->hwaccm.s.fForceTLBFlush = true;
1959
1960 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1961 if (pVCpu->hwaccm.s.fForceTLBFlush)
1962 {
1963 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1964 || pCpu->fFlushTLB)
1965 {
1966 pCpu->fFlushTLB = false;
1967 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1968 pCpu->cTLBFlushes++;
1969 }
1970 else
1971 {
1972 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1973 pVCpu->hwaccm.s.fForceTLBFlush = false;
1974 }
1975
1976 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1977 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1978 }
1979 else
1980 {
1981 Assert(!pCpu->fFlushTLB);
1982 Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
1983
1984 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1985 {
1986 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1987 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1988 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1989 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1990 }
1991 }
1992 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1993 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1994
1995 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1996 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1997 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1998
1999 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
2000 AssertRC(rc);
2001
2002 if (pVCpu->hwaccm.s.fForceTLBFlush)
2003 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
2004
2005#ifdef VBOX_WITH_STATISTICS
2006 if (pVCpu->hwaccm.s.fForceTLBFlush)
2007 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
2008 else
2009 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
2010#endif
2011}
2012#endif /* HWACCM_VTX_WITH_VPID */
2013
2014/**
2015 * Runs guest code in a VT-x VM.
2016 *
2017 * @returns VBox status code.
2018 * @param pVM The VM to operate on.
2019 * @param pVCpu The VMCPU to operate on.
2020 * @param pCtx Guest context
2021 */
2022VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2023{
2024 int rc = VINF_SUCCESS;
2025 RTGCUINTREG val;
2026 RTGCUINTREG exitReason = VMX_EXIT_INVALID;
2027 RTGCUINTREG instrError, cbInstr;
2028 RTGCUINTPTR exitQualification = 0;
2029 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
2030 RTGCUINTPTR errCode, instrInfo;
2031 bool fSetupTPRCaching = false;
2032 uint8_t u8LastTPR = 0;
2033 PHWACCM_CPUINFO pCpu = 0;
2034 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
2035 unsigned cResume = 0;
2036#ifdef VBOX_STRICT
2037 RTCPUID idCpuCheck;
2038#endif
2039#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2040 uint64_t u64LastTime = RTTimeMilliTS();
2041#endif
2042#ifdef VBOX_WITH_STATISTICS
2043 bool fStatEntryStarted = true;
2044 bool fStatExit2Started = false;
2045#endif
2046
2047 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) || (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
2048
2049 /* Check if we need to use TPR shadowing. */
2050 if ( CPUMIsGuestInLongModeEx(pCtx)
2051 || ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2052 && pVM->hwaccm.s.fHasIoApic)
2053 )
2054 {
2055 fSetupTPRCaching = true;
2056 }
2057
2058 Log2(("\nE"));
2059
2060 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
2061
2062#ifdef VBOX_STRICT
2063 {
2064 RTCCUINTREG val;
2065
2066 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
2067 AssertRC(rc);
2068 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
2069
2070 /* allowed zero */
2071 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
2072 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
2073
2074 /* allowed one */
2075 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
2076 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
2077
2078 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
2079 AssertRC(rc);
2080 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
2081
2082 /* Must be set according to the MSR, but can be cleared in case of EPT. */
2083 if (pVM->hwaccm.s.fNestedPaging)
2084 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
2085 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2086 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2087
2088 /* allowed zero */
2089 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2090 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2091
2092 /* allowed one */
2093 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2094 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2095
2096 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2097 AssertRC(rc);
2098 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2099
2100 /* allowed zero */
2101 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2102 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2103
2104 /* allowed one */
2105 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2106 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2107
2108 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2109 AssertRC(rc);
2110 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2111
2112 /* allowed zero */
2113 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2114 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2115
2116 /* allowed one */
2117 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2118 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2119 }
2120#endif
2121
2122#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2123 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2124#endif
2125
2126 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2127 */
2128ResumeExecution:
2129 STAM_STATS({
2130 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2131 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2132 });
2133 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2134 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2135 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2136 Assert(!HWACCMR0SuspendPending());
2137
2138 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2139 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
2140 {
2141 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2142 rc = VINF_EM_RAW_INTERRUPT;
2143 goto end;
2144 }
2145
2146 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2147 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2148 {
2149 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2150 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2151 {
2152 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2153 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2154 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2155 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2156 */
2157 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2158 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2159 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2160 AssertRC(rc);
2161 }
2162 }
2163 else
2164 {
2165 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2166 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2167 AssertRC(rc);
2168 }
2169
2170#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2171 if (RT_UNLIKELY(cResume & 0xf) == 0)
2172 {
2173 uint64_t u64CurTime = RTTimeMilliTS();
2174
2175 if (RT_UNLIKELY(u64CurTime > u64LastTime))
2176 {
2177 u64LastTime = u64CurTime;
2178 TMTimerPollVoid(pVM, pVCpu);
2179 }
2180 }
2181#endif
2182
2183 /* Check for pending actions that force us to go back to ring 3. */
2184#ifdef DEBUG
2185 /* Intercept X86_XCPT_DB if stepping is enabled */
2186 if (!DBGFIsStepping(pVCpu))
2187#endif
2188 {
2189 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2190 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2191 {
2192 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2193 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2194 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2195 goto end;
2196 }
2197 }
2198
2199 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2200 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2201 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2202 {
2203 rc = VINF_EM_PENDING_REQUEST;
2204 goto end;
2205 }
2206
2207#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2208 /*
2209 * Exit to ring-3 preemption/work is pending.
2210 *
2211 * Interrupts are disabled before the call to make sure we don't miss any interrupt
2212 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
2213 * further down, but VMXR0CheckPendingInterrupt makes that impossible.)
2214 *
2215 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
2216 * shootdowns rely on this.
2217 */
2218 uOldEFlags = ASMIntDisableFlags();
2219 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2220 {
2221 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
2222 rc = VINF_EM_RAW_INTERRUPT;
2223 goto end;
2224 }
2225 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2226#endif
2227
2228 /* When external interrupts are pending, we should exit the VM when IF is set. */
2229 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2230 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2231 if (RT_FAILURE(rc))
2232 goto end;
2233
2234 /** @todo check timers?? */
2235
2236 /* TPR caching using CR8 is only available in 64 bits mode */
2237 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2238 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2239 /**
2240 * @todo query and update the TPR only when it could have been changed (mmio access & wrmsr (x2apic))
2241 */
2242 if (fSetupTPRCaching)
2243 {
2244 /* TPR caching in CR8 */
2245 bool fPending;
2246
2247 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
2248 AssertRC(rc);
2249 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2250 pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8LastTPR;
2251
2252 /* Two options here:
2253 * - external interrupt pending, but masked by the TPR value.
2254 * -> a CR8 update that lower the current TPR value should cause an exit
2255 * - no pending interrupts
2256 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2257 */
2258 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? (u8LastTPR >> 4) : 0); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
2259 AssertRC(rc);
2260 }
2261
2262#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2263 if ( pVM->hwaccm.s.fNestedPaging
2264# ifdef HWACCM_VTX_WITH_VPID
2265 || pVM->hwaccm.s.vmx.fVPID
2266# endif /* HWACCM_VTX_WITH_VPID */
2267 )
2268 {
2269 pCpu = HWACCMR0GetCurrentCpu();
2270 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2271 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2272 {
2273 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2274 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2275 else
2276 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2277 }
2278 if (pCpu->fFlushTLB)
2279 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2280 else
2281 if (pVCpu->hwaccm.s.fForceTLBFlush)
2282 LogFlow(("Manual TLB flush\n"));
2283 }
2284#endif
2285#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2286 PGMDynMapFlushAutoSet(pVCpu);
2287#endif
2288
2289 /*
2290 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2291 * (until the actual world switch)
2292 */
2293#ifdef VBOX_STRICT
2294 idCpuCheck = RTMpCpuId();
2295#endif
2296#ifdef LOG_ENABLED
2297 VMMR0LogFlushDisable(pVCpu);
2298#endif
2299 /* Save the host state first. */
2300 rc = VMXR0SaveHostState(pVM, pVCpu);
2301 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2302 {
2303 VMMR0LogFlushEnable(pVCpu);
2304 goto end;
2305 }
2306 /* Load the guest state */
2307 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2308 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2309 {
2310 VMMR0LogFlushEnable(pVCpu);
2311 goto end;
2312 }
2313
2314#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2315 /* Disable interrupts to make sure a poke will interrupt execution.
2316 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
2317 */
2318 uOldEFlags = ASMIntDisableFlags();
2319 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2320#endif
2321
2322 /* Deal with tagged TLB setup and invalidation. */
2323 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2324
2325 /* Non-register state Guest Context */
2326 /** @todo change me according to cpu state */
2327 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2328 AssertRC(rc);
2329
2330 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2331
2332 /* Manual save and restore:
2333 * - General purpose registers except RIP, RSP
2334 *
2335 * Trashed:
2336 * - CR2 (we don't care)
2337 * - LDTR (reset to 0)
2338 * - DRx (presumably not changed at all)
2339 * - DR7 (reset to 0x400)
2340 * - EFLAGS (reset to RT_BIT(1); not relevant)
2341 *
2342 */
2343
2344
2345 /* All done! Let's start VM execution. */
2346 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2347 Assert(idCpuCheck == RTMpCpuId());
2348
2349#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2350 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2351 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2352#endif
2353
2354 TMNotifyStartOfExecution(pVCpu);
2355#ifdef VBOX_WITH_KERNEL_USING_XMM
2356 rc = hwaccmR0VMXStartVMWrapXMM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hwaccm.s.vmx.pfnStartVM);
2357#else
2358 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2359#endif
2360 TMNotifyEndOfExecution(pVCpu);
2361 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2362 Assert(!(ASMGetFlags() & X86_EFL_IF));
2363 ASMSetFlags(uOldEFlags);
2364#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2365 uOldEFlags = ~(RTCCUINTREG)0;
2366#endif
2367
2368 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2369
2370 /* In case we execute a goto ResumeExecution later on. */
2371 pVCpu->hwaccm.s.fResumeVM = true;
2372 pVCpu->hwaccm.s.fForceTLBFlush = false;
2373
2374 /*
2375 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2376 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2377 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2378 */
2379 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2380 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2381
2382 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2383 {
2384 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2385 VMMR0LogFlushEnable(pVCpu);
2386 goto end;
2387 }
2388
2389 /* Success. Query the guest state and figure out what has happened. */
2390
2391 /* Investigate why there was a VM-exit. */
2392 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2393 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2394
2395 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2396 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2397 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2398 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2399 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2400 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2401 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2402 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2403 AssertRC(rc);
2404
2405 /* Sync back the guest state */
2406 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2407 AssertRC(rc);
2408
2409 /* Note! NOW IT'S SAFE FOR LOGGING! */
2410 VMMR0LogFlushEnable(pVCpu);
2411 Log2(("Raw exit reason %08x\n", exitReason));
2412
2413 /* Check if an injected event was interrupted prematurely. */
2414 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2415 AssertRC(rc);
2416 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2417 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2418 /* Ignore 'int xx' as they'll be restarted anyway. */
2419 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2420 /* Ignore software exceptions (such as int3) as they'll reoccur when we restart the instruction anyway. */
2421 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2422 {
2423 Assert(!pVCpu->hwaccm.s.Event.fPending);
2424 pVCpu->hwaccm.s.Event.fPending = true;
2425 /* Error code present? */
2426 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2427 {
2428 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2429 AssertRC(rc);
2430 pVCpu->hwaccm.s.Event.errCode = val;
2431 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2432 }
2433 else
2434 {
2435 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2436 pVCpu->hwaccm.s.Event.errCode = 0;
2437 }
2438 }
2439#ifdef VBOX_STRICT
2440 else
2441 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2442 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2443 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2444 {
2445 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2446 }
2447
2448 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2449 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2450#endif
2451
2452 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2453 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2454 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2455 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2456 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2457
2458 /* Sync back the TPR if it was changed. */
2459 if ( fSetupTPRCaching
2460 && u8LastTPR != pVCpu->hwaccm.s.vmx.pVAPIC[0x80])
2461 {
2462 rc = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80]);
2463 AssertRC(rc);
2464 }
2465
2466 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2467 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2468
2469 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2470 switch (exitReason)
2471 {
2472 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2473 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2474 {
2475 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2476
2477 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2478 {
2479 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2480 /* External interrupt; leave to allow it to be dispatched again. */
2481 rc = VINF_EM_RAW_INTERRUPT;
2482 break;
2483 }
2484 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2485 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2486 {
2487 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2488 /* External interrupt; leave to allow it to be dispatched again. */
2489 rc = VINF_EM_RAW_INTERRUPT;
2490 break;
2491
2492 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2493 AssertFailed(); /* can't come here; fails the first check. */
2494 break;
2495
2496 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2497 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2498 Assert(vector == 1 || vector == 3 || vector == 4);
2499 /* no break */
2500 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2501 Log2(("Hardware/software interrupt %d\n", vector));
2502 switch (vector)
2503 {
2504 case X86_XCPT_NM:
2505 {
2506 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2507
2508 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2509 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2510 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2511 if (rc == VINF_SUCCESS)
2512 {
2513 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2514
2515 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2516
2517 /* Continue execution. */
2518 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2519
2520 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2521 goto ResumeExecution;
2522 }
2523
2524 Log(("Forward #NM fault to the guest\n"));
2525 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2526 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2527 AssertRC(rc);
2528 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2529 goto ResumeExecution;
2530 }
2531
2532 case X86_XCPT_PF: /* Page fault */
2533 {
2534#ifdef DEBUG
2535 if (pVM->hwaccm.s.fNestedPaging)
2536 { /* A genuine pagefault.
2537 * Forward the trap to the guest by injecting the exception and resuming execution.
2538 */
2539 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2540
2541 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2542
2543 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2544
2545 /* Now we must update CR2. */
2546 pCtx->cr2 = exitQualification;
2547 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2548 AssertRC(rc);
2549
2550 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2551 goto ResumeExecution;
2552 }
2553#endif
2554 Assert(!pVM->hwaccm.s.fNestedPaging);
2555
2556 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2557 /* Exit qualification contains the linear address of the page fault. */
2558 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2559 TRPMSetErrorCode(pVCpu, errCode);
2560 TRPMSetFaultAddress(pVCpu, exitQualification);
2561
2562 /* Shortcut for APIC TPR reads and writes. */
2563 if ( (exitQualification & 0xfff) == 0x080
2564 && !(errCode & X86_TRAP_PF_P) /* not present */
2565 && fSetupTPRCaching
2566 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
2567 {
2568 RTGCPHYS GCPhysApicBase, GCPhys;
2569 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
2570 GCPhysApicBase &= PAGE_BASE_GC_MASK;
2571
2572 rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
2573 if ( rc == VINF_SUCCESS
2574 && GCPhys == GCPhysApicBase)
2575 {
2576 Log(("Enable VT-x virtual APIC access filtering\n"));
2577 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
2578 AssertRC(rc);
2579 }
2580 }
2581
2582 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2583 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2584 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2585 if (rc == VINF_SUCCESS)
2586 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2587 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2588 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2589
2590 TRPMResetTrap(pVCpu);
2591
2592 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2593 goto ResumeExecution;
2594 }
2595 else
2596 if (rc == VINF_EM_RAW_GUEST_TRAP)
2597 { /* A genuine pagefault.
2598 * Forward the trap to the guest by injecting the exception and resuming execution.
2599 */
2600 Log2(("Forward page fault to the guest\n"));
2601
2602 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2603 /* The error code might have been changed. */
2604 errCode = TRPMGetErrorCode(pVCpu);
2605
2606 TRPMResetTrap(pVCpu);
2607
2608 /* Now we must update CR2. */
2609 pCtx->cr2 = exitQualification;
2610 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2611 AssertRC(rc);
2612
2613 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2614 goto ResumeExecution;
2615 }
2616#ifdef VBOX_STRICT
2617 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2618 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2619#endif
2620 /* Need to go back to the recompiler to emulate the instruction. */
2621 TRPMResetTrap(pVCpu);
2622 break;
2623 }
2624
2625 case X86_XCPT_MF: /* Floating point exception. */
2626 {
2627 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2628 if (!(pCtx->cr0 & X86_CR0_NE))
2629 {
2630 /* old style FPU error reporting needs some extra work. */
2631 /** @todo don't fall back to the recompiler, but do it manually. */
2632 rc = VINF_EM_RAW_EMULATE_INSTR;
2633 break;
2634 }
2635 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2636 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2637 AssertRC(rc);
2638
2639 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2640 goto ResumeExecution;
2641 }
2642
2643 case X86_XCPT_DB: /* Debug exception. */
2644 {
2645 uint64_t uDR6;
2646
2647 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2648 *
2649 * Exit qualification bits:
2650 * 3:0 B0-B3 which breakpoint condition was met
2651 * 12:4 Reserved (0)
2652 * 13 BD - debug register access detected
2653 * 14 BS - single step execution or branch taken
2654 * 63:15 Reserved (0)
2655 */
2656 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2657
2658 /* Note that we don't support guest and host-initiated debugging at the same time. */
2659 Assert(DBGFIsStepping(pVCpu) || CPUMIsGuestInRealModeEx(pCtx) || CPUMIsHyperDebugStateActive(pVCpu));
2660
2661 uDR6 = X86_DR6_INIT_VAL;
2662 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2663 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
2664 if (rc == VINF_EM_RAW_GUEST_TRAP)
2665 {
2666 /** @todo this isn't working, but we'll never get here normally. */
2667
2668 /* Update DR6 here. */
2669 pCtx->dr[6] = uDR6;
2670
2671 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2672 pCtx->dr[7] &= ~X86_DR7_GD;
2673
2674 /* Paranoia. */
2675 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2676 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2677 pCtx->dr[7] |= 0x400; /* must be one */
2678
2679 /* Resync DR7 */
2680 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2681 AssertRC(rc);
2682
2683 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2684 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2685 AssertRC(rc);
2686
2687 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2688 goto ResumeExecution;
2689 }
2690 /* Return to ring 3 to deal with the debug exit code. */
2691 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2692 break;
2693 }
2694
2695 case X86_XCPT_BP: /* Breakpoint. */
2696 {
2697 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2698 if (rc == VINF_EM_RAW_GUEST_TRAP)
2699 {
2700 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2701 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2702 AssertRC(rc);
2703 goto ResumeExecution;
2704 }
2705 if (rc == VINF_SUCCESS)
2706 goto ResumeExecution;
2707 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2708 break;
2709 }
2710
2711 case X86_XCPT_GP: /* General protection failure exception.*/
2712 {
2713 uint32_t cbOp;
2714 uint32_t cbSize;
2715 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2716
2717 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2718#ifdef VBOX_STRICT
2719 if (!CPUMIsGuestInRealModeEx(pCtx))
2720 {
2721 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2722 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2723 AssertRC(rc);
2724 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2725 goto ResumeExecution;
2726 }
2727#endif
2728 Assert(CPUMIsGuestInRealModeEx(pCtx));
2729
2730 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2731
2732 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2733 if (RT_SUCCESS(rc))
2734 {
2735 bool fUpdateRIP = true;
2736
2737 Assert(cbOp == pDis->opsize);
2738 switch (pDis->pCurInstr->opcode)
2739 {
2740 case OP_CLI:
2741 pCtx->eflags.Bits.u1IF = 0;
2742 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2743 break;
2744
2745 case OP_STI:
2746 pCtx->eflags.Bits.u1IF = 1;
2747 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2748 break;
2749
2750 case OP_HLT:
2751 fUpdateRIP = false;
2752 rc = VINF_EM_HALT;
2753 pCtx->rip += pDis->opsize;
2754 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2755 break;
2756
2757 case OP_POPF:
2758 {
2759 RTGCPTR GCPtrStack;
2760 uint32_t cbParm;
2761 uint32_t uMask;
2762 X86EFLAGS eflags;
2763
2764 if (pDis->prefix & PREFIX_OPSIZE)
2765 {
2766 cbParm = 4;
2767 uMask = 0xffffffff;
2768 }
2769 else
2770 {
2771 cbParm = 2;
2772 uMask = 0xffff;
2773 }
2774
2775 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2776 if (RT_FAILURE(rc))
2777 {
2778 rc = VERR_EM_INTERPRETER;
2779 break;
2780 }
2781 eflags.u = 0;
2782 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2783 if (RT_FAILURE(rc))
2784 {
2785 rc = VERR_EM_INTERPRETER;
2786 break;
2787 }
2788 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2789 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
2790 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
2791 pCtx->eflags.Bits.u1RF = 0;
2792 pCtx->esp += cbParm;
2793 pCtx->esp &= uMask;
2794
2795 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2796 break;
2797 }
2798
2799 case OP_PUSHF:
2800 {
2801 RTGCPTR GCPtrStack;
2802 uint32_t cbParm;
2803 uint32_t uMask;
2804 X86EFLAGS eflags;
2805
2806 if (pDis->prefix & PREFIX_OPSIZE)
2807 {
2808 cbParm = 4;
2809 uMask = 0xffffffff;
2810 }
2811 else
2812 {
2813 cbParm = 2;
2814 uMask = 0xffff;
2815 }
2816
2817 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2818 if (RT_FAILURE(rc))
2819 {
2820 rc = VERR_EM_INTERPRETER;
2821 break;
2822 }
2823 eflags = pCtx->eflags;
2824 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2825 eflags.Bits.u1RF = 0;
2826 eflags.Bits.u1VM = 0;
2827
2828 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2829 if (RT_FAILURE(rc))
2830 {
2831 rc = VERR_EM_INTERPRETER;
2832 break;
2833 }
2834 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2835 pCtx->esp -= cbParm;
2836 pCtx->esp &= uMask;
2837 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2838 break;
2839 }
2840
2841 case OP_IRET:
2842 {
2843 RTGCPTR GCPtrStack;
2844 uint32_t uMask = 0xffff;
2845 uint16_t aIretFrame[3];
2846
2847 if (pDis->prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
2848 {
2849 rc = VERR_EM_INTERPRETER;
2850 break;
2851 }
2852
2853 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2854 if (RT_FAILURE(rc))
2855 {
2856 rc = VERR_EM_INTERPRETER;
2857 break;
2858 }
2859 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2860 if (RT_FAILURE(rc))
2861 {
2862 rc = VERR_EM_INTERPRETER;
2863 break;
2864 }
2865 pCtx->ip = aIretFrame[0];
2866 pCtx->cs = aIretFrame[1];
2867 pCtx->csHid.u64Base = pCtx->cs << 4;
2868 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2869 pCtx->sp += sizeof(aIretFrame);
2870
2871 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2872 fUpdateRIP = false;
2873 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2874 break;
2875 }
2876
2877 case OP_INT:
2878 {
2879 RTGCUINTPTR intInfo;
2880
2881 LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
2882 intInfo = pDis->param1.parval & 0xff;
2883 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2884 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2885
2886 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2887 AssertRC(rc);
2888 fUpdateRIP = false;
2889 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2890 break;
2891 }
2892
2893 case OP_INTO:
2894 {
2895 if (pCtx->eflags.Bits.u1OF)
2896 {
2897 RTGCUINTPTR intInfo;
2898
2899 LogFlow(("Realmode: INTO\n"));
2900 intInfo = X86_XCPT_OF;
2901 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2902 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2903
2904 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2905 AssertRC(rc);
2906 fUpdateRIP = false;
2907 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2908 }
2909 break;
2910 }
2911
2912 case OP_INT3:
2913 {
2914 RTGCUINTPTR intInfo;
2915
2916 LogFlow(("Realmode: INT 3\n"));
2917 intInfo = 3;
2918 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2919 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2920
2921 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2922 AssertRC(rc);
2923 fUpdateRIP = false;
2924 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2925 break;
2926 }
2927
2928 default:
2929 rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
2930 break;
2931 }
2932
2933 if (rc == VINF_SUCCESS)
2934 {
2935 if (fUpdateRIP)
2936 pCtx->rip += cbOp; /* Move on to the next instruction. */
2937
2938 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2939 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2940
2941 /* Only resume if successful. */
2942 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2943 goto ResumeExecution;
2944 }
2945 }
2946 else
2947 rc = VERR_EM_INTERPRETER;
2948
2949 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2950 break;
2951 }
2952
2953#ifdef VBOX_STRICT
2954 case X86_XCPT_DE: /* Divide error. */
2955 case X86_XCPT_UD: /* Unknown opcode exception. */
2956 case X86_XCPT_SS: /* Stack segment exception. */
2957 case X86_XCPT_NP: /* Segment not present exception. */
2958 {
2959 switch(vector)
2960 {
2961 case X86_XCPT_DE:
2962 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2963 break;
2964 case X86_XCPT_UD:
2965 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2966 break;
2967 case X86_XCPT_SS:
2968 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2969 break;
2970 case X86_XCPT_NP:
2971 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2972 break;
2973 }
2974
2975 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2976 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2977 AssertRC(rc);
2978
2979 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2980 goto ResumeExecution;
2981 }
2982#endif
2983 default:
2984#ifdef HWACCM_VMX_EMULATE_REALMODE
2985 if (CPUMIsGuestInRealModeEx(pCtx))
2986 {
2987 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2988 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2989 AssertRC(rc);
2990
2991 /* Go back to ring 3 in case of a triple fault. */
2992 if ( vector == X86_XCPT_DF
2993 && rc == VINF_EM_RESET)
2994 break;
2995
2996 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2997 goto ResumeExecution;
2998 }
2999#endif
3000 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
3001 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
3002 break;
3003 } /* switch (vector) */
3004
3005 break;
3006
3007 default:
3008 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
3009 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
3010 break;
3011 }
3012
3013 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
3014 break;
3015 }
3016
3017 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
3018 {
3019 RTGCPHYS GCPhys;
3020
3021 Assert(pVM->hwaccm.s.fNestedPaging);
3022
3023 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3024 AssertRC(rc);
3025 Assert(((exitQualification >> 7) & 3) != 2);
3026
3027 /* Determine the kind of violation. */
3028 errCode = 0;
3029 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
3030 errCode |= X86_TRAP_PF_ID;
3031
3032 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
3033 errCode |= X86_TRAP_PF_RW;
3034
3035 /* If the page is present, then it's a page level protection fault. */
3036 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
3037 {
3038 errCode |= X86_TRAP_PF_P;
3039 }
3040 else {
3041 /* Shortcut for APIC TPR reads and writes. */
3042 if ( (GCPhys & 0xfff) == 0x080
3043 && GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
3044 && fSetupTPRCaching
3045 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
3046 {
3047 RTGCPHYS GCPhysApicBase;
3048 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
3049 GCPhysApicBase &= PAGE_BASE_GC_MASK;
3050 if (GCPhys == GCPhysApicBase + 0x80)
3051 {
3052 Log(("Enable VT-x virtual APIC access filtering\n"));
3053 rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW | X86_PTE_P);
3054 AssertRC(rc);
3055 }
3056 }
3057 }
3058 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
3059
3060 /* GCPhys contains the guest physical address of the page fault. */
3061 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
3062 TRPMSetErrorCode(pVCpu, errCode);
3063 TRPMSetFaultAddress(pVCpu, GCPhys);
3064
3065 /* Handle the pagefault trap for the nested shadow table. */
3066 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
3067 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
3068 if (rc == VINF_SUCCESS)
3069 { /* We've successfully synced our shadow pages, so let's just continue execution. */
3070 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
3071 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
3072
3073 TRPMResetTrap(pVCpu);
3074
3075 goto ResumeExecution;
3076 }
3077
3078#ifdef VBOX_STRICT
3079 if (rc != VINF_EM_RAW_EMULATE_INSTR)
3080 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
3081#endif
3082 /* Need to go back to the recompiler to emulate the instruction. */
3083 TRPMResetTrap(pVCpu);
3084 break;
3085 }
3086
3087 case VMX_EXIT_EPT_MISCONFIG:
3088 {
3089 RTGCPHYS GCPhys;
3090
3091 Assert(pVM->hwaccm.s.fNestedPaging);
3092
3093 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3094 AssertRC(rc);
3095
3096 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
3097 break;
3098 }
3099
3100 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3101 /* Clear VM-exit on IF=1 change. */
3102 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
3103 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
3104 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3105 AssertRC(rc);
3106 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
3107 goto ResumeExecution; /* we check for pending guest interrupts there */
3108
3109 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
3110 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
3111 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
3112 /* Skip instruction and continue directly. */
3113 pCtx->rip += cbInstr;
3114 /* Continue execution.*/
3115 goto ResumeExecution;
3116
3117 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3118 {
3119 Log2(("VMX: Cpuid %x\n", pCtx->eax));
3120 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
3121 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3122 if (rc == VINF_SUCCESS)
3123 {
3124 /* Update EIP and continue execution. */
3125 Assert(cbInstr == 2);
3126 pCtx->rip += cbInstr;
3127 goto ResumeExecution;
3128 }
3129 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
3130 rc = VINF_EM_RAW_EMULATE_INSTR;
3131 break;
3132 }
3133
3134 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3135 {
3136 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
3137 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
3138 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3139 if (rc == VINF_SUCCESS)
3140 {
3141 /* Update EIP and continue execution. */
3142 Assert(cbInstr == 2);
3143 pCtx->rip += cbInstr;
3144 goto ResumeExecution;
3145 }
3146 rc = VINF_EM_RAW_EMULATE_INSTR;
3147 break;
3148 }
3149
3150 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3151 {
3152 Log2(("VMX: Rdtsc\n"));
3153 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
3154 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3155 if (rc == VINF_SUCCESS)
3156 {
3157 /* Update EIP and continue execution. */
3158 Assert(cbInstr == 2);
3159 pCtx->rip += cbInstr;
3160 goto ResumeExecution;
3161 }
3162 rc = VINF_EM_RAW_EMULATE_INSTR;
3163 break;
3164 }
3165
3166 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3167 {
3168 Log2(("VMX: invlpg\n"));
3169 Assert(!pVM->hwaccm.s.fNestedPaging);
3170
3171 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
3172 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
3173 if (rc == VINF_SUCCESS)
3174 {
3175 /* Update EIP and continue execution. */
3176 pCtx->rip += cbInstr;
3177 goto ResumeExecution;
3178 }
3179 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
3180 break;
3181 }
3182
3183 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3184 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3185 {
3186 uint32_t cbSize;
3187
3188 STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
3189
3190 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3191 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3192 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3193 if (rc == VINF_SUCCESS)
3194 {
3195 /* EIP has been updated already. */
3196
3197 /* Only resume if successful. */
3198 goto ResumeExecution;
3199 }
3200 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
3201 break;
3202 }
3203
3204 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3205 {
3206 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3207
3208 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3209 {
3210 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3211 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3212 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3213 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3214 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3215 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3216
3217 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3218 {
3219 case 0:
3220 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3221 break;
3222 case 2:
3223 break;
3224 case 3:
3225 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3226 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3227 break;
3228 case 4:
3229 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3230 break;
3231 case 8:
3232 /* CR8 contains the APIC TPR */
3233 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3234 break;
3235
3236 default:
3237 AssertFailed();
3238 break;
3239 }
3240 /* Check if a sync operation is pending. */
3241 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3242 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3243 {
3244 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3245 AssertRC(rc);
3246 }
3247 break;
3248
3249 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3250 Log2(("VMX: mov x, crx\n"));
3251 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3252
3253 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3254
3255 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3256 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3257
3258 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3259 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3260 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3261 break;
3262
3263 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3264 Log2(("VMX: clts\n"));
3265 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3266 rc = EMInterpretCLTS(pVM, pVCpu);
3267 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3268 break;
3269
3270 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3271 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3272 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3273 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3274 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3275 break;
3276 }
3277
3278 /* Update EIP if no error occurred. */
3279 if (RT_SUCCESS(rc))
3280 pCtx->rip += cbInstr;
3281
3282 if (rc == VINF_SUCCESS)
3283 {
3284 /* Only resume if successful. */
3285 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3286 goto ResumeExecution;
3287 }
3288 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3289 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3290 break;
3291 }
3292
3293 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3294 {
3295 if ( !DBGFIsStepping(pVCpu)
3296 && !CPUMIsHyperDebugStateActive(pVCpu))
3297 {
3298 /* Disable drx move intercepts. */
3299 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3300 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3301 AssertRC(rc);
3302
3303 /* Save the host and load the guest debug state. */
3304 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3305 AssertRC(rc);
3306
3307#ifdef VBOX_WITH_STATISTICS
3308 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3309 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3310 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3311 else
3312 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3313#endif
3314
3315 goto ResumeExecution;
3316 }
3317
3318 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3319 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3320 {
3321 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3322 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3323 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3324 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3325 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3326 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3327 Log2(("DR7=%08x\n", pCtx->dr[7]));
3328 }
3329 else
3330 {
3331 Log2(("VMX: mov x, drx\n"));
3332 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3333 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3334 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3335 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3336 }
3337 /* Update EIP if no error occurred. */
3338 if (RT_SUCCESS(rc))
3339 pCtx->rip += cbInstr;
3340
3341 if (rc == VINF_SUCCESS)
3342 {
3343 /* Only resume if successful. */
3344 goto ResumeExecution;
3345 }
3346 Assert(rc == VERR_EM_INTERPRETER);
3347 break;
3348 }
3349
3350 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3351 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3352 {
3353 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3354 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3355 uint32_t uPort;
3356 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3357
3358 /** @todo necessary to make the distinction? */
3359 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3360 {
3361 uPort = pCtx->edx & 0xffff;
3362 }
3363 else
3364 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3365
3366 /* paranoia */
3367 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3368 {
3369 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3370 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3371 break;
3372 }
3373
3374 uint32_t cbSize = g_aIOSize[uIOWidth];
3375
3376 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3377 {
3378 /* ins/outs */
3379 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
3380
3381 /* Disassemble manually to deal with segment prefixes. */
3382 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3383 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3384 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
3385 if (rc == VINF_SUCCESS)
3386 {
3387 if (fIOWrite)
3388 {
3389 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3390 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3391 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3392 }
3393 else
3394 {
3395 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3396 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3397 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3398 }
3399 }
3400 else
3401 rc = VINF_EM_RAW_EMULATE_INSTR;
3402 }
3403 else
3404 {
3405 /* normal in/out */
3406 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3407
3408 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3409
3410 if (fIOWrite)
3411 {
3412 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3413 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3414 if (rc == VINF_IOM_HC_IOPORT_WRITE)
3415 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pCtx->rip + cbInstr, uPort, uAndVal, cbSize);
3416 }
3417 else
3418 {
3419 uint32_t u32Val = 0;
3420
3421 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3422 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3423 if (IOM_SUCCESS(rc))
3424 {
3425 /* Write back to the EAX register. */
3426 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3427 }
3428 else
3429 if (rc == VINF_IOM_HC_IOPORT_READ)
3430 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pCtx->rip + cbInstr, uPort, uAndVal, cbSize);
3431 }
3432 }
3433 /*
3434 * Handled the I/O return codes.
3435 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3436 */
3437 if (IOM_SUCCESS(rc))
3438 {
3439 /* Update EIP and continue execution. */
3440 pCtx->rip += cbInstr;
3441 if (RT_LIKELY(rc == VINF_SUCCESS))
3442 {
3443 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3444 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3445 {
3446 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3447 for (unsigned i=0;i<4;i++)
3448 {
3449 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3450
3451 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3452 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3453 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3454 {
3455 uint64_t uDR6;
3456
3457 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3458
3459 uDR6 = ASMGetDR6();
3460
3461 /* Clear all breakpoint status flags and set the one we just hit. */
3462 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3463 uDR6 |= (uint64_t)RT_BIT(i);
3464
3465 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3466 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3467 * the contents have been read.
3468 */
3469 ASMSetDR6(uDR6);
3470
3471 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3472 pCtx->dr[7] &= ~X86_DR7_GD;
3473
3474 /* Paranoia. */
3475 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3476 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3477 pCtx->dr[7] |= 0x400; /* must be one */
3478
3479 /* Resync DR7 */
3480 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3481 AssertRC(rc);
3482
3483 /* Construct inject info. */
3484 intInfo = X86_XCPT_DB;
3485 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3486 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3487
3488 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3489 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3490 AssertRC(rc);
3491
3492 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3493 goto ResumeExecution;
3494 }
3495 }
3496 }
3497
3498 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3499 goto ResumeExecution;
3500 }
3501 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3502 break;
3503 }
3504
3505#ifdef VBOX_STRICT
3506 if (rc == VINF_IOM_HC_IOPORT_READ)
3507 Assert(!fIOWrite);
3508 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3509 Assert(fIOWrite);
3510 else
3511 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3512#endif
3513 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3514 break;
3515 }
3516
3517 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3518 LogFlow(("VMX_EXIT_TPR\n"));
3519 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3520 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3521 goto ResumeExecution;
3522
3523 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3524 {
3525 LogFlow(("VMX_EXIT_APIC_ACCESS\n"));
3526 unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
3527
3528 switch(uAccessType)
3529 {
3530 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
3531 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
3532 {
3533 RTGCPHYS GCPhys;
3534 PDMApicGetBase(pVM, &GCPhys);
3535 GCPhys &= PAGE_BASE_GC_MASK;
3536 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
3537
3538 LogFlow(("Apic access at %RGp\n", GCPhys));
3539 rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
3540 if (rc == VINF_SUCCESS)
3541 {
3542 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3543 goto ResumeExecution; /* rip already updated */
3544 }
3545 break;
3546 }
3547
3548 default:
3549 rc = VINF_EM_RAW_EMULATE_INSTR;
3550 break;
3551 }
3552 break;
3553 }
3554
3555 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3556 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3557 goto ResumeExecution;
3558
3559 default:
3560 /* The rest is handled after syncing the entire CPU state. */
3561 break;
3562 }
3563
3564 /* Note: the guest state isn't entirely synced back at this stage. */
3565
3566 /* Investigate why there was a VM-exit. (part 2) */
3567 switch (exitReason)
3568 {
3569 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3570 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3571 case VMX_EXIT_EPT_VIOLATION:
3572 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3573 /* Already handled above. */
3574 break;
3575
3576 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3577 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3578 break;
3579
3580 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3581 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3582 rc = VINF_EM_RAW_INTERRUPT;
3583 AssertFailed(); /* Can't happen. Yet. */
3584 break;
3585
3586 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3587 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3588 rc = VINF_EM_RAW_INTERRUPT;
3589 AssertFailed(); /* Can't happen afaik. */
3590 break;
3591
3592 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3593 rc = VERR_EM_INTERPRETER;
3594 break;
3595
3596 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3597 /** Check if external interrupts are pending; if so, don't switch back. */
3598 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
3599 pCtx->rip++; /* skip hlt */
3600 if ( pCtx->eflags.Bits.u1IF
3601 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3602 goto ResumeExecution;
3603
3604 rc = VINF_EM_HALT;
3605 break;
3606
3607 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3608 Log2(("VMX: mwait\n"));
3609 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
3610 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3611 if ( rc == VINF_EM_HALT
3612 || rc == VINF_SUCCESS)
3613 {
3614 /* Update EIP and continue execution. */
3615 pCtx->rip += cbInstr;
3616
3617 /** Check if external interrupts are pending; if so, don't switch back. */
3618 if ( rc == VINF_SUCCESS
3619 || ( rc == VINF_EM_HALT
3620 && pCtx->eflags.Bits.u1IF
3621 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
3622 )
3623 goto ResumeExecution;
3624 }
3625 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
3626 break;
3627
3628 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3629 AssertFailed(); /* can't happen. */
3630 rc = VERR_EM_INTERPRETER;
3631 break;
3632
3633 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3634 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3635 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3636 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3637 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3638 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3639 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3640 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3641 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3642 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3643 /** @todo inject #UD immediately */
3644 rc = VERR_EM_INTERPRETER;
3645 break;
3646
3647 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3648 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3649 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3650 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3651 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3652 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3653 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3654 /* already handled above */
3655 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3656 || rc == VINF_EM_RAW_INTERRUPT
3657 || rc == VERR_EM_INTERPRETER
3658 || rc == VINF_EM_RAW_EMULATE_INSTR
3659 || rc == VINF_PGM_SYNC_CR3
3660 || rc == VINF_IOM_HC_IOPORT_READ
3661 || rc == VINF_IOM_HC_IOPORT_WRITE
3662 || rc == VINF_EM_RAW_GUEST_TRAP
3663 || rc == VINF_TRPM_XCPT_DISPATCHED
3664 || rc == VINF_EM_RESCHEDULE_REM,
3665 ("rc = %d\n", rc));
3666 break;
3667
3668 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3669 case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3670 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3671 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3672 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3673 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3674 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3675 rc = VERR_EM_INTERPRETER;
3676 break;
3677
3678 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3679 Assert(rc == VINF_EM_RAW_INTERRUPT);
3680 break;
3681
3682 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3683 {
3684#ifdef VBOX_STRICT
3685 RTCCUINTREG val = 0;
3686
3687 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3688
3689 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3690 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3691
3692 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3693 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3694
3695 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3696 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3697
3698 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3699 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3700
3701 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3702 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3703
3704 VMX_LOG_SELREG(CS, "CS");
3705 VMX_LOG_SELREG(DS, "DS");
3706 VMX_LOG_SELREG(ES, "ES");
3707 VMX_LOG_SELREG(FS, "FS");
3708 VMX_LOG_SELREG(GS, "GS");
3709 VMX_LOG_SELREG(SS, "SS");
3710 VMX_LOG_SELREG(TR, "TR");
3711 VMX_LOG_SELREG(LDTR, "LDTR");
3712
3713 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3714 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3715 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3716 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3717#endif /* VBOX_STRICT */
3718 rc = VERR_VMX_INVALID_GUEST_STATE;
3719 break;
3720 }
3721
3722 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3723 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3724 default:
3725 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3726 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3727 break;
3728
3729 }
3730end:
3731
3732 /* Signal changes for the recompiler. */
3733 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3734
3735 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3736 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3737 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3738 {
3739 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3740 /* On the next entry we'll only sync the host context. */
3741 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3742 }
3743 else
3744 {
3745 /* On the next entry we'll sync everything. */
3746 /** @todo we can do better than this */
3747 /* Not in the VINF_PGM_CHANGE_MODE though! */
3748 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3749 }
3750
3751 /* translate into a less severe return code */
3752 if (rc == VERR_EM_INTERPRETER)
3753 rc = VINF_EM_RAW_EMULATE_INSTR;
3754 else
3755 /* Try to extract more information about what might have gone wrong here. */
3756 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3757 {
3758 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3759 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3760 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3761 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3762 }
3763
3764 /* Just set the correct state here instead of trying to catch every goto above. */
3765 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
3766
3767#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
3768 /* Restore interrupts if we exitted after disabling them. */
3769 if (uOldEFlags != ~(RTCCUINTREG)0)
3770 ASMSetFlags(uOldEFlags);
3771#endif
3772
3773 STAM_STATS({
3774 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3775 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3776 });
3777 Log2(("X"));
3778 return rc;
3779}
3780
3781
3782/**
3783 * Enters the VT-x session
3784 *
3785 * @returns VBox status code.
3786 * @param pVM The VM to operate on.
3787 * @param pVCpu The VMCPU to operate on.
3788 * @param pCpu CPU info struct
3789 */
3790VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3791{
3792 Assert(pVM->hwaccm.s.vmx.fSupported);
3793
3794 unsigned cr4 = ASMGetCR4();
3795 if (!(cr4 & X86_CR4_VMXE))
3796 {
3797 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3798 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3799 }
3800
3801 /* Activate the VM Control Structure. */
3802 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3803 if (RT_FAILURE(rc))
3804 return rc;
3805
3806 pVCpu->hwaccm.s.fResumeVM = false;
3807 return VINF_SUCCESS;
3808}
3809
3810
3811/**
3812 * Leaves the VT-x session
3813 *
3814 * @returns VBox status code.
3815 * @param pVM The VM to operate on.
3816 * @param pVCpu The VMCPU to operate on.
3817 * @param pCtx CPU context
3818 */
3819VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3820{
3821 Assert(pVM->hwaccm.s.vmx.fSupported);
3822
3823#ifdef DEBUG
3824 if (CPUMIsHyperDebugStateActive(pVCpu))
3825 {
3826 CPUMR0LoadHostDebugState(pVM, pVCpu);
3827 }
3828 else
3829#endif
3830 /* Save the guest debug state if necessary. */
3831 if (CPUMIsGuestDebugStateActive(pVCpu))
3832 {
3833 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3834
3835 /* Enable drx move intercepts again. */
3836 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3837 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3838 AssertRC(rc);
3839
3840 /* Resync the debug registers the next time. */
3841 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3842 }
3843 else
3844 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3845
3846 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3847 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3848 AssertRC(rc);
3849
3850 return VINF_SUCCESS;
3851}
3852
3853/**
3854 * Flush the TLB (EPT)
3855 *
3856 * @returns VBox status code.
3857 * @param pVM The VM to operate on.
3858 * @param pVCpu The VM CPU to operate on.
3859 * @param enmFlush Type of flush
3860 * @param GCPhys Physical address of the page to flush
3861 */
3862static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3863{
3864 uint64_t descriptor[2];
3865
3866 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3867 Assert(pVM->hwaccm.s.fNestedPaging);
3868 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3869 descriptor[1] = GCPhys;
3870 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3871 AssertRC(rc);
3872}
3873
3874#ifdef HWACCM_VTX_WITH_VPID
3875/**
3876 * Flush the TLB (EPT)
3877 *
3878 * @returns VBox status code.
3879 * @param pVM The VM to operate on.
3880 * @param pVCpu The VM CPU to operate on.
3881 * @param enmFlush Type of flush
3882 * @param GCPtr Virtual address of the page to flush
3883 */
3884static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3885{
3886#if HC_ARCH_BITS == 32
3887 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3888 if ( CPUMIsGuestInLongMode(pVCpu)
3889 && !VMX_IS_64BIT_HOST_MODE())
3890 {
3891 pVCpu->hwaccm.s.fForceTLBFlush = true;
3892 }
3893 else
3894#endif
3895 {
3896 uint64_t descriptor[2];
3897
3898 Assert(pVM->hwaccm.s.vmx.fVPID);
3899 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3900 descriptor[1] = GCPtr;
3901 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3902 AssertRC(rc);
3903 }
3904}
3905#endif /* HWACCM_VTX_WITH_VPID */
3906
3907/**
3908 * Invalidates a guest page
3909 *
3910 * @returns VBox status code.
3911 * @param pVM The VM to operate on.
3912 * @param pVCpu The VM CPU to operate on.
3913 * @param GCVirt Page to invalidate
3914 */
3915VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3916{
3917 bool fFlushPending = VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
3918
3919 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3920
3921 /* Only relevant if we want to use VPID.
3922 * In the nested paging case we still see such calls, but
3923 * can safely ignore them. (e.g. after cr3 updates)
3924 */
3925#ifdef HWACCM_VTX_WITH_VPID
3926 /* Skip it if a TLB flush is already pending. */
3927 if ( !fFlushPending
3928 && pVM->hwaccm.s.vmx.fVPID)
3929 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3930#endif /* HWACCM_VTX_WITH_VPID */
3931
3932 return VINF_SUCCESS;
3933}
3934
3935/**
3936 * Invalidates a guest page by physical address
3937 *
3938 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3939 *
3940 * @returns VBox status code.
3941 * @param pVM The VM to operate on.
3942 * @param pVCpu The VM CPU to operate on.
3943 * @param GCPhys Page to invalidate
3944 */
3945VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3946{
3947 bool fFlushPending = VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
3948
3949 Assert(pVM->hwaccm.s.fNestedPaging);
3950
3951 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3952
3953 /* Skip it if a TLB flush is already pending. */
3954 if (!fFlushPending)
3955 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3956
3957 return VINF_SUCCESS;
3958}
3959
3960/**
3961 * Report world switch error and dump some useful debug info
3962 *
3963 * @param pVM The VM to operate on.
3964 * @param pVCpu The VMCPU to operate on.
3965 * @param rc Return code
3966 * @param pCtx Current CPU context (not updated)
3967 */
3968static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3969{
3970 switch (rc)
3971 {
3972 case VERR_VMX_INVALID_VMXON_PTR:
3973 AssertFailed();
3974 break;
3975
3976 case VERR_VMX_UNABLE_TO_START_VM:
3977 case VERR_VMX_UNABLE_TO_RESUME_VM:
3978 {
3979 int rc;
3980 RTCCUINTREG exitReason, instrError;
3981
3982 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3983 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3984 AssertRC(rc);
3985 if (rc == VINF_SUCCESS)
3986 {
3987 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3988 Log(("Current stack %08x\n", &rc));
3989
3990 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3991 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3992
3993#ifdef VBOX_STRICT
3994 RTGDTR gdtr;
3995 PX86DESCHC pDesc;
3996 RTCCUINTREG val;
3997
3998 ASMGetGDTR(&gdtr);
3999
4000 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
4001 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
4002 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
4003 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
4004 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
4005 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
4006 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
4007 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
4008 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
4009 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
4010
4011 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
4012 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
4013
4014 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
4015 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
4016
4017 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
4018 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
4019
4020 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
4021 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
4022
4023 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
4024 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
4025
4026 if (val < gdtr.cbGdt)
4027 {
4028 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4029 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
4030 }
4031
4032 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
4033 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
4034 if (val < gdtr.cbGdt)
4035 {
4036 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4037 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
4038 }
4039
4040 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
4041 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
4042 if (val < gdtr.cbGdt)
4043 {
4044 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4045 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
4046 }
4047
4048 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
4049 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
4050 if (val < gdtr.cbGdt)
4051 {
4052 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4053 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
4054 }
4055
4056 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
4057 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
4058 if (val < gdtr.cbGdt)
4059 {
4060 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4061 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
4062 }
4063
4064 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
4065 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
4066 if (val < gdtr.cbGdt)
4067 {
4068 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4069 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
4070 }
4071
4072 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
4073 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
4074 if (val < gdtr.cbGdt)
4075 {
4076 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4077 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
4078 }
4079
4080 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
4081 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
4082
4083 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
4084 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
4085 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
4086 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
4087
4088 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
4089 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
4090
4091 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
4092 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
4093
4094 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
4095 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
4096
4097 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
4098 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
4099 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
4100 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
4101
4102# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4103 if (VMX_IS_64BIT_HOST_MODE())
4104 {
4105 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
4106 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
4107 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
4108 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
4109 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
4110 }
4111# endif
4112#endif /* VBOX_STRICT */
4113 }
4114 break;
4115 }
4116
4117 default:
4118 /* impossible */
4119 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
4120 break;
4121 }
4122}
4123
4124#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4125/**
4126 * Prepares for and executes VMLAUNCH (64 bits guest mode)
4127 *
4128 * @returns VBox status code
4129 * @param fResume vmlauch/vmresume
4130 * @param pCtx Guest context
4131 * @param pCache VMCS cache
4132 * @param pVM The VM to operate on.
4133 * @param pVCpu The VMCPU to operate on.
4134 */
4135DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
4136{
4137 uint32_t aParam[6];
4138 PHWACCM_CPUINFO pCpu;
4139 RTHCPHYS pPageCpuPhys;
4140 int rc;
4141
4142 pCpu = HWACCMR0GetCurrentCpu();
4143 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4144
4145#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4146 pCache->uPos = 1;
4147 pCache->interPD = PGMGetInterPaeCR3(pVM);
4148 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
4149#endif
4150
4151#ifdef DEBUG
4152 pCache->TestIn.pPageCpuPhys = 0;
4153 pCache->TestIn.pVMCSPhys = 0;
4154 pCache->TestIn.pCache = 0;
4155 pCache->TestOut.pVMCSPhys = 0;
4156 pCache->TestOut.pCache = 0;
4157 pCache->TestOut.pCtx = 0;
4158 pCache->TestOut.eflags = 0;
4159#endif
4160
4161 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
4162 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
4163 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
4164 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
4165 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
4166 aParam[5] = 0;
4167
4168#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4169 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
4170 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
4171#endif
4172 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
4173
4174#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4175 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
4176 Assert(pCtx->dr[4] == 10);
4177 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
4178#endif
4179
4180#ifdef DEBUG
4181 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
4182 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
4183 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
4184 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
4185 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
4186 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
4187 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
4188#endif
4189 return rc;
4190}
4191
4192/**
4193 * Executes the specified handler in 64 mode
4194 *
4195 * @returns VBox status code.
4196 * @param pVM The VM to operate on.
4197 * @param pVCpu The VMCPU to operate on.
4198 * @param pCtx Guest context
4199 * @param pfnHandler RC handler
4200 * @param cbParam Number of parameters
4201 * @param paParam Array of 32 bits parameters
4202 */
4203VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
4204{
4205 int rc, rc2;
4206 PHWACCM_CPUINFO pCpu;
4207 RTHCPHYS pPageCpuPhys;
4208
4209 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
4210 AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
4211 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
4212 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
4213 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
4214
4215#ifdef VBOX_STRICT
4216 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
4217 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
4218
4219 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
4220 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
4221#endif
4222
4223 pCpu = HWACCMR0GetCurrentCpu();
4224 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4225
4226 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4227 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4228
4229 /* Leave VMX Root Mode. */
4230 VMXDisable();
4231
4232 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4233
4234 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
4235 CPUMSetHyperEIP(pVCpu, pfnHandler);
4236 for (int i=(int)cbParam-1;i>=0;i--)
4237 CPUMPushHyper(pVCpu, paParam[i]);
4238
4239 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4240 /* Call switcher. */
4241 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
4242 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4243
4244 /* Make sure the VMX instructions don't cause #UD faults. */
4245 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
4246
4247 /* Enter VMX Root Mode */
4248 rc2 = VMXEnable(pPageCpuPhys);
4249 if (RT_FAILURE(rc2))
4250 {
4251 if (pVM)
4252 VMXR0CheckError(pVM, pVCpu, rc2);
4253 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4254 return VERR_VMX_VMXON_FAILED;
4255 }
4256
4257 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4258 AssertRCReturn(rc2, rc2);
4259 Assert(!(ASMGetFlags() & X86_EFL_IF));
4260 return rc;
4261}
4262
4263#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4264
4265
4266#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4267/**
4268 * Executes VMWRITE
4269 *
4270 * @returns VBox status code
4271 * @param pVCpu The VMCPU to operate on.
4272 * @param idxField VMCS index
4273 * @param u64Val 16, 32 or 64 bits value
4274 */
4275VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4276{
4277 int rc;
4278
4279 switch (idxField)
4280 {
4281 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4282 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4283 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4284 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4285 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4286 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4287 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4288 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4289 case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
4290 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4291 case VMX_VMCS_GUEST_PDPTR0_FULL:
4292 case VMX_VMCS_GUEST_PDPTR1_FULL:
4293 case VMX_VMCS_GUEST_PDPTR2_FULL:
4294 case VMX_VMCS_GUEST_PDPTR3_FULL:
4295 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4296 case VMX_VMCS_GUEST_EFER_FULL:
4297 case VMX_VMCS_CTRL_EPTP_FULL:
4298 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4299 rc = VMXWriteVMCS32(idxField, u64Val);
4300 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4301 AssertRC(rc);
4302 return rc;
4303
4304 case VMX_VMCS64_GUEST_LDTR_BASE:
4305 case VMX_VMCS64_GUEST_TR_BASE:
4306 case VMX_VMCS64_GUEST_GDTR_BASE:
4307 case VMX_VMCS64_GUEST_IDTR_BASE:
4308 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4309 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4310 case VMX_VMCS64_GUEST_CR0:
4311 case VMX_VMCS64_GUEST_CR4:
4312 case VMX_VMCS64_GUEST_CR3:
4313 case VMX_VMCS64_GUEST_DR7:
4314 case VMX_VMCS64_GUEST_RIP:
4315 case VMX_VMCS64_GUEST_RSP:
4316 case VMX_VMCS64_GUEST_CS_BASE:
4317 case VMX_VMCS64_GUEST_DS_BASE:
4318 case VMX_VMCS64_GUEST_ES_BASE:
4319 case VMX_VMCS64_GUEST_FS_BASE:
4320 case VMX_VMCS64_GUEST_GS_BASE:
4321 case VMX_VMCS64_GUEST_SS_BASE:
4322 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4323 if (u64Val >> 32ULL)
4324 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4325 else
4326 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4327
4328 return rc;
4329
4330 default:
4331 AssertMsgFailed(("Unexpected field %x\n", idxField));
4332 return VERR_INVALID_PARAMETER;
4333 }
4334}
4335
4336/**
4337 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4338 *
4339 * @param pVCpu The VMCPU to operate on.
4340 * @param idxField VMCS field
4341 * @param u64Val Value
4342 */
4343VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4344{
4345 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4346
4347 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4348
4349 /* Make sure there are no duplicates. */
4350 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4351 {
4352 if (pCache->Write.aField[i] == idxField)
4353 {
4354 pCache->Write.aFieldVal[i] = u64Val;
4355 return VINF_SUCCESS;
4356 }
4357 }
4358
4359 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4360 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4361 pCache->Write.cValidEntries++;
4362 return VINF_SUCCESS;
4363}
4364
4365#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4366
4367#ifdef VBOX_STRICT
4368static bool vmxR0IsValidReadField(uint32_t idxField)
4369{
4370 switch(idxField)
4371 {
4372 case VMX_VMCS64_GUEST_RIP:
4373 case VMX_VMCS64_GUEST_RSP:
4374 case VMX_VMCS_GUEST_RFLAGS:
4375 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4376 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4377 case VMX_VMCS64_GUEST_CR0:
4378 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4379 case VMX_VMCS64_GUEST_CR4:
4380 case VMX_VMCS64_GUEST_DR7:
4381 case VMX_VMCS32_GUEST_SYSENTER_CS:
4382 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4383 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4384 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4385 case VMX_VMCS64_GUEST_GDTR_BASE:
4386 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4387 case VMX_VMCS64_GUEST_IDTR_BASE:
4388 case VMX_VMCS16_GUEST_FIELD_CS:
4389 case VMX_VMCS32_GUEST_CS_LIMIT:
4390 case VMX_VMCS64_GUEST_CS_BASE:
4391 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4392 case VMX_VMCS16_GUEST_FIELD_DS:
4393 case VMX_VMCS32_GUEST_DS_LIMIT:
4394 case VMX_VMCS64_GUEST_DS_BASE:
4395 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4396 case VMX_VMCS16_GUEST_FIELD_ES:
4397 case VMX_VMCS32_GUEST_ES_LIMIT:
4398 case VMX_VMCS64_GUEST_ES_BASE:
4399 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4400 case VMX_VMCS16_GUEST_FIELD_FS:
4401 case VMX_VMCS32_GUEST_FS_LIMIT:
4402 case VMX_VMCS64_GUEST_FS_BASE:
4403 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4404 case VMX_VMCS16_GUEST_FIELD_GS:
4405 case VMX_VMCS32_GUEST_GS_LIMIT:
4406 case VMX_VMCS64_GUEST_GS_BASE:
4407 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4408 case VMX_VMCS16_GUEST_FIELD_SS:
4409 case VMX_VMCS32_GUEST_SS_LIMIT:
4410 case VMX_VMCS64_GUEST_SS_BASE:
4411 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4412 case VMX_VMCS16_GUEST_FIELD_LDTR:
4413 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4414 case VMX_VMCS64_GUEST_LDTR_BASE:
4415 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4416 case VMX_VMCS16_GUEST_FIELD_TR:
4417 case VMX_VMCS32_GUEST_TR_LIMIT:
4418 case VMX_VMCS64_GUEST_TR_BASE:
4419 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4420 case VMX_VMCS32_RO_EXIT_REASON:
4421 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4422 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4423 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4424 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4425 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4426 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4427 case VMX_VMCS32_RO_IDT_INFO:
4428 case VMX_VMCS32_RO_IDT_ERRCODE:
4429 case VMX_VMCS64_GUEST_CR3:
4430 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4431 return true;
4432 }
4433 return false;
4434}
4435
4436static bool vmxR0IsValidWriteField(uint32_t idxField)
4437{
4438 switch(idxField)
4439 {
4440 case VMX_VMCS64_GUEST_LDTR_BASE:
4441 case VMX_VMCS64_GUEST_TR_BASE:
4442 case VMX_VMCS64_GUEST_GDTR_BASE:
4443 case VMX_VMCS64_GUEST_IDTR_BASE:
4444 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4445 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4446 case VMX_VMCS64_GUEST_CR0:
4447 case VMX_VMCS64_GUEST_CR4:
4448 case VMX_VMCS64_GUEST_CR3:
4449 case VMX_VMCS64_GUEST_DR7:
4450 case VMX_VMCS64_GUEST_RIP:
4451 case VMX_VMCS64_GUEST_RSP:
4452 case VMX_VMCS64_GUEST_CS_BASE:
4453 case VMX_VMCS64_GUEST_DS_BASE:
4454 case VMX_VMCS64_GUEST_ES_BASE:
4455 case VMX_VMCS64_GUEST_FS_BASE:
4456 case VMX_VMCS64_GUEST_GS_BASE:
4457 case VMX_VMCS64_GUEST_SS_BASE:
4458 return true;
4459 }
4460 return false;
4461}
4462
4463#endif
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