HWVMXR0.cpp@ 2733

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1	/* $Id: HWVMXR0.cpp 2699 2007-05-17 15:18:06Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include "HWVMXR0.h"
41
42
43	/* IO operation lookup arrays. */
44	static uint32_t aIOSize[4] = {1, 2, 0, 4};
45	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
46
47
48	/**
49	* Sets up and activates VMX
50	*
51	* @returns VBox status code.
52	* @param pVM The VM to operate on.
53	*/
54	HWACCMR0DECL(int) VMXR0Setup(PVM pVM)
55	{
56	int rc = VINF_SUCCESS;
57	uint32_t val;
58
59	if (pVM == NULL)
60	return VERR_INVALID_PARAMETER;
61
62	/* Setup Intel VMX. */
63	Assert(pVM->hwaccm.s.vmx.fSupported);
64
65	/* Set revision dword at the beginning of both structures. */
66	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
67	(uint32_t )pVM->hwaccm.s.vmx.pVMXON = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
68
69	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
70	* (which can have very bad consequences!!!)
71	*/
72
73	/* Make sure the VMX instructions don't cause #UD faults. */
74	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
75
76	/* Enter VMX Root Mode */
77	rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
78	if (VBOX_FAILURE(rc))
79	{
80	return rc;
81	}
82
83	/* Clear VM Control Structure. */
84	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
85	if (VBOX_FAILURE(rc))
86	goto vmx_end;
87
88	/* Activate the VM Control Structure. */
89	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
90	if (VBOX_FAILURE(rc))
91	goto vmx_end;
92
93	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
94	* Set required bits to one and zero according to the MSR capabilities.
95	*/
96	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
97	/* External and non-maskable interrupts cause VM-exits. */
98	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
99	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
100
101	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
102	AssertRC(rc);
103
104	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
105	* Set required bits to one and zero according to the MSR capabilities.
106	*/
107	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
108	/* Program which event cause VM-exits and which features we want to use. */
109	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
110	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
111	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
112	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
113	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
114	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
115
116	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
117
118	/*
119	if AMD64 guest mode
120	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
121	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
122	*/
123	/* Mask away the bits that the CPU doesn't support */
124	/** @todo make sure they don't conflict with the above requirements. */
125	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
126	pVM->hwaccm.s.vmx.proc_ctls = val;
127
128	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
129	AssertRC(rc);
130
131	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
132	* Set required bits to one and zero according to the MSR capabilities.
133	*/
134	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
135	AssertRC(rc);
136
137	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
138	* Set required bits to one and zero according to the MSR capabilities.
139	*/
140	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
141	if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
142	{
143	/** @todo 32 bits guest mode only for now. */
144	/* val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
145	}
146	/* Mask away the bits that the CPU doesn't support */
147	/** @todo make sure they don't conflict with the above requirements. */
148	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
149	/* else Must be zero when AMD64 is not available. */
150	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
151	AssertRC(rc);
152
153	/* VMX_VMCS_CTRL_EXIT_CONTROLS
154	* Set required bits to one and zero according to the MSR capabilities.
155	*/
156	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
157	#if HC_ARCH_BITS == 64
158	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
159	#else
160	/* else Must be zero when AMD64 is not available. */
161	#endif
162	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
163	/* Don't acknowledge external interrupts on VM-exit. */
164	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
165	AssertRC(rc);
166
167	/* Forward all exception except #NM & #PF to the guest.
168	* We always need to check pagefaults since our shadow page table can be out of sync.
169	* And we always lazily sync the FPU & XMM state.
170	*/
171
172	/*
173	* @todo Possible optimization:
174	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
175	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
176	* registers ourselves of course.
177	*
178	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
179	*/
180	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
181	AssertRC(rc);
182
183	/* Don't filter page faults; all of them should cause a switch. */
184	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
185	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
186	AssertRC(rc);
187
188	/* Init TSC offset to zero. */
189	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
190	#if HC_ARCH_BITS == 32
191	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
192	#endif
193	AssertRC(rc);
194
195	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
196	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
197	AssertRC(rc);
198
199	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
200	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
201	AssertRC(rc);
202
203	/* Clear MSR controls. */
204	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
205	{
206	/* Optional */
207	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
208	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
209	AssertRC(rc);
210	}
211	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
212	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
213	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
214	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
215	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
216	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH, 0);
217	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
218	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
219	AssertRC(rc);
220
221	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
222	{
223	/* Optional */
224	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
225	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
226	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
227	AssertRC(rc);
228	}
229
230	/* Set link pointer to -1. Not currently used. */
231	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
232	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
233	AssertRC(rc);
234
235	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
236	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
237	AssertRC(rc);
238
239	vmx_end:
240	/* Leave VMX Root Mode. */
241	VMXDisable();
242	return rc;
243	}
244
245
246	/**
247	* Injects an event (trap or external interrupt)
248	*
249	* @returns VBox status code.
250	* @param pVM The VM to operate on.
251	* @param pCtx CPU Context
252	* @param intInfo VMX interrupt info
253	* @param cbInstr Opcode length of faulting instruction
254	* @param errCode Error code (optional)
255	*/
256	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
257	{
258	int rc;
259
260	#ifdef VBOX_STRICT
261	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
262	if (iGate == 0xE)
263	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
264	else
265	if (iGate < 0x20)
266	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
267	else
268	{
269	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
270	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
271	Assert(pCtx->eflags.u32 & X86_EFL_IF);
272	}
273	#endif
274
275	/* Set event injection state. */
276	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
277	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
278	);
279
280	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
281	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
282
283	AssertRC(rc);
284	return rc;
285	}
286
287
288	/**
289	* Checks for pending guest interrupts and injects them
290	*
291	* @returns VBox status code.
292	* @param pVM The VM to operate on.
293	* @param pCtx CPU Context
294	*/
295	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
296	{
297	int rc;
298
299	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
300	if (pVM->hwaccm.s.Event.fPending)
301	{
302	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
303	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
304	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
305	AssertRC(rc);
306
307	pVM->hwaccm.s.Event.fPending = false;
308	return VINF_SUCCESS;
309	}
310
311	/* When external interrupts are pending, we should exit the VM when IF is set. */
312	if ( !TRPMHasTrap(pVM)
313	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
314	{
315	if (!(pCtx->eflags.u32 & X86_EFL_IF))
316	{
317	Log2(("Enable irq window exit!\n"));
318	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT);
319	AssertRC(rc);
320	}
321	else
322	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
323	{
324	uint8_t u8Interrupt;
325
326	rc = PDMGetInterrupt(pVM, &u8Interrupt);
327	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
328	if (VBOX_SUCCESS(rc))
329	{
330	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
331	AssertRC(rc);
332	}
333	else
334	{
335	/* can't happen... */
336	AssertFailed();
337	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
338	return VINF_EM_RAW_INTERRUPT_PENDING;
339	}
340	}
341	else
342	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
343	}
344
345	#ifdef VBOX_STRICT
346	if (TRPMHasTrap(pVM))
347	{
348	uint8_t u8Vector;
349	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
350	AssertRC(rc);
351	}
352	#endif
353
354	if ( pCtx->eflags.u32 & X86_EFL_IF
355	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
356	&& TRPMHasTrap(pVM)
357	)
358	{
359	uint8_t u8Vector;
360	int rc;
361	TRPMEVENT enmType;
362	RTGCUINTPTR intInfo, errCode;
363
364	/* If a new event is pending, then dispatch it now. */
365	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
366	AssertRC(rc);
367	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
368	Assert(enmType != TRPM_SOFTWARE_INT);
369
370	/* Clear the pending trap. */
371	rc = TRPMResetTrap(pVM);
372	AssertRC(rc);
373
374	intInfo = u8Vector;
375	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
376
377	if (enmType == TRPM_TRAP)
378	{
379	switch (u8Vector) {
380	case 8:
381	case 10:
382	case 11:
383	case 12:
384	case 13:
385	case 14:
386	case 17:
387	/* Valid error codes. */
388	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
389	break;
390	default:
391	break;
392	}
393	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
394	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
395	else
396	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
397	}
398	else
399	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
400
401	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
402	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
403	AssertRC(rc);
404	} /* if (interrupts can be dispatched) */
405
406	return VINF_SUCCESS;
407	}
408
409	/**
410	* Save the host state
411	*
412	* @returns VBox status code.
413	* @param pVM The VM to operate on.
414	*/
415	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
416	{
417	int rc = VINF_SUCCESS;
418
419	/*
420	* Host CPU Context
421	*/
422	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
423	{
424	RTIDTR idtr;
425	RTGDTR gdtr;
426	RTSEL SelTR;
427	PVBOXDESC pDesc;
428	uintptr_t trBase;
429
430	/* Control registers */
431	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
432	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
433	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
434	AssertRC(rc);
435	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
436	Log2(("VMX_VMCS_HOST_CR3 %08x\n", ASMGetCR3()));
437	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
438
439	/* Selector registers. */
440	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
441	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
442	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
443	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
444	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
445	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
446	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
447	SelTR = ASMGetTR();
448	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
449	AssertRC(rc);
450	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
451	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
452	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
453	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
454	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
455	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
456	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
457
458	/* GDTR & IDTR */
459	ASMGetGDTR(&gdtr);
460	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
461	ASMGetIDTR(&idtr);
462	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
463	AssertRC(rc);
464	Log2(("VMX_VMCS_HOST_GDTR_BASE %VGv\n", gdtr.pGdt));
465	Log2(("VMX_VMCS_HOST_IDTR_BASE %VGv\n", idtr.pIdt));
466
467	/* Save the base address of the TR selector. */
468	if (SelTR > gdtr.cbGdt)
469	{
470	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
471	return VERR_VMX_INVALID_HOST_STATE;
472	}
473
474	pDesc = &((PVBOXDESC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT];
475	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16) \| (pDesc->Gen.u8BaseHigh2 << 24);
476	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
477	AssertRC(rc);
478	Log2(("VMX_VMCS_HOST_TR_BASE %VGv\n", trBase));
479
480	/* FS and GS base. */
481	#if HC_ARCH_BITS == 32
482	rc = VMXWriteVMCS(VMX_VMCS_HOST_FS_BASE, 0);
483	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_GS_BASE, 0);
484	#else
485	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
486	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
487	#endif
488	AssertRC(rc);
489
490	/* Sysenter MSRs. */
491	/** @todo expensive!! */
492	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
493	#if HC_ARCH_BITS == 32
494	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
495	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
496	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
497	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VGv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
498	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VGv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
499	#else
500	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
501	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
502	#endif
503	AssertRC(rc);
504
505	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
506	}
507	return rc;
508	}
509
510
511	/**
512	* Loads the guest state
513	*
514	* @returns VBox status code.
515	* @param pVM The VM to operate on.
516	* @param pCtx Guest context
517	*/
518	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
519	{
520	int rc = VINF_SUCCESS;
521	RTGCUINTPTR val;
522
523	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
524	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
525	{
526	VMX_WRITE_SELREG(ES, es);
527	AssertRC(rc);
528
529	VMX_WRITE_SELREG(CS, cs);
530	AssertRC(rc);
531
532	VMX_WRITE_SELREG(SS, ss);
533	AssertRC(rc);
534
535	VMX_WRITE_SELREG(DS, ds);
536	AssertRC(rc);
537
538	VMX_WRITE_SELREG(FS, fs);
539	AssertRC(rc);
540
541	VMX_WRITE_SELREG(GS, gs);
542	AssertRC(rc);
543	}
544
545	/* Guest CPU context: LDTR. */
546	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
547	{
548	if (pCtx->ldtr == 0)
549	{
550	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
551	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
552	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
553	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
554	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
555	}
556	else
557	{
558	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
559	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
560	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
561	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
562	}
563	AssertRC(rc);
564	}
565	/* Guest CPU context: TR. */
566	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
567	{
568	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
569	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
570	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
571	val = pCtx->trHid.Attr.u;
572
573	/* The TSS selector must be busy. */
574	if ((val & 0xF) == X86_SEL_TYPE_SYS_386_TSS_AVAIL)
575	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
576	else
577	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
578	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
579
580	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
581	AssertRC(rc);
582	}
583	/* Guest CPU context: GDTR. */
584	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
585	{
586	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
587	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
588	AssertRC(rc);
589	}
590	/* Guest CPU context: IDTR. */
591	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
592	{
593	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
594	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
595	AssertRC(rc);
596	}
597
598	/*
599	* Sysenter MSRs
600	*/
601	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
602	{
603	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
604	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
605	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
606	AssertRC(rc);
607	}
608
609	/* Control registers */
610	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
611	{
612	val = pCtx->cr0;
613	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
614	Log2(("Guest CR0-shadow %08x\n", val));
615	if (CPUMIsGuestFPUStateActive(pVM) == false)
616	{
617	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
618	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
619	}
620	else
621	{
622	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
623	/** @todo check if we support the old style mess correctly. */
624	if (!(val & X86_CR0_NE))
625	{
626	Log(("Forcing X86_CR0_NE!!!\n"));
627
628	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
629	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
630	{
631	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| BIT(16));
632	AssertRC(rc);
633	pVM->hwaccm.s.fFPUOldStyleOverride = true;
634	}
635	}
636
637	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
638	}
639	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
640	Log2(("Guest CR0 %08x\n", val));
641	/* CR0 flags owned by the host; if the guests attempts to change them, then
642	* the VM will exit.
643	*/
644	val = X86_CR0_PE
645	\| X86_CR0_WP /** @todo do we care? (we do if we start patching the guest) */
646	\| X86_CR0_PG
647	\| X86_CR0_TS
648	\| X86_CR0_ET
649	\| X86_CR0_NE
650	\| X86_CR0_MP;
651	pVM->hwaccm.s.vmx.cr0_mask = val;
652
653	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
654	Log2(("Guest CR0-mask %08x\n", val));
655	AssertRC(rc);
656	}
657	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
658	{
659	/* CR4 */
660	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
661	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
662	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
663	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
664	switch(pVM->hwaccm.s.enmShadowMode)
665	{
666	case PGMMODE_REAL:
667	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
668	AssertFailed();
669	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
670
671	case PGMMODE_32_BIT: /* 32-bit paging. */
672	break;
673
674	case PGMMODE_PAE: /* PAE paging. */
675	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
676	/** @todo use normal 32 bits paging */
677	val \|= X86_CR4_PAE;
678	break;
679
680	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
681	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
682	AssertFailed();
683	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
684
685	default: /* shut up gcc */
686	AssertFailed();
687	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
688	}
689	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
690	Log2(("Guest CR4 %08x\n", val));
691	/* CR4 flags owned by the host; if the guests attempts to change them, then
692	* the VM will exit.
693	*/
694	val = X86_CR4_PAE
695	\| X86_CR4_PGE
696	\| X86_CR4_PSE
697	\| X86_CR4_VMXE;
698	pVM->hwaccm.s.vmx.cr4_mask = val;
699
700	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
701	Log2(("Guest CR4-mask %08x\n", val));
702	AssertRC(rc);
703	}
704
705	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
706	{
707	/* Save our shadow CR3 register. */
708	val = PGMGetHyperCR3(pVM);
709	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
710	AssertRC(rc);
711	}
712
713	/* Debug registers. */
714	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
715	{
716	/** @todo DR0-6 */
717	val = pCtx->dr7;
718	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
719	val \|= 0x400; /* must be one */
720	#ifdef VBOX_STRICT
721	val = 0x400;
722	#endif
723	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
724	AssertRC(rc);
725
726	/* IA32_DEBUGCTL MSR. */
727	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
728	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
729	AssertRC(rc);
730
731	/** @todo */
732	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
733	AssertRC(rc);
734	}
735
736	/* EIP, ESP and EFLAGS */
737	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
738	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
739	AssertRC(rc);
740
741	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
742	val = pCtx->eflags.u32;
743	val &= VMX_EFLAGS_RESERVED_0;
744	val \|= VMX_EFLAGS_RESERVED_1;
745	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, val);
746	AssertRC(rc);
747
748	/** TSC offset. */
749	/** @todo use host tsc if safe, other intercept rdtsc */
750	uint64_t u64TSCOffset = TMCpuTickGetOffset(pVM);
751
752	#if HC_ARCH_BITS == 64
753	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
754	#else
755	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
756	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
757	#endif
758	AssertRC(rc);
759
760	/* Done. */
761	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
762
763	return rc;
764	}
765
766	/**
767	* Runs guest code in a VMX VM.
768	*
769	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
770	*
771	* @returns VBox status code.
772	* @param pVM The VM to operate on.
773	* @param pCtx Guest context
774	*/
775	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
776	{
777	int rc = VINF_SUCCESS;
778	RTCCUINTREG val, valShadow;
779	RTCCUINTREG exitReason, instrError, cbInstr;
780	RTGCUINTPTR exitQualification;
781	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
782	RTGCUINTPTR errCode, instrInfo, uInterruptState;
783	bool fGuestStateSynced = false;
784
785	Log2(("\nE"));
786
787	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
788
789	#ifdef VBOX_STRICT
790	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
791	AssertRC(rc);
792	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
793
794	/* allowed zero */
795	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
796	{
797	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
798	}
799	/* allowed one */
800	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
801	{
802	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
803	}
804
805	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
806	AssertRC(rc);
807	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
808
809	/* allowed zero */
810	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
811	{
812	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
813	}
814	/* allowed one */
815	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
816	{
817	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
818	}
819
820	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
821	AssertRC(rc);
822	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
823
824	/* allowed zero */
825	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
826	{
827	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
828	}
829	/* allowed one */
830	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
831	{
832	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
833	}
834
835	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
836	AssertRC(rc);
837	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
838
839	/* allowed zero */
840	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
841	{
842	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
843	}
844	/* allowed one */
845	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
846	{
847	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
848	}
849	#endif
850
851	#if 0
852	/*
853	* Check if debug registers are armed.
854	*/
855	uint32_t u32DR7 = ASMGetDR7();
856	if (u32DR7 & X86_DR7_ENABLED_MASK)
857	{
858	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
859	}
860	else
861	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
862	#endif
863
864	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
865	*/
866	ResumeExecution:
867
868	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
869	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
870	{
871	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
872	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
873	{
874	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
875	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
876	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
877	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
878	*/
879	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
880	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
881	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
882	AssertRC(rc);
883	}
884	}
885	else
886	{
887	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
888	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
889	AssertRC(rc);
890	}
891
892	/* Check for pending actions that force us to go back to ring 3. */
893	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
894	{
895	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
896	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
897	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
898	rc = VINF_EM_RAW_TO_R3;
899	goto end;
900	}
901	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
902	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
903	{
904	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
905	rc = VINF_EM_PENDING_REQUEST;
906	goto end;
907	}
908
909	/* When external interrupts are pending, we should exit the VM when IF is set. */
910	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
911	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
912	if (VBOX_FAILURE(rc))
913	{
914	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
915	goto end;
916	}
917
918	/** @todo check timers?? */
919
920	/* Save the host state first. */
921	rc = VMXR0SaveHostState(pVM);
922	if (rc != VINF_SUCCESS)
923	{
924	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
925	goto end;
926	}
927	/* Load the guest state */
928	rc = VMXR0LoadGuestState(pVM, pCtx);
929	if (rc != VINF_SUCCESS)
930	{
931	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
932	goto end;
933	}
934	fGuestStateSynced = true;
935
936	/* Non-register state Guest Context */
937	/** @todo change me according to cpu state */
938	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
939	AssertRC(rc);
940
941	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
942
943	/* Manual save and restore:
944	* - General purpose registers except RIP, RSP
945	*
946	* Trashed:
947	* - CR2 (we don't care)
948	* - LDTR (reset to 0)
949	* - DRx (presumably not changed at all)
950	* - DR7 (reset to 0x400)
951	* - EFLAGS (reset to BIT(1); not relevant)
952	*
953	*/
954
955	/* All done! Let's start VM execution. */
956	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
957	if (pVM->hwaccm.s.vmx.fResumeVM == false)
958	{
959	rc = VMXStartVM(pCtx);
960	}
961	else
962	{
963	rc = VMXResumeVM(pCtx);
964	}
965
966	/* In case we execute a goto ResumeExecution later on. */
967	pVM->hwaccm.s.vmx.fResumeVM = true;
968
969	/**
970	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
971	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
972	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
973	*/
974
975	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
976	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
977
978	switch (rc)
979	{
980	case VINF_SUCCESS:
981	break;
982
983	case VERR_VMX_INVALID_VMXON_PTR:
984	AssertFailed();
985	goto end;
986
987	case VERR_VMX_UNABLE_TO_START_VM:
988	case VERR_VMX_UNABLE_TO_RESUME_VM:
989	{
990	#ifdef VBOX_STRICT
991	int rc1;
992
993	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
994	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
995	AssertRC(rc1);
996	if (rc1 == VINF_SUCCESS)
997	{
998	RTGDTR gdtr;
999	PVBOXDESC pDesc;
1000
1001	ASMGetGDTR(&gdtr);
1002	VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
1003
1004	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1005	Log(("Current stack %08x\n", &rc1));
1006
1007	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1008	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1009
1010	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1011	Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
1012
1013	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1014	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1015
1016	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1017	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1018	if (val < gdtr.cbGdt)
1019	{
1020	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1021	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1022	}
1023
1024	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1025	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1026	if (val < gdtr.cbGdt)
1027	{
1028	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1029	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1030	}
1031
1032	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1033	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1034	if (val < gdtr.cbGdt)
1035	{
1036	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1037	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1038	}
1039
1040	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1041	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1042	if (val < gdtr.cbGdt)
1043	{
1044	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1045	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1046	}
1047
1048	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1049	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1050	if (val < gdtr.cbGdt)
1051	{
1052	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1053	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1054	}
1055
1056	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1057	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1058	if (val < gdtr.cbGdt)
1059	{
1060	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1061	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1062	}
1063
1064	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1065	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1066	if (val < gdtr.cbGdt)
1067	{
1068	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1069	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1070	}
1071
1072	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1073	Log(("VMX_VMCS_HOST_TR_BASE %VGv\n", val));
1074
1075	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1076	Log(("VMX_VMCS_HOST_GDTR_BASE %VGv\n", val));
1077	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1078	Log(("VMX_VMCS_HOST_IDTR_BASE %VGv\n", val));
1079
1080	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1081	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1082
1083	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1084	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VGv\n", val));
1085
1086	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1087	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VGv\n", val));
1088
1089	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1090	Log(("VMX_VMCS_HOST_RSP %VGv\n", val));
1091	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1092	Log(("VMX_VMCS_HOST_RIP %VGv\n", val));
1093	}
1094	#endif /* VBOX_STRICT */
1095	goto end;
1096	}
1097
1098	default:
1099	/* impossible */
1100	AssertFailed();
1101	goto end;
1102	}
1103	/* Success. Query the guest state and figure out what has happened. */
1104
1105	/* Investigate why there was a VM-exit. */
1106	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1107	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1108
1109	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1110	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1111	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1112	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1113	intInfo = val;
1114	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1115	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1116	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1117	instrInfo = val;
1118	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1119	exitQualification = val;
1120	AssertRC(rc);
1121
1122	/* Take care of instruction fusing (sti, mov ss) */
1123	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1124	uInterruptState = val;
1125	if (uInterruptState != 0)
1126	{
1127	Assert(uInterruptState <= 2); /* only sti & mov ss */
1128	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1129	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1130	}
1131	else
1132	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1133
1134	/* Let's first sync back eip, esp, and eflags. */
1135	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1136	AssertRC(rc);
1137	pCtx->eip = val;
1138	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1139	AssertRC(rc);
1140	pCtx->esp = val;
1141	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1142	AssertRC(rc);
1143	pCtx->eflags.u32 = val;
1144
1145	/* Control registers. */
1146	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1147	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1148	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1149	CPUMSetGuestCR0(pVM, val);
1150
1151	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1152	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1153	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1154	CPUMSetGuestCR4(pVM, val);
1155
1156	CPUMSetGuestCR2(pVM, ASMGetCR2());
1157
1158	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1159	CPUMSetGuestDR7(pVM, val);
1160
1161	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1162	VMX_READ_SELREG(ES, es);
1163	VMX_READ_SELREG(SS, ss);
1164	VMX_READ_SELREG(CS, cs);
1165	VMX_READ_SELREG(DS, ds);
1166	VMX_READ_SELREG(FS, fs);
1167	VMX_READ_SELREG(GS, gs);
1168
1169	/** @note NOW IT'S SAFE FOR LOGGING! */
1170	Log2(("Raw exit reason %08x\n", exitReason));
1171
1172	/* Check if an injected event was interrupted prematurely. */
1173	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1174	AssertRC(rc);
1175	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1176	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1177	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1178	{
1179	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1180	pVM->hwaccm.s.Event.fPending = true;
1181	/* Error code present? */
1182	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1183	{
1184	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1185	AssertRC(rc);
1186	pVM->hwaccm.s.Event.errCode = val;
1187	}
1188	else
1189	pVM->hwaccm.s.Event.errCode = 0;
1190	}
1191
1192	#ifdef VBOX_STRICT
1193	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1194	HWACCMDumpRegs(pCtx);
1195	#endif
1196
1197	Log2(("E%d", exitReason));
1198	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1199	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1200	Log2(("Interruption error code %d\n", errCode));
1201	Log2(("IntInfo = %08x\n", intInfo));
1202	Log2(("New EIP=%VGv\n", pCtx->eip));
1203
1204	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1205	switch (exitReason)
1206	{
1207	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1208	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1209	{
1210	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1211
1212	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1213	{
1214	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1215	/* External interrupt; leave to allow it to be dispatched again. */
1216	rc = VINF_EM_RAW_INTERRUPT;
1217	break;
1218	}
1219	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1220	{
1221	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1222	/* External interrupt; leave to allow it to be dispatched again. */
1223	rc = VINF_EM_RAW_INTERRUPT;
1224	break;
1225
1226	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1227	AssertFailed(); /* can't come here; fails the first check. */
1228	break;
1229
1230	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1231	Assert(vector == 3 \|\| vector == 4);
1232	/* no break */
1233	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1234	Log2(("Hardware/software interrupt %d\n", vector));
1235	switch (vector)
1236	{
1237	case X86_XCPT_NM:
1238	{
1239	uint32_t oldCR0;
1240
1241	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1242
1243	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1244	oldCR0 = ASMGetCR0();
1245	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1246	rc = CPUMHandleLazyFPU(pVM);
1247	if (rc == VINF_SUCCESS)
1248	{
1249	Assert(CPUMIsGuestFPUStateActive(pVM));
1250
1251	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1252	ASMSetCR0(oldCR0);
1253
1254	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1255
1256	/* Continue execution. */
1257	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1258	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1259
1260	goto ResumeExecution;
1261	}
1262
1263	Log(("Forward #NM fault to the guest\n"));
1264	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1265	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1266	AssertRC(rc);
1267	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1268	goto ResumeExecution;
1269	}
1270
1271	case X86_XCPT_PF: /* Page fault */
1272	{
1273	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1274	/* Exit qualification contains the linear address of the page fault. */
1275	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1276	TRPMSetErrorCode(pVM, errCode);
1277	TRPMSetFaultAddress(pVM, exitQualification);
1278
1279	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1280	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1281	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1282	if (rc == VINF_SUCCESS)
1283	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1284	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1285	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1286
1287	TRPMResetTrap(pVM);
1288
1289	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1290	goto ResumeExecution;
1291	}
1292	else
1293	if (rc == VINF_EM_RAW_GUEST_TRAP)
1294	{ /* A genuine pagefault.
1295	* Forward the trap to the guest by injecting the exception and resuming execution.
1296	*/
1297	Log2(("Forward page fault to the guest\n"));
1298	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1299	/* The error code might have been changed. */
1300	errCode = TRPMGetErrorCode(pVM);
1301
1302	TRPMResetTrap(pVM);
1303
1304	/* Now we must update CR2. */
1305	pCtx->cr2 = exitQualification;
1306	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1307	AssertRC(rc);
1308
1309	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1310	goto ResumeExecution;
1311	}
1312	#ifdef VBOX_STRICT
1313	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1314	Log(("PGMTrap0eHandler failed with %d\n", rc));
1315	#endif
1316	/* Need to go back to the recompiler to emulate the instruction. */
1317	TRPMResetTrap(pVM);
1318	break;
1319	}
1320
1321	case X86_XCPT_MF: /* Floating point exception. */
1322	{
1323	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1324	if (!(pCtx->cr0 & X86_CR0_NE))
1325	{
1326	/* old style FPU error reporting needs some extra work. */
1327	/** @todo don't fall back to the recompiler, but do it manually. */
1328	rc = VINF_EM_RAW_EMULATE_INSTR;
1329	break;
1330	}
1331	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1332	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1333	AssertRC(rc);
1334
1335	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1336	goto ResumeExecution;
1337	}
1338
1339	#ifdef VBOX_STRICT
1340	case X86_XCPT_GP: /* General protection failure exception.*/
1341	case X86_XCPT_UD: /* Unknown opcode exception. */
1342	case X86_XCPT_DE: /* Debug exception. */
1343	case X86_XCPT_SS: /* Stack segment exception. */
1344	case X86_XCPT_NP: /* Segment not present exception. */
1345	{
1346	switch(vector)
1347	{
1348	case X86_XCPT_DE:
1349	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1350	break;
1351	case X86_XCPT_UD:
1352	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1353	break;
1354	case X86_XCPT_SS:
1355	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1356	break;
1357	case X86_XCPT_NP:
1358	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1359	break;
1360	case X86_XCPT_GP:
1361	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1362	break;
1363	}
1364
1365	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1366	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1367	AssertRC(rc);
1368
1369	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1370	goto ResumeExecution;
1371	}
1372	#endif
1373	default:
1374	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1375	rc = VERR_EM_INTERNAL_ERROR;
1376	break;
1377	} /* switch (vector) */
1378
1379	break;
1380
1381	default:
1382	rc = VERR_EM_INTERNAL_ERROR;
1383	AssertFailed();
1384	break;
1385	}
1386
1387	break;
1388	}
1389
1390	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1391	/* Clear VM-exit on IF=1 change. */
1392	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1393	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1394	AssertRC(rc);
1395	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1396	goto ResumeExecution; /* we check for pending guest interrupts there */
1397
1398	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1399	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1400	/* Skip instruction and continue directly. */
1401	pCtx->eip += cbInstr;
1402	/* Continue execution.*/
1403	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1404	goto ResumeExecution;
1405
1406	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1407	{
1408	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1409	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1410	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1411	if (rc == VINF_SUCCESS)
1412	{
1413	/* Update EIP and continue execution. */
1414	Assert(cbInstr == 2);
1415	pCtx->eip += cbInstr;
1416	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1417	goto ResumeExecution;
1418	}
1419	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1420	rc = VINF_EM_RAW_EMULATE_INSTR;
1421	break;
1422	}
1423
1424	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1425	{
1426	Log2(("VMX: Rdtsc\n"));
1427	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1428	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1429	if (rc == VINF_SUCCESS)
1430	{
1431	/* Update EIP and continue execution. */
1432	Assert(cbInstr == 2);
1433	pCtx->eip += cbInstr;
1434	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1435	goto ResumeExecution;
1436	}
1437	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1438	rc = VINF_EM_RAW_EMULATE_INSTR;
1439	break;
1440	}
1441
1442	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1443	{
1444	Log2(("VMX: invlpg\n"));
1445	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1446	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1447	if (rc == VINF_SUCCESS)
1448	{
1449	/* Update EIP and continue execution. */
1450	pCtx->eip += cbInstr;
1451	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1452	goto ResumeExecution;
1453	}
1454	AssertMsgFailed(("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1455	rc = VINF_EM_RAW_EMULATE_INSTR;
1456	break;
1457	}
1458
1459	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1460	{
1461	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1462	{
1463	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1464	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1465	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1466	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1467	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1468	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1469
1470	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1471	{
1472	case 0:
1473	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1474	break;
1475	case 2:
1476	break;
1477	case 3:
1478	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1479	break;
1480	case 4:
1481	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1482	break;
1483	default:
1484	AssertFailed();
1485	}
1486	/* Check if a sync operation is pending. */
1487	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1488	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1489	{
1490	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1491	AssertRC(rc);
1492	}
1493	break;
1494
1495	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1496	Log2(("VMX: mov x, crx\n"));
1497	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1498	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1499	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1500	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1501	break;
1502
1503	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1504	Log2(("VMX: clts\n"));
1505	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1506	rc = EMInterpretCLTS(pVM);
1507	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1508	break;
1509
1510	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1511	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1512	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1513	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1514	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1515	break;
1516	}
1517
1518	/* Update EIP if no error occurred. */
1519	if (VBOX_SUCCESS(rc))
1520	pCtx->eip += cbInstr;
1521
1522	if (rc == VINF_SUCCESS)
1523	{
1524	/* Only resume if successful. */
1525	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1526	goto ResumeExecution;
1527	}
1528	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1529	if (rc == VERR_EM_INTERPRETER)
1530	rc = VINF_EM_RAW_EMULATE_INSTR;
1531	break;
1532	}
1533
1534	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1535	{
1536	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1537	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1538	{
1539	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1540	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1541	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1542	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1543	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1544	Log2(("DR7=%08x\n", pCtx->dr7));
1545	}
1546	else
1547	{
1548	Log2(("VMX: mov x, drx\n"));
1549	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1550	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1551	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1552	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1553	}
1554	/* Update EIP if no error occurred. */
1555	if (VBOX_SUCCESS(rc))
1556	pCtx->eip += cbInstr;
1557
1558	if (rc == VINF_SUCCESS)
1559	{
1560	/* Only resume if successful. */
1561	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1562	goto ResumeExecution;
1563	}
1564	Assert(rc == VERR_EM_INTERPRETER);
1565	rc = VINF_EM_RAW_EMULATE_INSTR;
1566	break;
1567	}
1568
1569	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1570	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1571	{
1572	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1573	uint32_t uPort;
1574	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1575
1576	/** @todo necessary to make the distinction? */
1577	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1578	{
1579	uPort = pCtx->edx & 0xffff;
1580	}
1581	else
1582	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1583
1584	/* paranoia */
1585	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1586	{
1587	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1588	break;
1589	}
1590
1591	uint32_t cbSize = aIOSize[uIOWidth];
1592
1593	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1594	{
1595	/* ins/outs */
1596	uint32_t prefix = 0;
1597	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1598	prefix \|= PREFIX_REP;
1599
1600	if (fIOWrite)
1601	{
1602	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1603	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1604	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1605	}
1606	else
1607	{
1608	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1609	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1610	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1611	}
1612	}
1613	else
1614	{
1615	/* normal in/out */
1616	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1617
1618	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1619
1620	if (fIOWrite)
1621	{
1622	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1623	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1624	}
1625	else
1626	{
1627	uint32_t u32Val = 0;
1628
1629	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1630	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1631	if ( rc == VINF_SUCCESS
1632	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1633	{
1634	/* Write back to the EAX register. */
1635	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1636	}
1637	}
1638	}
1639	if ( rc == VINF_SUCCESS
1640	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1641	{
1642	/* Update EIP and continue execution. */
1643	pCtx->eip += cbInstr;
1644	if (RT_LIKELY(rc == VINF_SUCCESS))
1645	{
1646	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1647	goto ResumeExecution;
1648	}
1649	break;
1650	}
1651	#ifdef VBOX_STRICT
1652	if (rc == VINF_IOM_HC_IOPORT_READ)
1653	Assert(!fIOWrite);
1654	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1655	Assert(fIOWrite);
1656	else
1657	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_EM_RESCHEDULE_REM, ("%Vrc\n", rc));
1658	#endif
1659	break;
1660	}
1661
1662	default:
1663	/* The rest is handled after syncing the entire CPU state. */
1664	break;
1665	}
1666
1667	/* Note: the guest state isn't entirely synced back at this stage. */
1668
1669	/* Investigate why there was a VM-exit. (part 2) */
1670	switch (exitReason)
1671	{
1672	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1673	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1674	/* Already handled above. */
1675	break;
1676
1677	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1678	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1679	break;
1680
1681	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1682	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1683	rc = VINF_EM_RAW_INTERRUPT;
1684	AssertFailed(); /* Can't happen. Yet. */
1685	break;
1686
1687	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1688	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1689	rc = VINF_EM_RAW_INTERRUPT;
1690	AssertFailed(); /* Can't happen afaik. */
1691	break;
1692
1693	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1694	rc = VINF_EM_RAW_RING_SWITCH_INT;
1695	break;
1696
1697	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1698	/** Check if external interrupts are pending; if so, don't switch back. */
1699	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1700	{
1701	pCtx->eip++; /* skip hlt */
1702	goto ResumeExecution;
1703	}
1704
1705	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1706	break;
1707
1708	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1709	AssertFailed(); /* can't happen. */
1710	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1711	break;
1712
1713	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1714	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1715	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1716	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1717	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1718	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1719	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1720	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1721	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1722	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1723	/** @todo inject #UD immediately */
1724	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1725	break;
1726
1727	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1728	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1729	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1730	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1731	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1732	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1733	/* already handled above */
1734	AssertMsg(rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_EM_RAW_INTERRUPT \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_PGM_SYNC_CR3 \|\| rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE
1735	\|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc = %d\n", rc));
1736	break;
1737
1738	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1739	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1740	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1741	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1742	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1743	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1744	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1745	break;
1746
1747	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1748	Assert(rc == VINF_EM_RAW_INTERRUPT);
1749	break;
1750
1751	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1752	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1753	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1754	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1755	default:
1756	rc = VERR_EM_INTERNAL_ERROR;
1757	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1758	break;
1759
1760	}
1761	end:
1762	if (fGuestStateSynced)
1763	{
1764	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1765	VMX_READ_SELREG(LDTR, ldtr);
1766	VMX_READ_SELREG(TR, tr);
1767
1768	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1769	pCtx->gdtr.cbGdt = val;
1770	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1771	pCtx->gdtr.pGdt = val;
1772
1773	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1774	pCtx->idtr.cbIdt = val;
1775	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1776	pCtx->idtr.pIdt = val;
1777
1778	/*
1779	* System MSRs
1780	*/
1781	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1782	pCtx->SysEnter.cs = val;
1783	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1784	pCtx->SysEnter.eip = val;
1785	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1786	pCtx->SysEnter.esp = val;
1787	}
1788
1789	/* Signal changes for the recompiler. */
1790	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1791
1792	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
1793	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
1794	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1795	{
1796	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1797	/* On the next entry we'll only sync the host context. */
1798	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1799	}
1800	else
1801	{
1802	/* On the next entry we'll sync everything. */
1803	/** @todo we can do better than this */
1804	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1805	}
1806
1807	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1808	Log2(("X"));
1809	return rc;
1810	}
1811
1812
1813	/**
1814	* Enable VMX
1815	*
1816	* @returns VBox status code.
1817	* @param pVM The VM to operate on.
1818	*/
1819	HWACCMR0DECL(int) VMXR0Enable(PVM pVM)
1820	{
1821	Assert(pVM->hwaccm.s.vmx.fSupported);
1822
1823	/* Make sure the VMX instructions don't cause #UD faults. */
1824	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
1825
1826	/* Enter VMX Root Mode */
1827	int rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
1828	if (VBOX_FAILURE(rc))
1829	return rc;
1830
1831	/* Activate the VM Control Structure. */
1832	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1833	if (VBOX_FAILURE(rc))
1834	{
1835	/* Leave VMX Root Mode. */
1836	VMXDisable();
1837	return rc;
1838	}
1839	pVM->hwaccm.s.vmx.fResumeVM = false;
1840	return VINF_SUCCESS;
1841	}
1842
1843
1844	/**
1845	* Disable VMX
1846	*
1847	* @returns VBox status code.
1848	* @param pVM The VM to operate on.
1849	*/
1850	HWACCMR0DECL(int) VMXR0Disable(PVM pVM)
1851	{
1852	Assert(pVM->hwaccm.s.vmx.fSupported);
1853
1854	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
1855	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1856	AssertRC(rc);
1857
1858	/* Leave VMX Root Mode. */
1859	VMXDisable();
1860
1861	return VINF_SUCCESS;
1862	}
1863

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 2733

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