HWVMXR0.cpp@ 2762

Last change on this file since 2762 was 2762, checked in by vboxsync, 18 years ago
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1	/* $Id: HWVMXR0.cpp 2762 2007-05-22 12:05:15Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include "HWVMXR0.h"
41
42
43	/* IO operation lookup arrays. */
44	static uint32_t aIOSize[4] = {1, 2, 0, 4};
45	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
46
47
48	/**
49	* Sets up and activates VMX
50	*
51	* @returns VBox status code.
52	* @param pVM The VM to operate on.
53	*/
54	HWACCMR0DECL(int) VMXR0Setup(PVM pVM)
55	{
56	int rc = VINF_SUCCESS;
57	uint32_t val;
58
59	if (pVM == NULL)
60	return VERR_INVALID_PARAMETER;
61
62	/* Setup Intel VMX. */
63	Assert(pVM->hwaccm.s.vmx.fSupported);
64
65	/* Set revision dword at the beginning of both structures. */
66	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
67	(uint32_t )pVM->hwaccm.s.vmx.pVMXON = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
68
69	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
70	* (which can have very bad consequences!!!)
71	*/
72
73	/* Make sure the VMX instructions don't cause #UD faults. */
74	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
75
76	/* Enter VMX Root Mode */
77	rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
78	if (VBOX_FAILURE(rc))
79	{
80	return rc;
81	}
82
83	/* Clear VM Control Structure. */
84	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
85	if (VBOX_FAILURE(rc))
86	goto vmx_end;
87
88	/* Activate the VM Control Structure. */
89	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
90	if (VBOX_FAILURE(rc))
91	goto vmx_end;
92
93	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
94	* Set required bits to one and zero according to the MSR capabilities.
95	*/
96	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
97	/* External and non-maskable interrupts cause VM-exits. */
98	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
99	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
100
101	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
102	AssertRC(rc);
103
104	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
105	* Set required bits to one and zero according to the MSR capabilities.
106	*/
107	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
108	/* Program which event cause VM-exits and which features we want to use. */
109	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
110	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
111	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
112	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
113	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
114	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
115
116	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
117
118	/*
119	if AMD64 guest mode
120	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
121	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
122	*/
123	/* Mask away the bits that the CPU doesn't support */
124	/** @todo make sure they don't conflict with the above requirements. */
125	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
126	pVM->hwaccm.s.vmx.proc_ctls = val;
127
128	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
129	AssertRC(rc);
130
131	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
132	* Set required bits to one and zero according to the MSR capabilities.
133	*/
134	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
135	AssertRC(rc);
136
137	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
138	* Set required bits to one and zero according to the MSR capabilities.
139	*/
140	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
141	if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
142	{
143	/** @todo 32 bits guest mode only for now. */
144	/* val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
145	}
146	/* Mask away the bits that the CPU doesn't support */
147	/** @todo make sure they don't conflict with the above requirements. */
148	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
149	/* else Must be zero when AMD64 is not available. */
150	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
151	AssertRC(rc);
152
153	/* VMX_VMCS_CTRL_EXIT_CONTROLS
154	* Set required bits to one and zero according to the MSR capabilities.
155	*/
156	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
157	#if HC_ARCH_BITS == 64
158	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
159	#else
160	/* else Must be zero when AMD64 is not available. */
161	#endif
162	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
163	/* Don't acknowledge external interrupts on VM-exit. */
164	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
165	AssertRC(rc);
166
167	/* Forward all exception except #NM & #PF to the guest.
168	* We always need to check pagefaults since our shadow page table can be out of sync.
169	* And we always lazily sync the FPU & XMM state.
170	*/
171
172	/*
173	* @todo Possible optimization:
174	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
175	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
176	* registers ourselves of course.
177	*
178	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
179	*/
180	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
181	AssertRC(rc);
182
183	/* Don't filter page faults; all of them should cause a switch. */
184	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
185	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
186	AssertRC(rc);
187
188	/* Init TSC offset to zero. */
189	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
190	#if HC_ARCH_BITS == 32
191	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
192	#endif
193	AssertRC(rc);
194
195	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
196	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
197	AssertRC(rc);
198
199	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
200	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
201	AssertRC(rc);
202
203	/* Clear MSR controls. */
204	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
205	{
206	/* Optional */
207	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
208	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
209	AssertRC(rc);
210	}
211	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
212	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
213	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
214	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
215	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
216	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH, 0);
217	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
218	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
219	AssertRC(rc);
220
221	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
222	{
223	/* Optional */
224	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
225	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
226	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
227	AssertRC(rc);
228	}
229
230	/* Set link pointer to -1. Not currently used. */
231	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
232	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
233	AssertRC(rc);
234
235	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
236	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
237	AssertRC(rc);
238
239	vmx_end:
240	/* Leave VMX Root Mode. */
241	VMXDisable();
242	return rc;
243	}
244
245
246	/**
247	* Injects an event (trap or external interrupt)
248	*
249	* @returns VBox status code.
250	* @param pVM The VM to operate on.
251	* @param pCtx CPU Context
252	* @param intInfo VMX interrupt info
253	* @param cbInstr Opcode length of faulting instruction
254	* @param errCode Error code (optional)
255	*/
256	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
257	{
258	int rc;
259
260	#ifdef VBOX_STRICT
261	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
262	if (iGate == 0xE)
263	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
264	else
265	if (iGate < 0x20)
266	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
267	else
268	{
269	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
270	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
271	Assert(pCtx->eflags.u32 & X86_EFL_IF);
272	}
273	#endif
274
275	/* Set event injection state. */
276	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
277	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
278	);
279
280	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
281	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
282
283	AssertRC(rc);
284	return rc;
285	}
286
287
288	/**
289	* Checks for pending guest interrupts and injects them
290	*
291	* @returns VBox status code.
292	* @param pVM The VM to operate on.
293	* @param pCtx CPU Context
294	*/
295	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
296	{
297	int rc;
298
299	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
300	if (pVM->hwaccm.s.Event.fPending)
301	{
302	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
303	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
304	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
305	AssertRC(rc);
306
307	pVM->hwaccm.s.Event.fPending = false;
308	return VINF_SUCCESS;
309	}
310
311	/* When external interrupts are pending, we should exit the VM when IF is set. */
312	if ( !TRPMHasTrap(pVM)
313	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
314	{
315	if (!(pCtx->eflags.u32 & X86_EFL_IF))
316	{
317	Log2(("Enable irq window exit!\n"));
318	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT);
319	AssertRC(rc);
320	}
321	else
322	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
323	{
324	uint8_t u8Interrupt;
325
326	rc = PDMGetInterrupt(pVM, &u8Interrupt);
327	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
328	if (VBOX_SUCCESS(rc))
329	{
330	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
331	AssertRC(rc);
332	}
333	else
334	{
335	/* can't happen... */
336	AssertFailed();
337	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
338	return VINF_EM_RAW_INTERRUPT_PENDING;
339	}
340	}
341	else
342	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
343	}
344
345	#ifdef VBOX_STRICT
346	if (TRPMHasTrap(pVM))
347	{
348	uint8_t u8Vector;
349	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
350	AssertRC(rc);
351	}
352	#endif
353
354	if ( pCtx->eflags.u32 & X86_EFL_IF
355	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
356	&& TRPMHasTrap(pVM)
357	)
358	{
359	uint8_t u8Vector;
360	int rc;
361	TRPMEVENT enmType;
362	RTGCUINTPTR intInfo, errCode;
363
364	/* If a new event is pending, then dispatch it now. */
365	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
366	AssertRC(rc);
367	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
368	Assert(enmType != TRPM_SOFTWARE_INT);
369
370	/* Clear the pending trap. */
371	rc = TRPMResetTrap(pVM);
372	AssertRC(rc);
373
374	intInfo = u8Vector;
375	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
376
377	if (enmType == TRPM_TRAP)
378	{
379	switch (u8Vector) {
380	case 8:
381	case 10:
382	case 11:
383	case 12:
384	case 13:
385	case 14:
386	case 17:
387	/* Valid error codes. */
388	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
389	break;
390	default:
391	break;
392	}
393	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
394	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
395	else
396	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
397	}
398	else
399	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
400
401	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
402	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
403	AssertRC(rc);
404	} /* if (interrupts can be dispatched) */
405
406	return VINF_SUCCESS;
407	}
408
409	/**
410	* Save the host state
411	*
412	* @returns VBox status code.
413	* @param pVM The VM to operate on.
414	*/
415	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
416	{
417	int rc = VINF_SUCCESS;
418
419	/*
420	* Host CPU Context
421	*/
422	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
423	{
424	RTIDTR idtr;
425	RTGDTR gdtr;
426	RTSEL SelTR;
427	PVBOXDESC pDesc;
428	uintptr_t trBase;
429
430	/* Control registers */
431	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
432	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
433	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
434	AssertRC(rc);
435	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
436	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
437	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
438
439	/* Selector registers. */
440	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
441	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
442	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
443	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
444	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
445	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
446	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
447	SelTR = ASMGetTR();
448	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
449	AssertRC(rc);
450	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
451	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
452	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
453	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
454	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
455	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
456	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
457
458	/* GDTR & IDTR */
459	ASMGetGDTR(&gdtr);
460	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
461	ASMGetIDTR(&idtr);
462	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
463	AssertRC(rc);
464	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
465	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
466
467	/* Save the base address of the TR selector. */
468	if (SelTR > gdtr.cbGdt)
469	{
470	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
471	return VERR_VMX_INVALID_HOST_STATE;
472	}
473
474	pDesc = &((PVBOXDESC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT];
475	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16) \| (pDesc->Gen.u8BaseHigh2 << 24);
476	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
477	AssertRC(rc);
478	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
479
480	/* FS and GS base. */
481	#if HC_ARCH_BITS == 32
482	rc = VMXWriteVMCS(VMX_VMCS_HOST_FS_BASE, 0);
483	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_GS_BASE, 0);
484	#else
485	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
486	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
487	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
488	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
489	#endif
490	AssertRC(rc);
491
492	/* Sysenter MSRs. */
493	/** @todo expensive!! */
494	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
495	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
496	#if HC_ARCH_BITS == 32
497	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
498	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
499	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
500	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
501	#else
502	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
503	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
504	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
505	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
506	#endif
507	AssertRC(rc);
508
509	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
510	}
511	return rc;
512	}
513
514
515	/**
516	* Loads the guest state
517	*
518	* @returns VBox status code.
519	* @param pVM The VM to operate on.
520	* @param pCtx Guest context
521	*/
522	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
523	{
524	int rc = VINF_SUCCESS;
525	RTGCUINTPTR val;
526
527	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
528	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
529	{
530	VMX_WRITE_SELREG(ES, es);
531	AssertRC(rc);
532
533	VMX_WRITE_SELREG(CS, cs);
534	AssertRC(rc);
535
536	VMX_WRITE_SELREG(SS, ss);
537	AssertRC(rc);
538
539	VMX_WRITE_SELREG(DS, ds);
540	AssertRC(rc);
541
542	VMX_WRITE_SELREG(FS, fs);
543	AssertRC(rc);
544
545	VMX_WRITE_SELREG(GS, gs);
546	AssertRC(rc);
547	}
548
549	/* Guest CPU context: LDTR. */
550	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
551	{
552	if (pCtx->ldtr == 0)
553	{
554	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
555	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
556	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
557	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
558	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
559	}
560	else
561	{
562	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
563	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
564	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
565	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
566	}
567	AssertRC(rc);
568	}
569	/* Guest CPU context: TR. */
570	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
571	{
572	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
573	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
574	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
575	val = pCtx->trHid.Attr.u;
576
577	/* The TSS selector must be busy. */
578	if ((val & 0xF) == X86_SEL_TYPE_SYS_386_TSS_AVAIL)
579	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
580	else
581	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
582	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
583
584	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
585	AssertRC(rc);
586	}
587	/* Guest CPU context: GDTR. */
588	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
589	{
590	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
591	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
592	AssertRC(rc);
593	}
594	/* Guest CPU context: IDTR. */
595	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
596	{
597	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
598	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
599	AssertRC(rc);
600	}
601
602	/*
603	* Sysenter MSRs
604	*/
605	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
606	{
607	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
608	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
609	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
610	AssertRC(rc);
611	}
612
613	/* Control registers */
614	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
615	{
616	val = pCtx->cr0;
617	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
618	Log2(("Guest CR0-shadow %08x\n", val));
619	if (CPUMIsGuestFPUStateActive(pVM) == false)
620	{
621	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
622	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
623	}
624	else
625	{
626	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
627	/** @todo check if we support the old style mess correctly. */
628	if (!(val & X86_CR0_NE))
629	{
630	Log(("Forcing X86_CR0_NE!!!\n"));
631
632	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
633	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
634	{
635	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| BIT(16));
636	AssertRC(rc);
637	pVM->hwaccm.s.fFPUOldStyleOverride = true;
638	}
639	}
640
641	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
642	}
643	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
644	Log2(("Guest CR0 %08x\n", val));
645	/* CR0 flags owned by the host; if the guests attempts to change them, then
646	* the VM will exit.
647	*/
648	val = X86_CR0_PE
649	\| X86_CR0_WP /** @todo do we care? (we do if we start patching the guest) */
650	\| X86_CR0_PG
651	\| X86_CR0_TS
652	\| X86_CR0_ET
653	\| X86_CR0_NE
654	\| X86_CR0_MP;
655	pVM->hwaccm.s.vmx.cr0_mask = val;
656
657	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
658	Log2(("Guest CR0-mask %08x\n", val));
659	AssertRC(rc);
660	}
661	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
662	{
663	/* CR4 */
664	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
665	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
666	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
667	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
668	switch(pVM->hwaccm.s.enmShadowMode)
669	{
670	case PGMMODE_REAL:
671	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
672	AssertFailed();
673	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
674
675	case PGMMODE_32_BIT: /* 32-bit paging. */
676	break;
677
678	case PGMMODE_PAE: /* PAE paging. */
679	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
680	/** @todo use normal 32 bits paging */
681	val \|= X86_CR4_PAE;
682	break;
683
684	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
685	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
686	AssertFailed();
687	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
688
689	default: /* shut up gcc */
690	AssertFailed();
691	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
692	}
693	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
694	Log2(("Guest CR4 %08x\n", val));
695	/* CR4 flags owned by the host; if the guests attempts to change them, then
696	* the VM will exit.
697	*/
698	val = X86_CR4_PAE
699	\| X86_CR4_PGE
700	\| X86_CR4_PSE
701	\| X86_CR4_VMXE;
702	pVM->hwaccm.s.vmx.cr4_mask = val;
703
704	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
705	Log2(("Guest CR4-mask %08x\n", val));
706	AssertRC(rc);
707	}
708
709	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
710	{
711	/* Save our shadow CR3 register. */
712	val = PGMGetHyperCR3(pVM);
713	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
714	AssertRC(rc);
715	}
716
717	/* Debug registers. */
718	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
719	{
720	/** @todo DR0-6 */
721	val = pCtx->dr7;
722	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
723	val \|= 0x400; /* must be one */
724	#ifdef VBOX_STRICT
725	val = 0x400;
726	#endif
727	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
728	AssertRC(rc);
729
730	/* IA32_DEBUGCTL MSR. */
731	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
732	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
733	AssertRC(rc);
734
735	/** @todo */
736	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
737	AssertRC(rc);
738	}
739
740	/* EIP, ESP and EFLAGS */
741	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
742	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
743	AssertRC(rc);
744
745	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
746	val = pCtx->eflags.u32;
747	val &= VMX_EFLAGS_RESERVED_0;
748	val \|= VMX_EFLAGS_RESERVED_1;
749	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, val);
750	AssertRC(rc);
751
752	/** TSC offset. */
753	/** @todo use host tsc if safe, other intercept rdtsc */
754	uint64_t u64TSCOffset = TMCpuTickGetOffset(pVM);
755
756	#if HC_ARCH_BITS == 64
757	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
758	#else
759	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
760	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
761	#endif
762	AssertRC(rc);
763
764	/* Done. */
765	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
766
767	return rc;
768	}
769
770	/**
771	* Runs guest code in a VMX VM.
772	*
773	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
774	*
775	* @returns VBox status code.
776	* @param pVM The VM to operate on.
777	* @param pCtx Guest context
778	*/
779	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
780	{
781	int rc = VINF_SUCCESS;
782	RTCCUINTREG val, valShadow;
783	RTCCUINTREG exitReason, instrError, cbInstr;
784	RTGCUINTPTR exitQualification;
785	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
786	RTGCUINTPTR errCode, instrInfo, uInterruptState;
787	bool fGuestStateSynced = false;
788
789	Log2(("\nE"));
790
791	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
792
793	#ifdef VBOX_STRICT
794	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
795	AssertRC(rc);
796	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
797
798	/* allowed zero */
799	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
800	{
801	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
802	}
803	/* allowed one */
804	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
805	{
806	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
807	}
808
809	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
810	AssertRC(rc);
811	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
812
813	/* allowed zero */
814	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
815	{
816	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
817	}
818	/* allowed one */
819	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
820	{
821	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
822	}
823
824	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
825	AssertRC(rc);
826	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
827
828	/* allowed zero */
829	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
830	{
831	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
832	}
833	/* allowed one */
834	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
835	{
836	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
837	}
838
839	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
840	AssertRC(rc);
841	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
842
843	/* allowed zero */
844	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
845	{
846	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
847	}
848	/* allowed one */
849	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
850	{
851	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
852	}
853	#endif
854
855	#if 0
856	/*
857	* Check if debug registers are armed.
858	*/
859	uint32_t u32DR7 = ASMGetDR7();
860	if (u32DR7 & X86_DR7_ENABLED_MASK)
861	{
862	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
863	}
864	else
865	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
866	#endif
867
868	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
869	*/
870	ResumeExecution:
871
872	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
873	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
874	{
875	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
876	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
877	{
878	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
879	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
880	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
881	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
882	*/
883	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
884	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
885	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
886	AssertRC(rc);
887	}
888	}
889	else
890	{
891	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
892	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
893	AssertRC(rc);
894	}
895
896	/* Check for pending actions that force us to go back to ring 3. */
897	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
898	{
899	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
900	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
901	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
902	rc = VINF_EM_RAW_TO_R3;
903	goto end;
904	}
905	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
906	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
907	{
908	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
909	rc = VINF_EM_PENDING_REQUEST;
910	goto end;
911	}
912
913	/* When external interrupts are pending, we should exit the VM when IF is set. */
914	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
915	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
916	if (VBOX_FAILURE(rc))
917	{
918	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
919	goto end;
920	}
921
922	/** @todo check timers?? */
923
924	/* Save the host state first. */
925	rc = VMXR0SaveHostState(pVM);
926	if (rc != VINF_SUCCESS)
927	{
928	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
929	goto end;
930	}
931	/* Load the guest state */
932	rc = VMXR0LoadGuestState(pVM, pCtx);
933	if (rc != VINF_SUCCESS)
934	{
935	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
936	goto end;
937	}
938	fGuestStateSynced = true;
939
940	/* Non-register state Guest Context */
941	/** @todo change me according to cpu state */
942	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
943	AssertRC(rc);
944
945	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
946
947	/* Manual save and restore:
948	* - General purpose registers except RIP, RSP
949	*
950	* Trashed:
951	* - CR2 (we don't care)
952	* - LDTR (reset to 0)
953	* - DRx (presumably not changed at all)
954	* - DR7 (reset to 0x400)
955	* - EFLAGS (reset to BIT(1); not relevant)
956	*
957	*/
958
959	/* All done! Let's start VM execution. */
960	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
961	if (pVM->hwaccm.s.vmx.fResumeVM == false)
962	{
963	rc = VMXStartVM(pCtx);
964	}
965	else
966	{
967	rc = VMXResumeVM(pCtx);
968	}
969
970	/* In case we execute a goto ResumeExecution later on. */
971	pVM->hwaccm.s.vmx.fResumeVM = true;
972
973	/**
974	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
975	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
976	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
977	*/
978
979	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
980	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
981
982	switch (rc)
983	{
984	case VINF_SUCCESS:
985	break;
986
987	case VERR_VMX_INVALID_VMXON_PTR:
988	AssertFailed();
989	goto end;
990
991	case VERR_VMX_UNABLE_TO_START_VM:
992	case VERR_VMX_UNABLE_TO_RESUME_VM:
993	{
994	#ifdef VBOX_STRICT
995	int rc1;
996
997	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
998	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
999	AssertRC(rc1);
1000	if (rc1 == VINF_SUCCESS)
1001	{
1002	RTGDTR gdtr;
1003	PVBOXDESC pDesc;
1004
1005	ASMGetGDTR(&gdtr);
1006
1007	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1008	Log(("Current stack %08x\n", &rc1));
1009
1010	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1011	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1012
1013	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1014	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1015
1016	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1017	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1018
1019	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1020	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1021	if (val < gdtr.cbGdt)
1022	{
1023	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1024	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1025	}
1026
1027	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1028	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1029	if (val < gdtr.cbGdt)
1030	{
1031	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1032	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1033	}
1034
1035	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1036	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1037	if (val < gdtr.cbGdt)
1038	{
1039	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1040	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1041	}
1042
1043	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1044	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1045	if (val < gdtr.cbGdt)
1046	{
1047	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1048	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1049	}
1050
1051	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1052	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1053	if (val < gdtr.cbGdt)
1054	{
1055	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1056	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1057	}
1058
1059	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1060	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1061	if (val < gdtr.cbGdt)
1062	{
1063	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1064	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1065	}
1066
1067	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1068	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1069	if (val < gdtr.cbGdt)
1070	{
1071	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1072	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1073	}
1074
1075	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1076	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1077
1078	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1079	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1080	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1081	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1082
1083	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1084	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1085
1086	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1087	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1088
1089	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1090	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1091
1092	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1093	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1094	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1095	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1096	}
1097	#endif /* VBOX_STRICT */
1098	goto end;
1099	}
1100
1101	default:
1102	/* impossible */
1103	AssertFailed();
1104	goto end;
1105	}
1106	/* Success. Query the guest state and figure out what has happened. */
1107
1108	/* Investigate why there was a VM-exit. */
1109	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1110	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1111
1112	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1113	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1114	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1115	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1116	intInfo = val;
1117	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1118	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1119	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1120	instrInfo = val;
1121	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1122	exitQualification = val;
1123	AssertRC(rc);
1124
1125	/* Take care of instruction fusing (sti, mov ss) */
1126	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1127	uInterruptState = val;
1128	if (uInterruptState != 0)
1129	{
1130	Assert(uInterruptState <= 2); /* only sti & mov ss */
1131	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1132	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1133	}
1134	else
1135	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1136
1137	/* Let's first sync back eip, esp, and eflags. */
1138	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1139	AssertRC(rc);
1140	pCtx->eip = val;
1141	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1142	AssertRC(rc);
1143	pCtx->esp = val;
1144	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1145	AssertRC(rc);
1146	pCtx->eflags.u32 = val;
1147
1148	/* Control registers. */
1149	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1150	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1151	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1152	CPUMSetGuestCR0(pVM, val);
1153
1154	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1155	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1156	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1157	CPUMSetGuestCR4(pVM, val);
1158
1159	CPUMSetGuestCR2(pVM, ASMGetCR2());
1160
1161	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1162	CPUMSetGuestDR7(pVM, val);
1163
1164	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1165	VMX_READ_SELREG(ES, es);
1166	VMX_READ_SELREG(SS, ss);
1167	VMX_READ_SELREG(CS, cs);
1168	VMX_READ_SELREG(DS, ds);
1169	VMX_READ_SELREG(FS, fs);
1170	VMX_READ_SELREG(GS, gs);
1171
1172	/** @note NOW IT'S SAFE FOR LOGGING! */
1173	Log2(("Raw exit reason %08x\n", exitReason));
1174
1175	/* Check if an injected event was interrupted prematurely. */
1176	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1177	AssertRC(rc);
1178	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1179	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1180	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1181	{
1182	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1183	pVM->hwaccm.s.Event.fPending = true;
1184	/* Error code present? */
1185	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1186	{
1187	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1188	AssertRC(rc);
1189	pVM->hwaccm.s.Event.errCode = val;
1190	}
1191	else
1192	pVM->hwaccm.s.Event.errCode = 0;
1193	}
1194
1195	#ifdef VBOX_STRICT
1196	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1197	HWACCMDumpRegs(pCtx);
1198	#endif
1199
1200	Log2(("E%d", exitReason));
1201	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1202	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1203	Log2(("Interruption error code %d\n", errCode));
1204	Log2(("IntInfo = %08x\n", intInfo));
1205	Log2(("New EIP=%VGv\n", pCtx->eip));
1206
1207	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1208	switch (exitReason)
1209	{
1210	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1211	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1212	{
1213	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1214
1215	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1216	{
1217	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1218	/* External interrupt; leave to allow it to be dispatched again. */
1219	rc = VINF_EM_RAW_INTERRUPT;
1220	break;
1221	}
1222	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1223	{
1224	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1225	/* External interrupt; leave to allow it to be dispatched again. */
1226	rc = VINF_EM_RAW_INTERRUPT;
1227	break;
1228
1229	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1230	AssertFailed(); /* can't come here; fails the first check. */
1231	break;
1232
1233	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1234	Assert(vector == 3 \|\| vector == 4);
1235	/* no break */
1236	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1237	Log2(("Hardware/software interrupt %d\n", vector));
1238	switch (vector)
1239	{
1240	case X86_XCPT_NM:
1241	{
1242	uint32_t oldCR0;
1243
1244	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1245
1246	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1247	oldCR0 = ASMGetCR0();
1248	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1249	rc = CPUMHandleLazyFPU(pVM);
1250	if (rc == VINF_SUCCESS)
1251	{
1252	Assert(CPUMIsGuestFPUStateActive(pVM));
1253
1254	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1255	ASMSetCR0(oldCR0);
1256
1257	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1258
1259	/* Continue execution. */
1260	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1261	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1262
1263	goto ResumeExecution;
1264	}
1265
1266	Log(("Forward #NM fault to the guest\n"));
1267	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1268	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1269	AssertRC(rc);
1270	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1271	goto ResumeExecution;
1272	}
1273
1274	case X86_XCPT_PF: /* Page fault */
1275	{
1276	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1277	/* Exit qualification contains the linear address of the page fault. */
1278	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1279	TRPMSetErrorCode(pVM, errCode);
1280	TRPMSetFaultAddress(pVM, exitQualification);
1281
1282	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1283	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1284	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1285	if (rc == VINF_SUCCESS)
1286	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1287	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1288	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1289
1290	TRPMResetTrap(pVM);
1291
1292	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1293	goto ResumeExecution;
1294	}
1295	else
1296	if (rc == VINF_EM_RAW_GUEST_TRAP)
1297	{ /* A genuine pagefault.
1298	* Forward the trap to the guest by injecting the exception and resuming execution.
1299	*/
1300	Log2(("Forward page fault to the guest\n"));
1301	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1302	/* The error code might have been changed. */
1303	errCode = TRPMGetErrorCode(pVM);
1304
1305	TRPMResetTrap(pVM);
1306
1307	/* Now we must update CR2. */
1308	pCtx->cr2 = exitQualification;
1309	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1310	AssertRC(rc);
1311
1312	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1313	goto ResumeExecution;
1314	}
1315	#ifdef VBOX_STRICT
1316	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1317	Log(("PGMTrap0eHandler failed with %d\n", rc));
1318	#endif
1319	/* Need to go back to the recompiler to emulate the instruction. */
1320	TRPMResetTrap(pVM);
1321	break;
1322	}
1323
1324	case X86_XCPT_MF: /* Floating point exception. */
1325	{
1326	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1327	if (!(pCtx->cr0 & X86_CR0_NE))
1328	{
1329	/* old style FPU error reporting needs some extra work. */
1330	/** @todo don't fall back to the recompiler, but do it manually. */
1331	rc = VINF_EM_RAW_EMULATE_INSTR;
1332	break;
1333	}
1334	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1335	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1336	AssertRC(rc);
1337
1338	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1339	goto ResumeExecution;
1340	}
1341
1342	#ifdef VBOX_STRICT
1343	case X86_XCPT_GP: /* General protection failure exception.*/
1344	case X86_XCPT_UD: /* Unknown opcode exception. */
1345	case X86_XCPT_DE: /* Debug exception. */
1346	case X86_XCPT_SS: /* Stack segment exception. */
1347	case X86_XCPT_NP: /* Segment not present exception. */
1348	{
1349	switch(vector)
1350	{
1351	case X86_XCPT_DE:
1352	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1353	break;
1354	case X86_XCPT_UD:
1355	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1356	break;
1357	case X86_XCPT_SS:
1358	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1359	break;
1360	case X86_XCPT_NP:
1361	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1362	break;
1363	case X86_XCPT_GP:
1364	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1365	break;
1366	}
1367
1368	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1369	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1370	AssertRC(rc);
1371
1372	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1373	goto ResumeExecution;
1374	}
1375	#endif
1376	default:
1377	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1378	rc = VERR_EM_INTERNAL_ERROR;
1379	break;
1380	} /* switch (vector) */
1381
1382	break;
1383
1384	default:
1385	rc = VERR_EM_INTERNAL_ERROR;
1386	AssertFailed();
1387	break;
1388	}
1389
1390	break;
1391	}
1392
1393	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1394	/* Clear VM-exit on IF=1 change. */
1395	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1396	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1397	AssertRC(rc);
1398	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1399	goto ResumeExecution; /* we check for pending guest interrupts there */
1400
1401	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1402	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1403	/* Skip instruction and continue directly. */
1404	pCtx->eip += cbInstr;
1405	/* Continue execution.*/
1406	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1407	goto ResumeExecution;
1408
1409	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1410	{
1411	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1412	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1413	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1414	if (rc == VINF_SUCCESS)
1415	{
1416	/* Update EIP and continue execution. */
1417	Assert(cbInstr == 2);
1418	pCtx->eip += cbInstr;
1419	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1420	goto ResumeExecution;
1421	}
1422	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1423	rc = VINF_EM_RAW_EMULATE_INSTR;
1424	break;
1425	}
1426
1427	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1428	{
1429	Log2(("VMX: Rdtsc\n"));
1430	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1431	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1432	if (rc == VINF_SUCCESS)
1433	{
1434	/* Update EIP and continue execution. */
1435	Assert(cbInstr == 2);
1436	pCtx->eip += cbInstr;
1437	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1438	goto ResumeExecution;
1439	}
1440	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1441	rc = VINF_EM_RAW_EMULATE_INSTR;
1442	break;
1443	}
1444
1445	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1446	{
1447	Log2(("VMX: invlpg\n"));
1448	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1449	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1450	if (rc == VINF_SUCCESS)
1451	{
1452	/* Update EIP and continue execution. */
1453	pCtx->eip += cbInstr;
1454	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1455	goto ResumeExecution;
1456	}
1457	AssertMsgFailed(("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1458	rc = VINF_EM_RAW_EMULATE_INSTR;
1459	break;
1460	}
1461
1462	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1463	{
1464	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1465	{
1466	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1467	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1468	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1469	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1470	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1471	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1472
1473	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1474	{
1475	case 0:
1476	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1477	break;
1478	case 2:
1479	break;
1480	case 3:
1481	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1482	break;
1483	case 4:
1484	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1485	break;
1486	default:
1487	AssertFailed();
1488	}
1489	/* Check if a sync operation is pending. */
1490	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1491	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1492	{
1493	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1494	AssertRC(rc);
1495	}
1496	break;
1497
1498	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1499	Log2(("VMX: mov x, crx\n"));
1500	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1501	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1502	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1503	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1504	break;
1505
1506	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1507	Log2(("VMX: clts\n"));
1508	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1509	rc = EMInterpretCLTS(pVM);
1510	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1511	break;
1512
1513	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1514	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1515	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1516	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1517	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1518	break;
1519	}
1520
1521	/* Update EIP if no error occurred. */
1522	if (VBOX_SUCCESS(rc))
1523	pCtx->eip += cbInstr;
1524
1525	if (rc == VINF_SUCCESS)
1526	{
1527	/* Only resume if successful. */
1528	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1529	goto ResumeExecution;
1530	}
1531	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1532	if (rc == VERR_EM_INTERPRETER)
1533	rc = VINF_EM_RAW_EMULATE_INSTR;
1534	break;
1535	}
1536
1537	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1538	{
1539	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1540	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1541	{
1542	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1543	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1544	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1545	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1546	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1547	Log2(("DR7=%08x\n", pCtx->dr7));
1548	}
1549	else
1550	{
1551	Log2(("VMX: mov x, drx\n"));
1552	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1553	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1554	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1555	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1556	}
1557	/* Update EIP if no error occurred. */
1558	if (VBOX_SUCCESS(rc))
1559	pCtx->eip += cbInstr;
1560
1561	if (rc == VINF_SUCCESS)
1562	{
1563	/* Only resume if successful. */
1564	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1565	goto ResumeExecution;
1566	}
1567	Assert(rc == VERR_EM_INTERPRETER);
1568	rc = VINF_EM_RAW_EMULATE_INSTR;
1569	break;
1570	}
1571
1572	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1573	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1574	{
1575	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1576	uint32_t uPort;
1577	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1578
1579	/** @todo necessary to make the distinction? */
1580	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1581	{
1582	uPort = pCtx->edx & 0xffff;
1583	}
1584	else
1585	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1586
1587	/* paranoia */
1588	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1589	{
1590	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1591	break;
1592	}
1593
1594	uint32_t cbSize = aIOSize[uIOWidth];
1595
1596	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1597	{
1598	/* ins/outs */
1599	uint32_t prefix = 0;
1600	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1601	prefix \|= PREFIX_REP;
1602
1603	if (fIOWrite)
1604	{
1605	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1606	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1607	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1608	}
1609	else
1610	{
1611	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1612	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1613	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1614	}
1615	}
1616	else
1617	{
1618	/* normal in/out */
1619	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1620
1621	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1622
1623	if (fIOWrite)
1624	{
1625	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1626	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1627	}
1628	else
1629	{
1630	uint32_t u32Val = 0;
1631
1632	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1633	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1634	if ( rc == VINF_SUCCESS
1635	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1636	{
1637	/* Write back to the EAX register. */
1638	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1639	}
1640	}
1641	}
1642	if ( rc == VINF_SUCCESS
1643	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1644	{
1645	/* Update EIP and continue execution. */
1646	pCtx->eip += cbInstr;
1647	if (RT_LIKELY(rc == VINF_SUCCESS))
1648	{
1649	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1650	goto ResumeExecution;
1651	}
1652	break;
1653	}
1654	#ifdef VBOX_STRICT
1655	if (rc == VINF_IOM_HC_IOPORT_READ)
1656	Assert(!fIOWrite);
1657	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1658	Assert(fIOWrite);
1659	else
1660	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_EM_RESCHEDULE_REM, ("%Vrc\n", rc));
1661	#endif
1662	break;
1663	}
1664
1665	default:
1666	/* The rest is handled after syncing the entire CPU state. */
1667	break;
1668	}
1669
1670	/* Note: the guest state isn't entirely synced back at this stage. */
1671
1672	/* Investigate why there was a VM-exit. (part 2) */
1673	switch (exitReason)
1674	{
1675	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1676	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1677	/* Already handled above. */
1678	break;
1679
1680	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1681	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1682	break;
1683
1684	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1685	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1686	rc = VINF_EM_RAW_INTERRUPT;
1687	AssertFailed(); /* Can't happen. Yet. */
1688	break;
1689
1690	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1691	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1692	rc = VINF_EM_RAW_INTERRUPT;
1693	AssertFailed(); /* Can't happen afaik. */
1694	break;
1695
1696	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1697	rc = VINF_EM_RAW_RING_SWITCH_INT;
1698	break;
1699
1700	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1701	/** Check if external interrupts are pending; if so, don't switch back. */
1702	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1703	{
1704	pCtx->eip++; /* skip hlt */
1705	goto ResumeExecution;
1706	}
1707
1708	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1709	break;
1710
1711	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1712	AssertFailed(); /* can't happen. */
1713	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1714	break;
1715
1716	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1717	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1718	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1719	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1720	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1721	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1722	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1723	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1724	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1725	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1726	/** @todo inject #UD immediately */
1727	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1728	break;
1729
1730	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1731	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1732	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1733	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1734	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1735	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1736	/* already handled above */
1737	AssertMsg(rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_EM_RAW_INTERRUPT \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_PGM_SYNC_CR3 \|\| rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE
1738	\|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc = %d\n", rc));
1739	break;
1740
1741	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1742	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1743	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1744	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1745	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1746	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1747	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1748	break;
1749
1750	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1751	Assert(rc == VINF_EM_RAW_INTERRUPT);
1752	break;
1753
1754	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1755	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1756	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1757	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1758	default:
1759	rc = VERR_EM_INTERNAL_ERROR;
1760	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1761	break;
1762
1763	}
1764	end:
1765	if (fGuestStateSynced)
1766	{
1767	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1768	VMX_READ_SELREG(LDTR, ldtr);
1769	VMX_READ_SELREG(TR, tr);
1770
1771	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1772	pCtx->gdtr.cbGdt = val;
1773	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1774	pCtx->gdtr.pGdt = val;
1775
1776	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1777	pCtx->idtr.cbIdt = val;
1778	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1779	pCtx->idtr.pIdt = val;
1780
1781	/*
1782	* System MSRs
1783	*/
1784	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1785	pCtx->SysEnter.cs = val;
1786	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1787	pCtx->SysEnter.eip = val;
1788	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1789	pCtx->SysEnter.esp = val;
1790	}
1791
1792	/* Signal changes for the recompiler. */
1793	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1794
1795	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
1796	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
1797	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1798	{
1799	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1800	/* On the next entry we'll only sync the host context. */
1801	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1802	}
1803	else
1804	{
1805	/* On the next entry we'll sync everything. */
1806	/** @todo we can do better than this */
1807	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1808	}
1809
1810	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1811	Log2(("X"));
1812	return rc;
1813	}
1814
1815
1816	/**
1817	* Enable VMX
1818	*
1819	* @returns VBox status code.
1820	* @param pVM The VM to operate on.
1821	*/
1822	HWACCMR0DECL(int) VMXR0Enable(PVM pVM)
1823	{
1824	Assert(pVM->hwaccm.s.vmx.fSupported);
1825
1826	/* Make sure the VMX instructions don't cause #UD faults. */
1827	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
1828
1829	/* Enter VMX Root Mode */
1830	int rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
1831	if (VBOX_FAILURE(rc))
1832	return rc;
1833
1834	/* Activate the VM Control Structure. */
1835	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1836	if (VBOX_FAILURE(rc))
1837	{
1838	/* Leave VMX Root Mode. */
1839	VMXDisable();
1840	return rc;
1841	}
1842	pVM->hwaccm.s.vmx.fResumeVM = false;
1843	return VINF_SUCCESS;
1844	}
1845
1846
1847	/**
1848	* Disable VMX
1849	*
1850	* @returns VBox status code.
1851	* @param pVM The VM to operate on.
1852	*/
1853	HWACCMR0DECL(int) VMXR0Disable(PVM pVM)
1854	{
1855	Assert(pVM->hwaccm.s.vmx.fSupported);
1856
1857	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
1858	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1859	AssertRC(rc);
1860
1861	/* Leave VMX Root Mode. */
1862	VMXDisable();
1863
1864	return VINF_SUCCESS;
1865	}
1866

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 2762

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