HWVMXR0.cpp@ 2800

Last change on this file since 2800 was 2800, checked in by vboxsync, 18 years ago
More logging in failure case.
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1	/* $Id: HWVMXR0.cpp 2800 2007-05-23 12:03:32Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include "HWVMXR0.h"
41
42
43	/* IO operation lookup arrays. */
44	static uint32_t aIOSize[4] = {1, 2, 0, 4};
45	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
46
47
48	/**
49	* Sets up and activates VMX
50	*
51	* @returns VBox status code.
52	* @param pVM The VM to operate on.
53	*/
54	HWACCMR0DECL(int) VMXR0Setup(PVM pVM)
55	{
56	int rc = VINF_SUCCESS;
57	uint32_t val;
58
59	if (pVM == NULL)
60	return VERR_INVALID_PARAMETER;
61
62	/* Setup Intel VMX. */
63	Assert(pVM->hwaccm.s.vmx.fSupported);
64
65	/* Set revision dword at the beginning of both structures. */
66	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
67	(uint32_t )pVM->hwaccm.s.vmx.pVMXON = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
68
69	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
70	* (which can have very bad consequences!!!)
71	*/
72
73	/* Make sure the VMX instructions don't cause #UD faults. */
74	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
75
76	/* Enter VMX Root Mode */
77	Log(("pVMXONPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMXONPhys));
78	rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
79	if (VBOX_FAILURE(rc))
80	{
81	return rc;
82	}
83
84	/* Clear VM Control Structure. */
85	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
86	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
87	if (VBOX_FAILURE(rc))
88	goto vmx_end;
89
90	/* Activate the VM Control Structure. */
91	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
92	if (VBOX_FAILURE(rc))
93	goto vmx_end;
94
95	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
96	* Set required bits to one and zero according to the MSR capabilities.
97	*/
98	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
99	/* External and non-maskable interrupts cause VM-exits. */
100	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
101	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
102
103	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
104	AssertRC(rc);
105
106	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
107	* Set required bits to one and zero according to the MSR capabilities.
108	*/
109	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
110	/* Program which event cause VM-exits and which features we want to use. */
111	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
112	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
113	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
114	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
115	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
116	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
117
118	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
119
120	/*
121	if AMD64 guest mode
122	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
123	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
124	*/
125	#if HC_ARCH_BITS == 64
126	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
127	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
128	#endif
129	/* Mask away the bits that the CPU doesn't support */
130	/** @todo make sure they don't conflict with the above requirements. */
131	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
132	pVM->hwaccm.s.vmx.proc_ctls = val;
133
134	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
135	AssertRC(rc);
136
137	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
138	* Set required bits to one and zero according to the MSR capabilities.
139	*/
140	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
141	AssertRC(rc);
142
143	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
144	* Set required bits to one and zero according to the MSR capabilities.
145	*/
146	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
147	if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
148	{
149	/** @todo 32 bits guest mode only for now. */
150	/* val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
151	}
152	/* Mask away the bits that the CPU doesn't support */
153	/** @todo make sure they don't conflict with the above requirements. */
154	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
155	/* else Must be zero when AMD64 is not available. */
156	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
157	AssertRC(rc);
158
159	/* VMX_VMCS_CTRL_EXIT_CONTROLS
160	* Set required bits to one and zero according to the MSR capabilities.
161	*/
162	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
163	#if HC_ARCH_BITS == 64
164	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
165	#else
166	/* else Must be zero when AMD64 is not available. */
167	#endif
168	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
169	/* Don't acknowledge external interrupts on VM-exit. */
170	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
171	AssertRC(rc);
172
173	/* Forward all exception except #NM & #PF to the guest.
174	* We always need to check pagefaults since our shadow page table can be out of sync.
175	* And we always lazily sync the FPU & XMM state.
176	*/
177
178	/*
179	* @todo Possible optimization:
180	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
181	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
182	* registers ourselves of course.
183	*
184	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
185	*/
186	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
187	AssertRC(rc);
188
189	/* Don't filter page faults; all of them should cause a switch. */
190	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
191	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
192	AssertRC(rc);
193
194	/* Init TSC offset to zero. */
195	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
196	#if HC_ARCH_BITS == 32
197	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
198	#endif
199	AssertRC(rc);
200
201	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
202	#if HC_ARCH_BITS == 32
203	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
204	#endif
205	AssertRC(rc);
206
207	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
208	#if HC_ARCH_BITS == 32
209	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
210	#endif
211	AssertRC(rc);
212
213	/* Clear MSR controls. */
214	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
215	{
216	/* Optional */
217	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
218	#if HC_ARCH_BITS == 32
219	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
220	#endif
221	AssertRC(rc);
222	}
223	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
224	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
225	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
226	#if HC_ARCH_BITS == 32
227	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
228	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
229	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
230	#endif
231	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
232	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
233	AssertRC(rc);
234
235	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
236	{
237	/* Optional */
238	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
239	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
240	#if HC_ARCH_BITS == 32
241	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
242	#endif
243	AssertRC(rc);
244	}
245
246	/* Set link pointer to -1. Not currently used. */
247	#if HC_ARCH_BITS == 32
248	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
249	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
250	#else
251	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
252	#endif
253	AssertRC(rc);
254
255	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
256	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
257	AssertRC(rc);
258
259	vmx_end:
260	/* Leave VMX Root Mode. */
261	VMXDisable();
262	return rc;
263	}
264
265
266	/**
267	* Injects an event (trap or external interrupt)
268	*
269	* @returns VBox status code.
270	* @param pVM The VM to operate on.
271	* @param pCtx CPU Context
272	* @param intInfo VMX interrupt info
273	* @param cbInstr Opcode length of faulting instruction
274	* @param errCode Error code (optional)
275	*/
276	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
277	{
278	int rc;
279
280	#ifdef VBOX_STRICT
281	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
282	if (iGate == 0xE)
283	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
284	else
285	if (iGate < 0x20)
286	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
287	else
288	{
289	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
290	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
291	Assert(pCtx->eflags.u32 & X86_EFL_IF);
292	}
293	#endif
294
295	/* Set event injection state. */
296	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
297	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
298	);
299
300	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
301	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
302
303	AssertRC(rc);
304	return rc;
305	}
306
307
308	/**
309	* Checks for pending guest interrupts and injects them
310	*
311	* @returns VBox status code.
312	* @param pVM The VM to operate on.
313	* @param pCtx CPU Context
314	*/
315	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
316	{
317	int rc;
318
319	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
320	if (pVM->hwaccm.s.Event.fPending)
321	{
322	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
323	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
324	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
325	AssertRC(rc);
326
327	pVM->hwaccm.s.Event.fPending = false;
328	return VINF_SUCCESS;
329	}
330
331	/* When external interrupts are pending, we should exit the VM when IF is set. */
332	if ( !TRPMHasTrap(pVM)
333	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
334	{
335	if (!(pCtx->eflags.u32 & X86_EFL_IF))
336	{
337	Log2(("Enable irq window exit!\n"));
338	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT);
339	AssertRC(rc);
340	}
341	else
342	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
343	{
344	uint8_t u8Interrupt;
345
346	rc = PDMGetInterrupt(pVM, &u8Interrupt);
347	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
348	if (VBOX_SUCCESS(rc))
349	{
350	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
351	AssertRC(rc);
352	}
353	else
354	{
355	/* can't happen... */
356	AssertFailed();
357	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
358	return VINF_EM_RAW_INTERRUPT_PENDING;
359	}
360	}
361	else
362	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
363	}
364
365	#ifdef VBOX_STRICT
366	if (TRPMHasTrap(pVM))
367	{
368	uint8_t u8Vector;
369	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
370	AssertRC(rc);
371	}
372	#endif
373
374	if ( pCtx->eflags.u32 & X86_EFL_IF
375	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
376	&& TRPMHasTrap(pVM)
377	)
378	{
379	uint8_t u8Vector;
380	int rc;
381	TRPMEVENT enmType;
382	RTGCUINTPTR intInfo, errCode;
383
384	/* If a new event is pending, then dispatch it now. */
385	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
386	AssertRC(rc);
387	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
388	Assert(enmType != TRPM_SOFTWARE_INT);
389
390	/* Clear the pending trap. */
391	rc = TRPMResetTrap(pVM);
392	AssertRC(rc);
393
394	intInfo = u8Vector;
395	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
396
397	if (enmType == TRPM_TRAP)
398	{
399	switch (u8Vector) {
400	case 8:
401	case 10:
402	case 11:
403	case 12:
404	case 13:
405	case 14:
406	case 17:
407	/* Valid error codes. */
408	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
409	break;
410	default:
411	break;
412	}
413	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
414	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
415	else
416	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
417	}
418	else
419	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
420
421	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
422	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
423	AssertRC(rc);
424	} /* if (interrupts can be dispatched) */
425
426	return VINF_SUCCESS;
427	}
428
429	/**
430	* Save the host state
431	*
432	* @returns VBox status code.
433	* @param pVM The VM to operate on.
434	*/
435	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
436	{
437	int rc = VINF_SUCCESS;
438
439	/*
440	* Host CPU Context
441	*/
442	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
443	{
444	RTIDTR idtr;
445	RTGDTR gdtr;
446	RTSEL SelTR;
447	PVBOXDESC pDesc;
448	uintptr_t trBase;
449
450	/* Control registers */
451	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
452	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
453	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
454	AssertRC(rc);
455	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
456	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
457	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
458
459	/* Selector registers. */
460	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
461	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
462	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
463	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
464	#if HC_ARCH_BITS == 32
465	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
466	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
467	#endif
468	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
469	SelTR = ASMGetTR();
470	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
471	AssertRC(rc);
472	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
473	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
474	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
475	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
476	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
477	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
478	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
479
480	/* GDTR & IDTR */
481	ASMGetGDTR(&gdtr);
482	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
483	ASMGetIDTR(&idtr);
484	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
485	AssertRC(rc);
486	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
487	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
488
489	/* Save the base address of the TR selector. */
490	if (SelTR > gdtr.cbGdt)
491	{
492	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
493	return VERR_VMX_INVALID_HOST_STATE;
494	}
495
496	pDesc = &((PVBOXDESC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT];
497	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16) \| (pDesc->Gen.u8BaseHigh2 << 24);
498	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
499	AssertRC(rc);
500	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
501
502	/* FS and GS base. */
503	#if HC_ARCH_BITS == 64
504	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
505	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
506	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
507	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
508	#endif
509	AssertRC(rc);
510
511	/* Sysenter MSRs. */
512	/** @todo expensive!! */
513	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
514	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
515	#if HC_ARCH_BITS == 32
516	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
517	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
518	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
519	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
520	#else
521	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
522	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
523	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
524	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
525	#endif
526	AssertRC(rc);
527
528	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
529	}
530	return rc;
531	}
532
533
534	/**
535	* Loads the guest state
536	*
537	* @returns VBox status code.
538	* @param pVM The VM to operate on.
539	* @param pCtx Guest context
540	*/
541	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
542	{
543	int rc = VINF_SUCCESS;
544	RTGCUINTPTR val;
545
546	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
547	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
548	{
549	VMX_WRITE_SELREG(ES, es);
550	AssertRC(rc);
551
552	VMX_WRITE_SELREG(CS, cs);
553	AssertRC(rc);
554
555	VMX_WRITE_SELREG(SS, ss);
556	AssertRC(rc);
557
558	VMX_WRITE_SELREG(DS, ds);
559	AssertRC(rc);
560
561	VMX_WRITE_SELREG(FS, fs);
562	AssertRC(rc);
563
564	VMX_WRITE_SELREG(GS, gs);
565	AssertRC(rc);
566	}
567
568	/* Guest CPU context: LDTR. */
569	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
570	{
571	if (pCtx->ldtr == 0)
572	{
573	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
574	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
575	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
576	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
577	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
578	}
579	else
580	{
581	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
582	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
583	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
584	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
585	}
586	AssertRC(rc);
587	}
588	/* Guest CPU context: TR. */
589	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
590	{
591	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
592	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
593	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
594	val = pCtx->trHid.Attr.u;
595
596	/* The TSS selector must be busy. */
597	if ((val & 0xF) == X86_SEL_TYPE_SYS_386_TSS_AVAIL)
598	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
599	else
600	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
601	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
602
603	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
604	AssertRC(rc);
605	}
606	/* Guest CPU context: GDTR. */
607	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
608	{
609	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
610	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
611	AssertRC(rc);
612	}
613	/* Guest CPU context: IDTR. */
614	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
615	{
616	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
617	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
618	AssertRC(rc);
619	}
620
621	/*
622	* Sysenter MSRs
623	*/
624	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
625	{
626	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
627	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
628	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
629	AssertRC(rc);
630	}
631
632	/* Control registers */
633	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
634	{
635	val = pCtx->cr0;
636	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
637	Log2(("Guest CR0-shadow %08x\n", val));
638	if (CPUMIsGuestFPUStateActive(pVM) == false)
639	{
640	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
641	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
642	}
643	else
644	{
645	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
646	/** @todo check if we support the old style mess correctly. */
647	if (!(val & X86_CR0_NE))
648	{
649	Log(("Forcing X86_CR0_NE!!!\n"));
650
651	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
652	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
653	{
654	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| BIT(16));
655	AssertRC(rc);
656	pVM->hwaccm.s.fFPUOldStyleOverride = true;
657	}
658	}
659
660	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
661	}
662	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
663	Log2(("Guest CR0 %08x\n", val));
664	/* CR0 flags owned by the host; if the guests attempts to change them, then
665	* the VM will exit.
666	*/
667	val = X86_CR0_PE
668	\| X86_CR0_WP /** @todo do we care? (we do if we start patching the guest) */
669	\| X86_CR0_PG
670	\| X86_CR0_TS
671	\| X86_CR0_ET
672	\| X86_CR0_NE
673	\| X86_CR0_MP;
674	pVM->hwaccm.s.vmx.cr0_mask = val;
675
676	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
677	Log2(("Guest CR0-mask %08x\n", val));
678	AssertRC(rc);
679	}
680	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
681	{
682	/* CR4 */
683	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
684	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
685	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
686	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
687	switch(pVM->hwaccm.s.enmShadowMode)
688	{
689	case PGMMODE_REAL:
690	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
691	AssertFailed();
692	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
693
694	case PGMMODE_32_BIT: /* 32-bit paging. */
695	break;
696
697	case PGMMODE_PAE: /* PAE paging. */
698	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
699	/** @todo use normal 32 bits paging */
700	val \|= X86_CR4_PAE;
701	break;
702
703	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
704	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
705	AssertFailed();
706	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
707
708	default: /* shut up gcc */
709	AssertFailed();
710	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
711	}
712	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
713	Log2(("Guest CR4 %08x\n", val));
714	/* CR4 flags owned by the host; if the guests attempts to change them, then
715	* the VM will exit.
716	*/
717	val = X86_CR4_PAE
718	\| X86_CR4_PGE
719	\| X86_CR4_PSE
720	\| X86_CR4_VMXE;
721	pVM->hwaccm.s.vmx.cr4_mask = val;
722
723	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
724	Log2(("Guest CR4-mask %08x\n", val));
725	AssertRC(rc);
726	}
727
728	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
729	{
730	/* Save our shadow CR3 register. */
731	val = PGMGetHyperCR3(pVM);
732	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
733	AssertRC(rc);
734	}
735
736	/* Debug registers. */
737	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
738	{
739	/** @todo DR0-6 */
740	val = pCtx->dr7;
741	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
742	val \|= 0x400; /* must be one */
743	#ifdef VBOX_STRICT
744	val = 0x400;
745	#endif
746	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
747	AssertRC(rc);
748
749	/* IA32_DEBUGCTL MSR. */
750	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
751	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
752	AssertRC(rc);
753
754	/** @todo */
755	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
756	AssertRC(rc);
757	}
758
759	/* EIP, ESP and EFLAGS */
760	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
761	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
762	AssertRC(rc);
763
764	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
765	val = pCtx->eflags.u32;
766	val &= VMX_EFLAGS_RESERVED_0;
767	val \|= VMX_EFLAGS_RESERVED_1;
768	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, val);
769	AssertRC(rc);
770
771	/** TSC offset. */
772	/** @todo use host tsc if safe, other intercept rdtsc */
773	uint64_t u64TSCOffset = TMCpuTickGetOffset(pVM);
774
775	#if HC_ARCH_BITS == 64
776	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
777	#else
778	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
779	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
780	#endif
781	AssertRC(rc);
782
783	/* Done. */
784	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
785
786	return rc;
787	}
788
789	/**
790	* Runs guest code in a VMX VM.
791	*
792	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
793	*
794	* @returns VBox status code.
795	* @param pVM The VM to operate on.
796	* @param pCtx Guest context
797	*/
798	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
799	{
800	int rc = VINF_SUCCESS;
801	RTCCUINTREG val, valShadow;
802	RTCCUINTREG exitReason, instrError, cbInstr;
803	RTGCUINTPTR exitQualification;
804	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
805	RTGCUINTPTR errCode, instrInfo, uInterruptState;
806	bool fGuestStateSynced = false;
807
808	Log2(("\nE"));
809
810	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
811
812	#ifdef VBOX_STRICT
813	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
814	AssertRC(rc);
815	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
816
817	/* allowed zero */
818	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
819	{
820	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
821	}
822	/* allowed one */
823	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
824	{
825	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
826	}
827
828	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
829	AssertRC(rc);
830	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
831
832	/* allowed zero */
833	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
834	{
835	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
836	}
837	/* allowed one */
838	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
839	{
840	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
841	}
842
843	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
844	AssertRC(rc);
845	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
846
847	/* allowed zero */
848	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
849	{
850	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
851	}
852	/* allowed one */
853	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
854	{
855	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
856	}
857
858	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
859	AssertRC(rc);
860	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
861
862	/* allowed zero */
863	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
864	{
865	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
866	}
867	/* allowed one */
868	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
869	{
870	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
871	}
872	#endif
873
874	#if 0
875	/*
876	* Check if debug registers are armed.
877	*/
878	uint32_t u32DR7 = ASMGetDR7();
879	if (u32DR7 & X86_DR7_ENABLED_MASK)
880	{
881	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
882	}
883	else
884	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
885	#endif
886
887	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
888	*/
889	ResumeExecution:
890
891	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
892	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
893	{
894	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
895	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
896	{
897	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
898	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
899	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
900	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
901	*/
902	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
903	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
904	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
905	AssertRC(rc);
906	}
907	}
908	else
909	{
910	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
911	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
912	AssertRC(rc);
913	}
914
915	/* Check for pending actions that force us to go back to ring 3. */
916	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
917	{
918	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
919	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
920	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
921	rc = VINF_EM_RAW_TO_R3;
922	goto end;
923	}
924	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
925	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
926	{
927	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
928	rc = VINF_EM_PENDING_REQUEST;
929	goto end;
930	}
931
932	/* When external interrupts are pending, we should exit the VM when IF is set. */
933	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
934	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
935	if (VBOX_FAILURE(rc))
936	{
937	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
938	goto end;
939	}
940
941	/** @todo check timers?? */
942
943	/* Save the host state first. */
944	rc = VMXR0SaveHostState(pVM);
945	if (rc != VINF_SUCCESS)
946	{
947	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
948	goto end;
949	}
950	/* Load the guest state */
951	rc = VMXR0LoadGuestState(pVM, pCtx);
952	if (rc != VINF_SUCCESS)
953	{
954	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
955	goto end;
956	}
957	fGuestStateSynced = true;
958
959	/* Non-register state Guest Context */
960	/** @todo change me according to cpu state */
961	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
962	AssertRC(rc);
963
964	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
965
966	/* Manual save and restore:
967	* - General purpose registers except RIP, RSP
968	*
969	* Trashed:
970	* - CR2 (we don't care)
971	* - LDTR (reset to 0)
972	* - DRx (presumably not changed at all)
973	* - DR7 (reset to 0x400)
974	* - EFLAGS (reset to BIT(1); not relevant)
975	*
976	*/
977
978	/* All done! Let's start VM execution. */
979	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
980	if (pVM->hwaccm.s.vmx.fResumeVM == false)
981	{
982	rc = VMXStartVM(pCtx);
983	}
984	else
985	{
986	rc = VMXResumeVM(pCtx);
987	}
988
989	/* In case we execute a goto ResumeExecution later on. */
990	pVM->hwaccm.s.vmx.fResumeVM = true;
991
992	/**
993	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
994	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
995	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
996	*/
997
998	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
999	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1000
1001	switch (rc)
1002	{
1003	case VINF_SUCCESS:
1004	break;
1005
1006	case VERR_VMX_INVALID_VMXON_PTR:
1007	AssertFailed();
1008	goto end;
1009
1010	case VERR_VMX_UNABLE_TO_START_VM:
1011	case VERR_VMX_UNABLE_TO_RESUME_VM:
1012	{
1013	#ifdef VBOX_STRICT
1014	int rc1;
1015
1016	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1017	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1018	AssertRC(rc1);
1019	if (rc1 == VINF_SUCCESS)
1020	{
1021	RTGDTR gdtr;
1022	PVBOXDESC pDesc;
1023
1024	ASMGetGDTR(&gdtr);
1025
1026	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1027	Log(("Current stack %08x\n", &rc1));
1028
1029
1030	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1031	Log(("Old eip %VGv new %VGv\n", pCtx->eip, (RTGCPTR)val));
1032	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1033	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1034	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1035	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1036	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1037	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1038	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1039	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1040
1041	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1042	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1043
1044	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1045	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1046
1047	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1048	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1049
1050	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1051	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1052	if (val < gdtr.cbGdt)
1053	{
1054	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1055	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1056	}
1057
1058	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1059	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1060	if (val < gdtr.cbGdt)
1061	{
1062	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1063	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1064	}
1065
1066	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1067	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1068	if (val < gdtr.cbGdt)
1069	{
1070	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1071	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1072	}
1073
1074	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1075	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1076	if (val < gdtr.cbGdt)
1077	{
1078	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1079	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1080	}
1081
1082	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1083	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1084	if (val < gdtr.cbGdt)
1085	{
1086	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1087	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1088	}
1089
1090	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1091	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1092	if (val < gdtr.cbGdt)
1093	{
1094	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1095	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1096	}
1097
1098	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1099	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1100	if (val < gdtr.cbGdt)
1101	{
1102	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1103	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1104	}
1105
1106	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1107	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1108
1109	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1110	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1111	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1112	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1113
1114	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1115	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1116
1117	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1118	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1119
1120	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1121	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1122
1123	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1124	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1125	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1126	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1127
1128	#if HC_ARCH_BITS == 64
1129	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1130	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1131	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1132	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1133	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1134	#endif
1135	}
1136	#endif /* VBOX_STRICT */
1137	goto end;
1138	}
1139
1140	default:
1141	/* impossible */
1142	AssertFailed();
1143	goto end;
1144	}
1145	/* Success. Query the guest state and figure out what has happened. */
1146
1147	/* Investigate why there was a VM-exit. */
1148	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1149	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1150
1151	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1152	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1153	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1154	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1155	intInfo = val;
1156	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1157	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1158	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1159	instrInfo = val;
1160	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1161	exitQualification = val;
1162	AssertRC(rc);
1163
1164	/* Take care of instruction fusing (sti, mov ss) */
1165	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1166	uInterruptState = val;
1167	if (uInterruptState != 0)
1168	{
1169	Assert(uInterruptState <= 2); /* only sti & mov ss */
1170	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1171	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1172	}
1173	else
1174	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1175
1176	/* Let's first sync back eip, esp, and eflags. */
1177	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1178	AssertRC(rc);
1179	pCtx->eip = val;
1180	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1181	AssertRC(rc);
1182	pCtx->esp = val;
1183	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1184	AssertRC(rc);
1185	pCtx->eflags.u32 = val;
1186
1187	/* Control registers. */
1188	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1189	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1190	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1191	CPUMSetGuestCR0(pVM, val);
1192
1193	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1194	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1195	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1196	CPUMSetGuestCR4(pVM, val);
1197
1198	CPUMSetGuestCR2(pVM, ASMGetCR2());
1199
1200	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1201	CPUMSetGuestDR7(pVM, val);
1202
1203	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1204	VMX_READ_SELREG(ES, es);
1205	VMX_READ_SELREG(SS, ss);
1206	VMX_READ_SELREG(CS, cs);
1207	VMX_READ_SELREG(DS, ds);
1208	VMX_READ_SELREG(FS, fs);
1209	VMX_READ_SELREG(GS, gs);
1210
1211	/** @note NOW IT'S SAFE FOR LOGGING! */
1212	Log2(("Raw exit reason %08x\n", exitReason));
1213
1214	/* Check if an injected event was interrupted prematurely. */
1215	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1216	AssertRC(rc);
1217	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1218	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1219	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1220	{
1221	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1222	pVM->hwaccm.s.Event.fPending = true;
1223	/* Error code present? */
1224	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1225	{
1226	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1227	AssertRC(rc);
1228	pVM->hwaccm.s.Event.errCode = val;
1229	}
1230	else
1231	pVM->hwaccm.s.Event.errCode = 0;
1232	}
1233
1234	#ifdef VBOX_STRICT
1235	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1236	HWACCMDumpRegs(pCtx);
1237	#endif
1238
1239	Log2(("E%d", exitReason));
1240	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1241	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1242	Log2(("Interruption error code %d\n", errCode));
1243	Log2(("IntInfo = %08x\n", intInfo));
1244	Log2(("New EIP=%VGv\n", pCtx->eip));
1245
1246	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1247	switch (exitReason)
1248	{
1249	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1250	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1251	{
1252	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1253
1254	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1255	{
1256	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1257	/* External interrupt; leave to allow it to be dispatched again. */
1258	rc = VINF_EM_RAW_INTERRUPT;
1259	break;
1260	}
1261	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1262	{
1263	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1264	/* External interrupt; leave to allow it to be dispatched again. */
1265	rc = VINF_EM_RAW_INTERRUPT;
1266	break;
1267
1268	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1269	AssertFailed(); /* can't come here; fails the first check. */
1270	break;
1271
1272	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1273	Assert(vector == 3 \|\| vector == 4);
1274	/* no break */
1275	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1276	Log2(("Hardware/software interrupt %d\n", vector));
1277	switch (vector)
1278	{
1279	case X86_XCPT_NM:
1280	{
1281	uint32_t oldCR0;
1282
1283	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1284
1285	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1286	oldCR0 = ASMGetCR0();
1287	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1288	rc = CPUMHandleLazyFPU(pVM);
1289	if (rc == VINF_SUCCESS)
1290	{
1291	Assert(CPUMIsGuestFPUStateActive(pVM));
1292
1293	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1294	ASMSetCR0(oldCR0);
1295
1296	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1297
1298	/* Continue execution. */
1299	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1300	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1301
1302	goto ResumeExecution;
1303	}
1304
1305	Log(("Forward #NM fault to the guest\n"));
1306	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1307	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1308	AssertRC(rc);
1309	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1310	goto ResumeExecution;
1311	}
1312
1313	case X86_XCPT_PF: /* Page fault */
1314	{
1315	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1316	/* Exit qualification contains the linear address of the page fault. */
1317	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1318	TRPMSetErrorCode(pVM, errCode);
1319	TRPMSetFaultAddress(pVM, exitQualification);
1320
1321	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1322	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1323	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1324	if (rc == VINF_SUCCESS)
1325	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1326	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1327	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1328
1329	TRPMResetTrap(pVM);
1330
1331	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1332	goto ResumeExecution;
1333	}
1334	else
1335	if (rc == VINF_EM_RAW_GUEST_TRAP)
1336	{ /* A genuine pagefault.
1337	* Forward the trap to the guest by injecting the exception and resuming execution.
1338	*/
1339	Log2(("Forward page fault to the guest\n"));
1340	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1341	/* The error code might have been changed. */
1342	errCode = TRPMGetErrorCode(pVM);
1343
1344	TRPMResetTrap(pVM);
1345
1346	/* Now we must update CR2. */
1347	pCtx->cr2 = exitQualification;
1348	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1349	AssertRC(rc);
1350
1351	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1352	goto ResumeExecution;
1353	}
1354	#ifdef VBOX_STRICT
1355	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1356	Log(("PGMTrap0eHandler failed with %d\n", rc));
1357	#endif
1358	/* Need to go back to the recompiler to emulate the instruction. */
1359	TRPMResetTrap(pVM);
1360	break;
1361	}
1362
1363	case X86_XCPT_MF: /* Floating point exception. */
1364	{
1365	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1366	if (!(pCtx->cr0 & X86_CR0_NE))
1367	{
1368	/* old style FPU error reporting needs some extra work. */
1369	/** @todo don't fall back to the recompiler, but do it manually. */
1370	rc = VINF_EM_RAW_EMULATE_INSTR;
1371	break;
1372	}
1373	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1374	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1375	AssertRC(rc);
1376
1377	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1378	goto ResumeExecution;
1379	}
1380
1381	#ifdef VBOX_STRICT
1382	case X86_XCPT_GP: /* General protection failure exception.*/
1383	case X86_XCPT_UD: /* Unknown opcode exception. */
1384	case X86_XCPT_DE: /* Debug exception. */
1385	case X86_XCPT_SS: /* Stack segment exception. */
1386	case X86_XCPT_NP: /* Segment not present exception. */
1387	{
1388	switch(vector)
1389	{
1390	case X86_XCPT_DE:
1391	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1392	break;
1393	case X86_XCPT_UD:
1394	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1395	break;
1396	case X86_XCPT_SS:
1397	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1398	break;
1399	case X86_XCPT_NP:
1400	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1401	break;
1402	case X86_XCPT_GP:
1403	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1404	break;
1405	}
1406
1407	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1408	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1409	AssertRC(rc);
1410
1411	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1412	goto ResumeExecution;
1413	}
1414	#endif
1415	default:
1416	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1417	rc = VERR_EM_INTERNAL_ERROR;
1418	break;
1419	} /* switch (vector) */
1420
1421	break;
1422
1423	default:
1424	rc = VERR_EM_INTERNAL_ERROR;
1425	AssertFailed();
1426	break;
1427	}
1428
1429	break;
1430	}
1431
1432	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1433	/* Clear VM-exit on IF=1 change. */
1434	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1435	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1436	AssertRC(rc);
1437	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1438	goto ResumeExecution; /* we check for pending guest interrupts there */
1439
1440	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1441	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1442	/* Skip instruction and continue directly. */
1443	pCtx->eip += cbInstr;
1444	/* Continue execution.*/
1445	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1446	goto ResumeExecution;
1447
1448	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1449	{
1450	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1451	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1452	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1453	if (rc == VINF_SUCCESS)
1454	{
1455	/* Update EIP and continue execution. */
1456	Assert(cbInstr == 2);
1457	pCtx->eip += cbInstr;
1458	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1459	goto ResumeExecution;
1460	}
1461	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1462	rc = VINF_EM_RAW_EMULATE_INSTR;
1463	break;
1464	}
1465
1466	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1467	{
1468	Log2(("VMX: Rdtsc\n"));
1469	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1470	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1471	if (rc == VINF_SUCCESS)
1472	{
1473	/* Update EIP and continue execution. */
1474	Assert(cbInstr == 2);
1475	pCtx->eip += cbInstr;
1476	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1477	goto ResumeExecution;
1478	}
1479	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1480	rc = VINF_EM_RAW_EMULATE_INSTR;
1481	break;
1482	}
1483
1484	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1485	{
1486	Log2(("VMX: invlpg\n"));
1487	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1488	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1489	if (rc == VINF_SUCCESS)
1490	{
1491	/* Update EIP and continue execution. */
1492	pCtx->eip += cbInstr;
1493	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1494	goto ResumeExecution;
1495	}
1496	AssertMsgFailed(("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1497	rc = VINF_EM_RAW_EMULATE_INSTR;
1498	break;
1499	}
1500
1501	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1502	{
1503	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1504	{
1505	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1506	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1507	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1508	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1509	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1510	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1511
1512	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1513	{
1514	case 0:
1515	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1516	break;
1517	case 2:
1518	break;
1519	case 3:
1520	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1521	break;
1522	case 4:
1523	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1524	break;
1525	default:
1526	AssertFailed();
1527	}
1528	/* Check if a sync operation is pending. */
1529	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1530	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1531	{
1532	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1533	AssertRC(rc);
1534	}
1535	break;
1536
1537	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1538	Log2(("VMX: mov x, crx\n"));
1539	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1540	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1541	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1542	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1543	break;
1544
1545	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1546	Log2(("VMX: clts\n"));
1547	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1548	rc = EMInterpretCLTS(pVM);
1549	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1550	break;
1551
1552	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1553	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1554	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1555	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1556	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1557	break;
1558	}
1559
1560	/* Update EIP if no error occurred. */
1561	if (VBOX_SUCCESS(rc))
1562	pCtx->eip += cbInstr;
1563
1564	if (rc == VINF_SUCCESS)
1565	{
1566	/* Only resume if successful. */
1567	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1568	goto ResumeExecution;
1569	}
1570	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1571	if (rc == VERR_EM_INTERPRETER)
1572	rc = VINF_EM_RAW_EMULATE_INSTR;
1573	break;
1574	}
1575
1576	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1577	{
1578	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1579	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1580	{
1581	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1582	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1583	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1584	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1585	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1586	Log2(("DR7=%08x\n", pCtx->dr7));
1587	}
1588	else
1589	{
1590	Log2(("VMX: mov x, drx\n"));
1591	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1592	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1593	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1594	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1595	}
1596	/* Update EIP if no error occurred. */
1597	if (VBOX_SUCCESS(rc))
1598	pCtx->eip += cbInstr;
1599
1600	if (rc == VINF_SUCCESS)
1601	{
1602	/* Only resume if successful. */
1603	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1604	goto ResumeExecution;
1605	}
1606	Assert(rc == VERR_EM_INTERPRETER);
1607	rc = VINF_EM_RAW_EMULATE_INSTR;
1608	break;
1609	}
1610
1611	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1612	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1613	{
1614	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1615	uint32_t uPort;
1616	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1617
1618	/** @todo necessary to make the distinction? */
1619	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1620	{
1621	uPort = pCtx->edx & 0xffff;
1622	}
1623	else
1624	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1625
1626	/* paranoia */
1627	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1628	{
1629	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1630	break;
1631	}
1632
1633	uint32_t cbSize = aIOSize[uIOWidth];
1634
1635	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1636	{
1637	/* ins/outs */
1638	uint32_t prefix = 0;
1639	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1640	prefix \|= PREFIX_REP;
1641
1642	if (fIOWrite)
1643	{
1644	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1645	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1646	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1647	}
1648	else
1649	{
1650	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1651	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1652	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1653	}
1654	}
1655	else
1656	{
1657	/* normal in/out */
1658	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1659
1660	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1661
1662	if (fIOWrite)
1663	{
1664	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1665	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1666	}
1667	else
1668	{
1669	uint32_t u32Val = 0;
1670
1671	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1672	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1673	if ( rc == VINF_SUCCESS
1674	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1675	{
1676	/* Write back to the EAX register. */
1677	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1678	}
1679	}
1680	}
1681	if ( rc == VINF_SUCCESS
1682	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1683	{
1684	/* Update EIP and continue execution. */
1685	pCtx->eip += cbInstr;
1686	if (RT_LIKELY(rc == VINF_SUCCESS))
1687	{
1688	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1689	goto ResumeExecution;
1690	}
1691	break;
1692	}
1693	#ifdef VBOX_STRICT
1694	if (rc == VINF_IOM_HC_IOPORT_READ)
1695	Assert(!fIOWrite);
1696	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1697	Assert(fIOWrite);
1698	else
1699	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_EM_RESCHEDULE_REM, ("%Vrc\n", rc));
1700	#endif
1701	break;
1702	}
1703
1704	default:
1705	/* The rest is handled after syncing the entire CPU state. */
1706	break;
1707	}
1708
1709	/* Note: the guest state isn't entirely synced back at this stage. */
1710
1711	/* Investigate why there was a VM-exit. (part 2) */
1712	switch (exitReason)
1713	{
1714	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1715	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1716	/* Already handled above. */
1717	break;
1718
1719	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1720	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1721	break;
1722
1723	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1724	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1725	rc = VINF_EM_RAW_INTERRUPT;
1726	AssertFailed(); /* Can't happen. Yet. */
1727	break;
1728
1729	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1730	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1731	rc = VINF_EM_RAW_INTERRUPT;
1732	AssertFailed(); /* Can't happen afaik. */
1733	break;
1734
1735	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1736	rc = VINF_EM_RAW_RING_SWITCH_INT;
1737	break;
1738
1739	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1740	/** Check if external interrupts are pending; if so, don't switch back. */
1741	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1742	{
1743	pCtx->eip++; /* skip hlt */
1744	goto ResumeExecution;
1745	}
1746
1747	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1748	break;
1749
1750	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1751	AssertFailed(); /* can't happen. */
1752	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1753	break;
1754
1755	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1756	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1757	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1758	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1759	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1760	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1761	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1762	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1763	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1764	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1765	/** @todo inject #UD immediately */
1766	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1767	break;
1768
1769	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1770	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1771	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1772	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1773	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1774	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1775	/* already handled above */
1776	AssertMsg(rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_EM_RAW_INTERRUPT \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_PGM_SYNC_CR3 \|\| rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE
1777	\|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc = %d\n", rc));
1778	break;
1779
1780	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1781	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1782	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1783	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1784	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1785	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1786	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1787	break;
1788
1789	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1790	Assert(rc == VINF_EM_RAW_INTERRUPT);
1791	break;
1792
1793	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1794	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1795	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1796	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1797	default:
1798	rc = VERR_EM_INTERNAL_ERROR;
1799	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1800	break;
1801
1802	}
1803	end:
1804	if (fGuestStateSynced)
1805	{
1806	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1807	VMX_READ_SELREG(LDTR, ldtr);
1808	VMX_READ_SELREG(TR, tr);
1809
1810	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1811	pCtx->gdtr.cbGdt = val;
1812	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1813	pCtx->gdtr.pGdt = val;
1814
1815	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1816	pCtx->idtr.cbIdt = val;
1817	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1818	pCtx->idtr.pIdt = val;
1819
1820	/*
1821	* System MSRs
1822	*/
1823	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1824	pCtx->SysEnter.cs = val;
1825	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1826	pCtx->SysEnter.eip = val;
1827	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1828	pCtx->SysEnter.esp = val;
1829	}
1830
1831	/* Signal changes for the recompiler. */
1832	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1833
1834	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
1835	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
1836	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1837	{
1838	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1839	/* On the next entry we'll only sync the host context. */
1840	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1841	}
1842	else
1843	{
1844	/* On the next entry we'll sync everything. */
1845	/** @todo we can do better than this */
1846	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1847	}
1848
1849	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1850	Log2(("X"));
1851	return rc;
1852	}
1853
1854
1855	/**
1856	* Enable VMX
1857	*
1858	* @returns VBox status code.
1859	* @param pVM The VM to operate on.
1860	*/
1861	HWACCMR0DECL(int) VMXR0Enable(PVM pVM)
1862	{
1863	Assert(pVM->hwaccm.s.vmx.fSupported);
1864
1865	/* Make sure the VMX instructions don't cause #UD faults. */
1866	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
1867
1868	/* Enter VMX Root Mode */
1869	int rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
1870	if (VBOX_FAILURE(rc))
1871	return rc;
1872
1873	/* Activate the VM Control Structure. */
1874	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1875	if (VBOX_FAILURE(rc))
1876	{
1877	/* Leave VMX Root Mode. */
1878	VMXDisable();
1879	return rc;
1880	}
1881	pVM->hwaccm.s.vmx.fResumeVM = false;
1882	return VINF_SUCCESS;
1883	}
1884
1885
1886	/**
1887	* Disable VMX
1888	*
1889	* @returns VBox status code.
1890	* @param pVM The VM to operate on.
1891	*/
1892	HWACCMR0DECL(int) VMXR0Disable(PVM pVM)
1893	{
1894	Assert(pVM->hwaccm.s.vmx.fSupported);
1895
1896	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
1897	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1898	AssertRC(rc);
1899
1900	/* Leave VMX Root Mode. */
1901	VMXDisable();
1902
1903	return VINF_SUCCESS;
1904	}
1905

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 2800

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