HWVMXR0.cpp@ 4920

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1	/* $Id: HWVMXR0.cpp 4790 2007-09-14 11:40:40Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/hwaccm.h>
24	#include "HWACCMInternal.h"
25	#include <VBox/vm.h>
26	#include <VBox/x86.h>
27	#include <VBox/pgm.h>
28	#include <VBox/pdm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <VBox/selm.h>
32	#include <VBox/iom.h>
33	#include <iprt/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36	#include "HWVMXR0.h"
37
38
39	/* IO operation lookup arrays. */
40	static uint32_t aIOSize[4] = {1, 2, 0, 4};
41	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
42
43
44	static void VMXR0CheckError(PVM pVM, int rc)
45	{
46	if (rc == VERR_VMX_GENERIC)
47	{
48	RTCCUINTREG instrError;
49
50	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
51	Log(("VMXR0CheckError -> generic error %x\n", instrError));
52
53	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
54	}
55	else
56	{
57	Log(("VMXR0CheckError failed with %Vrc\n", rc));
58	}
59	pVM->hwaccm.s.lLastError = rc;
60	}
61
62	/**
63	* Sets up and activates VMX
64	*
65	* @returns VBox status code.
66	* @param pVM The VM to operate on.
67	*/
68	HWACCMR0DECL(int) VMXR0Setup(PVM pVM)
69	{
70	int rc = VINF_SUCCESS;
71	uint32_t val;
72
73	if (pVM == NULL)
74	return VERR_INVALID_PARAMETER;
75
76	/* Setup Intel VMX. */
77	Assert(pVM->hwaccm.s.vmx.fSupported);
78
79	/* Set revision dword at the beginning of both structures. */
80	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
81	(uint32_t )pVM->hwaccm.s.vmx.pVMXON = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
82
83	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
84	* (which can have very bad consequences!!!)
85	*/
86
87	/* Make sure the VMX instructions don't cause #UD faults. */
88	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
89
90	/* Enter VMX Root Mode */
91	Log(("pVMXONPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMXONPhys));
92	rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
93	if (VBOX_FAILURE(rc))
94	{
95	VMXR0CheckError(pVM, rc);
96	return VERR_VMX_VMXON_FAILED;
97	}
98
99	/* Clear VM Control Structure. */
100	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
101	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
102	if (VBOX_FAILURE(rc))
103	goto vmx_end;
104
105	/* Activate the VM Control Structure. */
106	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
107	if (VBOX_FAILURE(rc))
108	goto vmx_end;
109
110	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
111	* Set required bits to one and zero according to the MSR capabilities.
112	*/
113	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
114	/* External and non-maskable interrupts cause VM-exits. */
115	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
116	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
117
118	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
119	AssertRC(rc);
120
121	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
122	* Set required bits to one and zero according to the MSR capabilities.
123	*/
124	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
125	/* Program which event cause VM-exits and which features we want to use. */
126	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
127	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
128	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
129	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
130	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
131	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
132
133	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
134
135	/*
136	if AMD64 guest mode
137	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
138	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
139	*/
140	#if HC_ARCH_BITS == 64
141	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
142	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
143	#endif
144	/* Mask away the bits that the CPU doesn't support */
145	/** @todo make sure they don't conflict with the above requirements. */
146	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
147	pVM->hwaccm.s.vmx.proc_ctls = val;
148
149	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
150	AssertRC(rc);
151
152	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
153	* Set required bits to one and zero according to the MSR capabilities.
154	*/
155	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
156	AssertRC(rc);
157
158	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
159	* Set required bits to one and zero according to the MSR capabilities.
160	*/
161	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
162	if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
163	{
164	/** @todo 32 bits guest mode only for now. */
165	/* val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
166	}
167	/* Mask away the bits that the CPU doesn't support */
168	/** @todo make sure they don't conflict with the above requirements. */
169	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
170	/* else Must be zero when AMD64 is not available. */
171	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
172	AssertRC(rc);
173
174	/* VMX_VMCS_CTRL_EXIT_CONTROLS
175	* Set required bits to one and zero according to the MSR capabilities.
176	*/
177	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
178	#if HC_ARCH_BITS == 64
179	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
180	#else
181	/* else Must be zero when AMD64 is not available. */
182	#endif
183	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
184	/* Don't acknowledge external interrupts on VM-exit. */
185	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
186	AssertRC(rc);
187
188	/* Forward all exception except #NM & #PF to the guest.
189	* We always need to check pagefaults since our shadow page table can be out of sync.
190	* And we always lazily sync the FPU & XMM state.
191	*/
192
193	/*
194	* @todo Possible optimization:
195	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
196	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
197	* registers ourselves of course.
198	*
199	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
200	*/
201	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
202	AssertRC(rc);
203
204	/* Don't filter page faults; all of them should cause a switch. */
205	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
206	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
207	AssertRC(rc);
208
209	/* Init TSC offset to zero. */
210	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
211	#if HC_ARCH_BITS == 32
212	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
213	#endif
214	AssertRC(rc);
215
216	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
217	#if HC_ARCH_BITS == 32
218	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
219	#endif
220	AssertRC(rc);
221
222	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
223	#if HC_ARCH_BITS == 32
224	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
225	#endif
226	AssertRC(rc);
227
228	/* Clear MSR controls. */
229	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
230	{
231	/* Optional */
232	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
233	#if HC_ARCH_BITS == 32
234	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
235	#endif
236	AssertRC(rc);
237	}
238	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
239	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
240	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
241	#if HC_ARCH_BITS == 32
242	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
243	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
244	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
245	#endif
246	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
247	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
248	AssertRC(rc);
249
250	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
251	{
252	/* Optional */
253	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
254	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
255	#if HC_ARCH_BITS == 32
256	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
257	#endif
258	AssertRC(rc);
259	}
260
261	/* Set link pointer to -1. Not currently used. */
262	#if HC_ARCH_BITS == 32
263	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
264	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
265	#else
266	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
267	#endif
268	AssertRC(rc);
269
270	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
271	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
272	AssertRC(rc);
273
274	vmx_end:
275	VMXR0CheckError(pVM, rc);
276	/* Leave VMX Root Mode. */
277	VMXDisable();
278	return rc;
279	}
280
281
282	/**
283	* Injects an event (trap or external interrupt)
284	*
285	* @returns VBox status code.
286	* @param pVM The VM to operate on.
287	* @param pCtx CPU Context
288	* @param intInfo VMX interrupt info
289	* @param cbInstr Opcode length of faulting instruction
290	* @param errCode Error code (optional)
291	*/
292	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
293	{
294	int rc;
295
296	#ifdef VBOX_STRICT
297	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
298	if (iGate == 0xE)
299	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
300	else
301	if (iGate < 0x20)
302	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
303	else
304	{
305	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
306	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
307	Assert(pCtx->eflags.u32 & X86_EFL_IF);
308	}
309	#endif
310
311	/* Set event injection state. */
312	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
313	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
314	);
315
316	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
317	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
318
319	AssertRC(rc);
320	return rc;
321	}
322
323
324	/**
325	* Checks for pending guest interrupts and injects them
326	*
327	* @returns VBox status code.
328	* @param pVM The VM to operate on.
329	* @param pCtx CPU Context
330	*/
331	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
332	{
333	int rc;
334
335	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
336	if (pVM->hwaccm.s.Event.fPending)
337	{
338	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
339	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
340	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
341	AssertRC(rc);
342
343	pVM->hwaccm.s.Event.fPending = false;
344	return VINF_SUCCESS;
345	}
346
347	/* When external interrupts are pending, we should exit the VM when IF is set. */
348	if ( !TRPMHasTrap(pVM)
349	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
350	{
351	if (!(pCtx->eflags.u32 & X86_EFL_IF))
352	{
353	Log2(("Enable irq window exit!\n"));
354	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
355	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
356	AssertRC(rc);
357	}
358	else
359	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
360	{
361	uint8_t u8Interrupt;
362
363	rc = PDMGetInterrupt(pVM, &u8Interrupt);
364	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
365	if (VBOX_SUCCESS(rc))
366	{
367	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
368	AssertRC(rc);
369	}
370	else
371	{
372	/* can't happen... */
373	AssertFailed();
374	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
375	return VINF_EM_RAW_INTERRUPT_PENDING;
376	}
377	}
378	else
379	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
380	}
381
382	#ifdef VBOX_STRICT
383	if (TRPMHasTrap(pVM))
384	{
385	uint8_t u8Vector;
386	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
387	AssertRC(rc);
388	}
389	#endif
390
391	if ( pCtx->eflags.u32 & X86_EFL_IF
392	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
393	&& TRPMHasTrap(pVM)
394	)
395	{
396	uint8_t u8Vector;
397	int rc;
398	TRPMEVENT enmType;
399	RTGCUINTPTR intInfo, errCode;
400
401	/* If a new event is pending, then dispatch it now. */
402	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
403	AssertRC(rc);
404	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
405	Assert(enmType != TRPM_SOFTWARE_INT);
406
407	/* Clear the pending trap. */
408	rc = TRPMResetTrap(pVM);
409	AssertRC(rc);
410
411	intInfo = u8Vector;
412	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
413
414	if (enmType == TRPM_TRAP)
415	{
416	switch (u8Vector) {
417	case 8:
418	case 10:
419	case 11:
420	case 12:
421	case 13:
422	case 14:
423	case 17:
424	/* Valid error codes. */
425	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
426	break;
427	default:
428	break;
429	}
430	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
431	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
432	else
433	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
434	}
435	else
436	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
437
438	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
439	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
440	AssertRC(rc);
441	} /* if (interrupts can be dispatched) */
442
443	return VINF_SUCCESS;
444	}
445
446	/**
447	* Save the host state
448	*
449	* @returns VBox status code.
450	* @param pVM The VM to operate on.
451	*/
452	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
453	{
454	int rc = VINF_SUCCESS;
455
456	/*
457	* Host CPU Context
458	*/
459	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
460	{
461	RTIDTR idtr;
462	RTGDTR gdtr;
463	RTSEL SelTR;
464	PX86DESCHC pDesc;
465	uintptr_t trBase;
466
467	/* Control registers */
468	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
469	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
470	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
471	AssertRC(rc);
472	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
473	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
474	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
475
476	/* Selector registers. */
477	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
478	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
479	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
480	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
481	#if HC_ARCH_BITS == 32
482	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
483	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
484	#endif
485	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
486	SelTR = ASMGetTR();
487	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
488	AssertRC(rc);
489	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
490	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
491	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
492	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
493	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
494	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
495	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
496
497	/* GDTR & IDTR */
498	ASMGetGDTR(&gdtr);
499	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
500	ASMGetIDTR(&idtr);
501	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
502	AssertRC(rc);
503	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
504	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
505
506	/* Save the base address of the TR selector. */
507	if (SelTR > gdtr.cbGdt)
508	{
509	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
510	return VERR_VMX_INVALID_HOST_STATE;
511	}
512
513	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
514	#if HC_ARCH_BITS == 64
515	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16ULL) \| (pDesc->Gen.u8BaseHigh2 << 24ULL) \| ((uintptr_t)pDesc->Gen.u32BaseHigh3 << 32ULL);
516	#else
517	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16) \| (pDesc->Gen.u8BaseHigh2 << 24);
518	#endif
519	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
520	AssertRC(rc);
521	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
522
523	/* FS and GS base. */
524	#if HC_ARCH_BITS == 64
525	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
526	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
527	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
528	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
529	#endif
530	AssertRC(rc);
531
532	/* Sysenter MSRs. */
533	/** @todo expensive!! */
534	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
535	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
536	#if HC_ARCH_BITS == 32
537	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
538	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
539	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
540	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
541	#else
542	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
543	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
544	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
545	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
546	#endif
547	AssertRC(rc);
548
549	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
550	}
551	return rc;
552	}
553
554
555	/**
556	* Loads the guest state
557	*
558	* @returns VBox status code.
559	* @param pVM The VM to operate on.
560	* @param pCtx Guest context
561	*/
562	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
563	{
564	int rc = VINF_SUCCESS;
565	RTGCUINTPTR val;
566	X86EFLAGS eflags;
567
568	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
569	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
570	{
571	VMX_WRITE_SELREG(ES, es);
572	AssertRC(rc);
573
574	VMX_WRITE_SELREG(CS, cs);
575	AssertRC(rc);
576
577	VMX_WRITE_SELREG(SS, ss);
578	AssertRC(rc);
579
580	VMX_WRITE_SELREG(DS, ds);
581	AssertRC(rc);
582
583	VMX_WRITE_SELREG(FS, fs);
584	AssertRC(rc);
585
586	VMX_WRITE_SELREG(GS, gs);
587	AssertRC(rc);
588	}
589
590	/* Guest CPU context: LDTR. */
591	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
592	{
593	if (pCtx->ldtr == 0)
594	{
595	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
596	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
597	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
598	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
599	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
600	}
601	else
602	{
603	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
604	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
605	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
606	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
607	}
608	AssertRC(rc);
609	}
610	/* Guest CPU context: TR. */
611	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
612	{
613	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
614
615	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
616	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
617	{
618	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
619	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
620	}
621	else
622	{
623	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
624	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
625	}
626	val = pCtx->trHid.Attr.u;
627
628	/* The TSS selector must be busy. */
629	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
630	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
631	else
632	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
633	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
634
635	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
636	AssertRC(rc);
637	}
638	/* Guest CPU context: GDTR. */
639	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
640	{
641	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
642	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
643	AssertRC(rc);
644	}
645	/* Guest CPU context: IDTR. */
646	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
647	{
648	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
649	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
650	AssertRC(rc);
651	}
652
653	/*
654	* Sysenter MSRs
655	*/
656	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
657	{
658	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
659	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
660	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
661	AssertRC(rc);
662	}
663
664	/* Control registers */
665	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
666	{
667	val = pCtx->cr0;
668	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
669	Log2(("Guest CR0-shadow %08x\n", val));
670	if (CPUMIsGuestFPUStateActive(pVM) == false)
671	{
672	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
673	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
674	}
675	else
676	{
677	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
678	/** @todo check if we support the old style mess correctly. */
679	if (!(val & X86_CR0_NE))
680	{
681	Log(("Forcing X86_CR0_NE!!!\n"));
682
683	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
684	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
685	{
686	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| BIT(16));
687	AssertRC(rc);
688	pVM->hwaccm.s.fFPUOldStyleOverride = true;
689	}
690	}
691
692	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
693	}
694	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
695	val \|= X86_CR0_PE \| X86_CR0_PG;
696
697	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
698	Log2(("Guest CR0 %08x\n", val));
699	/* CR0 flags owned by the host; if the guests attempts to change them, then
700	* the VM will exit.
701	*/
702	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
703	\| X86_CR0_WP /** @todo do we care? (we do if we start patching the guest) */
704	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
705	\| X86_CR0_TS
706	\| X86_CR0_ET
707	\| X86_CR0_NE
708	\| X86_CR0_MP;
709	pVM->hwaccm.s.vmx.cr0_mask = val;
710
711	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
712	Log2(("Guest CR0-mask %08x\n", val));
713	AssertRC(rc);
714	}
715	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
716	{
717	/* CR4 */
718	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
719	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
720	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
721	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
722	switch(pVM->hwaccm.s.enmShadowMode)
723	{
724	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
725	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
726	case PGMMODE_32_BIT: /* 32-bit paging. */
727	break;
728
729	case PGMMODE_PAE: /* PAE paging. */
730	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
731	/** @todo use normal 32 bits paging */
732	val \|= X86_CR4_PAE;
733	break;
734
735	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
736	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
737	AssertFailed();
738	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
739
740	default: /* shut up gcc */
741	AssertFailed();
742	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
743	}
744	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
745	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
746	val \|= X86_CR4_VME;
747
748	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
749	Log2(("Guest CR4 %08x\n", val));
750	/* CR4 flags owned by the host; if the guests attempts to change them, then
751	* the VM will exit.
752	*/
753	val = X86_CR4_PAE
754	\| X86_CR4_PGE
755	\| X86_CR4_PSE
756	\| X86_CR4_VMXE;
757	pVM->hwaccm.s.vmx.cr4_mask = val;
758
759	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
760	Log2(("Guest CR4-mask %08x\n", val));
761	AssertRC(rc);
762	}
763
764	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
765	{
766	/* Save our shadow CR3 register. */
767	val = PGMGetHyperCR3(pVM);
768	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
769	AssertRC(rc);
770	}
771
772	/* Debug registers. */
773	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
774	{
775	/** @todo DR0-6 */
776	val = pCtx->dr7;
777	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
778	val \|= 0x400; /* must be one */
779	#ifdef VBOX_STRICT
780	val = 0x400;
781	#endif
782	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
783	AssertRC(rc);
784
785	/* IA32_DEBUGCTL MSR. */
786	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
787	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
788	AssertRC(rc);
789
790	/** @todo */
791	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
792	AssertRC(rc);
793	}
794
795	/* EIP, ESP and EFLAGS */
796	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
797	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
798	AssertRC(rc);
799
800	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
801	eflags = pCtx->eflags;
802	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
803	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
804
805	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
806	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
807	{
808	eflags.Bits.u1VM = 1;
809	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
810	eflags.Bits.u2IOPL = 3;
811	}
812
813	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
814	AssertRC(rc);
815
816	/** TSC offset. */
817	uint64_t u64TSCOffset;
818
819	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
820	{
821	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
822	#if HC_ARCH_BITS == 64
823	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
824	#else
825	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
826	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
827	#endif
828	AssertRC(rc);
829
830	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
831	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
832	AssertRC(rc);
833	}
834	else
835	{
836	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
837	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
838	AssertRC(rc);
839	}
840
841	/* Done. */
842	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
843
844	return rc;
845	}
846
847	/**
848	* Runs guest code in a VMX VM.
849	*
850	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
851	*
852	* @returns VBox status code.
853	* @param pVM The VM to operate on.
854	* @param pCtx Guest context
855	*/
856	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
857	{
858	int rc = VINF_SUCCESS;
859	RTCCUINTREG val, valShadow;
860	RTCCUINTREG exitReason, instrError, cbInstr;
861	RTGCUINTPTR exitQualification;
862	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
863	RTGCUINTPTR errCode, instrInfo, uInterruptState;
864	bool fGuestStateSynced = false;
865
866	Log2(("\nE"));
867
868	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
869
870	#ifdef VBOX_STRICT
871	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
872	AssertRC(rc);
873	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
874
875	/* allowed zero */
876	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
877	{
878	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
879	}
880	/* allowed one */
881	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
882	{
883	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
884	}
885
886	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
887	AssertRC(rc);
888	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
889
890	/* allowed zero */
891	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
892	{
893	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
894	}
895	/* allowed one */
896	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
897	{
898	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
899	}
900
901	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
902	AssertRC(rc);
903	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
904
905	/* allowed zero */
906	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
907	{
908	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
909	}
910	/* allowed one */
911	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
912	{
913	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
914	}
915
916	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
917	AssertRC(rc);
918	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
919
920	/* allowed zero */
921	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
922	{
923	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
924	}
925	/* allowed one */
926	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
927	{
928	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
929	}
930	#endif
931
932	#if 0
933	/*
934	* Check if debug registers are armed.
935	*/
936	uint32_t u32DR7 = ASMGetDR7();
937	if (u32DR7 & X86_DR7_ENABLED_MASK)
938	{
939	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
940	}
941	else
942	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
943	#endif
944
945	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
946	*/
947	ResumeExecution:
948
949	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
950	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
951	{
952	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
953	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
954	{
955	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
956	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
957	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
958	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
959	*/
960	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
961	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
962	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
963	AssertRC(rc);
964	}
965	}
966	else
967	{
968	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
969	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
970	AssertRC(rc);
971	}
972
973	/* Check for pending actions that force us to go back to ring 3. */
974	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
975	{
976	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
977	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
978	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
979	rc = VINF_EM_RAW_TO_R3;
980	goto end;
981	}
982	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
983	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
984	{
985	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
986	rc = VINF_EM_PENDING_REQUEST;
987	goto end;
988	}
989
990	/* When external interrupts are pending, we should exit the VM when IF is set. */
991	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
992	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
993	if (VBOX_FAILURE(rc))
994	{
995	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
996	goto end;
997	}
998
999	/** @todo check timers?? */
1000
1001	/* Save the host state first. */
1002	rc = VMXR0SaveHostState(pVM);
1003	if (rc != VINF_SUCCESS)
1004	{
1005	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1006	goto end;
1007	}
1008	/* Load the guest state */
1009	rc = VMXR0LoadGuestState(pVM, pCtx);
1010	if (rc != VINF_SUCCESS)
1011	{
1012	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1013	goto end;
1014	}
1015	fGuestStateSynced = true;
1016
1017	/* Non-register state Guest Context */
1018	/** @todo change me according to cpu state */
1019	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1020	AssertRC(rc);
1021
1022	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1023
1024	/* Manual save and restore:
1025	* - General purpose registers except RIP, RSP
1026	*
1027	* Trashed:
1028	* - CR2 (we don't care)
1029	* - LDTR (reset to 0)
1030	* - DRx (presumably not changed at all)
1031	* - DR7 (reset to 0x400)
1032	* - EFLAGS (reset to BIT(1); not relevant)
1033	*
1034	*/
1035
1036	/* All done! Let's start VM execution. */
1037	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1038	Assert(!(ASMGetFlags() & X86_EFL_IF));
1039	if (pVM->hwaccm.s.vmx.fResumeVM == false)
1040	rc = VMXStartVM(pCtx);
1041	else
1042	rc = VMXResumeVM(pCtx);
1043	Assert(!(ASMGetFlags() & X86_EFL_IF));
1044
1045	/* In case we execute a goto ResumeExecution later on. */
1046	pVM->hwaccm.s.vmx.fResumeVM = true;
1047
1048	/**
1049	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1050	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1051	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1052	*/
1053
1054	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1055	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1056
1057	switch (rc)
1058	{
1059	case VINF_SUCCESS:
1060	break;
1061
1062	case VERR_VMX_INVALID_VMXON_PTR:
1063	AssertFailed();
1064	goto end;
1065
1066	case VERR_VMX_UNABLE_TO_START_VM:
1067	case VERR_VMX_UNABLE_TO_RESUME_VM:
1068	{
1069	#ifdef VBOX_STRICT
1070	int rc1;
1071
1072	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1073	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1074	AssertRC(rc1);
1075	if (rc1 == VINF_SUCCESS)
1076	{
1077	RTGDTR gdtr;
1078	PX86DESCHC pDesc;
1079
1080	ASMGetGDTR(&gdtr);
1081
1082	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1083	Log(("Current stack %08x\n", &rc1));
1084
1085
1086	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1087	Log(("Old eip %VGv new %VGv\n", pCtx->eip, (RTGCPTR)val));
1088	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1089	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1090	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1091	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1092	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1093	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1094	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1095	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1096
1097	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1098	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1099
1100	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1101	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1102
1103	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1104	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1105
1106	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1107	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1108	if (val < gdtr.cbGdt)
1109	{
1110	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1111	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1112	}
1113
1114	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1115	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1116	if (val < gdtr.cbGdt)
1117	{
1118	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1119	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1120	}
1121
1122	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1123	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1124	if (val < gdtr.cbGdt)
1125	{
1126	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1127	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1128	}
1129
1130	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1131	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1132	if (val < gdtr.cbGdt)
1133	{
1134	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1135	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1136	}
1137
1138	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1139	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1140	if (val < gdtr.cbGdt)
1141	{
1142	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1143	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1144	}
1145
1146	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1147	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1148	if (val < gdtr.cbGdt)
1149	{
1150	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1151	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1152	}
1153
1154	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1155	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1156	if (val < gdtr.cbGdt)
1157	{
1158	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1159	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1160	}
1161
1162	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1163	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1164
1165	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1166	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1167	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1168	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1169
1170	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1171	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1172
1173	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1174	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1175
1176	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1177	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1178
1179	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1180	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1181	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1182	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1183
1184	#if HC_ARCH_BITS == 64
1185	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1186	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1187	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1188	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1189	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1190	#endif
1191	}
1192	#endif /* VBOX_STRICT */
1193	goto end;
1194	}
1195
1196	default:
1197	/* impossible */
1198	AssertFailed();
1199	goto end;
1200	}
1201	/* Success. Query the guest state and figure out what has happened. */
1202
1203	/* Investigate why there was a VM-exit. */
1204	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1205	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1206
1207	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1208	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1209	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1210	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1211	intInfo = val;
1212	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1213	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1214	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1215	instrInfo = val;
1216	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1217	exitQualification = val;
1218	AssertRC(rc);
1219
1220	/* Take care of instruction fusing (sti, mov ss) */
1221	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1222	uInterruptState = val;
1223	if (uInterruptState != 0)
1224	{
1225	Assert(uInterruptState <= 2); /* only sti & mov ss */
1226	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1227	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1228	}
1229	else
1230	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1231
1232	/* Let's first sync back eip, esp, and eflags. */
1233	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1234	AssertRC(rc);
1235	pCtx->eip = val;
1236	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1237	AssertRC(rc);
1238	pCtx->esp = val;
1239	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1240	AssertRC(rc);
1241	pCtx->eflags.u32 = val;
1242
1243	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1244	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1245	{
1246	/* Hide our emulation flags */
1247	pCtx->eflags.Bits.u1VM = 0;
1248	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1249	pCtx->eflags.Bits.u1VIF = 0;
1250	pCtx->eflags.Bits.u2IOPL = 0;
1251	}
1252
1253	/* Control registers. */
1254	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1255	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1256	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1257	CPUMSetGuestCR0(pVM, val);
1258
1259	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1260	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1261	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1262	CPUMSetGuestCR4(pVM, val);
1263
1264	CPUMSetGuestCR2(pVM, ASMGetCR2());
1265
1266	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1267	CPUMSetGuestDR7(pVM, val);
1268
1269	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1270	VMX_READ_SELREG(ES, es);
1271	VMX_READ_SELREG(SS, ss);
1272	VMX_READ_SELREG(CS, cs);
1273	VMX_READ_SELREG(DS, ds);
1274	VMX_READ_SELREG(FS, fs);
1275	VMX_READ_SELREG(GS, gs);
1276
1277	/** @note NOW IT'S SAFE FOR LOGGING! */
1278	Log2(("Raw exit reason %08x\n", exitReason));
1279
1280	/* Check if an injected event was interrupted prematurely. */
1281	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1282	AssertRC(rc);
1283	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1284	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1285	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1286	{
1287	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1288	pVM->hwaccm.s.Event.fPending = true;
1289	/* Error code present? */
1290	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1291	{
1292	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1293	AssertRC(rc);
1294	pVM->hwaccm.s.Event.errCode = val;
1295	}
1296	else
1297	pVM->hwaccm.s.Event.errCode = 0;
1298	}
1299
1300	#ifdef VBOX_STRICT
1301	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1302	HWACCMDumpRegs(pCtx);
1303	#endif
1304
1305	Log2(("E%d", exitReason));
1306	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1307	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1308	Log2(("Interruption error code %d\n", errCode));
1309	Log2(("IntInfo = %08x\n", intInfo));
1310	Log2(("New EIP=%VGv\n", pCtx->eip));
1311
1312	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1313	switch (exitReason)
1314	{
1315	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1316	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1317	{
1318	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1319
1320	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1321	{
1322	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1323	/* External interrupt; leave to allow it to be dispatched again. */
1324	rc = VINF_EM_RAW_INTERRUPT;
1325	break;
1326	}
1327	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1328	{
1329	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1330	/* External interrupt; leave to allow it to be dispatched again. */
1331	rc = VINF_EM_RAW_INTERRUPT;
1332	break;
1333
1334	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1335	AssertFailed(); /* can't come here; fails the first check. */
1336	break;
1337
1338	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1339	Assert(vector == 3 \|\| vector == 4);
1340	/* no break */
1341	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1342	Log2(("Hardware/software interrupt %d\n", vector));
1343	switch (vector)
1344	{
1345	case X86_XCPT_NM:
1346	{
1347	uint32_t oldCR0;
1348
1349	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1350
1351	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1352	oldCR0 = ASMGetCR0();
1353	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1354	rc = CPUMHandleLazyFPU(pVM);
1355	if (rc == VINF_SUCCESS)
1356	{
1357	Assert(CPUMIsGuestFPUStateActive(pVM));
1358
1359	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1360	ASMSetCR0(oldCR0);
1361
1362	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1363
1364	/* Continue execution. */
1365	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1366	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1367
1368	goto ResumeExecution;
1369	}
1370
1371	Log(("Forward #NM fault to the guest\n"));
1372	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1373	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1374	AssertRC(rc);
1375	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1376	goto ResumeExecution;
1377	}
1378
1379	case X86_XCPT_PF: /* Page fault */
1380	{
1381	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1382	/* Exit qualification contains the linear address of the page fault. */
1383	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1384	TRPMSetErrorCode(pVM, errCode);
1385	TRPMSetFaultAddress(pVM, exitQualification);
1386
1387	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1388	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1389	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1390	if (rc == VINF_SUCCESS)
1391	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1392	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1393	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1394
1395	TRPMResetTrap(pVM);
1396
1397	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1398	goto ResumeExecution;
1399	}
1400	else
1401	if (rc == VINF_EM_RAW_GUEST_TRAP)
1402	{ /* A genuine pagefault.
1403	* Forward the trap to the guest by injecting the exception and resuming execution.
1404	*/
1405	Log2(("Forward page fault to the guest\n"));
1406	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1407	/* The error code might have been changed. */
1408	errCode = TRPMGetErrorCode(pVM);
1409
1410	TRPMResetTrap(pVM);
1411
1412	/* Now we must update CR2. */
1413	pCtx->cr2 = exitQualification;
1414	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1415	AssertRC(rc);
1416
1417	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1418	goto ResumeExecution;
1419	}
1420	#ifdef VBOX_STRICT
1421	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1422	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1423	#endif
1424	/* Need to go back to the recompiler to emulate the instruction. */
1425	TRPMResetTrap(pVM);
1426	break;
1427	}
1428
1429	case X86_XCPT_MF: /* Floating point exception. */
1430	{
1431	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1432	if (!(pCtx->cr0 & X86_CR0_NE))
1433	{
1434	/* old style FPU error reporting needs some extra work. */
1435	/** @todo don't fall back to the recompiler, but do it manually. */
1436	rc = VINF_EM_RAW_EMULATE_INSTR;
1437	break;
1438	}
1439	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1440	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1441	AssertRC(rc);
1442
1443	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1444	goto ResumeExecution;
1445	}
1446
1447	#ifdef VBOX_STRICT
1448	case X86_XCPT_GP: /* General protection failure exception.*/
1449	case X86_XCPT_UD: /* Unknown opcode exception. */
1450	case X86_XCPT_DE: /* Debug exception. */
1451	case X86_XCPT_SS: /* Stack segment exception. */
1452	case X86_XCPT_NP: /* Segment not present exception. */
1453	{
1454	switch(vector)
1455	{
1456	case X86_XCPT_DE:
1457	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1458	break;
1459	case X86_XCPT_UD:
1460	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1461	break;
1462	case X86_XCPT_SS:
1463	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1464	break;
1465	case X86_XCPT_NP:
1466	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1467	break;
1468	case X86_XCPT_GP:
1469	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1470	break;
1471	}
1472
1473	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1474	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1475	AssertRC(rc);
1476
1477	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1478	goto ResumeExecution;
1479	}
1480	#endif
1481	default:
1482	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1483	rc = VERR_EM_INTERNAL_ERROR;
1484	break;
1485	} /* switch (vector) */
1486
1487	break;
1488
1489	default:
1490	rc = VERR_EM_INTERNAL_ERROR;
1491	AssertFailed();
1492	break;
1493	}
1494
1495	break;
1496	}
1497
1498	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1499	/* Clear VM-exit on IF=1 change. */
1500	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1501	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1502	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1503	AssertRC(rc);
1504	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1505	goto ResumeExecution; /* we check for pending guest interrupts there */
1506
1507	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1508	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1509	/* Skip instruction and continue directly. */
1510	pCtx->eip += cbInstr;
1511	/* Continue execution.*/
1512	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1513	goto ResumeExecution;
1514
1515	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1516	{
1517	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1518	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1519	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1520	if (rc == VINF_SUCCESS)
1521	{
1522	/* Update EIP and continue execution. */
1523	Assert(cbInstr == 2);
1524	pCtx->eip += cbInstr;
1525	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1526	goto ResumeExecution;
1527	}
1528	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1529	rc = VINF_EM_RAW_EMULATE_INSTR;
1530	break;
1531	}
1532
1533	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1534	{
1535	Log2(("VMX: Rdtsc\n"));
1536	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1537	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1538	if (rc == VINF_SUCCESS)
1539	{
1540	/* Update EIP and continue execution. */
1541	Assert(cbInstr == 2);
1542	pCtx->eip += cbInstr;
1543	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1544	goto ResumeExecution;
1545	}
1546	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1547	rc = VINF_EM_RAW_EMULATE_INSTR;
1548	break;
1549	}
1550
1551	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1552	{
1553	Log2(("VMX: invlpg\n"));
1554	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1555	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1556	if (rc == VINF_SUCCESS)
1557	{
1558	/* Update EIP and continue execution. */
1559	pCtx->eip += cbInstr;
1560	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1561	goto ResumeExecution;
1562	}
1563	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1564	break;
1565	}
1566
1567	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1568	{
1569	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1570	{
1571	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1572	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1573	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1574	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1575	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1576	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1577
1578	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1579	{
1580	case 0:
1581	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1582	break;
1583	case 2:
1584	break;
1585	case 3:
1586	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1587	break;
1588	case 4:
1589	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1590	break;
1591	default:
1592	AssertFailed();
1593	}
1594	/* Check if a sync operation is pending. */
1595	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1596	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1597	{
1598	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1599	AssertRC(rc);
1600	}
1601	break;
1602
1603	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1604	Log2(("VMX: mov x, crx\n"));
1605	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1606	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1607	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1608	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1609	break;
1610
1611	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1612	Log2(("VMX: clts\n"));
1613	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1614	rc = EMInterpretCLTS(pVM);
1615	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1616	break;
1617
1618	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1619	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1620	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1621	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1622	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1623	break;
1624	}
1625
1626	/* Update EIP if no error occurred. */
1627	if (VBOX_SUCCESS(rc))
1628	pCtx->eip += cbInstr;
1629
1630	if (rc == VINF_SUCCESS)
1631	{
1632	/* Only resume if successful. */
1633	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1634	goto ResumeExecution;
1635	}
1636	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1637	break;
1638	}
1639
1640	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1641	{
1642	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1643	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1644	{
1645	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1646	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1647	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1648	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1649	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1650	Log2(("DR7=%08x\n", pCtx->dr7));
1651	}
1652	else
1653	{
1654	Log2(("VMX: mov x, drx\n"));
1655	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1656	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1657	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1658	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1659	}
1660	/* Update EIP if no error occurred. */
1661	if (VBOX_SUCCESS(rc))
1662	pCtx->eip += cbInstr;
1663
1664	if (rc == VINF_SUCCESS)
1665	{
1666	/* Only resume if successful. */
1667	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1668	goto ResumeExecution;
1669	}
1670	Assert(rc == VERR_EM_INTERPRETER);
1671	break;
1672	}
1673
1674	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1675	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1676	{
1677	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1678	uint32_t uPort;
1679	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1680
1681	/** @todo necessary to make the distinction? */
1682	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1683	{
1684	uPort = pCtx->edx & 0xffff;
1685	}
1686	else
1687	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1688
1689	/* paranoia */
1690	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1691	{
1692	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1693	break;
1694	}
1695
1696	uint32_t cbSize = aIOSize[uIOWidth];
1697
1698	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1699	{
1700	/* ins/outs */
1701	uint32_t prefix = 0;
1702	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1703	prefix \|= PREFIX_REP;
1704
1705	if (fIOWrite)
1706	{
1707	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1708	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1709	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1710	}
1711	else
1712	{
1713	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1714	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1715	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1716	}
1717	}
1718	else
1719	{
1720	/* normal in/out */
1721	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1722
1723	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1724
1725	if (fIOWrite)
1726	{
1727	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1728	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1729	}
1730	else
1731	{
1732	uint32_t u32Val = 0;
1733
1734	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1735	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1736	if (IOM_SUCCESS(rc))
1737	{
1738	/* Write back to the EAX register. */
1739	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1740	}
1741	}
1742	}
1743	/*
1744	* Handled the I/O return codes.
1745	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1746	*/
1747	if (IOM_SUCCESS(rc))
1748	{
1749	/* Update EIP and continue execution. */
1750	pCtx->eip += cbInstr;
1751	if (RT_LIKELY(rc == VINF_SUCCESS))
1752	{
1753	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1754	goto ResumeExecution;
1755	}
1756	break;
1757	}
1758
1759	#ifdef VBOX_STRICT
1760	if (rc == VINF_IOM_HC_IOPORT_READ)
1761	Assert(!fIOWrite);
1762	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1763	Assert(fIOWrite);
1764	else
1765	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1766	#endif
1767	break;
1768	}
1769
1770	default:
1771	/* The rest is handled after syncing the entire CPU state. */
1772	break;
1773	}
1774
1775	/* Note: the guest state isn't entirely synced back at this stage. */
1776
1777	/* Investigate why there was a VM-exit. (part 2) */
1778	switch (exitReason)
1779	{
1780	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1781	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1782	/* Already handled above. */
1783	break;
1784
1785	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1786	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1787	break;
1788
1789	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1790	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1791	rc = VINF_EM_RAW_INTERRUPT;
1792	AssertFailed(); /* Can't happen. Yet. */
1793	break;
1794
1795	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1796	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1797	rc = VINF_EM_RAW_INTERRUPT;
1798	AssertFailed(); /* Can't happen afaik. */
1799	break;
1800
1801	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1802	rc = VINF_EM_RAW_RING_SWITCH_INT;
1803	break;
1804
1805	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1806	/** Check if external interrupts are pending; if so, don't switch back. */
1807	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1808	{
1809	pCtx->eip++; /* skip hlt */
1810	goto ResumeExecution;
1811	}
1812
1813	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1814	break;
1815
1816	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1817	AssertFailed(); /* can't happen. */
1818	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1819	break;
1820
1821	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1822	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1823	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1824	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1825	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1826	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1827	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1828	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1829	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1830	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1831	/** @todo inject #UD immediately */
1832	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1833	break;
1834
1835	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1836	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1837	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1838	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1839	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1840	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1841	/* already handled above */
1842	AssertMsg( rc == VINF_PGM_CHANGE_MODE
1843	\|\| rc == VINF_EM_RAW_INTERRUPT
1844	\|\| rc == VERR_EM_INTERPRETER
1845	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
1846	\|\| rc == VINF_PGM_SYNC_CR3
1847	\|\| rc == VINF_IOM_HC_IOPORT_READ
1848	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
1849	\|\| rc == VINF_EM_RAW_GUEST_TRAP
1850	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
1851	\|\| rc == VINF_EM_RESCHEDULE_REM,
1852	("rc = %d\n", rc));
1853	break;
1854
1855	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1856	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1857	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1858	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1859	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1860	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1861	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1862	break;
1863
1864	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1865	Assert(rc == VINF_EM_RAW_INTERRUPT);
1866	break;
1867
1868	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1869	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1870	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1871	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1872	default:
1873	rc = VERR_EM_INTERNAL_ERROR;
1874	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1875	break;
1876
1877	}
1878	end:
1879	if (fGuestStateSynced)
1880	{
1881	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1882	VMX_READ_SELREG(LDTR, ldtr);
1883	VMX_READ_SELREG(TR, tr);
1884
1885	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1886	pCtx->gdtr.cbGdt = val;
1887	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1888	pCtx->gdtr.pGdt = val;
1889
1890	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1891	pCtx->idtr.cbIdt = val;
1892	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1893	pCtx->idtr.pIdt = val;
1894
1895	/*
1896	* System MSRs
1897	*/
1898	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1899	pCtx->SysEnter.cs = val;
1900	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1901	pCtx->SysEnter.eip = val;
1902	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1903	pCtx->SysEnter.esp = val;
1904	}
1905
1906	/* Signal changes for the recompiler. */
1907	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1908
1909	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
1910	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
1911	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1912	{
1913	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1914	/* On the next entry we'll only sync the host context. */
1915	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1916	}
1917	else
1918	{
1919	/* On the next entry we'll sync everything. */
1920	/** @todo we can do better than this */
1921	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1922	}
1923
1924	/* translate into a less severe return code */
1925	if (rc == VERR_EM_INTERPRETER)
1926	rc = VINF_EM_RAW_EMULATE_INSTR;
1927
1928	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1929	Log2(("X"));
1930	return rc;
1931	}
1932
1933
1934	/**
1935	* Enable VMX
1936	*
1937	* @returns VBox status code.
1938	* @param pVM The VM to operate on.
1939	*/
1940	HWACCMR0DECL(int) VMXR0Enable(PVM pVM)
1941	{
1942	Assert(pVM->hwaccm.s.vmx.fSupported);
1943
1944	/* Make sure the VMX instructions don't cause #UD faults. */
1945	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
1946
1947	/* Enter VMX Root Mode */
1948	int rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
1949	if (VBOX_FAILURE(rc))
1950	return rc;
1951
1952	/* Activate the VM Control Structure. */
1953	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1954	if (VBOX_FAILURE(rc))
1955	{
1956	/* Leave VMX Root Mode. */
1957	VMXDisable();
1958	return rc;
1959	}
1960	Assert(!(ASMGetFlags() & X86_EFL_IF));
1961	pVM->hwaccm.s.vmx.fResumeVM = false;
1962	return VINF_SUCCESS;
1963	}
1964
1965
1966	/**
1967	* Disable VMX
1968	*
1969	* @returns VBox status code.
1970	* @param pVM The VM to operate on.
1971	*/
1972	HWACCMR0DECL(int) VMXR0Disable(PVM pVM)
1973	{
1974	Assert(pVM->hwaccm.s.vmx.fSupported);
1975
1976	Assert(!(ASMGetFlags() & X86_EFL_IF));
1977
1978	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
1979	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1980	AssertRC(rc);
1981
1982	/* Leave VMX Root Mode. */
1983	VMXDisable();
1984
1985	return VINF_SUCCESS;
1986	}
1987

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 4920

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