HWVMXR0.cpp@ 5605

Last change on this file since 5605 was 5605, checked in by vboxsync, 17 years ago
BIT => RT_BIT, BIT64 => RT_BIT_64. BIT() is defined in Linux 2.6.24
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 74.6 KB

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1	/* $Id: HWVMXR0.cpp 5605 2007-11-01 16:09:26Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/hwaccm.h>
24	#include "HWACCMInternal.h"
25	#include <VBox/vm.h>
26	#include <VBox/x86.h>
27	#include <VBox/pgm.h>
28	#include <VBox/pdm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <VBox/selm.h>
32	#include <VBox/iom.h>
33	#include <iprt/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36	#include "HWVMXR0.h"
37
38
39	/* IO operation lookup arrays. */
40	static uint32_t aIOSize[4] = {1, 2, 0, 4};
41	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
42
43
44	static void VMXR0CheckError(PVM pVM, int rc)
45	{
46	if (rc == VERR_VMX_GENERIC)
47	{
48	RTCCUINTREG instrError;
49
50	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
51	Log(("VMXR0CheckError -> generic error %x\n", instrError));
52
53	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
54	}
55	else
56	{
57	Log(("VMXR0CheckError failed with %Vrc\n", rc));
58	}
59	pVM->hwaccm.s.lLastError = rc;
60	}
61
62	/**
63	* Sets up and activates VMX
64	*
65	* @returns VBox status code.
66	* @param pVM The VM to operate on.
67	*/
68	HWACCMR0DECL(int) VMXR0Setup(PVM pVM)
69	{
70	int rc = VINF_SUCCESS;
71	uint32_t val;
72
73	if (pVM == NULL)
74	return VERR_INVALID_PARAMETER;
75
76	/* Setup Intel VMX. */
77	Assert(pVM->hwaccm.s.vmx.fSupported);
78
79	/* Set revision dword at the beginning of both structures. */
80	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
81	(uint32_t )pVM->hwaccm.s.vmx.pVMXON = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
82
83	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
84	* (which can have very bad consequences!!!)
85	*/
86
87	/* Make sure the VMX instructions don't cause #UD faults. */
88	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
89
90	/* Enter VMX Root Mode */
91	Log(("pVMXONPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMXONPhys));
92	rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
93	if (VBOX_FAILURE(rc))
94	{
95	VMXR0CheckError(pVM, rc);
96	return VERR_VMX_VMXON_FAILED;
97	}
98
99	/* Clear VM Control Structure. */
100	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
101	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
102	if (VBOX_FAILURE(rc))
103	goto vmx_end;
104
105	/* Activate the VM Control Structure. */
106	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
107	if (VBOX_FAILURE(rc))
108	goto vmx_end;
109
110	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
111	* Set required bits to one and zero according to the MSR capabilities.
112	*/
113	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
114	/* External and non-maskable interrupts cause VM-exits. */
115	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
116	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
117
118	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
119	AssertRC(rc);
120
121	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
122	* Set required bits to one and zero according to the MSR capabilities.
123	*/
124	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
125	/* Program which event cause VM-exits and which features we want to use. */
126	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
127	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
128	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
129	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
130	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
131	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
132
133	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
134
135	/*
136	if AMD64 guest mode
137	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
138	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
139	*/
140	#if HC_ARCH_BITS == 64
141	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
142	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
143	#endif
144	/* Mask away the bits that the CPU doesn't support */
145	/** @todo make sure they don't conflict with the above requirements. */
146	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
147	pVM->hwaccm.s.vmx.proc_ctls = val;
148
149	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
150	AssertRC(rc);
151
152	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
153	* Set required bits to one and zero according to the MSR capabilities.
154	*/
155	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
156	AssertRC(rc);
157
158	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
159	* Set required bits to one and zero according to the MSR capabilities.
160	*/
161	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
162	if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
163	{
164	/** @todo 32 bits guest mode only for now. */
165	/* val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
166	}
167	/* Mask away the bits that the CPU doesn't support */
168	/** @todo make sure they don't conflict with the above requirements. */
169	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
170	/* else Must be zero when AMD64 is not available. */
171	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
172	AssertRC(rc);
173
174	/* VMX_VMCS_CTRL_EXIT_CONTROLS
175	* Set required bits to one and zero according to the MSR capabilities.
176	*/
177	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
178	#if HC_ARCH_BITS == 64
179	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
180	#else
181	/* else Must be zero when AMD64 is not available. */
182	#endif
183	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
184	/* Don't acknowledge external interrupts on VM-exit. */
185	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
186	AssertRC(rc);
187
188	/* Forward all exception except #NM & #PF to the guest.
189	* We always need to check pagefaults since our shadow page table can be out of sync.
190	* And we always lazily sync the FPU & XMM state.
191	*/
192
193	/*
194	* @todo Possible optimization:
195	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
196	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
197	* registers ourselves of course.
198	*
199	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
200	*/
201	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
202	AssertRC(rc);
203
204	/* Don't filter page faults; all of them should cause a switch. */
205	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
206	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
207	AssertRC(rc);
208
209	/* Init TSC offset to zero. */
210	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
211	#if HC_ARCH_BITS == 32
212	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
213	#endif
214	AssertRC(rc);
215
216	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
217	#if HC_ARCH_BITS == 32
218	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
219	#endif
220	AssertRC(rc);
221
222	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
223	#if HC_ARCH_BITS == 32
224	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
225	#endif
226	AssertRC(rc);
227
228	/* Clear MSR controls. */
229	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
230	{
231	/* Optional */
232	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
233	#if HC_ARCH_BITS == 32
234	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
235	#endif
236	AssertRC(rc);
237	}
238	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
239	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
240	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
241	#if HC_ARCH_BITS == 32
242	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
243	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
244	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
245	#endif
246	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
247	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
248	AssertRC(rc);
249
250	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
251	{
252	/* Optional */
253	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
254	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
255	#if HC_ARCH_BITS == 32
256	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
257	#endif
258	AssertRC(rc);
259	}
260
261	/* Set link pointer to -1. Not currently used. */
262	#if HC_ARCH_BITS == 32
263	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
264	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
265	#else
266	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
267	#endif
268	AssertRC(rc);
269
270	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
271	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
272	AssertRC(rc);
273
274	vmx_end:
275	VMXR0CheckError(pVM, rc);
276	/* Leave VMX Root Mode. */
277	VMXDisable();
278	return rc;
279	}
280
281
282	/**
283	* Injects an event (trap or external interrupt)
284	*
285	* @returns VBox status code.
286	* @param pVM The VM to operate on.
287	* @param pCtx CPU Context
288	* @param intInfo VMX interrupt info
289	* @param cbInstr Opcode length of faulting instruction
290	* @param errCode Error code (optional)
291	*/
292	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
293	{
294	int rc;
295
296	#ifdef VBOX_STRICT
297	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
298	if (iGate == 0xE)
299	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
300	else
301	if (iGate < 0x20)
302	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
303	else
304	{
305	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
306	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
307	Assert(pCtx->eflags.u32 & X86_EFL_IF);
308	}
309	#endif
310
311	/* Set event injection state. */
312	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
313	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
314	);
315
316	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
317	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
318
319	AssertRC(rc);
320	return rc;
321	}
322
323
324	/**
325	* Checks for pending guest interrupts and injects them
326	*
327	* @returns VBox status code.
328	* @param pVM The VM to operate on.
329	* @param pCtx CPU Context
330	*/
331	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
332	{
333	int rc;
334
335	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
336	if (pVM->hwaccm.s.Event.fPending)
337	{
338	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
339	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
340	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
341	AssertRC(rc);
342
343	pVM->hwaccm.s.Event.fPending = false;
344	return VINF_SUCCESS;
345	}
346
347	/* When external interrupts are pending, we should exit the VM when IF is set. */
348	if ( !TRPMHasTrap(pVM)
349	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
350	{
351	if (!(pCtx->eflags.u32 & X86_EFL_IF))
352	{
353	Log2(("Enable irq window exit!\n"));
354	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
355	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
356	AssertRC(rc);
357	}
358	else
359	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
360	{
361	uint8_t u8Interrupt;
362
363	rc = PDMGetInterrupt(pVM, &u8Interrupt);
364	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
365	if (VBOX_SUCCESS(rc))
366	{
367	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
368	AssertRC(rc);
369	}
370	else
371	{
372	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
373	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
374	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
375	/* Just continue */
376	}
377	}
378	else
379	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
380	}
381
382	#ifdef VBOX_STRICT
383	if (TRPMHasTrap(pVM))
384	{
385	uint8_t u8Vector;
386	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
387	AssertRC(rc);
388	}
389	#endif
390
391	if ( pCtx->eflags.u32 & X86_EFL_IF
392	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
393	&& TRPMHasTrap(pVM)
394	)
395	{
396	uint8_t u8Vector;
397	int rc;
398	TRPMEVENT enmType;
399	RTGCUINTPTR intInfo, errCode;
400
401	/* If a new event is pending, then dispatch it now. */
402	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
403	AssertRC(rc);
404	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
405	Assert(enmType != TRPM_SOFTWARE_INT);
406
407	/* Clear the pending trap. */
408	rc = TRPMResetTrap(pVM);
409	AssertRC(rc);
410
411	intInfo = u8Vector;
412	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
413
414	if (enmType == TRPM_TRAP)
415	{
416	switch (u8Vector) {
417	case 8:
418	case 10:
419	case 11:
420	case 12:
421	case 13:
422	case 14:
423	case 17:
424	/* Valid error codes. */
425	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
426	break;
427	default:
428	break;
429	}
430	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
431	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
432	else
433	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
434	}
435	else
436	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
437
438	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
439	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
440	AssertRC(rc);
441	} /* if (interrupts can be dispatched) */
442
443	return VINF_SUCCESS;
444	}
445
446	/**
447	* Save the host state
448	*
449	* @returns VBox status code.
450	* @param pVM The VM to operate on.
451	*/
452	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
453	{
454	int rc = VINF_SUCCESS;
455
456	/*
457	* Host CPU Context
458	*/
459	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
460	{
461	RTIDTR idtr;
462	RTGDTR gdtr;
463	RTSEL SelTR;
464	PX86DESCHC pDesc;
465	uintptr_t trBase;
466
467	/* Control registers */
468	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
469	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
470	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
471	AssertRC(rc);
472	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
473	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
474	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
475
476	/* Selector registers. */
477	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
478	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
479	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
480	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
481	#if HC_ARCH_BITS == 32
482	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
483	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
484	#endif
485	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
486	SelTR = ASMGetTR();
487	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
488	AssertRC(rc);
489	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
490	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
491	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
492	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
493	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
494	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
495	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
496
497	/* GDTR & IDTR */
498	ASMGetGDTR(&gdtr);
499	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
500	ASMGetIDTR(&idtr);
501	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
502	AssertRC(rc);
503	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
504	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
505
506	/* Save the base address of the TR selector. */
507	if (SelTR > gdtr.cbGdt)
508	{
509	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
510	return VERR_VMX_INVALID_HOST_STATE;
511	}
512
513	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
514	#if HC_ARCH_BITS == 64
515	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16ULL) \| (pDesc->Gen.u8BaseHigh2 << 24ULL) \| ((uintptr_t)pDesc->Gen.u32BaseHigh3 << 32ULL);
516	#else
517	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16) \| (pDesc->Gen.u8BaseHigh2 << 24);
518	#endif
519	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
520	AssertRC(rc);
521	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
522
523	/* FS and GS base. */
524	#if HC_ARCH_BITS == 64
525	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
526	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
527	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
528	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
529	#endif
530	AssertRC(rc);
531
532	/* Sysenter MSRs. */
533	/** @todo expensive!! */
534	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
535	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
536	#if HC_ARCH_BITS == 32
537	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
538	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
539	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
540	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
541	#else
542	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
543	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
544	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
545	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
546	#endif
547	AssertRC(rc);
548
549	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
550	}
551	return rc;
552	}
553
554
555	/**
556	* Loads the guest state
557	*
558	* @returns VBox status code.
559	* @param pVM The VM to operate on.
560	* @param pCtx Guest context
561	*/
562	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
563	{
564	int rc = VINF_SUCCESS;
565	RTGCUINTPTR val;
566	X86EFLAGS eflags;
567
568	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
569	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
570	{
571	VMX_WRITE_SELREG(ES, es);
572	AssertRC(rc);
573
574	VMX_WRITE_SELREG(CS, cs);
575	AssertRC(rc);
576
577	VMX_WRITE_SELREG(SS, ss);
578	AssertRC(rc);
579
580	VMX_WRITE_SELREG(DS, ds);
581	AssertRC(rc);
582
583	VMX_WRITE_SELREG(FS, fs);
584	AssertRC(rc);
585
586	VMX_WRITE_SELREG(GS, gs);
587	AssertRC(rc);
588	}
589
590	/* Guest CPU context: LDTR. */
591	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
592	{
593	if (pCtx->ldtr == 0)
594	{
595	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
596	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
597	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
598	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
599	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
600	}
601	else
602	{
603	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
604	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
605	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
606	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
607	}
608	AssertRC(rc);
609	}
610	/* Guest CPU context: TR. */
611	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
612	{
613	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
614
615	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
616	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
617	{
618	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
619	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
620	}
621	else
622	{
623	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
624	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
625	}
626	val = pCtx->trHid.Attr.u;
627
628	/* The TSS selector must be busy. */
629	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
630	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
631	else
632	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
633	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
634
635	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
636	AssertRC(rc);
637	}
638	/* Guest CPU context: GDTR. */
639	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
640	{
641	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
642	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
643	AssertRC(rc);
644	}
645	/* Guest CPU context: IDTR. */
646	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
647	{
648	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
649	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
650	AssertRC(rc);
651	}
652
653	/*
654	* Sysenter MSRs
655	*/
656	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
657	{
658	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
659	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
660	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
661	AssertRC(rc);
662	}
663
664	/* Control registers */
665	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
666	{
667	val = pCtx->cr0;
668	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
669	Log2(("Guest CR0-shadow %08x\n", val));
670	if (CPUMIsGuestFPUStateActive(pVM) == false)
671	{
672	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
673	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
674	}
675	else
676	{
677	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
678	/** @todo check if we support the old style mess correctly. */
679	if (!(val & X86_CR0_NE))
680	{
681	Log(("Forcing X86_CR0_NE!!!\n"));
682
683	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
684	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
685	{
686	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| RT_BIT(16));
687	AssertRC(rc);
688	pVM->hwaccm.s.fFPUOldStyleOverride = true;
689	}
690	}
691
692	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
693	}
694	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
695	val \|= X86_CR0_PE \| X86_CR0_PG;
696
697	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
698	Log2(("Guest CR0 %08x\n", val));
699	/* CR0 flags owned by the host; if the guests attempts to change them, then
700	* the VM will exit.
701	*/
702	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
703	\| X86_CR0_WP /** @todo do we care? (we do if we start patching the guest) */
704	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
705	\| X86_CR0_TS
706	\| X86_CR0_ET
707	\| X86_CR0_NE
708	\| X86_CR0_MP;
709	pVM->hwaccm.s.vmx.cr0_mask = val;
710
711	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
712	Log2(("Guest CR0-mask %08x\n", val));
713	AssertRC(rc);
714	}
715	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
716	{
717	/* CR4 */
718	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
719	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
720	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
721	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
722	switch(pVM->hwaccm.s.enmShadowMode)
723	{
724	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
725	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
726	case PGMMODE_32_BIT: /* 32-bit paging. */
727	break;
728
729	case PGMMODE_PAE: /* PAE paging. */
730	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
731	/** @todo use normal 32 bits paging */
732	val \|= X86_CR4_PAE;
733	break;
734
735	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
736	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
737	AssertFailed();
738	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
739
740	default: /* shut up gcc */
741	AssertFailed();
742	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
743	}
744	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
745	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
746	val \|= X86_CR4_VME;
747
748	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
749	Log2(("Guest CR4 %08x\n", val));
750	/* CR4 flags owned by the host; if the guests attempts to change them, then
751	* the VM will exit.
752	*/
753	val = X86_CR4_PAE
754	\| X86_CR4_PGE
755	\| X86_CR4_PSE
756	\| X86_CR4_VMXE;
757	pVM->hwaccm.s.vmx.cr4_mask = val;
758
759	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
760	Log2(("Guest CR4-mask %08x\n", val));
761	AssertRC(rc);
762	}
763
764	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
765	{
766	/* Save our shadow CR3 register. */
767	val = PGMGetHyperCR3(pVM);
768	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
769	AssertRC(rc);
770	}
771
772	/* Debug registers. */
773	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
774	{
775	/** @todo DR0-6 */
776	val = pCtx->dr7;
777	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
778	val \|= 0x400; /* must be one */
779	#ifdef VBOX_STRICT
780	val = 0x400;
781	#endif
782	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
783	AssertRC(rc);
784
785	/* IA32_DEBUGCTL MSR. */
786	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
787	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
788	AssertRC(rc);
789
790	/** @todo */
791	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
792	AssertRC(rc);
793	}
794
795	/* EIP, ESP and EFLAGS */
796	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
797	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
798	AssertRC(rc);
799
800	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
801	eflags = pCtx->eflags;
802	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
803	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
804
805	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
806	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
807	{
808	eflags.Bits.u1VM = 1;
809	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
810	eflags.Bits.u2IOPL = 3;
811	}
812
813	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
814	AssertRC(rc);
815
816	/** TSC offset. */
817	uint64_t u64TSCOffset;
818
819	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
820	{
821	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
822	#if HC_ARCH_BITS == 64
823	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
824	#else
825	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
826	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
827	#endif
828	AssertRC(rc);
829
830	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
831	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
832	AssertRC(rc);
833	}
834	else
835	{
836	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
837	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
838	AssertRC(rc);
839	}
840
841	/* Done. */
842	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
843
844	return rc;
845	}
846
847	/**
848	* Runs guest code in a VMX VM.
849	*
850	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
851	*
852	* @returns VBox status code.
853	* @param pVM The VM to operate on.
854	* @param pCtx Guest context
855	*/
856	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
857	{
858	int rc = VINF_SUCCESS;
859	RTCCUINTREG val, valShadow;
860	RTCCUINTREG exitReason, instrError, cbInstr;
861	RTGCUINTPTR exitQualification;
862	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
863	RTGCUINTPTR errCode, instrInfo, uInterruptState;
864	bool fGuestStateSynced = false;
865	unsigned cResume = 0;
866
867	Log2(("\nE"));
868
869	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
870
871	#ifdef VBOX_STRICT
872	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
873	AssertRC(rc);
874	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
875
876	/* allowed zero */
877	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
878	{
879	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
880	}
881	/* allowed one */
882	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
883	{
884	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
885	}
886
887	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
888	AssertRC(rc);
889	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
890
891	/* allowed zero */
892	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
893	{
894	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
895	}
896	/* allowed one */
897	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
898	{
899	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
900	}
901
902	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
903	AssertRC(rc);
904	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
905
906	/* allowed zero */
907	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
908	{
909	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
910	}
911	/* allowed one */
912	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
913	{
914	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
915	}
916
917	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
918	AssertRC(rc);
919	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
920
921	/* allowed zero */
922	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
923	{
924	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
925	}
926	/* allowed one */
927	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
928	{
929	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
930	}
931	#endif
932
933	#if 0
934	/*
935	* Check if debug registers are armed.
936	*/
937	uint32_t u32DR7 = ASMGetDR7();
938	if (u32DR7 & X86_DR7_ENABLED_MASK)
939	{
940	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
941	}
942	else
943	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
944	#endif
945
946	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
947	*/
948	ResumeExecution:
949	/* Safety precaution; looping for too long here can have a very bad effect on the host */
950	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
951	{
952	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
953	rc = VINF_EM_RAW_INTERRUPT;
954	goto end;
955	}
956
957	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
958	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
959	{
960	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
961	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
962	{
963	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
964	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
965	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
966	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
967	*/
968	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
969	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
970	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
971	AssertRC(rc);
972	}
973	}
974	else
975	{
976	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
977	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
978	AssertRC(rc);
979	}
980
981	/* Check for pending actions that force us to go back to ring 3. */
982	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
983	{
984	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
985	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
986	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
987	rc = VINF_EM_RAW_TO_R3;
988	goto end;
989	}
990	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
991	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
992	{
993	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
994	rc = VINF_EM_PENDING_REQUEST;
995	goto end;
996	}
997
998	/* When external interrupts are pending, we should exit the VM when IF is set. */
999	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
1000	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1001	if (VBOX_FAILURE(rc))
1002	{
1003	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1004	goto end;
1005	}
1006
1007	/** @todo check timers?? */
1008
1009	/* Save the host state first. */
1010	rc = VMXR0SaveHostState(pVM);
1011	if (rc != VINF_SUCCESS)
1012	{
1013	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1014	goto end;
1015	}
1016	/* Load the guest state */
1017	rc = VMXR0LoadGuestState(pVM, pCtx);
1018	if (rc != VINF_SUCCESS)
1019	{
1020	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1021	goto end;
1022	}
1023	fGuestStateSynced = true;
1024
1025	/* Non-register state Guest Context */
1026	/** @todo change me according to cpu state */
1027	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1028	AssertRC(rc);
1029
1030	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1031
1032	/* Manual save and restore:
1033	* - General purpose registers except RIP, RSP
1034	*
1035	* Trashed:
1036	* - CR2 (we don't care)
1037	* - LDTR (reset to 0)
1038	* - DRx (presumably not changed at all)
1039	* - DR7 (reset to 0x400)
1040	* - EFLAGS (reset to RT_BIT(1); not relevant)
1041	*
1042	*/
1043
1044	/* All done! Let's start VM execution. */
1045	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1046	if (pVM->hwaccm.s.vmx.fResumeVM == false)
1047	rc = VMXStartVM(pCtx);
1048	else
1049	rc = VMXResumeVM(pCtx);
1050
1051	/* In case we execute a goto ResumeExecution later on. */
1052	pVM->hwaccm.s.vmx.fResumeVM = true;
1053
1054	/**
1055	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1056	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1057	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1058	*/
1059
1060	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1061	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1062
1063	switch (rc)
1064	{
1065	case VINF_SUCCESS:
1066	break;
1067
1068	case VERR_VMX_INVALID_VMXON_PTR:
1069	AssertFailed();
1070	goto end;
1071
1072	case VERR_VMX_UNABLE_TO_START_VM:
1073	case VERR_VMX_UNABLE_TO_RESUME_VM:
1074	{
1075	#ifdef VBOX_STRICT
1076	int rc1;
1077
1078	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1079	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1080	AssertRC(rc1);
1081	if (rc1 == VINF_SUCCESS)
1082	{
1083	RTGDTR gdtr;
1084	PX86DESCHC pDesc;
1085
1086	ASMGetGDTR(&gdtr);
1087
1088	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1089	Log(("Current stack %08x\n", &rc1));
1090
1091
1092	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1093	Log(("Old eip %VGv new %VGv\n", pCtx->eip, (RTGCPTR)val));
1094	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1095	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1096	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1097	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1098	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1099	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1100	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1101	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1102
1103	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1104	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1105
1106	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1107	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1108
1109	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1110	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1111
1112	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1113	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1114	if (val < gdtr.cbGdt)
1115	{
1116	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1117	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1118	}
1119
1120	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1121	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1122	if (val < gdtr.cbGdt)
1123	{
1124	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1125	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1126	}
1127
1128	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1129	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1130	if (val < gdtr.cbGdt)
1131	{
1132	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1133	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1134	}
1135
1136	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1137	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1138	if (val < gdtr.cbGdt)
1139	{
1140	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1141	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1142	}
1143
1144	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1145	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1146	if (val < gdtr.cbGdt)
1147	{
1148	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1149	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1150	}
1151
1152	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1153	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1154	if (val < gdtr.cbGdt)
1155	{
1156	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1157	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1158	}
1159
1160	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1161	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1162	if (val < gdtr.cbGdt)
1163	{
1164	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1165	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1166	}
1167
1168	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1169	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1170
1171	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1172	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1173	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1174	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1175
1176	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1177	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1178
1179	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1180	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1181
1182	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1183	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1184
1185	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1186	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1187	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1188	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1189
1190	#if HC_ARCH_BITS == 64
1191	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1192	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1193	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1194	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1195	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1196	#endif
1197	}
1198	#endif /* VBOX_STRICT */
1199	goto end;
1200	}
1201
1202	default:
1203	/* impossible */
1204	AssertFailed();
1205	goto end;
1206	}
1207	/* Success. Query the guest state and figure out what has happened. */
1208
1209	/* Investigate why there was a VM-exit. */
1210	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1211	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1212
1213	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1214	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1215	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1216	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1217	intInfo = val;
1218	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1219	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1220	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1221	instrInfo = val;
1222	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1223	exitQualification = val;
1224	AssertRC(rc);
1225
1226	/* Take care of instruction fusing (sti, mov ss) */
1227	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1228	uInterruptState = val;
1229	if (uInterruptState != 0)
1230	{
1231	Assert(uInterruptState <= 2); /* only sti & mov ss */
1232	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1233	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1234	}
1235	else
1236	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1237
1238	/* Let's first sync back eip, esp, and eflags. */
1239	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1240	AssertRC(rc);
1241	pCtx->eip = val;
1242	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1243	AssertRC(rc);
1244	pCtx->esp = val;
1245	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1246	AssertRC(rc);
1247	pCtx->eflags.u32 = val;
1248
1249	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1250	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1251	{
1252	/* Hide our emulation flags */
1253	pCtx->eflags.Bits.u1VM = 0;
1254	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1255	pCtx->eflags.Bits.u1VIF = 0;
1256	pCtx->eflags.Bits.u2IOPL = 0;
1257	}
1258
1259	/* Control registers. */
1260	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1261	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1262	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1263	CPUMSetGuestCR0(pVM, val);
1264
1265	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1266	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1267	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1268	CPUMSetGuestCR4(pVM, val);
1269
1270	CPUMSetGuestCR2(pVM, ASMGetCR2());
1271
1272	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1273	CPUMSetGuestDR7(pVM, val);
1274
1275	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1276	VMX_READ_SELREG(ES, es);
1277	VMX_READ_SELREG(SS, ss);
1278	VMX_READ_SELREG(CS, cs);
1279	VMX_READ_SELREG(DS, ds);
1280	VMX_READ_SELREG(FS, fs);
1281	VMX_READ_SELREG(GS, gs);
1282
1283	/** @note NOW IT'S SAFE FOR LOGGING! */
1284	Log2(("Raw exit reason %08x\n", exitReason));
1285
1286	/* Check if an injected event was interrupted prematurely. */
1287	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1288	AssertRC(rc);
1289	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1290	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1291	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1292	{
1293	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1294	pVM->hwaccm.s.Event.fPending = true;
1295	/* Error code present? */
1296	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1297	{
1298	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1299	AssertRC(rc);
1300	pVM->hwaccm.s.Event.errCode = val;
1301	}
1302	else
1303	pVM->hwaccm.s.Event.errCode = 0;
1304	}
1305
1306	#ifdef VBOX_STRICT
1307	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1308	HWACCMDumpRegs(pCtx);
1309	#endif
1310
1311	Log2(("E%d", exitReason));
1312	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1313	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1314	Log2(("Interruption error code %d\n", errCode));
1315	Log2(("IntInfo = %08x\n", intInfo));
1316	Log2(("New EIP=%VGv\n", pCtx->eip));
1317
1318	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1319	switch (exitReason)
1320	{
1321	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1322	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1323	{
1324	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1325
1326	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1327	{
1328	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1329	/* External interrupt; leave to allow it to be dispatched again. */
1330	rc = VINF_EM_RAW_INTERRUPT;
1331	break;
1332	}
1333	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1334	{
1335	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1336	/* External interrupt; leave to allow it to be dispatched again. */
1337	rc = VINF_EM_RAW_INTERRUPT;
1338	break;
1339
1340	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1341	AssertFailed(); /* can't come here; fails the first check. */
1342	break;
1343
1344	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1345	Assert(vector == 3 \|\| vector == 4);
1346	/* no break */
1347	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1348	Log2(("Hardware/software interrupt %d\n", vector));
1349	switch (vector)
1350	{
1351	case X86_XCPT_NM:
1352	{
1353	uint32_t oldCR0;
1354
1355	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1356
1357	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1358	oldCR0 = ASMGetCR0();
1359	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1360	rc = CPUMHandleLazyFPU(pVM);
1361	if (rc == VINF_SUCCESS)
1362	{
1363	Assert(CPUMIsGuestFPUStateActive(pVM));
1364
1365	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1366	ASMSetCR0(oldCR0);
1367
1368	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1369
1370	/* Continue execution. */
1371	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1372	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1373
1374	goto ResumeExecution;
1375	}
1376
1377	Log(("Forward #NM fault to the guest\n"));
1378	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1379	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1380	AssertRC(rc);
1381	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1382	goto ResumeExecution;
1383	}
1384
1385	case X86_XCPT_PF: /* Page fault */
1386	{
1387	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1388	/* Exit qualification contains the linear address of the page fault. */
1389	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1390	TRPMSetErrorCode(pVM, errCode);
1391	TRPMSetFaultAddress(pVM, exitQualification);
1392
1393	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1394	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1395	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1396	if (rc == VINF_SUCCESS)
1397	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1398	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1399	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1400
1401	TRPMResetTrap(pVM);
1402
1403	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1404	goto ResumeExecution;
1405	}
1406	else
1407	if (rc == VINF_EM_RAW_GUEST_TRAP)
1408	{ /* A genuine pagefault.
1409	* Forward the trap to the guest by injecting the exception and resuming execution.
1410	*/
1411	Log2(("Forward page fault to the guest\n"));
1412	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1413	/* The error code might have been changed. */
1414	errCode = TRPMGetErrorCode(pVM);
1415
1416	TRPMResetTrap(pVM);
1417
1418	/* Now we must update CR2. */
1419	pCtx->cr2 = exitQualification;
1420	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1421	AssertRC(rc);
1422
1423	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1424	goto ResumeExecution;
1425	}
1426	#ifdef VBOX_STRICT
1427	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1428	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1429	#endif
1430	/* Need to go back to the recompiler to emulate the instruction. */
1431	TRPMResetTrap(pVM);
1432	break;
1433	}
1434
1435	case X86_XCPT_MF: /* Floating point exception. */
1436	{
1437	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1438	if (!(pCtx->cr0 & X86_CR0_NE))
1439	{
1440	/* old style FPU error reporting needs some extra work. */
1441	/** @todo don't fall back to the recompiler, but do it manually. */
1442	rc = VINF_EM_RAW_EMULATE_INSTR;
1443	break;
1444	}
1445	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1446	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1447	AssertRC(rc);
1448
1449	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1450	goto ResumeExecution;
1451	}
1452
1453	#ifdef VBOX_STRICT
1454	case X86_XCPT_GP: /* General protection failure exception.*/
1455	case X86_XCPT_UD: /* Unknown opcode exception. */
1456	case X86_XCPT_DE: /* Debug exception. */
1457	case X86_XCPT_SS: /* Stack segment exception. */
1458	case X86_XCPT_NP: /* Segment not present exception. */
1459	{
1460	switch(vector)
1461	{
1462	case X86_XCPT_DE:
1463	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1464	break;
1465	case X86_XCPT_UD:
1466	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1467	break;
1468	case X86_XCPT_SS:
1469	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1470	break;
1471	case X86_XCPT_NP:
1472	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1473	break;
1474	case X86_XCPT_GP:
1475	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1476	break;
1477	}
1478
1479	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1480	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1481	AssertRC(rc);
1482
1483	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1484	goto ResumeExecution;
1485	}
1486	#endif
1487	default:
1488	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1489	rc = VERR_EM_INTERNAL_ERROR;
1490	break;
1491	} /* switch (vector) */
1492
1493	break;
1494
1495	default:
1496	rc = VERR_EM_INTERNAL_ERROR;
1497	AssertFailed();
1498	break;
1499	}
1500
1501	break;
1502	}
1503
1504	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1505	/* Clear VM-exit on IF=1 change. */
1506	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1507	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1508	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1509	AssertRC(rc);
1510	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1511	goto ResumeExecution; /* we check for pending guest interrupts there */
1512
1513	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1514	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1515	/* Skip instruction and continue directly. */
1516	pCtx->eip += cbInstr;
1517	/* Continue execution.*/
1518	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1519	goto ResumeExecution;
1520
1521	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1522	{
1523	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1524	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1525	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1526	if (rc == VINF_SUCCESS)
1527	{
1528	/* Update EIP and continue execution. */
1529	Assert(cbInstr == 2);
1530	pCtx->eip += cbInstr;
1531	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1532	goto ResumeExecution;
1533	}
1534	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1535	rc = VINF_EM_RAW_EMULATE_INSTR;
1536	break;
1537	}
1538
1539	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1540	{
1541	Log2(("VMX: Rdtsc\n"));
1542	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1543	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1544	if (rc == VINF_SUCCESS)
1545	{
1546	/* Update EIP and continue execution. */
1547	Assert(cbInstr == 2);
1548	pCtx->eip += cbInstr;
1549	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1550	goto ResumeExecution;
1551	}
1552	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1553	rc = VINF_EM_RAW_EMULATE_INSTR;
1554	break;
1555	}
1556
1557	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1558	{
1559	Log2(("VMX: invlpg\n"));
1560	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1561	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1562	if (rc == VINF_SUCCESS)
1563	{
1564	/* Update EIP and continue execution. */
1565	pCtx->eip += cbInstr;
1566	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1567	goto ResumeExecution;
1568	}
1569	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1570	break;
1571	}
1572
1573	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1574	{
1575	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1576	{
1577	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1578	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1579	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1580	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1581	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1582	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1583
1584	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1585	{
1586	case 0:
1587	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1588	break;
1589	case 2:
1590	break;
1591	case 3:
1592	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1593	break;
1594	case 4:
1595	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1596	break;
1597	default:
1598	AssertFailed();
1599	}
1600	/* Check if a sync operation is pending. */
1601	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1602	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1603	{
1604	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1605	AssertRC(rc);
1606	}
1607	break;
1608
1609	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1610	Log2(("VMX: mov x, crx\n"));
1611	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1612	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1613	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1614	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1615	break;
1616
1617	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1618	Log2(("VMX: clts\n"));
1619	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1620	rc = EMInterpretCLTS(pVM);
1621	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1622	break;
1623
1624	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1625	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1626	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1627	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1628	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1629	break;
1630	}
1631
1632	/* Update EIP if no error occurred. */
1633	if (VBOX_SUCCESS(rc))
1634	pCtx->eip += cbInstr;
1635
1636	if (rc == VINF_SUCCESS)
1637	{
1638	/* Only resume if successful. */
1639	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1640	goto ResumeExecution;
1641	}
1642	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1643	break;
1644	}
1645
1646	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1647	{
1648	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1649	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1650	{
1651	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1652	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1653	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1654	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1655	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1656	Log2(("DR7=%08x\n", pCtx->dr7));
1657	}
1658	else
1659	{
1660	Log2(("VMX: mov x, drx\n"));
1661	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1662	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1663	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1664	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1665	}
1666	/* Update EIP if no error occurred. */
1667	if (VBOX_SUCCESS(rc))
1668	pCtx->eip += cbInstr;
1669
1670	if (rc == VINF_SUCCESS)
1671	{
1672	/* Only resume if successful. */
1673	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1674	goto ResumeExecution;
1675	}
1676	Assert(rc == VERR_EM_INTERPRETER);
1677	break;
1678	}
1679
1680	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1681	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1682	{
1683	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1684	uint32_t uPort;
1685	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1686
1687	/** @todo necessary to make the distinction? */
1688	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1689	{
1690	uPort = pCtx->edx & 0xffff;
1691	}
1692	else
1693	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1694
1695	/* paranoia */
1696	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1697	{
1698	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1699	break;
1700	}
1701
1702	uint32_t cbSize = aIOSize[uIOWidth];
1703
1704	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1705	{
1706	/* ins/outs */
1707	uint32_t prefix = 0;
1708	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1709	prefix \|= PREFIX_REP;
1710
1711	if (fIOWrite)
1712	{
1713	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1714	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1715	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1716	}
1717	else
1718	{
1719	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1720	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1721	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1722	}
1723	}
1724	else
1725	{
1726	/* normal in/out */
1727	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1728
1729	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1730
1731	if (fIOWrite)
1732	{
1733	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1734	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1735	}
1736	else
1737	{
1738	uint32_t u32Val = 0;
1739
1740	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1741	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1742	if (IOM_SUCCESS(rc))
1743	{
1744	/* Write back to the EAX register. */
1745	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1746	}
1747	}
1748	}
1749	/*
1750	* Handled the I/O return codes.
1751	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1752	*/
1753	if (IOM_SUCCESS(rc))
1754	{
1755	/* Update EIP and continue execution. */
1756	pCtx->eip += cbInstr;
1757	if (RT_LIKELY(rc == VINF_SUCCESS))
1758	{
1759	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1760	goto ResumeExecution;
1761	}
1762	break;
1763	}
1764
1765	#ifdef VBOX_STRICT
1766	if (rc == VINF_IOM_HC_IOPORT_READ)
1767	Assert(!fIOWrite);
1768	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1769	Assert(fIOWrite);
1770	else
1771	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1772	#endif
1773	break;
1774	}
1775
1776	default:
1777	/* The rest is handled after syncing the entire CPU state. */
1778	break;
1779	}
1780
1781	/* Note: the guest state isn't entirely synced back at this stage. */
1782
1783	/* Investigate why there was a VM-exit. (part 2) */
1784	switch (exitReason)
1785	{
1786	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1787	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1788	/* Already handled above. */
1789	break;
1790
1791	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1792	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1793	break;
1794
1795	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1796	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1797	rc = VINF_EM_RAW_INTERRUPT;
1798	AssertFailed(); /* Can't happen. Yet. */
1799	break;
1800
1801	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1802	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1803	rc = VINF_EM_RAW_INTERRUPT;
1804	AssertFailed(); /* Can't happen afaik. */
1805	break;
1806
1807	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1808	rc = VERR_EM_INTERPRETER;
1809	break;
1810
1811	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1812	/** Check if external interrupts are pending; if so, don't switch back. */
1813	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1814	{
1815	pCtx->eip++; /* skip hlt */
1816	goto ResumeExecution;
1817	}
1818
1819	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1820	break;
1821
1822	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1823	AssertFailed(); /* can't happen. */
1824	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1825	break;
1826
1827	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1828	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1829	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1830	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1831	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1832	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1833	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1834	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1835	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1836	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1837	/** @todo inject #UD immediately */
1838	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1839	break;
1840
1841	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1842	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1843	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1844	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1845	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1846	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1847	/* already handled above */
1848	AssertMsg( rc == VINF_PGM_CHANGE_MODE
1849	\|\| rc == VINF_EM_RAW_INTERRUPT
1850	\|\| rc == VERR_EM_INTERPRETER
1851	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
1852	\|\| rc == VINF_PGM_SYNC_CR3
1853	\|\| rc == VINF_IOM_HC_IOPORT_READ
1854	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
1855	\|\| rc == VINF_EM_RAW_GUEST_TRAP
1856	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
1857	\|\| rc == VINF_EM_RESCHEDULE_REM,
1858	("rc = %d\n", rc));
1859	break;
1860
1861	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1862	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1863	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1864	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1865	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1866	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1867	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1868	break;
1869
1870	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1871	Assert(rc == VINF_EM_RAW_INTERRUPT);
1872	break;
1873
1874	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1875	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1876	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1877	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1878	default:
1879	rc = VERR_EM_INTERNAL_ERROR;
1880	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1881	break;
1882
1883	}
1884	end:
1885	if (fGuestStateSynced)
1886	{
1887	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1888	VMX_READ_SELREG(LDTR, ldtr);
1889	VMX_READ_SELREG(TR, tr);
1890
1891	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1892	pCtx->gdtr.cbGdt = val;
1893	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1894	pCtx->gdtr.pGdt = val;
1895
1896	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1897	pCtx->idtr.cbIdt = val;
1898	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1899	pCtx->idtr.pIdt = val;
1900
1901	/*
1902	* System MSRs
1903	*/
1904	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1905	pCtx->SysEnter.cs = val;
1906	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1907	pCtx->SysEnter.eip = val;
1908	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1909	pCtx->SysEnter.esp = val;
1910	}
1911
1912	/* Signal changes for the recompiler. */
1913	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1914
1915	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
1916	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
1917	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1918	{
1919	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1920	/* On the next entry we'll only sync the host context. */
1921	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1922	}
1923	else
1924	{
1925	/* On the next entry we'll sync everything. */
1926	/** @todo we can do better than this */
1927	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1928	}
1929
1930	/* translate into a less severe return code */
1931	if (rc == VERR_EM_INTERPRETER)
1932	rc = VINF_EM_RAW_EMULATE_INSTR;
1933
1934	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1935	Log2(("X"));
1936	return rc;
1937	}
1938
1939
1940	/**
1941	* Enable VMX
1942	*
1943	* @returns VBox status code.
1944	* @param pVM The VM to operate on.
1945	*/
1946	HWACCMR0DECL(int) VMXR0Enable(PVM pVM)
1947	{
1948	Assert(pVM->hwaccm.s.vmx.fSupported);
1949
1950	/* Make sure the VMX instructions don't cause #UD faults. */
1951	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
1952
1953	/* Enter VMX Root Mode */
1954	int rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
1955	if (VBOX_FAILURE(rc))
1956	return rc;
1957
1958	/* Activate the VM Control Structure. */
1959	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1960	if (VBOX_FAILURE(rc))
1961	{
1962	/* Leave VMX Root Mode. */
1963	VMXDisable();
1964	return rc;
1965	}
1966	pVM->hwaccm.s.vmx.fResumeVM = false;
1967	return VINF_SUCCESS;
1968	}
1969
1970
1971	/**
1972	* Disable VMX
1973	*
1974	* @returns VBox status code.
1975	* @param pVM The VM to operate on.
1976	*/
1977	HWACCMR0DECL(int) VMXR0Disable(PVM pVM)
1978	{
1979	Assert(pVM->hwaccm.s.vmx.fSupported);
1980
1981	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
1982	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1983	AssertRC(rc);
1984
1985	/* Leave VMX Root Mode. */
1986	VMXDisable();
1987
1988	return VINF_SUCCESS;
1989	}
1990

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 5605

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