VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 7500

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1/* $Id: HWVMXR0.cpp 7500 2008-03-19 12:20:58Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HWACCM
23#include <VBox/hwaccm.h>
24#include "HWACCMInternal.h"
25#include <VBox/vm.h>
26#include <VBox/x86.h>
27#include <VBox/pgm.h>
28#include <VBox/pdm.h>
29#include <VBox/err.h>
30#include <VBox/log.h>
31#include <VBox/selm.h>
32#include <VBox/iom.h>
33#include <iprt/param.h>
34#include <iprt/assert.h>
35#include <iprt/asm.h>
36#include <iprt/string.h>
37#include "HWVMXR0.h"
38
39
40/* IO operation lookup arrays. */
41static uint32_t aIOSize[4] = {1, 2, 0, 4};
42static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
43
44
45static void VMXR0CheckError(PVM pVM, int rc)
46{
47 if (rc == VERR_VMX_GENERIC)
48 {
49 RTCCUINTREG instrError;
50
51 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
52 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
53 }
54 pVM->hwaccm.s.lLastError = rc;
55}
56
57/**
58 * Sets up and activates VT-x on the current CPU
59 *
60 * @returns VBox status code.
61 * @param idCpu The identifier for the CPU the function is called on.
62 * @param pVM The VM to operate on.
63 * @param pvPageCpu Pointer to the global cpu page
64 * @param pPageCpuPhys Physical address of the global cpu page
65 */
66HWACCMR0DECL(int) VMXR0EnableCpu(RTCPUID idCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
67{
68 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
69 AssertReturn(pVM, VERR_INVALID_PARAMETER);
70 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
71
72 /* Setup Intel VMX. */
73 Assert(pVM->hwaccm.s.vmx.fSupported);
74
75#ifdef LOG_ENABLED
76 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
77#endif
78 /* Set revision dword at the beginning of the VMXON structure. */
79 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
80
81 /* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
82 * (which can have very bad consequences!!!)
83 */
84
85 /* Make sure the VMX instructions don't cause #UD faults. */
86 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
87
88 /* Enter VMX Root Mode */
89 int rc = VMXEnable(pPageCpuPhys);
90 if (VBOX_FAILURE(rc))
91 {
92 VMXR0CheckError(pVM, rc);
93 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
94 return VERR_VMX_VMXON_FAILED;
95 }
96 return VINF_SUCCESS;
97}
98
99/**
100 * Deactivates VT-x on the current CPU
101 *
102 * @returns VBox status code.
103 * @param idCpu The identifier for the CPU the function is called on.
104 * @param pvPageCpu Pointer to the global cpu page
105 * @param pPageCpuPhys Physical address of the global cpu page
106 */
107HWACCMR0DECL(int) VMXR0DisableCpu(RTCPUID idCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
108{
109 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
110 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
111
112 /* Leave VMX Root Mode. */
113 VMXDisable();
114
115 /* And clear the X86_CR4_VMXE bit */
116 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
117
118#ifdef LOG_ENABLED
119 SUPR0Printf("VMXR0DisableCpu cpu %d\n", idCpu);
120#endif
121 return VINF_SUCCESS;
122}
123
124/**
125 * Does Ring-0 per VM VT-x init.
126 *
127 * @returns VBox status code.
128 * @param pVM The VM to operate on.
129 */
130HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
131{
132 int rc;
133
134#ifdef LOG_ENABLED
135 SUPR0Printf("VMXR0InitVM %x\n", pVM);
136#endif
137
138 /* Allocate one page for the VM control structure (VMCS). */
139 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
140 AssertRC(rc);
141 if (RT_FAILURE(rc))
142 return rc;
143
144 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
145 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
146 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
147
148 /* Allocate one page for the TSS we need for real mode emulation. */
149 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
150 AssertRC(rc);
151 if (RT_FAILURE(rc))
152 return rc;
153
154 pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
155 pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
156
157 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
158 * for I/O operations. */
159 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
160 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
161 /* Bit set to 0 means redirection enabled. */
162 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
163
164#ifdef LOG_ENABLED
165 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
166#endif
167 return VINF_SUCCESS;
168}
169
170/**
171 * Does Ring-0 per VM VT-x termination.
172 *
173 * @returns VBox status code.
174 * @param pVM The VM to operate on.
175 */
176HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
177{
178 if (pVM->hwaccm.s.vmx.pMemObjVMCS)
179 {
180 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
181 pVM->hwaccm.s.vmx.pMemObjVMCS = 0;
182 pVM->hwaccm.s.vmx.pVMCS = 0;
183 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
184 }
185 if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS)
186 {
187 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
188 pVM->hwaccm.s.vmx.pMemObjRealModeTSS = 0;
189 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
190 pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
191 }
192 return VINF_SUCCESS;
193}
194
195/**
196 * Sets up VT-x for the specified VM
197 *
198 * @returns VBox status code.
199 * @param pVM The VM to operate on.
200 */
201HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
202{
203 int rc = VINF_SUCCESS;
204 uint32_t val;
205
206 AssertReturn(pVM, VERR_INVALID_PARAMETER);
207 Assert(pVM->hwaccm.s.vmx.pVMCS);
208
209 /* Set revision dword at the beginning of the VMCS structure. */
210 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
211
212 /* Clear VM Control Structure. */
213 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
214 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
215 if (VBOX_FAILURE(rc))
216 goto vmx_end;
217
218 /* Activate the VM Control Structure. */
219 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
220 if (VBOX_FAILURE(rc))
221 goto vmx_end;
222
223 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
224 * Set required bits to one and zero according to the MSR capabilities.
225 */
226 val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
227 /* External and non-maskable interrupts cause VM-exits. */
228 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
229 val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
230
231 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
232 AssertRC(rc);
233
234 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
235 * Set required bits to one and zero according to the MSR capabilities.
236 */
237 val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
238 /* Program which event cause VM-exits and which features we want to use. */
239 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
240 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
241 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
242 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
243 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
244 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
245
246 /** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
247
248 /*
249 if AMD64 guest mode
250 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
251 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
252 */
253#if HC_ARCH_BITS == 64
254 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
255 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
256#endif
257 /* Mask away the bits that the CPU doesn't support */
258 /** @todo make sure they don't conflict with the above requirements. */
259 val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
260 pVM->hwaccm.s.vmx.proc_ctls = val;
261
262 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
263 AssertRC(rc);
264
265 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
266 * Set required bits to one and zero according to the MSR capabilities.
267 */
268 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
269 AssertRC(rc);
270
271 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
272 * Set required bits to one and zero according to the MSR capabilities.
273 */
274 val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
275 if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
276 {
277 /** @todo 32 bits guest mode only for now. */
278 /* val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
279 }
280 /* Mask away the bits that the CPU doesn't support */
281 /** @todo make sure they don't conflict with the above requirements. */
282 val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
283 /* else Must be zero when AMD64 is not available. */
284 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
285 AssertRC(rc);
286
287 /* VMX_VMCS_CTRL_EXIT_CONTROLS
288 * Set required bits to one and zero according to the MSR capabilities.
289 */
290 val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
291#if HC_ARCH_BITS == 64
292 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
293#else
294 /* else Must be zero when AMD64 is not available. */
295#endif
296 val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
297 /* Don't acknowledge external interrupts on VM-exit. */
298 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
299 AssertRC(rc);
300
301 /* Forward all exception except #NM & #PF to the guest.
302 * We always need to check pagefaults since our shadow page table can be out of sync.
303 * And we always lazily sync the FPU & XMM state.
304 */
305
306 /*
307 * @todo Possible optimization:
308 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
309 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
310 * registers ourselves of course.
311 *
312 * @note only possible if the current state is actually ours (X86_CR0_TS flag)
313 */
314 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
315 AssertRC(rc);
316
317 /* Don't filter page faults; all of them should cause a switch. */
318 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
319 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
320 AssertRC(rc);
321
322 /* Init TSC offset to zero. */
323 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
324#if HC_ARCH_BITS == 32
325 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
326#endif
327 AssertRC(rc);
328
329 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
330#if HC_ARCH_BITS == 32
331 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
332#endif
333 AssertRC(rc);
334
335 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
336#if HC_ARCH_BITS == 32
337 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
338#endif
339 AssertRC(rc);
340
341 /* Clear MSR controls. */
342 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
343 {
344 /* Optional */
345 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
346#if HC_ARCH_BITS == 32
347 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
348#endif
349 AssertRC(rc);
350 }
351 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
352 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
353 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
354#if HC_ARCH_BITS == 32
355 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
356 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
357 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
358#endif
359 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
360 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
361 AssertRC(rc);
362
363 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
364 {
365 /* Optional */
366 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
367 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
368#if HC_ARCH_BITS == 32
369 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
370#endif
371 AssertRC(rc);
372 }
373
374 /* Set link pointer to -1. Not currently used. */
375#if HC_ARCH_BITS == 32
376 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
377 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
378#else
379 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
380#endif
381 AssertRC(rc);
382
383 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
384 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
385 AssertRC(rc);
386
387vmx_end:
388 VMXR0CheckError(pVM, rc);
389 return rc;
390}
391
392
393/**
394 * Injects an event (trap or external interrupt)
395 *
396 * @returns VBox status code.
397 * @param pVM The VM to operate on.
398 * @param pCtx CPU Context
399 * @param intInfo VMX interrupt info
400 * @param cbInstr Opcode length of faulting instruction
401 * @param errCode Error code (optional)
402 */
403static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
404{
405 int rc;
406
407#ifdef VBOX_STRICT
408 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
409 if (iGate == 0xE)
410 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
411 else
412 if (iGate < 0x20)
413 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
414 else
415 {
416 Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
417 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
418 Assert(pCtx->eflags.u32 & X86_EFL_IF);
419 }
420#endif
421
422 /* Set event injection state. */
423 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
424 intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
425 );
426
427 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
428 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
429
430 AssertRC(rc);
431 return rc;
432}
433
434
435/**
436 * Checks for pending guest interrupts and injects them
437 *
438 * @returns VBox status code.
439 * @param pVM The VM to operate on.
440 * @param pCtx CPU Context
441 */
442static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
443{
444 int rc;
445
446 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
447 if (pVM->hwaccm.s.Event.fPending)
448 {
449 Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
450 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
451 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
452 AssertRC(rc);
453
454 pVM->hwaccm.s.Event.fPending = false;
455 return VINF_SUCCESS;
456 }
457
458 /* When external interrupts are pending, we should exit the VM when IF is set. */
459 if ( !TRPMHasTrap(pVM)
460 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
461 {
462 if (!(pCtx->eflags.u32 & X86_EFL_IF))
463 {
464 Log2(("Enable irq window exit!\n"));
465 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
466 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
467 AssertRC(rc);
468 }
469 else
470 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
471 {
472 uint8_t u8Interrupt;
473
474 rc = PDMGetInterrupt(pVM, &u8Interrupt);
475 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
476 if (VBOX_SUCCESS(rc))
477 {
478 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
479 AssertRC(rc);
480 }
481 else
482 {
483 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
484 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
485 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
486 /* Just continue */
487 }
488 }
489 else
490 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
491 }
492
493#ifdef VBOX_STRICT
494 if (TRPMHasTrap(pVM))
495 {
496 uint8_t u8Vector;
497 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
498 AssertRC(rc);
499 }
500#endif
501
502 if ( pCtx->eflags.u32 & X86_EFL_IF
503 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
504 && TRPMHasTrap(pVM)
505 )
506 {
507 uint8_t u8Vector;
508 int rc;
509 TRPMEVENT enmType;
510 RTGCUINTPTR intInfo, errCode;
511
512 /* If a new event is pending, then dispatch it now. */
513 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
514 AssertRC(rc);
515 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
516 Assert(enmType != TRPM_SOFTWARE_INT);
517
518 /* Clear the pending trap. */
519 rc = TRPMResetTrap(pVM);
520 AssertRC(rc);
521
522 intInfo = u8Vector;
523 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
524
525 if (enmType == TRPM_TRAP)
526 {
527 switch (u8Vector) {
528 case 8:
529 case 10:
530 case 11:
531 case 12:
532 case 13:
533 case 14:
534 case 17:
535 /* Valid error codes. */
536 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
537 break;
538 default:
539 break;
540 }
541 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
542 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
543 else
544 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
545 }
546 else
547 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
548
549 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
550 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
551 AssertRC(rc);
552 } /* if (interrupts can be dispatched) */
553
554 return VINF_SUCCESS;
555}
556
557/**
558 * Save the host state
559 *
560 * @returns VBox status code.
561 * @param pVM The VM to operate on.
562 */
563HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
564{
565 int rc = VINF_SUCCESS;
566
567 /*
568 * Host CPU Context
569 */
570 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
571 {
572 RTIDTR idtr;
573 RTGDTR gdtr;
574 RTSEL SelTR;
575 PX86DESCHC pDesc;
576 uintptr_t trBase;
577
578 /* Control registers */
579 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
580 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
581 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
582 AssertRC(rc);
583 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
584 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
585 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
586
587 /* Selector registers. */
588 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
589 /** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
590 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
591 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
592#if HC_ARCH_BITS == 32
593 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
594 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
595#endif
596 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
597 SelTR = ASMGetTR();
598 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
599 AssertRC(rc);
600 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
601 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
602 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
603 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
604 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
605 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
606 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
607
608 /* GDTR & IDTR */
609 ASMGetGDTR(&gdtr);
610 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
611 ASMGetIDTR(&idtr);
612 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
613 AssertRC(rc);
614 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
615 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
616
617 /* Save the base address of the TR selector. */
618 if (SelTR > gdtr.cbGdt)
619 {
620 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
621 return VERR_VMX_INVALID_HOST_STATE;
622 }
623
624 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
625#if HC_ARCH_BITS == 64
626 trBase = pDesc->Gen.u16BaseLow | (pDesc->Gen.u8BaseHigh1 << 16ULL) | (pDesc->Gen.u8BaseHigh2 << 24ULL) | ((uintptr_t)pDesc->Gen.u32BaseHigh3 << 32ULL);
627#else
628 trBase = pDesc->Gen.u16BaseLow | (pDesc->Gen.u8BaseHigh1 << 16) | (pDesc->Gen.u8BaseHigh2 << 24);
629#endif
630 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
631 AssertRC(rc);
632 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
633
634 /* FS and GS base. */
635#if HC_ARCH_BITS == 64
636 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
637 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
638 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
639 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
640#endif
641 AssertRC(rc);
642
643 /* Sysenter MSRs. */
644 /** @todo expensive!! */
645 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
646 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
647#if HC_ARCH_BITS == 32
648 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
649 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
650 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
651 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
652#else
653 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
654 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
655 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
656 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
657#endif
658 AssertRC(rc);
659
660 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
661 }
662 return rc;
663}
664
665
666/**
667 * Loads the guest state
668 *
669 * @returns VBox status code.
670 * @param pVM The VM to operate on.
671 * @param pCtx Guest context
672 */
673HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
674{
675 int rc = VINF_SUCCESS;
676 RTGCUINTPTR val;
677 X86EFLAGS eflags;
678
679 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
680 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
681 {
682 VMX_WRITE_SELREG(ES, es);
683 AssertRC(rc);
684
685 VMX_WRITE_SELREG(CS, cs);
686 AssertRC(rc);
687
688 VMX_WRITE_SELREG(SS, ss);
689 AssertRC(rc);
690
691 VMX_WRITE_SELREG(DS, ds);
692 AssertRC(rc);
693
694 VMX_WRITE_SELREG(FS, fs);
695 AssertRC(rc);
696
697 VMX_WRITE_SELREG(GS, gs);
698 AssertRC(rc);
699 }
700
701 /* Guest CPU context: LDTR. */
702 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
703 {
704 if (pCtx->ldtr == 0)
705 {
706 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
707 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
708 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
709 /** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
710 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
711 }
712 else
713 {
714 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
715 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
716 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
717 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
718 }
719 AssertRC(rc);
720 }
721 /* Guest CPU context: TR. */
722 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
723 {
724 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
725
726 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
727 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
728 {
729 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
730 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
731 }
732 else
733 {
734 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
735 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
736 }
737 val = pCtx->trHid.Attr.u;
738
739 /* The TSS selector must be busy. */
740 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
741 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
742 else
743 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
744 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
745
746 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
747 AssertRC(rc);
748 }
749 /* Guest CPU context: GDTR. */
750 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
751 {
752 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
753 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
754 AssertRC(rc);
755 }
756 /* Guest CPU context: IDTR. */
757 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
758 {
759 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
760 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
761 AssertRC(rc);
762 }
763
764 /*
765 * Sysenter MSRs
766 */
767 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
768 {
769 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
770 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
771 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
772 AssertRC(rc);
773 }
774
775 /* Control registers */
776 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
777 {
778 val = pCtx->cr0;
779 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
780 Log2(("Guest CR0-shadow %08x\n", val));
781 if (CPUMIsGuestFPUStateActive(pVM) == false)
782 {
783 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
784 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
785 }
786 else
787 {
788 Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
789 /** @todo check if we support the old style mess correctly. */
790 if (!(val & X86_CR0_NE))
791 {
792 Log(("Forcing X86_CR0_NE!!!\n"));
793
794 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
795 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
796 {
797 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK | RT_BIT(16));
798 AssertRC(rc);
799 pVM->hwaccm.s.fFPUOldStyleOverride = true;
800 }
801 }
802
803 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
804 }
805 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
806 val |= X86_CR0_PE | X86_CR0_PG;
807
808 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
809 Log2(("Guest CR0 %08x\n", val));
810 /* CR0 flags owned by the host; if the guests attempts to change them, then
811 * the VM will exit.
812 */
813 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
814 | X86_CR0_WP /** @todo do we care? (we do if we start patching the guest) */
815 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
816 | X86_CR0_TS
817 | X86_CR0_ET
818 | X86_CR0_NE
819 | X86_CR0_MP;
820 pVM->hwaccm.s.vmx.cr0_mask = val;
821
822 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
823 Log2(("Guest CR0-mask %08x\n", val));
824 AssertRC(rc);
825 }
826 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
827 {
828 /* CR4 */
829 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
830 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
831 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
832 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
833 switch(pVM->hwaccm.s.enmShadowMode)
834 {
835 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
836 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
837 case PGMMODE_32_BIT: /* 32-bit paging. */
838 break;
839
840 case PGMMODE_PAE: /* PAE paging. */
841 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
842 /** @todo use normal 32 bits paging */
843 val |= X86_CR4_PAE;
844 break;
845
846 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
847 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
848 AssertFailed();
849 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
850
851 default: /* shut up gcc */
852 AssertFailed();
853 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
854 }
855 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
856 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
857 val |= X86_CR4_VME;
858
859 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
860 Log2(("Guest CR4 %08x\n", val));
861 /* CR4 flags owned by the host; if the guests attempts to change them, then
862 * the VM will exit.
863 */
864 val = X86_CR4_PAE
865 | X86_CR4_PGE
866 | X86_CR4_PSE
867 | X86_CR4_VMXE;
868 pVM->hwaccm.s.vmx.cr4_mask = val;
869
870 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
871 Log2(("Guest CR4-mask %08x\n", val));
872 AssertRC(rc);
873 }
874
875 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
876 {
877 /* Save our shadow CR3 register. */
878 val = PGMGetHyperCR3(pVM);
879 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
880 AssertRC(rc);
881 }
882
883 /* Debug registers. */
884 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
885 {
886 /** @todo DR0-6 */
887 val = pCtx->dr7;
888 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
889 val |= 0x400; /* must be one */
890#ifdef VBOX_STRICT
891 val = 0x400;
892#endif
893 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
894 AssertRC(rc);
895
896 /* IA32_DEBUGCTL MSR. */
897 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
898 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
899 AssertRC(rc);
900
901 /** @todo */
902 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
903 AssertRC(rc);
904 }
905
906 /* EIP, ESP and EFLAGS */
907 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
908 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
909 AssertRC(rc);
910
911 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
912 eflags = pCtx->eflags;
913 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
914 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
915
916 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
917 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
918 {
919 eflags.Bits.u1VM = 1;
920 eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
921 eflags.Bits.u2IOPL = 3;
922 }
923
924 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
925 AssertRC(rc);
926
927 /** TSC offset. */
928 uint64_t u64TSCOffset;
929
930 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
931 {
932 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
933#if HC_ARCH_BITS == 64
934 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
935#else
936 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
937 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
938#endif
939 AssertRC(rc);
940
941 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
942 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
943 AssertRC(rc);
944 }
945 else
946 {
947 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
948 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
949 AssertRC(rc);
950 }
951
952 /* Done. */
953 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
954
955 return rc;
956}
957
958/**
959 * Runs guest code in a VMX VM.
960 *
961 * @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
962 *
963 * @returns VBox status code.
964 * @param pVM The VM to operate on.
965 * @param pCtx Guest context
966 */
967HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
968{
969 int rc = VINF_SUCCESS;
970 RTCCUINTREG val, valShadow;
971 RTCCUINTREG exitReason, instrError, cbInstr;
972 RTGCUINTPTR exitQualification;
973 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
974 RTGCUINTPTR errCode, instrInfo, uInterruptState;
975 bool fGuestStateSynced = false;
976 unsigned cResume = 0;
977
978 Log2(("\nE"));
979
980 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
981
982#ifdef VBOX_STRICT
983 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
984 AssertRC(rc);
985 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
986
987 /* allowed zero */
988 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
989 {
990 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
991 }
992 /* allowed one */
993 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
994 {
995 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
996 }
997
998 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
999 AssertRC(rc);
1000 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1001
1002 /* allowed zero */
1003 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
1004 {
1005 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1006 }
1007 /* allowed one */
1008 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
1009 {
1010 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1011 }
1012
1013 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1014 AssertRC(rc);
1015 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1016
1017 /* allowed zero */
1018 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
1019 {
1020 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1021 }
1022 /* allowed one */
1023 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
1024 {
1025 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1026 }
1027
1028 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1029 AssertRC(rc);
1030 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1031
1032 /* allowed zero */
1033 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
1034 {
1035 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1036 }
1037 /* allowed one */
1038 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
1039 {
1040 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1041 }
1042#endif
1043
1044#if 0
1045 /*
1046 * Check if debug registers are armed.
1047 */
1048 uint32_t u32DR7 = ASMGetDR7();
1049 if (u32DR7 & X86_DR7_ENABLED_MASK)
1050 {
1051 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
1052 }
1053 else
1054 pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1055#endif
1056
1057 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1058 */
1059ResumeExecution:
1060 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1061 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1062 {
1063 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1064 rc = VINF_EM_RAW_INTERRUPT;
1065 goto end;
1066 }
1067
1068 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1069 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1070 {
1071 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
1072 if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
1073 {
1074 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1075 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1076 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1077 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1078 */
1079 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1080 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1081 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1082 AssertRC(rc);
1083 }
1084 }
1085 else
1086 {
1087 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1088 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1089 AssertRC(rc);
1090 }
1091
1092 /* Check for pending actions that force us to go back to ring 3. */
1093 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1094 {
1095 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1096 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1097 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1098 rc = VINF_EM_RAW_TO_R3;
1099 goto end;
1100 }
1101 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1102 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1103 {
1104 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1105 rc = VINF_EM_PENDING_REQUEST;
1106 goto end;
1107 }
1108
1109 /* When external interrupts are pending, we should exit the VM when IF is set. */
1110 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
1111 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1112 if (VBOX_FAILURE(rc))
1113 {
1114 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1115 goto end;
1116 }
1117
1118 /** @todo check timers?? */
1119
1120 /* Save the host state first. */
1121 rc = VMXR0SaveHostState(pVM);
1122 if (rc != VINF_SUCCESS)
1123 {
1124 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1125 goto end;
1126 }
1127 /* Load the guest state */
1128 rc = VMXR0LoadGuestState(pVM, pCtx);
1129 if (rc != VINF_SUCCESS)
1130 {
1131 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1132 goto end;
1133 }
1134 fGuestStateSynced = true;
1135
1136 /* Non-register state Guest Context */
1137 /** @todo change me according to cpu state */
1138 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1139 AssertRC(rc);
1140
1141 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1142
1143 /* Manual save and restore:
1144 * - General purpose registers except RIP, RSP
1145 *
1146 * Trashed:
1147 * - CR2 (we don't care)
1148 * - LDTR (reset to 0)
1149 * - DRx (presumably not changed at all)
1150 * - DR7 (reset to 0x400)
1151 * - EFLAGS (reset to RT_BIT(1); not relevant)
1152 *
1153 */
1154
1155 /* All done! Let's start VM execution. */
1156 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1157 if (pVM->hwaccm.s.vmx.fResumeVM == false)
1158 rc = VMXStartVM(pCtx);
1159 else
1160 rc = VMXResumeVM(pCtx);
1161
1162 /* In case we execute a goto ResumeExecution later on. */
1163 pVM->hwaccm.s.vmx.fResumeVM = true;
1164
1165 /**
1166 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1167 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1168 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1169 */
1170
1171 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1172 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1173
1174 switch (rc)
1175 {
1176 case VINF_SUCCESS:
1177 break;
1178
1179 case VERR_VMX_INVALID_VMXON_PTR:
1180 AssertFailed();
1181 goto end;
1182
1183 case VERR_VMX_UNABLE_TO_START_VM:
1184 case VERR_VMX_UNABLE_TO_RESUME_VM:
1185 {
1186#ifdef VBOX_STRICT
1187 int rc1;
1188
1189 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1190 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1191 AssertRC(rc1);
1192 if (rc1 == VINF_SUCCESS)
1193 {
1194 RTGDTR gdtr;
1195 PX86DESCHC pDesc;
1196
1197 ASMGetGDTR(&gdtr);
1198
1199 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1200 Log(("Current stack %08x\n", &rc1));
1201
1202
1203 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1204 Log(("Old eip %VGv new %VGv\n", pCtx->eip, (RTGCPTR)val));
1205 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1206 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1207 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1208 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1209 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1210 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1211 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1212 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1213
1214 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1215 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1216
1217 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1218 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1219
1220 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1221 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1222
1223 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1224 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1225 if (val < gdtr.cbGdt)
1226 {
1227 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1228 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1229 }
1230
1231 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1232 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1233 if (val < gdtr.cbGdt)
1234 {
1235 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1236 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1237 }
1238
1239 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1240 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1241 if (val < gdtr.cbGdt)
1242 {
1243 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1244 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1245 }
1246
1247 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1248 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1249 if (val < gdtr.cbGdt)
1250 {
1251 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1252 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1253 }
1254
1255 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1256 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1257 if (val < gdtr.cbGdt)
1258 {
1259 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1260 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1261 }
1262
1263 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1264 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1265 if (val < gdtr.cbGdt)
1266 {
1267 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1268 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1269 }
1270
1271 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1272 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1273 if (val < gdtr.cbGdt)
1274 {
1275 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1276 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1277 }
1278
1279 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1280 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1281
1282 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1283 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1284 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1285 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1286
1287 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1288 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1289
1290 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1291 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1292
1293 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1294 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1295
1296 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1297 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1298 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1299 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1300
1301#if HC_ARCH_BITS == 64
1302 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1303 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1304 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1305 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1306 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1307#endif
1308 }
1309#endif /* VBOX_STRICT */
1310 goto end;
1311 }
1312
1313 default:
1314 /* impossible */
1315 AssertFailed();
1316 goto end;
1317 }
1318 /* Success. Query the guest state and figure out what has happened. */
1319
1320 /* Investigate why there was a VM-exit. */
1321 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1322 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1323
1324 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1325 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1326 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1327 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1328 intInfo = val;
1329 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1330 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1331 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1332 instrInfo = val;
1333 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1334 exitQualification = val;
1335 AssertRC(rc);
1336
1337 /* Take care of instruction fusing (sti, mov ss) */
1338 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1339 uInterruptState = val;
1340 if (uInterruptState != 0)
1341 {
1342 Assert(uInterruptState <= 2); /* only sti & mov ss */
1343 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1344 EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1345 }
1346 else
1347 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1348
1349 /* Let's first sync back eip, esp, and eflags. */
1350 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1351 AssertRC(rc);
1352 pCtx->eip = val;
1353 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1354 AssertRC(rc);
1355 pCtx->esp = val;
1356 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1357 AssertRC(rc);
1358 pCtx->eflags.u32 = val;
1359
1360 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1361 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1362 {
1363 /* Hide our emulation flags */
1364 pCtx->eflags.Bits.u1VM = 0;
1365 pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1366 pCtx->eflags.Bits.u1VIF = 0;
1367 pCtx->eflags.Bits.u2IOPL = 0;
1368 }
1369
1370 /* Control registers. */
1371 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1372 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1373 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1374 CPUMSetGuestCR0(pVM, val);
1375
1376 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1377 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1378 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1379 CPUMSetGuestCR4(pVM, val);
1380
1381 CPUMSetGuestCR2(pVM, ASMGetCR2());
1382
1383 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1384 CPUMSetGuestDR7(pVM, val);
1385
1386 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1387 VMX_READ_SELREG(ES, es);
1388 VMX_READ_SELREG(SS, ss);
1389 VMX_READ_SELREG(CS, cs);
1390 VMX_READ_SELREG(DS, ds);
1391 VMX_READ_SELREG(FS, fs);
1392 VMX_READ_SELREG(GS, gs);
1393
1394 /** @note NOW IT'S SAFE FOR LOGGING! */
1395 Log2(("Raw exit reason %08x\n", exitReason));
1396
1397 /* Check if an injected event was interrupted prematurely. */
1398 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1399 AssertRC(rc);
1400 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1401 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1402 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1403 {
1404 Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1405 pVM->hwaccm.s.Event.fPending = true;
1406 /* Error code present? */
1407 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1408 {
1409 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1410 AssertRC(rc);
1411 pVM->hwaccm.s.Event.errCode = val;
1412 }
1413 else
1414 pVM->hwaccm.s.Event.errCode = 0;
1415 }
1416
1417#ifdef VBOX_STRICT
1418 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1419 HWACCMDumpRegs(pCtx);
1420#endif
1421
1422 Log2(("E%d", exitReason));
1423 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1424 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1425 Log2(("Interruption error code %d\n", errCode));
1426 Log2(("IntInfo = %08x\n", intInfo));
1427 Log2(("New EIP=%VGv\n", pCtx->eip));
1428
1429 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1430 switch (exitReason)
1431 {
1432 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1433 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1434 {
1435 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1436
1437 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1438 {
1439 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1440 /* External interrupt; leave to allow it to be dispatched again. */
1441 rc = VINF_EM_RAW_INTERRUPT;
1442 break;
1443 }
1444 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1445 {
1446 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1447 /* External interrupt; leave to allow it to be dispatched again. */
1448 rc = VINF_EM_RAW_INTERRUPT;
1449 break;
1450
1451 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1452 AssertFailed(); /* can't come here; fails the first check. */
1453 break;
1454
1455 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1456 Assert(vector == 3 || vector == 4);
1457 /* no break */
1458 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1459 Log2(("Hardware/software interrupt %d\n", vector));
1460 switch (vector)
1461 {
1462 case X86_XCPT_NM:
1463 {
1464 uint32_t oldCR0;
1465
1466 Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1467
1468 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1469 oldCR0 = ASMGetCR0();
1470 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1471 rc = CPUMHandleLazyFPU(pVM);
1472 if (rc == VINF_SUCCESS)
1473 {
1474 Assert(CPUMIsGuestFPUStateActive(pVM));
1475
1476 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
1477 ASMSetCR0(oldCR0);
1478
1479 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1480
1481 /* Continue execution. */
1482 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1483 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1484
1485 goto ResumeExecution;
1486 }
1487
1488 Log(("Forward #NM fault to the guest\n"));
1489 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1490 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1491 AssertRC(rc);
1492 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1493 goto ResumeExecution;
1494 }
1495
1496 case X86_XCPT_PF: /* Page fault */
1497 {
1498 Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1499 /* Exit qualification contains the linear address of the page fault. */
1500 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1501 TRPMSetErrorCode(pVM, errCode);
1502 TRPMSetFaultAddress(pVM, exitQualification);
1503
1504 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1505 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1506 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1507 if (rc == VINF_SUCCESS)
1508 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1509 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1510 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1511
1512 TRPMResetTrap(pVM);
1513
1514 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1515 goto ResumeExecution;
1516 }
1517 else
1518 if (rc == VINF_EM_RAW_GUEST_TRAP)
1519 { /* A genuine pagefault.
1520 * Forward the trap to the guest by injecting the exception and resuming execution.
1521 */
1522 Log2(("Forward page fault to the guest\n"));
1523 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1524 /* The error code might have been changed. */
1525 errCode = TRPMGetErrorCode(pVM);
1526
1527 TRPMResetTrap(pVM);
1528
1529 /* Now we must update CR2. */
1530 pCtx->cr2 = exitQualification;
1531 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1532 AssertRC(rc);
1533
1534 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1535 goto ResumeExecution;
1536 }
1537#ifdef VBOX_STRICT
1538 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1539 Log2(("PGMTrap0eHandler failed with %d\n", rc));
1540#endif
1541 /* Need to go back to the recompiler to emulate the instruction. */
1542 TRPMResetTrap(pVM);
1543 break;
1544 }
1545
1546 case X86_XCPT_MF: /* Floating point exception. */
1547 {
1548 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1549 if (!(pCtx->cr0 & X86_CR0_NE))
1550 {
1551 /* old style FPU error reporting needs some extra work. */
1552 /** @todo don't fall back to the recompiler, but do it manually. */
1553 rc = VINF_EM_RAW_EMULATE_INSTR;
1554 break;
1555 }
1556 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1557 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1558 AssertRC(rc);
1559
1560 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1561 goto ResumeExecution;
1562 }
1563
1564#ifdef VBOX_STRICT
1565 case X86_XCPT_GP: /* General protection failure exception.*/
1566 case X86_XCPT_UD: /* Unknown opcode exception. */
1567 case X86_XCPT_DE: /* Debug exception. */
1568 case X86_XCPT_SS: /* Stack segment exception. */
1569 case X86_XCPT_NP: /* Segment not present exception. */
1570 {
1571 switch(vector)
1572 {
1573 case X86_XCPT_DE:
1574 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1575 break;
1576 case X86_XCPT_UD:
1577 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1578 break;
1579 case X86_XCPT_SS:
1580 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1581 break;
1582 case X86_XCPT_NP:
1583 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1584 break;
1585 case X86_XCPT_GP:
1586 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1587 break;
1588 }
1589
1590 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1591 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1592 AssertRC(rc);
1593
1594 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1595 goto ResumeExecution;
1596 }
1597#endif
1598 default:
1599 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1600 rc = VERR_EM_INTERNAL_ERROR;
1601 break;
1602 } /* switch (vector) */
1603
1604 break;
1605
1606 default:
1607 rc = VERR_EM_INTERNAL_ERROR;
1608 AssertFailed();
1609 break;
1610 }
1611
1612 break;
1613 }
1614
1615 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1616 /* Clear VM-exit on IF=1 change. */
1617 Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1618 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1619 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1620 AssertRC(rc);
1621 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1622 goto ResumeExecution; /* we check for pending guest interrupts there */
1623
1624 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1625 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1626 /* Skip instruction and continue directly. */
1627 pCtx->eip += cbInstr;
1628 /* Continue execution.*/
1629 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1630 goto ResumeExecution;
1631
1632 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1633 {
1634 Log2(("VMX: Cpuid %x\n", pCtx->eax));
1635 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1636 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1637 if (rc == VINF_SUCCESS)
1638 {
1639 /* Update EIP and continue execution. */
1640 Assert(cbInstr == 2);
1641 pCtx->eip += cbInstr;
1642 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1643 goto ResumeExecution;
1644 }
1645 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1646 rc = VINF_EM_RAW_EMULATE_INSTR;
1647 break;
1648 }
1649
1650 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1651 {
1652 Log2(("VMX: Rdtsc\n"));
1653 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1654 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1655 if (rc == VINF_SUCCESS)
1656 {
1657 /* Update EIP and continue execution. */
1658 Assert(cbInstr == 2);
1659 pCtx->eip += cbInstr;
1660 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1661 goto ResumeExecution;
1662 }
1663 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1664 rc = VINF_EM_RAW_EMULATE_INSTR;
1665 break;
1666 }
1667
1668 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1669 {
1670 Log2(("VMX: invlpg\n"));
1671 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1672 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1673 if (rc == VINF_SUCCESS)
1674 {
1675 /* Update EIP and continue execution. */
1676 pCtx->eip += cbInstr;
1677 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1678 goto ResumeExecution;
1679 }
1680 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1681 break;
1682 }
1683
1684 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1685 {
1686 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1687 {
1688 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1689 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1690 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1691 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1692 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1693 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1694
1695 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1696 {
1697 case 0:
1698 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1699 break;
1700 case 2:
1701 break;
1702 case 3:
1703 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1704 break;
1705 case 4:
1706 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1707 break;
1708 default:
1709 AssertFailed();
1710 }
1711 /* Check if a sync operation is pending. */
1712 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1713 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1714 {
1715 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1716 AssertRC(rc);
1717 }
1718 break;
1719
1720 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1721 Log2(("VMX: mov x, crx\n"));
1722 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1723 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1724 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1725 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1726 break;
1727
1728 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1729 Log2(("VMX: clts\n"));
1730 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1731 rc = EMInterpretCLTS(pVM);
1732 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1733 break;
1734
1735 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1736 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1737 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1738 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1739 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1740 break;
1741 }
1742
1743 /* Update EIP if no error occurred. */
1744 if (VBOX_SUCCESS(rc))
1745 pCtx->eip += cbInstr;
1746
1747 if (rc == VINF_SUCCESS)
1748 {
1749 /* Only resume if successful. */
1750 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1751 goto ResumeExecution;
1752 }
1753 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1754 break;
1755 }
1756
1757 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1758 {
1759 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1760 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1761 {
1762 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1763 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1764 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1765 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1766 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1767 Log2(("DR7=%08x\n", pCtx->dr7));
1768 }
1769 else
1770 {
1771 Log2(("VMX: mov x, drx\n"));
1772 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1773 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1774 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1775 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1776 }
1777 /* Update EIP if no error occurred. */
1778 if (VBOX_SUCCESS(rc))
1779 pCtx->eip += cbInstr;
1780
1781 if (rc == VINF_SUCCESS)
1782 {
1783 /* Only resume if successful. */
1784 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1785 goto ResumeExecution;
1786 }
1787 Assert(rc == VERR_EM_INTERPRETER);
1788 break;
1789 }
1790
1791 /** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1792 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1793 {
1794 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1795 uint32_t uPort;
1796 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1797
1798 /** @todo necessary to make the distinction? */
1799 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1800 {
1801 uPort = pCtx->edx & 0xffff;
1802 }
1803 else
1804 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1805
1806 /* paranoia */
1807 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
1808 {
1809 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1810 break;
1811 }
1812
1813 uint32_t cbSize = aIOSize[uIOWidth];
1814
1815 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1816 {
1817 /* ins/outs */
1818 uint32_t prefix = 0;
1819 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1820 prefix |= PREFIX_REP;
1821
1822 if (fIOWrite)
1823 {
1824 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1825 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1826 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1827 }
1828 else
1829 {
1830 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1831 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1832 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1833 }
1834 }
1835 else
1836 {
1837 /* normal in/out */
1838 uint32_t uAndVal = aIOOpAnd[uIOWidth];
1839
1840 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1841
1842 if (fIOWrite)
1843 {
1844 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1845 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1846 }
1847 else
1848 {
1849 uint32_t u32Val = 0;
1850
1851 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1852 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1853 if (IOM_SUCCESS(rc))
1854 {
1855 /* Write back to the EAX register. */
1856 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1857 }
1858 }
1859 }
1860 /*
1861 * Handled the I/O return codes.
1862 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1863 */
1864 if (IOM_SUCCESS(rc))
1865 {
1866 /* Update EIP and continue execution. */
1867 pCtx->eip += cbInstr;
1868 if (RT_LIKELY(rc == VINF_SUCCESS))
1869 {
1870 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1871 goto ResumeExecution;
1872 }
1873 break;
1874 }
1875
1876#ifdef VBOX_STRICT
1877 if (rc == VINF_IOM_HC_IOPORT_READ)
1878 Assert(!fIOWrite);
1879 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1880 Assert(fIOWrite);
1881 else
1882 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1883#endif
1884 break;
1885 }
1886
1887 default:
1888 /* The rest is handled after syncing the entire CPU state. */
1889 break;
1890 }
1891
1892 /* Note: the guest state isn't entirely synced back at this stage. */
1893
1894 /* Investigate why there was a VM-exit. (part 2) */
1895 switch (exitReason)
1896 {
1897 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1898 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1899 /* Already handled above. */
1900 break;
1901
1902 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1903 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1904 break;
1905
1906 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1907 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1908 rc = VINF_EM_RAW_INTERRUPT;
1909 AssertFailed(); /* Can't happen. Yet. */
1910 break;
1911
1912 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1913 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1914 rc = VINF_EM_RAW_INTERRUPT;
1915 AssertFailed(); /* Can't happen afaik. */
1916 break;
1917
1918 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1919 rc = VERR_EM_INTERPRETER;
1920 break;
1921
1922 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1923 /** Check if external interrupts are pending; if so, don't switch back. */
1924 if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
1925 {
1926 pCtx->eip++; /* skip hlt */
1927 goto ResumeExecution;
1928 }
1929
1930 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1931 break;
1932
1933 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1934 AssertFailed(); /* can't happen. */
1935 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1936 break;
1937
1938 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1939 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1940 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1941 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1942 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1943 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1944 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1945 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1946 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1947 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1948 /** @todo inject #UD immediately */
1949 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1950 break;
1951
1952 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1953 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1954 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1955 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1956 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1957 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1958 /* already handled above */
1959 AssertMsg( rc == VINF_PGM_CHANGE_MODE
1960 || rc == VINF_EM_RAW_INTERRUPT
1961 || rc == VERR_EM_INTERPRETER
1962 || rc == VINF_EM_RAW_EMULATE_INSTR
1963 || rc == VINF_PGM_SYNC_CR3
1964 || rc == VINF_IOM_HC_IOPORT_READ
1965 || rc == VINF_IOM_HC_IOPORT_WRITE
1966 || rc == VINF_EM_RAW_GUEST_TRAP
1967 || rc == VINF_TRPM_XCPT_DISPATCHED
1968 || rc == VINF_EM_RESCHEDULE_REM,
1969 ("rc = %d\n", rc));
1970 break;
1971
1972 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1973 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1974 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1975 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1976 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1977 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1978 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1979 break;
1980
1981 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1982 Assert(rc == VINF_EM_RAW_INTERRUPT);
1983 break;
1984
1985 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1986 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1987 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1988 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1989 default:
1990 rc = VERR_EM_INTERNAL_ERROR;
1991 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1992 break;
1993
1994 }
1995end:
1996 if (fGuestStateSynced)
1997 {
1998 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1999 VMX_READ_SELREG(LDTR, ldtr);
2000 VMX_READ_SELREG(TR, tr);
2001
2002 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2003 pCtx->gdtr.cbGdt = val;
2004 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2005 pCtx->gdtr.pGdt = val;
2006
2007 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2008 pCtx->idtr.cbIdt = val;
2009 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2010 pCtx->idtr.pIdt = val;
2011
2012 /*
2013 * System MSRs
2014 */
2015 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
2016 pCtx->SysEnter.cs = val;
2017 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
2018 pCtx->SysEnter.eip = val;
2019 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
2020 pCtx->SysEnter.esp = val;
2021 }
2022
2023 /* Signal changes for the recompiler. */
2024 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2025
2026 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2027 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2028 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2029 {
2030 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2031 /* On the next entry we'll only sync the host context. */
2032 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2033 }
2034 else
2035 {
2036 /* On the next entry we'll sync everything. */
2037 /** @todo we can do better than this */
2038 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2039 }
2040
2041 /* translate into a less severe return code */
2042 if (rc == VERR_EM_INTERPRETER)
2043 rc = VINF_EM_RAW_EMULATE_INSTR;
2044
2045 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2046 Log2(("X"));
2047 return rc;
2048}
2049
2050
2051/**
2052 * Enters the VT-x session
2053 *
2054 * @returns VBox status code.
2055 * @param pVM The VM to operate on.
2056 */
2057HWACCMR0DECL(int) VMXR0Enter(PVM pVM)
2058{
2059 Assert(pVM->hwaccm.s.vmx.fSupported);
2060
2061 unsigned cr4 = ASMGetCR4();
2062 if (!(cr4 & X86_CR4_VMXE))
2063 {
2064 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2065 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2066 }
2067
2068 /* Activate the VM Control Structure. */
2069 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2070 if (VBOX_FAILURE(rc))
2071 return rc;
2072
2073 pVM->hwaccm.s.vmx.fResumeVM = false;
2074 return VINF_SUCCESS;
2075}
2076
2077
2078/**
2079 * Leaves the VT-x session
2080 *
2081 * @returns VBox status code.
2082 * @param pVM The VM to operate on.
2083 */
2084HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2085{
2086 Assert(pVM->hwaccm.s.vmx.fSupported);
2087
2088 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2089 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2090 AssertRC(rc);
2091
2092 return VINF_SUCCESS;
2093}
2094
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