HWVMXR0.cpp@ 9701

Last change on this file since 9701 was 9535, checked in by vboxsync, 17 years ago
Log guest state in case of failure.
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1	/* $Id: HWVMXR0.cpp 9535 2008-06-09 11:49:52Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/string.h>
41	#include "HWVMXR0.h"
42
43
44	/* IO operation lookup arrays. */
45	static uint32_t aIOSize[4] = {1, 2, 0, 4};
46	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49	static void VMXR0CheckError(PVM pVM, int rc)
50	{
51	if (rc == VERR_VMX_GENERIC)
52	{
53	RTCCUINTREG instrError;
54
55	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57	}
58	pVM->hwaccm.s.lLastError = rc;
59	}
60
61	/**
62	* Sets up and activates VT-x on the current CPU
63	*
64	* @returns VBox status code.
65	* @param pCpu CPU info struct
66	* @param pVM The VM to operate on.
67	* @param pvPageCpu Pointer to the global cpu page
68	* @param pPageCpuPhys Physical address of the global cpu page
69	*/
70	HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71	{
72	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73	AssertReturn(pVM, VERR_INVALID_PARAMETER);
74	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76	/* Setup Intel VMX. */
77	Assert(pVM->hwaccm.s.vmx.fSupported);
78
79	#ifdef LOG_ENABLED
80	SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81	#endif
82	/* Set revision dword at the beginning of the VMXON structure. */
83	(uint32_t )pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86	* (which can have very bad consequences!!!)
87	*/
88
89	/* Make sure the VMX instructions don't cause #UD faults. */
90	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
91
92	/* Enter VMX Root Mode */
93	int rc = VMXEnable(pPageCpuPhys);
94	if (VBOX_FAILURE(rc))
95	{
96	VMXR0CheckError(pVM, rc);
97	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98	return VERR_VMX_VMXON_FAILED;
99	}
100	return VINF_SUCCESS;
101	}
102
103	/**
104	* Deactivates VT-x on the current CPU
105	*
106	* @returns VBox status code.
107	* @param pCpu CPU info struct
108	* @param pvPageCpu Pointer to the global cpu page
109	* @param pPageCpuPhys Physical address of the global cpu page
110	*/
111	HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112	{
113	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116	/* Leave VMX Root Mode. */
117	VMXDisable();
118
119	/* And clear the X86_CR4_VMXE bit */
120	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122	#ifdef LOG_ENABLED
123	SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124	#endif
125	return VINF_SUCCESS;
126	}
127
128	/**
129	* Does Ring-0 per VM VT-x init.
130	*
131	* @returns VBox status code.
132	* @param pVM The VM to operate on.
133	*/
134	HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135	{
136	int rc;
137
138	#ifdef LOG_ENABLED
139	SUPR0Printf("VMXR0InitVM %x\n", pVM);
140	#endif
141
142	/* Allocate one page for the VM control structure (VMCS). */
143	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
144	AssertRC(rc);
145	if (RT_FAILURE(rc))
146	return rc;
147
148	pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
149	pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
150	ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
151
152	/* Allocate one page for the TSS we need for real mode emulation. */
153	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
154	AssertRC(rc);
155	if (RT_FAILURE(rc))
156	return rc;
157
158	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
159	pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
160
161	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
162	* for I/O operations. */
163	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
164	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
165	/* Bit set to 0 means redirection enabled. */
166	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
167
168	#ifdef LOG_ENABLED
169	SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
170	#endif
171	return VINF_SUCCESS;
172	}
173
174	/**
175	* Does Ring-0 per VM VT-x termination.
176	*
177	* @returns VBox status code.
178	* @param pVM The VM to operate on.
179	*/
180	HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
181	{
182	if (pVM->hwaccm.s.vmx.pMemObjVMCS)
183	{
184	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
185	pVM->hwaccm.s.vmx.pMemObjVMCS = 0;
186	pVM->hwaccm.s.vmx.pVMCS = 0;
187	pVM->hwaccm.s.vmx.pVMCSPhys = 0;
188	}
189	if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS)
190	{
191	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
192	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = 0;
193	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
194	pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
195	}
196	return VINF_SUCCESS;
197	}
198
199	/**
200	* Sets up VT-x for the specified VM
201	*
202	* @returns VBox status code.
203	* @param pVM The VM to operate on.
204	*/
205	HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
206	{
207	int rc = VINF_SUCCESS;
208	uint32_t val;
209
210	AssertReturn(pVM, VERR_INVALID_PARAMETER);
211	Assert(pVM->hwaccm.s.vmx.pVMCS);
212
213	/* Set revision dword at the beginning of the VMCS structure. */
214	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
215
216	/* Clear VM Control Structure. */
217	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
218	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
219	if (VBOX_FAILURE(rc))
220	goto vmx_end;
221
222	/* Activate the VM Control Structure. */
223	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
224	if (VBOX_FAILURE(rc))
225	goto vmx_end;
226
227	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
228	* Set required bits to one and zero according to the MSR capabilities.
229	*/
230	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
231	/* External and non-maskable interrupts cause VM-exits. */
232	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
233	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
234
235	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
236	AssertRC(rc);
237
238	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
239	* Set required bits to one and zero according to the MSR capabilities.
240	*/
241	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
242	/* Program which event cause VM-exits and which features we want to use. */
243	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
244	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
245	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
246	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
247	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
248	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
249
250	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
251
252	/*
253	if AMD64 guest mode
254	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
255	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
256	*/
257	#if HC_ARCH_BITS == 64
258	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
259	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
260	#endif
261	/* Mask away the bits that the CPU doesn't support */
262	/** @todo make sure they don't conflict with the above requirements. */
263	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
264	pVM->hwaccm.s.vmx.proc_ctls = val;
265
266	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
267	AssertRC(rc);
268
269	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
270	* Set required bits to one and zero according to the MSR capabilities.
271	*/
272	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
273	AssertRC(rc);
274
275	/* VMX_VMCS_CTRL_EXIT_CONTROLS
276	* Set required bits to one and zero according to the MSR capabilities.
277	*/
278	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
279	#if HC_ARCH_BITS == 64
280	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
281	#else
282	/* else Must be zero when AMD64 is not available. */
283	#endif
284	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
285	/* Don't acknowledge external interrupts on VM-exit. */
286	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
287	AssertRC(rc);
288
289	/* Forward all exception except #NM & #PF to the guest.
290	* We always need to check pagefaults since our shadow page table can be out of sync.
291	* And we always lazily sync the FPU & XMM state.
292	*/
293
294	/*
295	* @todo Possible optimization:
296	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
297	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
298	* registers ourselves of course.
299	*
300	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
301	*/
302	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
303	AssertRC(rc);
304
305	/* Don't filter page faults; all of them should cause a switch. */
306	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
307	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
308	AssertRC(rc);
309
310	/* Init TSC offset to zero. */
311	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
312	#if HC_ARCH_BITS == 32
313	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
314	#endif
315	AssertRC(rc);
316
317	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
318	#if HC_ARCH_BITS == 32
319	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
320	#endif
321	AssertRC(rc);
322
323	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
324	#if HC_ARCH_BITS == 32
325	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
326	#endif
327	AssertRC(rc);
328
329	/* Clear MSR controls. */
330	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
331	{
332	/* Optional */
333	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
334	#if HC_ARCH_BITS == 32
335	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
336	#endif
337	AssertRC(rc);
338	}
339	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
340	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
341	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
342	#if HC_ARCH_BITS == 32
343	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
344	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
345	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
346	#endif
347	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
348	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
349	AssertRC(rc);
350
351	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
352	{
353	/* Optional */
354	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
355	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
356	#if HC_ARCH_BITS == 32
357	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
358	#endif
359	AssertRC(rc);
360	}
361
362	/* Set link pointer to -1. Not currently used. */
363	#if HC_ARCH_BITS == 32
364	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
365	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
366	#else
367	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
368	#endif
369	AssertRC(rc);
370
371	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
372	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
373	AssertRC(rc);
374
375	vmx_end:
376	VMXR0CheckError(pVM, rc);
377	return rc;
378	}
379
380
381	/**
382	* Injects an event (trap or external interrupt)
383	*
384	* @returns VBox status code.
385	* @param pVM The VM to operate on.
386	* @param pCtx CPU Context
387	* @param intInfo VMX interrupt info
388	* @param cbInstr Opcode length of faulting instruction
389	* @param errCode Error code (optional)
390	*/
391	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
392	{
393	int rc;
394
395	#ifdef VBOX_STRICT
396	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
397	if (iGate == 0xE)
398	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
399	else
400	if (iGate < 0x20)
401	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
402	else
403	{
404	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
405	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
406	Assert(pCtx->eflags.u32 & X86_EFL_IF);
407	}
408	#endif
409
410	/* Set event injection state. */
411	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
412	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
413	);
414
415	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
416	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
417
418	AssertRC(rc);
419	return rc;
420	}
421
422
423	/**
424	* Checks for pending guest interrupts and injects them
425	*
426	* @returns VBox status code.
427	* @param pVM The VM to operate on.
428	* @param pCtx CPU Context
429	*/
430	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
431	{
432	int rc;
433
434	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
435	if (pVM->hwaccm.s.Event.fPending)
436	{
437	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
438	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
439	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
440	AssertRC(rc);
441
442	pVM->hwaccm.s.Event.fPending = false;
443	return VINF_SUCCESS;
444	}
445
446	/* When external interrupts are pending, we should exit the VM when IF is set. */
447	if ( !TRPMHasTrap(pVM)
448	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
449	{
450	if (!(pCtx->eflags.u32 & X86_EFL_IF))
451	{
452	Log2(("Enable irq window exit!\n"));
453	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
454	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
455	AssertRC(rc);
456	}
457	else
458	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
459	{
460	uint8_t u8Interrupt;
461
462	rc = PDMGetInterrupt(pVM, &u8Interrupt);
463	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
464	if (VBOX_SUCCESS(rc))
465	{
466	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
467	AssertRC(rc);
468	}
469	else
470	{
471	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
472	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
473	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
474	/* Just continue */
475	}
476	}
477	else
478	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
479	}
480
481	#ifdef VBOX_STRICT
482	if (TRPMHasTrap(pVM))
483	{
484	uint8_t u8Vector;
485	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
486	AssertRC(rc);
487	}
488	#endif
489
490	if ( pCtx->eflags.u32 & X86_EFL_IF
491	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
492	&& TRPMHasTrap(pVM)
493	)
494	{
495	uint8_t u8Vector;
496	int rc;
497	TRPMEVENT enmType;
498	RTGCUINTPTR intInfo;
499	RTGCUINT errCode;
500
501	/* If a new event is pending, then dispatch it now. */
502	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
503	AssertRC(rc);
504	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
505	Assert(enmType != TRPM_SOFTWARE_INT);
506
507	/* Clear the pending trap. */
508	rc = TRPMResetTrap(pVM);
509	AssertRC(rc);
510
511	intInfo = u8Vector;
512	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
513
514	if (enmType == TRPM_TRAP)
515	{
516	switch (u8Vector) {
517	case 8:
518	case 10:
519	case 11:
520	case 12:
521	case 13:
522	case 14:
523	case 17:
524	/* Valid error codes. */
525	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
526	break;
527	default:
528	break;
529	}
530	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
531	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
532	else
533	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
534	}
535	else
536	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
537
538	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
539	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
540	AssertRC(rc);
541	} /* if (interrupts can be dispatched) */
542
543	return VINF_SUCCESS;
544	}
545
546	/**
547	* Save the host state
548	*
549	* @returns VBox status code.
550	* @param pVM The VM to operate on.
551	*/
552	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
553	{
554	int rc = VINF_SUCCESS;
555
556	/*
557	* Host CPU Context
558	*/
559	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
560	{
561	RTIDTR idtr;
562	RTGDTR gdtr;
563	RTSEL SelTR;
564	PX86DESCHC pDesc;
565	uintptr_t trBase;
566
567	/* Control registers */
568	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
569	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
570	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
571	AssertRC(rc);
572	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
573	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
574	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
575
576	/* Selector registers. */
577	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
578	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
579	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
580	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
581	#if HC_ARCH_BITS == 32
582	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
583	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
584	#endif
585	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
586	SelTR = ASMGetTR();
587	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
588	AssertRC(rc);
589	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
590	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
591	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
592	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
593	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
594	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
595	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
596
597	/* GDTR & IDTR */
598	ASMGetGDTR(&gdtr);
599	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
600	ASMGetIDTR(&idtr);
601	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
602	AssertRC(rc);
603	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
604	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
605
606	/* Save the base address of the TR selector. */
607	if (SelTR > gdtr.cbGdt)
608	{
609	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
610	return VERR_VMX_INVALID_HOST_STATE;
611	}
612
613	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
614	#if HC_ARCH_BITS == 64
615	trBase = X86DESC64_BASE(*pDesc);
616	#else
617	trBase = X86DESC_BASE(*pDesc);
618	#endif
619	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
620	AssertRC(rc);
621	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
622
623	/* FS and GS base. */
624	#if HC_ARCH_BITS == 64
625	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
626	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
627	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
628	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
629	#endif
630	AssertRC(rc);
631
632	/* Sysenter MSRs. */
633	/** @todo expensive!! */
634	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
635	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
636	#if HC_ARCH_BITS == 32
637	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
638	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
639	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
640	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
641	#else
642	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
643	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
644	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
645	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
646	#endif
647	AssertRC(rc);
648
649	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
650	}
651	return rc;
652	}
653
654
655	/**
656	* Loads the guest state
657	*
658	* @returns VBox status code.
659	* @param pVM The VM to operate on.
660	* @param pCtx Guest context
661	*/
662	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
663	{
664	int rc = VINF_SUCCESS;
665	RTGCUINTPTR val;
666	X86EFLAGS eflags;
667
668	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
669	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
670	{
671	VMX_WRITE_SELREG(ES, es);
672	AssertRC(rc);
673
674	VMX_WRITE_SELREG(CS, cs);
675	AssertRC(rc);
676
677	VMX_WRITE_SELREG(SS, ss);
678	AssertRC(rc);
679
680	VMX_WRITE_SELREG(DS, ds);
681	AssertRC(rc);
682
683	/* @todo are the hidden base registers in sync with the MSRs? */
684	VMX_WRITE_SELREG(FS, fs);
685	AssertRC(rc);
686
687	VMX_WRITE_SELREG(GS, gs);
688	AssertRC(rc);
689	}
690
691	/* Guest CPU context: LDTR. */
692	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
693	{
694	if (pCtx->ldtr == 0)
695	{
696	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
697	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
698	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
699	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
700	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
701	}
702	else
703	{
704	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
705	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
706	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
707	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
708	}
709	AssertRC(rc);
710	}
711	/* Guest CPU context: TR. */
712	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
713	{
714	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
715
716	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
717	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
718	{
719	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
720	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
721	}
722	else
723	{
724	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
725	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
726	}
727	val = pCtx->trHid.Attr.u;
728
729	/* The TSS selector must be busy. */
730	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
731	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
732	else
733	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
734	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
735
736	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
737	AssertRC(rc);
738	}
739	/* Guest CPU context: GDTR. */
740	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
741	{
742	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
743	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
744	AssertRC(rc);
745	}
746	/* Guest CPU context: IDTR. */
747	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
748	{
749	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
750	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
751	AssertRC(rc);
752	}
753
754	/*
755	* Sysenter MSRs
756	*/
757	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
758	{
759	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
760	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
761	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
762	AssertRC(rc);
763	}
764
765	/* Control registers */
766	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
767	{
768	val = pCtx->cr0;
769	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
770	Log2(("Guest CR0-shadow %08x\n", val));
771	if (CPUMIsGuestFPUStateActive(pVM) == false)
772	{
773	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
774	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
775	}
776	else
777	{
778	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
779	/** @todo check if we support the old style mess correctly. */
780	if (!(val & X86_CR0_NE))
781	{
782	Log(("Forcing X86_CR0_NE!!!\n"));
783
784	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
785	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
786	{
787	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| RT_BIT(X86_XCPT_MF));
788	AssertRC(rc);
789	pVM->hwaccm.s.fFPUOldStyleOverride = true;
790	}
791	}
792
793	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
794	}
795	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
796	val \|= X86_CR0_PE \| X86_CR0_PG;
797	/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
798	val \|= X86_CR0_WP;
799
800	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
801	Log2(("Guest CR0 %08x\n", val));
802	/* CR0 flags owned by the host; if the guests attempts to change them, then
803	* the VM will exit.
804	*/
805	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
806	\| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
807	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
808	\| X86_CR0_TS
809	\| X86_CR0_ET
810	\| X86_CR0_NE
811	\| X86_CR0_MP;
812	pVM->hwaccm.s.vmx.cr0_mask = val;
813
814	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
815	Log2(("Guest CR0-mask %08x\n", val));
816	AssertRC(rc);
817	}
818	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
819	{
820	/* CR4 */
821	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
822	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
823	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
824	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
825	switch(pVM->hwaccm.s.enmShadowMode)
826	{
827	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
828	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
829	case PGMMODE_32_BIT: /* 32-bit paging. */
830	break;
831
832	case PGMMODE_PAE: /* PAE paging. */
833	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
834	/** @todo use normal 32 bits paging */
835	val \|= X86_CR4_PAE;
836	break;
837
838	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
839	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
840	#ifdef VBOX_ENABLE_64_BITS_GUESTS
841	break;
842	#else
843	AssertFailed();
844	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
845	#endif
846	default: /* shut up gcc */
847	AssertFailed();
848	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
849	}
850	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
851	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
852	val \|= X86_CR4_VME;
853
854	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
855	Log2(("Guest CR4 %08x\n", val));
856	/* CR4 flags owned by the host; if the guests attempts to change them, then
857	* the VM will exit.
858	*/
859	val = X86_CR4_PAE
860	\| X86_CR4_PGE
861	\| X86_CR4_PSE
862	\| X86_CR4_VMXE;
863	pVM->hwaccm.s.vmx.cr4_mask = val;
864
865	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
866	Log2(("Guest CR4-mask %08x\n", val));
867	AssertRC(rc);
868	}
869
870	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
871	{
872	/* Save our shadow CR3 register. */
873	val = PGMGetHyperCR3(pVM);
874	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
875	AssertRC(rc);
876	}
877
878	/* Debug registers. */
879	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
880	{
881	/** @todo DR0-6 */
882	val = pCtx->dr7;
883	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
884	val \|= 0x400; /* must be one */
885	#ifdef VBOX_STRICT
886	val = 0x400;
887	#endif
888	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
889	AssertRC(rc);
890
891	/* IA32_DEBUGCTL MSR. */
892	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
893	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
894	AssertRC(rc);
895
896	/** @todo */
897	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
898	AssertRC(rc);
899	}
900
901	/* EIP, ESP and EFLAGS */
902	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
903	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
904	AssertRC(rc);
905
906	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
907	eflags = pCtx->eflags;
908	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
909	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
910
911	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
912	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
913	{
914	eflags.Bits.u1VM = 1;
915	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
916	eflags.Bits.u2IOPL = 3;
917	}
918
919	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
920	AssertRC(rc);
921
922	/** TSC offset. */
923	uint64_t u64TSCOffset;
924
925	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
926	{
927	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
928	#if HC_ARCH_BITS == 64
929	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
930	#else
931	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
932	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
933	#endif
934	AssertRC(rc);
935
936	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
937	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
938	AssertRC(rc);
939	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
940	}
941	else
942	{
943	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
944	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
945	AssertRC(rc);
946	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
947	}
948
949	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
950	* Set required bits to one and zero according to the MSR capabilities.
951	*/
952	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
953	/* 64 bits guest mode? */
954	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
955	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
956	/* else Must be zero when AMD64 is not available. */
957
958	/* Mask away the bits that the CPU doesn't support */
959	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
960	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
961	AssertRC(rc);
962
963	/* 64 bits guest mode? */
964	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
965	{
966	#ifndef VBOX_WITH_64_BITS_GUESTS
967	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
968	#else
969	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
970	#endif
971	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->msrFSBASE);
972	AssertRC(rc);
973	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->msrGSBASE);
974	AssertRC(rc);
975	}
976	else
977	{
978	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
979	}
980
981	/* Done. */
982	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
983
984	return rc;
985	}
986
987	/**
988	* Runs guest code in a VT-x VM.
989	*
990	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
991	*
992	* @returns VBox status code.
993	* @param pVM The VM to operate on.
994	* @param pCtx Guest context
995	* @param pCpu CPU info struct
996	*/
997	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
998	{
999	int rc = VINF_SUCCESS;
1000	RTCCUINTREG val, valShadow;
1001	RTCCUINTREG exitReason, instrError, cbInstr;
1002	RTGCUINTPTR exitQualification;
1003	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1004	RTGCUINTPTR errCode, instrInfo, uInterruptState;
1005	bool fGuestStateSynced = false;
1006	unsigned cResume = 0;
1007
1008	Log2(("\nE"));
1009
1010	AssertReturn(pCpu->fConfigured, VERR_EM_INTERNAL_ERROR);
1011
1012	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1013
1014	#ifdef VBOX_STRICT
1015	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1016	AssertRC(rc);
1017	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1018
1019	/* allowed zero */
1020	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
1021	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1022
1023	/* allowed one */
1024	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
1025	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1026
1027	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1028	AssertRC(rc);
1029	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1030
1031	/* allowed zero */
1032	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
1033	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1034
1035	/* allowed one */
1036	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
1037	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1038
1039	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1040	AssertRC(rc);
1041	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1042
1043	/* allowed zero */
1044	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
1045	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1046
1047	/* allowed one */
1048	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
1049	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1050
1051	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1052	AssertRC(rc);
1053	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1054
1055	/* allowed zero */
1056	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
1057	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1058
1059	/* allowed one */
1060	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
1061	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1062	#endif
1063
1064	#if 0
1065	/*
1066	* Check if debug registers are armed.
1067	*/
1068	uint32_t u32DR7 = ASMGetDR7();
1069	if (u32DR7 & X86_DR7_ENABLED_MASK)
1070	{
1071	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
1072	}
1073	else
1074	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1075	#endif
1076
1077	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1078	*/
1079	ResumeExecution:
1080	/* Safety precaution; looping for too long here can have a very bad effect on the host */
1081	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1082	{
1083	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1084	rc = VINF_EM_RAW_INTERRUPT;
1085	goto end;
1086	}
1087
1088	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1089	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1090	{
1091	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
1092	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
1093	{
1094	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1095	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1096	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1097	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1098	*/
1099	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1100	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1101	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1102	AssertRC(rc);
1103	}
1104	}
1105	else
1106	{
1107	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1108	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1109	AssertRC(rc);
1110	}
1111
1112	/* Check for pending actions that force us to go back to ring 3. */
1113	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
1114	{
1115	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1116	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1117	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1118	rc = VINF_EM_RAW_TO_R3;
1119	goto end;
1120	}
1121	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1122	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1123	{
1124	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1125	rc = VINF_EM_PENDING_REQUEST;
1126	goto end;
1127	}
1128
1129	/* When external interrupts are pending, we should exit the VM when IF is set. */
1130	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
1131	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1132	if (VBOX_FAILURE(rc))
1133	{
1134	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1135	goto end;
1136	}
1137
1138	/** @todo check timers?? */
1139
1140	/* Save the host state first. */
1141	rc = VMXR0SaveHostState(pVM);
1142	if (rc != VINF_SUCCESS)
1143	{
1144	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1145	goto end;
1146	}
1147	/* Load the guest state */
1148	rc = VMXR0LoadGuestState(pVM, pCtx);
1149	if (rc != VINF_SUCCESS)
1150	{
1151	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1152	goto end;
1153	}
1154	fGuestStateSynced = true;
1155
1156	/* Non-register state Guest Context */
1157	/** @todo change me according to cpu state */
1158	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1159	AssertRC(rc);
1160
1161	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1162
1163	/* Manual save and restore:
1164	* - General purpose registers except RIP, RSP
1165	*
1166	* Trashed:
1167	* - CR2 (we don't care)
1168	* - LDTR (reset to 0)
1169	* - DRx (presumably not changed at all)
1170	* - DR7 (reset to 0x400)
1171	* - EFLAGS (reset to RT_BIT(1); not relevant)
1172	*
1173	*/
1174
1175	/* All done! Let's start VM execution. */
1176	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1177	rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1178
1179	/* In case we execute a goto ResumeExecution later on. */
1180	pVM->hwaccm.s.vmx.fResumeVM = true;
1181
1182	/**
1183	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1184	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1185	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1186	*/
1187
1188	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1189	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1190
1191	switch (rc)
1192	{
1193	case VINF_SUCCESS:
1194	break;
1195
1196	case VERR_VMX_INVALID_VMXON_PTR:
1197	AssertFailed();
1198	goto end;
1199
1200	case VERR_VMX_UNABLE_TO_START_VM:
1201	case VERR_VMX_UNABLE_TO_RESUME_VM:
1202	{
1203	#ifdef VBOX_STRICT
1204	int rc1;
1205
1206	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1207	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1208	AssertRC(rc1);
1209	if (rc1 == VINF_SUCCESS)
1210	{
1211	RTGDTR gdtr;
1212	PX86DESCHC pDesc;
1213
1214	ASMGetGDTR(&gdtr);
1215
1216	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1217	Log(("Current stack %08x\n", &rc1));
1218
1219
1220	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1221	Log(("Old eip %VGv new %VGv\n", pCtx->eip, (RTGCPTR)val));
1222	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1223	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1224	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1225	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1226	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1227	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1228	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1229	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1230
1231	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1232	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1233
1234	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1235	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1236
1237	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1238	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1239
1240	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1241	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1242	if (val < gdtr.cbGdt)
1243	{
1244	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1245	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1246	}
1247
1248	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1249	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1250	if (val < gdtr.cbGdt)
1251	{
1252	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1253	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1254	}
1255
1256	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1257	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1258	if (val < gdtr.cbGdt)
1259	{
1260	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1261	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1262	}
1263
1264	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1265	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1266	if (val < gdtr.cbGdt)
1267	{
1268	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1269	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1270	}
1271
1272	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1273	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1274	if (val < gdtr.cbGdt)
1275	{
1276	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1277	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1278	}
1279
1280	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1281	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1282	if (val < gdtr.cbGdt)
1283	{
1284	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1285	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1286	}
1287
1288	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1289	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1290	if (val < gdtr.cbGdt)
1291	{
1292	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1293	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1294	}
1295
1296	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1297	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1298
1299	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1300	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1301	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1302	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1303
1304	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1305	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1306
1307	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1308	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1309
1310	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1311	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1312
1313	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1314	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1315	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1316	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1317
1318	#if HC_ARCH_BITS == 64
1319	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1320	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1321	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1322	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1323	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1324	#endif
1325	}
1326	#endif /* VBOX_STRICT */
1327	goto end;
1328	}
1329
1330	default:
1331	/* impossible */
1332	AssertFailed();
1333	goto end;
1334	}
1335	/* Success. Query the guest state and figure out what has happened. */
1336
1337	/* Investigate why there was a VM-exit. */
1338	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1339	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1340
1341	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1342	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1343	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1344	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1345	intInfo = val;
1346	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1347	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1348	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1349	instrInfo = val;
1350	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1351	exitQualification = val;
1352	AssertRC(rc);
1353
1354	/* Let's first sync back eip, esp, and eflags. */
1355	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1356	AssertRC(rc);
1357	pCtx->rip = val;
1358	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1359	AssertRC(rc);
1360	pCtx->rsp = val;
1361	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1362	AssertRC(rc);
1363	pCtx->eflags.u32 = val;
1364
1365	/* Take care of instruction fusing (sti, mov ss) */
1366	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1367	uInterruptState = val;
1368	if (uInterruptState != 0)
1369	{
1370	Assert(uInterruptState <= 2); /* only sti & mov ss */
1371	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1372	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1373	}
1374	else
1375	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1376
1377	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1378	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1379	{
1380	/* Hide our emulation flags */
1381	pCtx->eflags.Bits.u1VM = 0;
1382	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1383	pCtx->eflags.Bits.u1VIF = 0;
1384	pCtx->eflags.Bits.u2IOPL = 0;
1385	}
1386
1387	/* Control registers. */
1388	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1389	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1390	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1391	CPUMSetGuestCR0(pVM, val);
1392
1393	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1394	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1395	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1396	CPUMSetGuestCR4(pVM, val);
1397
1398	CPUMSetGuestCR2(pVM, ASMGetCR2());
1399
1400	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1401	CPUMSetGuestDR7(pVM, val);
1402
1403	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1404	VMX_READ_SELREG(ES, es);
1405	VMX_READ_SELREG(SS, ss);
1406	VMX_READ_SELREG(CS, cs);
1407	VMX_READ_SELREG(DS, ds);
1408	VMX_READ_SELREG(FS, fs);
1409	VMX_READ_SELREG(GS, gs);
1410
1411	/** @note NOW IT'S SAFE FOR LOGGING! */
1412	Log2(("Raw exit reason %08x\n", exitReason));
1413
1414	/* Check if an injected event was interrupted prematurely. */
1415	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1416	AssertRC(rc);
1417	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1418	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1419	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1420	{
1421	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1422	pVM->hwaccm.s.Event.fPending = true;
1423	/* Error code present? */
1424	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1425	{
1426	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1427	AssertRC(rc);
1428	pVM->hwaccm.s.Event.errCode = val;
1429	}
1430	else
1431	pVM->hwaccm.s.Event.errCode = 0;
1432	}
1433
1434	#ifdef VBOX_STRICT
1435	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1436	HWACCMDumpRegs(pCtx);
1437	#endif
1438
1439	Log2(("E%d", exitReason));
1440	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1441	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1442	Log2(("Interruption error code %d\n", errCode));
1443	Log2(("IntInfo = %08x\n", intInfo));
1444	Log2(("New EIP=%VGv\n", pCtx->eip));
1445
1446	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1447	switch (exitReason)
1448	{
1449	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1450	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1451	{
1452	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1453
1454	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1455	{
1456	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1457	/* External interrupt; leave to allow it to be dispatched again. */
1458	rc = VINF_EM_RAW_INTERRUPT;
1459	break;
1460	}
1461	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1462	{
1463	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1464	/* External interrupt; leave to allow it to be dispatched again. */
1465	rc = VINF_EM_RAW_INTERRUPT;
1466	break;
1467
1468	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1469	AssertFailed(); /* can't come here; fails the first check. */
1470	break;
1471
1472	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1473	Assert(vector == 3 \|\| vector == 4);
1474	/* no break */
1475	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1476	Log2(("Hardware/software interrupt %d\n", vector));
1477	switch (vector)
1478	{
1479	case X86_XCPT_NM:
1480	{
1481	uint32_t oldCR0;
1482
1483	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1484
1485	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1486	oldCR0 = ASMGetCR0();
1487	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1488	rc = CPUMHandleLazyFPU(pVM);
1489	if (rc == VINF_SUCCESS)
1490	{
1491	Assert(CPUMIsGuestFPUStateActive(pVM));
1492
1493	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1494	ASMSetCR0(oldCR0);
1495
1496	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1497
1498	/* Continue execution. */
1499	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1500	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1501
1502	goto ResumeExecution;
1503	}
1504
1505	Log(("Forward #NM fault to the guest\n"));
1506	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1507	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1508	AssertRC(rc);
1509	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1510	goto ResumeExecution;
1511	}
1512
1513	case X86_XCPT_PF: /* Page fault */
1514	{
1515	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1516	/* Exit qualification contains the linear address of the page fault. */
1517	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1518	TRPMSetErrorCode(pVM, errCode);
1519	TRPMSetFaultAddress(pVM, exitQualification);
1520
1521	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1522	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1523	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1524	if (rc == VINF_SUCCESS)
1525	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1526	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1527	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1528
1529	TRPMResetTrap(pVM);
1530
1531	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1532	goto ResumeExecution;
1533	}
1534	else
1535	if (rc == VINF_EM_RAW_GUEST_TRAP)
1536	{ /* A genuine pagefault.
1537	* Forward the trap to the guest by injecting the exception and resuming execution.
1538	*/
1539	Log2(("Forward page fault to the guest\n"));
1540	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1541	/* The error code might have been changed. */
1542	errCode = TRPMGetErrorCode(pVM);
1543
1544	TRPMResetTrap(pVM);
1545
1546	/* Now we must update CR2. */
1547	pCtx->cr2 = exitQualification;
1548	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1549	AssertRC(rc);
1550
1551	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1552	goto ResumeExecution;
1553	}
1554	#ifdef VBOX_STRICT
1555	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1556	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1557	#endif
1558	/* Need to go back to the recompiler to emulate the instruction. */
1559	TRPMResetTrap(pVM);
1560	break;
1561	}
1562
1563	case X86_XCPT_MF: /* Floating point exception. */
1564	{
1565	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1566	if (!(pCtx->cr0 & X86_CR0_NE))
1567	{
1568	/* old style FPU error reporting needs some extra work. */
1569	/** @todo don't fall back to the recompiler, but do it manually. */
1570	rc = VINF_EM_RAW_EMULATE_INSTR;
1571	break;
1572	}
1573	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1574	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1575	AssertRC(rc);
1576
1577	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1578	goto ResumeExecution;
1579	}
1580
1581	#ifdef VBOX_STRICT
1582	case X86_XCPT_GP: /* General protection failure exception.*/
1583	case X86_XCPT_UD: /* Unknown opcode exception. */
1584	case X86_XCPT_DE: /* Debug exception. */
1585	case X86_XCPT_SS: /* Stack segment exception. */
1586	case X86_XCPT_NP: /* Segment not present exception. */
1587	{
1588	switch(vector)
1589	{
1590	case X86_XCPT_DE:
1591	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1592	break;
1593	case X86_XCPT_UD:
1594	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1595	break;
1596	case X86_XCPT_SS:
1597	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1598	break;
1599	case X86_XCPT_NP:
1600	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1601	break;
1602	case X86_XCPT_GP:
1603	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1604	break;
1605	}
1606
1607	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1608	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1609	AssertRC(rc);
1610
1611	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1612	goto ResumeExecution;
1613	}
1614	#endif
1615	default:
1616	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1617	rc = VERR_EM_INTERNAL_ERROR;
1618	break;
1619	} /* switch (vector) */
1620
1621	break;
1622
1623	default:
1624	rc = VERR_EM_INTERNAL_ERROR;
1625	AssertFailed();
1626	break;
1627	}
1628
1629	break;
1630	}
1631
1632	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1633	/* Clear VM-exit on IF=1 change. */
1634	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1635	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1636	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1637	AssertRC(rc);
1638	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1639	goto ResumeExecution; /* we check for pending guest interrupts there */
1640
1641	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1642	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1643	/* Skip instruction and continue directly. */
1644	pCtx->eip += cbInstr;
1645	/* Continue execution.*/
1646	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1647	goto ResumeExecution;
1648
1649	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1650	{
1651	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1652	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1653	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1654	if (rc == VINF_SUCCESS)
1655	{
1656	/* Update EIP and continue execution. */
1657	Assert(cbInstr == 2);
1658	pCtx->eip += cbInstr;
1659	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1660	goto ResumeExecution;
1661	}
1662	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1663	rc = VINF_EM_RAW_EMULATE_INSTR;
1664	break;
1665	}
1666
1667	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1668	{
1669	Log2(("VMX: Rdtsc\n"));
1670	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1671	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1672	if (rc == VINF_SUCCESS)
1673	{
1674	/* Update EIP and continue execution. */
1675	Assert(cbInstr == 2);
1676	pCtx->eip += cbInstr;
1677	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1678	goto ResumeExecution;
1679	}
1680	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1681	rc = VINF_EM_RAW_EMULATE_INSTR;
1682	break;
1683	}
1684
1685	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1686	{
1687	Log2(("VMX: invlpg\n"));
1688	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1689	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1690	if (rc == VINF_SUCCESS)
1691	{
1692	/* Update EIP and continue execution. */
1693	pCtx->eip += cbInstr;
1694	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1695	goto ResumeExecution;
1696	}
1697	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1698	break;
1699	}
1700
1701	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1702	{
1703	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1704	{
1705	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1706	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1707	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1708	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1709	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1710	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1711
1712	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1713	{
1714	case 0:
1715	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1716	break;
1717	case 2:
1718	break;
1719	case 3:
1720	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1721	break;
1722	case 4:
1723	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1724	break;
1725	default:
1726	AssertFailed();
1727	}
1728	/* Check if a sync operation is pending. */
1729	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1730	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1731	{
1732	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1733	AssertRC(rc);
1734	}
1735	break;
1736
1737	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1738	Log2(("VMX: mov x, crx\n"));
1739	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1740	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1741	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1742	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1743	break;
1744
1745	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1746	Log2(("VMX: clts\n"));
1747	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1748	rc = EMInterpretCLTS(pVM);
1749	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1750	break;
1751
1752	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1753	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1754	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1755	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1756	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1757	break;
1758	}
1759
1760	/* Update EIP if no error occurred. */
1761	if (VBOX_SUCCESS(rc))
1762	pCtx->eip += cbInstr;
1763
1764	if (rc == VINF_SUCCESS)
1765	{
1766	/* Only resume if successful. */
1767	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1768	goto ResumeExecution;
1769	}
1770	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1771	break;
1772	}
1773
1774	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1775	{
1776	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1777	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1778	{
1779	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1780	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1781	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1782	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1783	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1784	Log2(("DR7=%08x\n", pCtx->dr7));
1785	}
1786	else
1787	{
1788	Log2(("VMX: mov x, drx\n"));
1789	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1790	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1791	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1792	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1793	}
1794	/* Update EIP if no error occurred. */
1795	if (VBOX_SUCCESS(rc))
1796	pCtx->eip += cbInstr;
1797
1798	if (rc == VINF_SUCCESS)
1799	{
1800	/* Only resume if successful. */
1801	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1802	goto ResumeExecution;
1803	}
1804	Assert(rc == VERR_EM_INTERPRETER);
1805	break;
1806	}
1807
1808	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1809	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1810	{
1811	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1812	uint32_t uPort;
1813	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1814
1815	/** @todo necessary to make the distinction? */
1816	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1817	{
1818	uPort = pCtx->edx & 0xffff;
1819	}
1820	else
1821	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1822
1823	/* paranoia */
1824	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1825	{
1826	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1827	break;
1828	}
1829
1830	uint32_t cbSize = aIOSize[uIOWidth];
1831
1832	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1833	{
1834	/* ins/outs */
1835	uint32_t prefix = 0;
1836	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1837	prefix \|= PREFIX_REP;
1838
1839	if (fIOWrite)
1840	{
1841	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1842	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1843	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1844	}
1845	else
1846	{
1847	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
1848	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1849	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1850	}
1851	}
1852	else
1853	{
1854	/* normal in/out */
1855	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1856
1857	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1858
1859	if (fIOWrite)
1860	{
1861	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1862	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1863	}
1864	else
1865	{
1866	uint32_t u32Val = 0;
1867
1868	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1869	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1870	if (IOM_SUCCESS(rc))
1871	{
1872	/* Write back to the EAX register. */
1873	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1874	}
1875	}
1876	}
1877	/*
1878	* Handled the I/O return codes.
1879	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1880	*/
1881	if (IOM_SUCCESS(rc))
1882	{
1883	/* Update EIP and continue execution. */
1884	pCtx->eip += cbInstr;
1885	if (RT_LIKELY(rc == VINF_SUCCESS))
1886	{
1887	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1888	goto ResumeExecution;
1889	}
1890	break;
1891	}
1892
1893	#ifdef VBOX_STRICT
1894	if (rc == VINF_IOM_HC_IOPORT_READ)
1895	Assert(!fIOWrite);
1896	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1897	Assert(fIOWrite);
1898	else
1899	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1900	#endif
1901	break;
1902	}
1903
1904	default:
1905	/* The rest is handled after syncing the entire CPU state. */
1906	break;
1907	}
1908
1909	/* Note: the guest state isn't entirely synced back at this stage. */
1910
1911	/* Investigate why there was a VM-exit. (part 2) */
1912	switch (exitReason)
1913	{
1914	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1915	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1916	/* Already handled above. */
1917	break;
1918
1919	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1920	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1921	break;
1922
1923	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1924	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1925	rc = VINF_EM_RAW_INTERRUPT;
1926	AssertFailed(); /* Can't happen. Yet. */
1927	break;
1928
1929	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1930	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1931	rc = VINF_EM_RAW_INTERRUPT;
1932	AssertFailed(); /* Can't happen afaik. */
1933	break;
1934
1935	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1936	rc = VERR_EM_INTERPRETER;
1937	break;
1938
1939	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1940	/** Check if external interrupts are pending; if so, don't switch back. */
1941	if ( pCtx->eflags.Bits.u1IF
1942	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1943	{
1944	pCtx->eip++; /* skip hlt */
1945	goto ResumeExecution;
1946	}
1947
1948	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1949	break;
1950
1951	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1952	AssertFailed(); /* can't happen. */
1953	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1954	break;
1955
1956	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1957	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1958	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1959	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1960	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1961	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1962	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1963	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1964	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1965	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1966	/** @todo inject #UD immediately */
1967	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1968	break;
1969
1970	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1971	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1972	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1973	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1974	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1975	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1976	/* already handled above */
1977	AssertMsg( rc == VINF_PGM_CHANGE_MODE
1978	\|\| rc == VINF_EM_RAW_INTERRUPT
1979	\|\| rc == VERR_EM_INTERPRETER
1980	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
1981	\|\| rc == VINF_PGM_SYNC_CR3
1982	\|\| rc == VINF_IOM_HC_IOPORT_READ
1983	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
1984	\|\| rc == VINF_EM_RAW_GUEST_TRAP
1985	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
1986	\|\| rc == VINF_EM_RESCHEDULE_REM,
1987	("rc = %d\n", rc));
1988	break;
1989
1990	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1991	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1992	/* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
1993	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1994	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1995	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1996	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1997	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1998	break;
1999
2000	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2001	Assert(rc == VINF_EM_RAW_INTERRUPT);
2002	break;
2003
2004	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2005	{
2006	#ifdef VBOX_STRICT
2007	Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2008
2009	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2010	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2011
2012	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2013	Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2014
2015	VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2016	Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2017
2018	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2019	Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2020
2021	VMX_LOG_SELREG(CS, "CS");
2022	VMX_LOG_SELREG(DS, "DS");
2023	VMX_LOG_SELREG(ES, "ES");
2024	VMX_LOG_SELREG(FS, "FS");
2025	VMX_LOG_SELREG(GS, "GS");
2026	VMX_LOG_SELREG(SS, "SS");
2027	VMX_LOG_SELREG(TR, "TR");
2028	VMX_LOG_SELREG(LDTR, "LDTR");
2029
2030	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2031	Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2032	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2033	Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2034	#endif /* VBOX_STRICT */
2035	rc = VERR_EM_INTERNAL_ERROR;
2036	break;
2037	}
2038
2039	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2040	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2041	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2042	default:
2043	rc = VERR_EM_INTERNAL_ERROR;
2044	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2045	break;
2046
2047	}
2048	end:
2049	if (fGuestStateSynced)
2050	{
2051	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2052	VMX_READ_SELREG(LDTR, ldtr);
2053	VMX_READ_SELREG(TR, tr);
2054
2055	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2056	pCtx->gdtr.cbGdt = val;
2057	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2058	pCtx->gdtr.pGdt = val;
2059
2060	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2061	pCtx->idtr.cbIdt = val;
2062	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2063	pCtx->idtr.pIdt = val;
2064
2065	/*
2066	* System MSRs
2067	*/
2068	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
2069	pCtx->SysEnter.cs = val;
2070	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
2071	pCtx->SysEnter.eip = val;
2072	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
2073	pCtx->SysEnter.esp = val;
2074
2075	/* 64 bits guest mode? */
2076	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
2077	{
2078	/* Note: we assume that either you can't rely on fs/gs base staying intact when switching in and out of 64 bits mode or that in
2079	* reality it really doesn't matter (as the guest OS restores them manually).
2080	*/
2081	VMXReadVMCS(VMX_VMCS_GUEST_FS_BASE, &val);
2082	pCtx->msrFSBASE = val;
2083	VMXReadVMCS(VMX_VMCS_GUEST_GS_BASE, &val);
2084	pCtx->msrGSBASE = val;
2085	}
2086	}
2087
2088	/* Signal changes for the recompiler. */
2089	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2090
2091	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2092	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2093	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2094	{
2095	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2096	/* On the next entry we'll only sync the host context. */
2097	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2098	}
2099	else
2100	{
2101	/* On the next entry we'll sync everything. */
2102	/** @todo we can do better than this */
2103	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2104	}
2105
2106	/* translate into a less severe return code */
2107	if (rc == VERR_EM_INTERPRETER)
2108	rc = VINF_EM_RAW_EMULATE_INSTR;
2109
2110	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2111	Log2(("X"));
2112	return rc;
2113	}
2114
2115
2116	/**
2117	* Enters the VT-x session
2118	*
2119	* @returns VBox status code.
2120	* @param pVM The VM to operate on.
2121	* @param pCpu CPU info struct
2122	*/
2123	HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2124	{
2125	Assert(pVM->hwaccm.s.vmx.fSupported);
2126
2127	unsigned cr4 = ASMGetCR4();
2128	if (!(cr4 & X86_CR4_VMXE))
2129	{
2130	AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2131	return VERR_VMX_X86_CR4_VMXE_CLEARED;
2132	}
2133
2134	/* Activate the VM Control Structure. */
2135	int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2136	if (VBOX_FAILURE(rc))
2137	return rc;
2138
2139	pVM->hwaccm.s.vmx.fResumeVM = false;
2140	return VINF_SUCCESS;
2141	}
2142
2143
2144	/**
2145	* Leaves the VT-x session
2146	*
2147	* @returns VBox status code.
2148	* @param pVM The VM to operate on.
2149	*/
2150	HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2151	{
2152	Assert(pVM->hwaccm.s.vmx.fSupported);
2153
2154	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2155	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2156	AssertRC(rc);
2157
2158	return VINF_SUCCESS;
2159	}
2160

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 9701

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