VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 9804

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1/* $Id: HWVMXR0.cpp 9804 2008-06-18 16:14:48Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include "HWVMXR0.h"
42
43
44/* IO operation lookup arrays. */
45static uint32_t aIOSize[4] = {1, 2, 0, 4};
46static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49static void VMXR0CheckError(PVM pVM, int rc)
50{
51 if (rc == VERR_VMX_GENERIC)
52 {
53 RTCCUINTREG instrError;
54
55 VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56 pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57 }
58 pVM->hwaccm.s.lLastError = rc;
59}
60
61/**
62 * Sets up and activates VT-x on the current CPU
63 *
64 * @returns VBox status code.
65 * @param pCpu CPU info struct
66 * @param pVM The VM to operate on.
67 * @param pvPageCpu Pointer to the global cpu page
68 * @param pPageCpuPhys Physical address of the global cpu page
69 */
70HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71{
72 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73 AssertReturn(pVM, VERR_INVALID_PARAMETER);
74 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76 /* Setup Intel VMX. */
77 Assert(pVM->hwaccm.s.vmx.fSupported);
78
79#ifdef LOG_ENABLED
80 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81#endif
82 /* Set revision dword at the beginning of the VMXON structure. */
83 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85 /* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86 * (which can have very bad consequences!!!)
87 */
88
89 /* Make sure the VMX instructions don't cause #UD faults. */
90 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
91
92 /* Enter VMX Root Mode */
93 int rc = VMXEnable(pPageCpuPhys);
94 if (VBOX_FAILURE(rc))
95 {
96 VMXR0CheckError(pVM, rc);
97 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98 return VERR_VMX_VMXON_FAILED;
99 }
100 return VINF_SUCCESS;
101}
102
103/**
104 * Deactivates VT-x on the current CPU
105 *
106 * @returns VBox status code.
107 * @param pCpu CPU info struct
108 * @param pvPageCpu Pointer to the global cpu page
109 * @param pPageCpuPhys Physical address of the global cpu page
110 */
111HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112{
113 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116 /* Leave VMX Root Mode. */
117 VMXDisable();
118
119 /* And clear the X86_CR4_VMXE bit */
120 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122#ifdef LOG_ENABLED
123 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124#endif
125 return VINF_SUCCESS;
126}
127
128/**
129 * Does Ring-0 per VM VT-x init.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135{
136 int rc;
137
138#ifdef LOG_ENABLED
139 SUPR0Printf("VMXR0InitVM %x\n", pVM);
140#endif
141
142 /* Allocate one page for the VM control structure (VMCS). */
143 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
144 AssertRC(rc);
145 if (RT_FAILURE(rc))
146 return rc;
147
148 pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
149 pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
150 ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
151
152 /* Allocate one page for the TSS we need for real mode emulation. */
153 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
154 AssertRC(rc);
155 if (RT_FAILURE(rc))
156 return rc;
157
158 pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
159 pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
160
161 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
162 * for I/O operations. */
163 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
164 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
165 /* Bit set to 0 means redirection enabled. */
166 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
167
168#ifdef LOG_ENABLED
169 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
170#endif
171 return VINF_SUCCESS;
172}
173
174/**
175 * Does Ring-0 per VM VT-x termination.
176 *
177 * @returns VBox status code.
178 * @param pVM The VM to operate on.
179 */
180HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
181{
182 if (pVM->hwaccm.s.vmx.pMemObjVMCS)
183 {
184 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
185 pVM->hwaccm.s.vmx.pMemObjVMCS = 0;
186 pVM->hwaccm.s.vmx.pVMCS = 0;
187 pVM->hwaccm.s.vmx.pVMCSPhys = 0;
188 }
189 if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS)
190 {
191 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
192 pVM->hwaccm.s.vmx.pMemObjRealModeTSS = 0;
193 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
194 pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
195 }
196 return VINF_SUCCESS;
197}
198
199/**
200 * Sets up VT-x for the specified VM
201 *
202 * @returns VBox status code.
203 * @param pVM The VM to operate on.
204 */
205HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
206{
207 int rc = VINF_SUCCESS;
208 uint32_t val;
209
210 AssertReturn(pVM, VERR_INVALID_PARAMETER);
211 Assert(pVM->hwaccm.s.vmx.pVMCS);
212
213 /* Set revision dword at the beginning of the VMCS structure. */
214 *(uint32_t *)pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
215
216 /* Clear VM Control Structure. */
217 Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
218 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
219 if (VBOX_FAILURE(rc))
220 goto vmx_end;
221
222 /* Activate the VM Control Structure. */
223 rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
224 if (VBOX_FAILURE(rc))
225 goto vmx_end;
226
227 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
228 * Set required bits to one and zero according to the MSR capabilities.
229 */
230 val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
231 /* External and non-maskable interrupts cause VM-exits. */
232 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
233 val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
234
235 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
236 AssertRC(rc);
237
238 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
239 * Set required bits to one and zero according to the MSR capabilities.
240 */
241 val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
242 /* Program which event cause VM-exits and which features we want to use. */
243 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
244 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
245 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
246 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
247 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
248 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
249
250 /** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
251
252 /*
253 if AMD64 guest mode
254 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
255 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
256 */
257#if HC_ARCH_BITS == 64
258 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
259 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
260#endif
261 /* Mask away the bits that the CPU doesn't support */
262 /** @todo make sure they don't conflict with the above requirements. */
263 val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
264 pVM->hwaccm.s.vmx.proc_ctls = val;
265
266 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
267 AssertRC(rc);
268
269 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
270 * Set required bits to one and zero according to the MSR capabilities.
271 */
272 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
273 AssertRC(rc);
274
275 /* VMX_VMCS_CTRL_EXIT_CONTROLS
276 * Set required bits to one and zero according to the MSR capabilities.
277 */
278 val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
279#if HC_ARCH_BITS == 64
280 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
281#else
282 /* else Must be zero when AMD64 is not available. */
283#endif
284 val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
285 /* Don't acknowledge external interrupts on VM-exit. */
286 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
287 AssertRC(rc);
288
289 /* Forward all exception except #NM & #PF to the guest.
290 * We always need to check pagefaults since our shadow page table can be out of sync.
291 * And we always lazily sync the FPU & XMM state.
292 */
293
294 /*
295 * @todo Possible optimization:
296 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
297 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
298 * registers ourselves of course.
299 *
300 * @note only possible if the current state is actually ours (X86_CR0_TS flag)
301 */
302 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
303 AssertRC(rc);
304
305 /* Don't filter page faults; all of them should cause a switch. */
306 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
307 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
308 AssertRC(rc);
309
310 /* Init TSC offset to zero. */
311 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
312#if HC_ARCH_BITS == 32
313 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
314#endif
315 AssertRC(rc);
316
317 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
318#if HC_ARCH_BITS == 32
319 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
320#endif
321 AssertRC(rc);
322
323 rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
324#if HC_ARCH_BITS == 32
325 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
326#endif
327 AssertRC(rc);
328
329 /* Clear MSR controls. */
330 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
331 {
332 /* Optional */
333 rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
334#if HC_ARCH_BITS == 32
335 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
336#endif
337 AssertRC(rc);
338 }
339 rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
340 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
341 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
342#if HC_ARCH_BITS == 32
343 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
344 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
345 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
346#endif
347 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
348 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
349 AssertRC(rc);
350
351 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
352 {
353 /* Optional */
354 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
355 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
356#if HC_ARCH_BITS == 32
357 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
358#endif
359 AssertRC(rc);
360 }
361
362 /* Set link pointer to -1. Not currently used. */
363#if HC_ARCH_BITS == 32
364 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
365 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
366#else
367 rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
368#endif
369 AssertRC(rc);
370
371 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
372 rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
373 AssertRC(rc);
374
375vmx_end:
376 VMXR0CheckError(pVM, rc);
377 return rc;
378}
379
380
381/**
382 * Injects an event (trap or external interrupt)
383 *
384 * @returns VBox status code.
385 * @param pVM The VM to operate on.
386 * @param pCtx CPU Context
387 * @param intInfo VMX interrupt info
388 * @param cbInstr Opcode length of faulting instruction
389 * @param errCode Error code (optional)
390 */
391static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
392{
393 int rc;
394
395#ifdef VBOX_STRICT
396 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
397 if (iGate == 0xE)
398 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
399 else
400 if (iGate < 0x20)
401 Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
402 else
403 {
404 Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
405 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
406 Assert(pCtx->eflags.u32 & X86_EFL_IF);
407 }
408#endif
409
410 /* Set event injection state. */
411 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
412 intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
413 );
414
415 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
416 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
417
418 AssertRC(rc);
419 return rc;
420}
421
422
423/**
424 * Checks for pending guest interrupts and injects them
425 *
426 * @returns VBox status code.
427 * @param pVM The VM to operate on.
428 * @param pCtx CPU Context
429 */
430static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
431{
432 int rc;
433
434 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
435 if (pVM->hwaccm.s.Event.fPending)
436 {
437 Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
438 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
439 rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
440 AssertRC(rc);
441
442 pVM->hwaccm.s.Event.fPending = false;
443 return VINF_SUCCESS;
444 }
445
446 /* When external interrupts are pending, we should exit the VM when IF is set. */
447 if ( !TRPMHasTrap(pVM)
448 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
449 {
450 if (!(pCtx->eflags.u32 & X86_EFL_IF))
451 {
452 Log2(("Enable irq window exit!\n"));
453 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
454 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
455 AssertRC(rc);
456 }
457 else
458 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
459 {
460 uint8_t u8Interrupt;
461
462 rc = PDMGetInterrupt(pVM, &u8Interrupt);
463 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
464 if (VBOX_SUCCESS(rc))
465 {
466 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
467 AssertRC(rc);
468 }
469 else
470 {
471 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
472 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
473 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
474 /* Just continue */
475 }
476 }
477 else
478 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
479 }
480
481#ifdef VBOX_STRICT
482 if (TRPMHasTrap(pVM))
483 {
484 uint8_t u8Vector;
485 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
486 AssertRC(rc);
487 }
488#endif
489
490 if ( pCtx->eflags.u32 & X86_EFL_IF
491 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
492 && TRPMHasTrap(pVM)
493 )
494 {
495 uint8_t u8Vector;
496 int rc;
497 TRPMEVENT enmType;
498 RTGCUINTPTR intInfo;
499 RTGCUINT errCode;
500
501 /* If a new event is pending, then dispatch it now. */
502 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
503 AssertRC(rc);
504 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
505 Assert(enmType != TRPM_SOFTWARE_INT);
506
507 /* Clear the pending trap. */
508 rc = TRPMResetTrap(pVM);
509 AssertRC(rc);
510
511 intInfo = u8Vector;
512 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
513
514 if (enmType == TRPM_TRAP)
515 {
516 switch (u8Vector) {
517 case 8:
518 case 10:
519 case 11:
520 case 12:
521 case 13:
522 case 14:
523 case 17:
524 /* Valid error codes. */
525 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
526 break;
527 default:
528 break;
529 }
530 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
531 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
532 else
533 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
534 }
535 else
536 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
537
538 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
539 rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
540 AssertRC(rc);
541 } /* if (interrupts can be dispatched) */
542
543 return VINF_SUCCESS;
544}
545
546/**
547 * Save the host state
548 *
549 * @returns VBox status code.
550 * @param pVM The VM to operate on.
551 */
552HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
553{
554 int rc = VINF_SUCCESS;
555
556 /*
557 * Host CPU Context
558 */
559 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
560 {
561 RTIDTR idtr;
562 RTGDTR gdtr;
563 RTSEL SelTR;
564 PX86DESCHC pDesc;
565 uintptr_t trBase;
566
567 /* Control registers */
568 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
569 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
570 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
571 AssertRC(rc);
572 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
573 Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
574 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
575
576 /* Selector registers. */
577 rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
578 /** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
579 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
580 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
581#if HC_ARCH_BITS == 32
582 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
583 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
584#endif
585 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
586 SelTR = ASMGetTR();
587 rc |= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
588 AssertRC(rc);
589 Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
590 Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
591 Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
592 Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
593 Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
594 Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
595 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
596
597 /* GDTR & IDTR */
598 ASMGetGDTR(&gdtr);
599 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
600 ASMGetIDTR(&idtr);
601 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
602 AssertRC(rc);
603 Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
604 Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
605
606 /* Save the base address of the TR selector. */
607 if (SelTR > gdtr.cbGdt)
608 {
609 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
610 return VERR_VMX_INVALID_HOST_STATE;
611 }
612
613 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
614#if HC_ARCH_BITS == 64
615 trBase = X86DESC64_BASE(*pDesc);
616#else
617 trBase = X86DESC_BASE(*pDesc);
618#endif
619 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
620 AssertRC(rc);
621 Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
622
623 /* FS and GS base. */
624#if HC_ARCH_BITS == 64
625 Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
626 Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
627 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
628 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
629#endif
630 AssertRC(rc);
631
632 /* Sysenter MSRs. */
633 /** @todo expensive!! */
634 rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
635 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
636#if HC_ARCH_BITS == 32
637 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
638 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
639 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
640 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
641#else
642 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
643 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
644 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
645 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
646#endif
647 AssertRC(rc);
648
649 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
650 }
651 return rc;
652}
653
654
655/**
656 * Loads the guest state
657 *
658 * @returns VBox status code.
659 * @param pVM The VM to operate on.
660 * @param pCtx Guest context
661 */
662HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
663{
664 int rc = VINF_SUCCESS;
665 RTGCUINTPTR val;
666 X86EFLAGS eflags;
667
668 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
669 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
670 {
671 VMX_WRITE_SELREG(ES, es);
672 AssertRC(rc);
673
674 VMX_WRITE_SELREG(CS, cs);
675 AssertRC(rc);
676
677 VMX_WRITE_SELREG(SS, ss);
678 AssertRC(rc);
679
680 VMX_WRITE_SELREG(DS, ds);
681 AssertRC(rc);
682
683 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
684 if (CPUMIsGuestIn64BitCodeEx(pCtx))
685 {
686 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_FS, pCtx->fs);
687 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_FS_LIMIT, pCtx->fsHid.u32Limit);
688 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
689 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_FS_ACCESS_RIGHTS, pCtx->fsHid.Attr.u);
690 AssertRC(rc);
691
692 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_GS, pCtx->gs);
693 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GS_LIMIT, pCtx->gsHid.u32Limit);
694 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
695 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GS_ACCESS_RIGHTS, pCtx->gsHid.Attr.u);
696 AssertRC(rc);
697 }
698 else
699 {
700 VMX_WRITE_SELREG(FS, fs);
701 AssertRC(rc);
702
703 VMX_WRITE_SELREG(GS, gs);
704 AssertRC(rc);
705 }
706 }
707
708 /* Guest CPU context: LDTR. */
709 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
710 {
711 if (pCtx->ldtr == 0)
712 {
713 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
714 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
715 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
716 /** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
717 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
718 }
719 else
720 {
721 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
722 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
723 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
724 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
725 }
726 AssertRC(rc);
727 }
728 /* Guest CPU context: TR. */
729 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
730 {
731 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
732
733 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
734 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
735 {
736 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
737 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
738 }
739 else
740 {
741 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
742 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
743 }
744 val = pCtx->trHid.Attr.u;
745
746 /* The TSS selector must be busy. */
747 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
748 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
749 else
750 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
751 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
752
753 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
754 AssertRC(rc);
755 }
756 /* Guest CPU context: GDTR. */
757 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
758 {
759 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
760 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
761 AssertRC(rc);
762 }
763 /* Guest CPU context: IDTR. */
764 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
765 {
766 rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
767 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
768 AssertRC(rc);
769 }
770
771 /*
772 * Sysenter MSRs
773 */
774 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
775 {
776 rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
777 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
778 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
779 AssertRC(rc);
780 }
781
782 /* Control registers */
783 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
784 {
785 val = pCtx->cr0;
786 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
787 Log2(("Guest CR0-shadow %08x\n", val));
788 if (CPUMIsGuestFPUStateActive(pVM) == false)
789 {
790 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
791 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
792 }
793 else
794 {
795 Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
796 /** @todo check if we support the old style mess correctly. */
797 if (!(val & X86_CR0_NE))
798 {
799 Log(("Forcing X86_CR0_NE!!!\n"));
800
801 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
802 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
803 {
804 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK | RT_BIT(X86_XCPT_MF));
805 AssertRC(rc);
806 pVM->hwaccm.s.fFPUOldStyleOverride = true;
807 }
808 }
809
810 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
811 }
812 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
813 val |= X86_CR0_PE | X86_CR0_PG;
814 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
815 val |= X86_CR0_WP;
816
817 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
818 Log2(("Guest CR0 %08x\n", val));
819 /* CR0 flags owned by the host; if the guests attempts to change them, then
820 * the VM will exit.
821 */
822 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
823 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
824 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
825 | X86_CR0_TS
826 | X86_CR0_ET
827 | X86_CR0_NE
828 | X86_CR0_MP;
829 pVM->hwaccm.s.vmx.cr0_mask = val;
830
831 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
832 Log2(("Guest CR0-mask %08x\n", val));
833 AssertRC(rc);
834 }
835 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
836 {
837 /* CR4 */
838 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
839 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
840 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
841 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
842 switch(pVM->hwaccm.s.enmShadowMode)
843 {
844 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
845 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
846 case PGMMODE_32_BIT: /* 32-bit paging. */
847 break;
848
849 case PGMMODE_PAE: /* PAE paging. */
850 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
851 /** @todo use normal 32 bits paging */
852 val |= X86_CR4_PAE;
853 break;
854
855 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
856 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
857#ifdef VBOX_ENABLE_64_BITS_GUESTS
858 break;
859#else
860 AssertFailed();
861 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
862#endif
863 default: /* shut up gcc */
864 AssertFailed();
865 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
866 }
867 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
868 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
869 val |= X86_CR4_VME;
870
871 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
872 Log2(("Guest CR4 %08x\n", val));
873 /* CR4 flags owned by the host; if the guests attempts to change them, then
874 * the VM will exit.
875 */
876 val = X86_CR4_PAE
877 | X86_CR4_PGE
878 | X86_CR4_PSE
879 | X86_CR4_VMXE;
880 pVM->hwaccm.s.vmx.cr4_mask = val;
881
882 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
883 Log2(("Guest CR4-mask %08x\n", val));
884 AssertRC(rc);
885 }
886
887 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
888 {
889 /* Save our shadow CR3 register. */
890 val = PGMGetHyperCR3(pVM);
891 rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
892 AssertRC(rc);
893 }
894
895 /* Debug registers. */
896 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
897 {
898 /** @todo DR0-6 */
899 val = pCtx->dr7;
900 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
901 val |= 0x400; /* must be one */
902#ifdef VBOX_STRICT
903 val = 0x400;
904#endif
905 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
906 AssertRC(rc);
907
908 /* IA32_DEBUGCTL MSR. */
909 rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
910 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
911 AssertRC(rc);
912
913 /** @todo */
914 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
915 AssertRC(rc);
916 }
917
918 /* EIP, ESP and EFLAGS */
919 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
920 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
921 AssertRC(rc);
922
923 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
924 eflags = pCtx->eflags;
925 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
926 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
927
928 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
929 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
930 {
931 eflags.Bits.u1VM = 1;
932 eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
933 eflags.Bits.u2IOPL = 3;
934 }
935
936 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
937 AssertRC(rc);
938
939 /** TSC offset. */
940 uint64_t u64TSCOffset;
941
942 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
943 {
944 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
945#if HC_ARCH_BITS == 64
946 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
947#else
948 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
949 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
950#endif
951 AssertRC(rc);
952
953 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
954 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
955 AssertRC(rc);
956 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
957 }
958 else
959 {
960 pVM->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
961 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
962 AssertRC(rc);
963 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
964 }
965
966 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
967 * Set required bits to one and zero according to the MSR capabilities.
968 */
969 val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
970 /* 64 bits guest mode? */
971 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
972 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
973 /* else Must be zero when AMD64 is not available. */
974
975 /* Mask away the bits that the CPU doesn't support */
976 val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
977 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
978 AssertRC(rc);
979
980 /* 64 bits guest mode? */
981 if (CPUMIsGuestIn64BitCodeEx(pCtx))
982 {
983#ifndef VBOX_WITH_64_BITS_GUESTS
984 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
985#else
986 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
987#endif
988 rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->msrFSBASE);
989 AssertRC(rc);
990 rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->msrGSBASE);
991 AssertRC(rc);
992 }
993 else
994 {
995 pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
996 }
997
998 /* Done. */
999 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1000
1001 return rc;
1002}
1003
1004/**
1005 * Runs guest code in a VT-x VM.
1006 *
1007 * @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
1008 *
1009 * @returns VBox status code.
1010 * @param pVM The VM to operate on.
1011 * @param pCtx Guest context
1012 * @param pCpu CPU info struct
1013 */
1014HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx, PHWACCM_CPUINFO pCpu)
1015{
1016 int rc = VINF_SUCCESS;
1017 RTCCUINTREG val, valShadow;
1018 RTCCUINTREG exitReason, instrError, cbInstr;
1019 RTGCUINTPTR exitQualification;
1020 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1021 RTGCUINTPTR errCode, instrInfo, uInterruptState;
1022 bool fGuestStateSynced = false;
1023 unsigned cResume = 0;
1024
1025 Log2(("\nE"));
1026
1027 AssertReturn(pCpu->fConfigured, VERR_EM_INTERNAL_ERROR);
1028
1029 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1030
1031#ifdef VBOX_STRICT
1032 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1033 AssertRC(rc);
1034 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1035
1036 /* allowed zero */
1037 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
1038 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1039
1040 /* allowed one */
1041 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
1042 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1043
1044 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1045 AssertRC(rc);
1046 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1047
1048 /* allowed zero */
1049 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
1050 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1051
1052 /* allowed one */
1053 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
1054 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1055
1056 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1057 AssertRC(rc);
1058 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1059
1060 /* allowed zero */
1061 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
1062 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1063
1064 /* allowed one */
1065 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
1066 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1067
1068 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1069 AssertRC(rc);
1070 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1071
1072 /* allowed zero */
1073 if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
1074 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1075
1076 /* allowed one */
1077 if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
1078 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1079#endif
1080
1081#if 0
1082 /*
1083 * Check if debug registers are armed.
1084 */
1085 uint32_t u32DR7 = ASMGetDR7();
1086 if (u32DR7 & X86_DR7_ENABLED_MASK)
1087 {
1088 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
1089 }
1090 else
1091 pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1092#endif
1093
1094 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1095 */
1096ResumeExecution:
1097 /* Safety precaution; looping for too long here can have a very bad effect on the host */
1098 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1099 {
1100 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1101 rc = VINF_EM_RAW_INTERRUPT;
1102 goto end;
1103 }
1104
1105 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1106 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1107 {
1108 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1109 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1110 {
1111 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1112 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1113 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1114 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1115 */
1116 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1117 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1118 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1119 AssertRC(rc);
1120 }
1121 }
1122 else
1123 {
1124 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
1125 rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1126 AssertRC(rc);
1127 }
1128
1129 /* Check for pending actions that force us to go back to ring 3. */
1130 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
1131 {
1132 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1133 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1134 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1135 rc = VINF_EM_RAW_TO_R3;
1136 goto end;
1137 }
1138 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1139 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1140 {
1141 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1142 rc = VINF_EM_PENDING_REQUEST;
1143 goto end;
1144 }
1145
1146 /* When external interrupts are pending, we should exit the VM when IF is set. */
1147 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
1148 rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1149 if (VBOX_FAILURE(rc))
1150 {
1151 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1152 goto end;
1153 }
1154
1155 /** @todo check timers?? */
1156
1157 /* Save the host state first. */
1158 rc = VMXR0SaveHostState(pVM);
1159 if (rc != VINF_SUCCESS)
1160 {
1161 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1162 goto end;
1163 }
1164 /* Load the guest state */
1165 rc = VMXR0LoadGuestState(pVM, pCtx);
1166 if (rc != VINF_SUCCESS)
1167 {
1168 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1169 goto end;
1170 }
1171 fGuestStateSynced = true;
1172
1173 /* Non-register state Guest Context */
1174 /** @todo change me according to cpu state */
1175 rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1176 AssertRC(rc);
1177
1178 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1179
1180 /* Manual save and restore:
1181 * - General purpose registers except RIP, RSP
1182 *
1183 * Trashed:
1184 * - CR2 (we don't care)
1185 * - LDTR (reset to 0)
1186 * - DRx (presumably not changed at all)
1187 * - DR7 (reset to 0x400)
1188 * - EFLAGS (reset to RT_BIT(1); not relevant)
1189 *
1190 */
1191
1192 /* All done! Let's start VM execution. */
1193 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1194 rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1195
1196 /* In case we execute a goto ResumeExecution later on. */
1197 pVM->hwaccm.s.vmx.fResumeVM = true;
1198
1199 /**
1200 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1201 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1202 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1203 */
1204
1205 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1206 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1207
1208 switch (rc)
1209 {
1210 case VINF_SUCCESS:
1211 break;
1212
1213 case VERR_VMX_INVALID_VMXON_PTR:
1214 AssertFailed();
1215 goto end;
1216
1217 case VERR_VMX_UNABLE_TO_START_VM:
1218 case VERR_VMX_UNABLE_TO_RESUME_VM:
1219 {
1220#ifdef VBOX_STRICT
1221 int rc1;
1222
1223 rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1224 rc1 |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1225 AssertRC(rc1);
1226 if (rc1 == VINF_SUCCESS)
1227 {
1228 RTGDTR gdtr;
1229 PX86DESCHC pDesc;
1230
1231 ASMGetGDTR(&gdtr);
1232
1233 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1234 Log(("Current stack %08x\n", &rc1));
1235
1236
1237 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1238 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1239 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1240 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1241 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1242 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1243 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1244 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1245 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1246 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1247
1248 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1249 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1250
1251 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1252 Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1253
1254 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1255 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1256
1257 VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1258 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1259 if (val < gdtr.cbGdt)
1260 {
1261 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1262 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1263 }
1264
1265 VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1266 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1267 if (val < gdtr.cbGdt)
1268 {
1269 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1270 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1271 }
1272
1273 VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1274 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1275 if (val < gdtr.cbGdt)
1276 {
1277 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1278 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1279 }
1280
1281 VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1282 Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1283 if (val < gdtr.cbGdt)
1284 {
1285 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1286 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1287 }
1288
1289 VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1290 Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1291 if (val < gdtr.cbGdt)
1292 {
1293 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1294 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1295 }
1296
1297 VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1298 Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1299 if (val < gdtr.cbGdt)
1300 {
1301 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1302 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1303 }
1304
1305 VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1306 Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1307 if (val < gdtr.cbGdt)
1308 {
1309 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1310 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1311 }
1312
1313 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1314 Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1315
1316 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1317 Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1318 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1319 Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1320
1321 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1322 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1323
1324 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1325 Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1326
1327 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1328 Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1329
1330 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1331 Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1332 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1333 Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1334
1335#if HC_ARCH_BITS == 64
1336 Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1337 Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1338 Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1339 Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1340 Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1341#endif
1342 }
1343#endif /* VBOX_STRICT */
1344 goto end;
1345 }
1346
1347 default:
1348 /* impossible */
1349 AssertFailed();
1350 goto end;
1351 }
1352 /* Success. Query the guest state and figure out what has happened. */
1353
1354 /* Investigate why there was a VM-exit. */
1355 rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1356 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1357
1358 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1359 rc |= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1360 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1361 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1362 intInfo = val;
1363 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1364 errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1365 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1366 instrInfo = val;
1367 rc |= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1368 exitQualification = val;
1369 AssertRC(rc);
1370
1371 /* Let's first sync back eip, esp, and eflags. */
1372 rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1373 AssertRC(rc);
1374 pCtx->rip = val;
1375 rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1376 AssertRC(rc);
1377 pCtx->rsp = val;
1378 rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1379 AssertRC(rc);
1380 pCtx->eflags.u32 = val;
1381
1382 /* Take care of instruction fusing (sti, mov ss) */
1383 rc |= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1384 uInterruptState = val;
1385 if (uInterruptState != 0)
1386 {
1387 Assert(uInterruptState <= 2); /* only sti & mov ss */
1388 Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1389 EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1390 }
1391 else
1392 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1393
1394 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1395 if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1396 {
1397 /* Hide our emulation flags */
1398 pCtx->eflags.Bits.u1VM = 0;
1399 pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1400 pCtx->eflags.Bits.u1VIF = 0;
1401 pCtx->eflags.Bits.u2IOPL = 0;
1402 }
1403
1404 /* Control registers. */
1405 VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1406 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1407 val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) | (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1408 CPUMSetGuestCR0(pVM, val);
1409
1410 VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1411 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1412 val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) | (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1413 CPUMSetGuestCR4(pVM, val);
1414
1415 CPUMSetGuestCR2(pVM, ASMGetCR2());
1416
1417 VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1418 CPUMSetGuestDR7(pVM, val);
1419
1420 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1421 VMX_READ_SELREG(ES, es);
1422 VMX_READ_SELREG(SS, ss);
1423 VMX_READ_SELREG(CS, cs);
1424 VMX_READ_SELREG(DS, ds);
1425 VMX_READ_SELREG(FS, fs);
1426 VMX_READ_SELREG(GS, gs);
1427
1428 /** @note NOW IT'S SAFE FOR LOGGING! */
1429 Log2(("Raw exit reason %08x\n", exitReason));
1430
1431 /* Check if an injected event was interrupted prematurely. */
1432 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1433 AssertRC(rc);
1434 pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1435 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1436 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1437 {
1438 Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1439 pVM->hwaccm.s.Event.fPending = true;
1440 /* Error code present? */
1441 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1442 {
1443 rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1444 AssertRC(rc);
1445 pVM->hwaccm.s.Event.errCode = val;
1446 }
1447 else
1448 pVM->hwaccm.s.Event.errCode = 0;
1449 }
1450
1451#ifdef VBOX_STRICT
1452 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1453 HWACCMDumpRegs(pCtx);
1454#endif
1455
1456 Log2(("E%d", exitReason));
1457 Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1458 Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1459 Log2(("Interruption error code %d\n", errCode));
1460 Log2(("IntInfo = %08x\n", intInfo));
1461 Log2(("New EIP=%VGv\n", pCtx->rip));
1462
1463 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1464 switch (exitReason)
1465 {
1466 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1467 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1468 {
1469 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1470
1471 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1472 {
1473 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1474 /* External interrupt; leave to allow it to be dispatched again. */
1475 rc = VINF_EM_RAW_INTERRUPT;
1476 break;
1477 }
1478 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1479 {
1480 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1481 /* External interrupt; leave to allow it to be dispatched again. */
1482 rc = VINF_EM_RAW_INTERRUPT;
1483 break;
1484
1485 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1486 AssertFailed(); /* can't come here; fails the first check. */
1487 break;
1488
1489 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1490 Assert(vector == 3 || vector == 4);
1491 /* no break */
1492 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1493 Log2(("Hardware/software interrupt %d\n", vector));
1494 switch (vector)
1495 {
1496 case X86_XCPT_NM:
1497 {
1498 uint32_t oldCR0;
1499
1500 Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1501
1502 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1503 oldCR0 = ASMGetCR0();
1504 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1505 rc = CPUMHandleLazyFPU(pVM);
1506 if (rc == VINF_SUCCESS)
1507 {
1508 Assert(CPUMIsGuestFPUStateActive(pVM));
1509
1510 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
1511 ASMSetCR0(oldCR0);
1512
1513 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1514
1515 /* Continue execution. */
1516 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1517 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1518
1519 goto ResumeExecution;
1520 }
1521
1522 Log(("Forward #NM fault to the guest\n"));
1523 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1524 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1525 AssertRC(rc);
1526 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1527 goto ResumeExecution;
1528 }
1529
1530 case X86_XCPT_PF: /* Page fault */
1531 {
1532 Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1533 /* Exit qualification contains the linear address of the page fault. */
1534 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1535 TRPMSetErrorCode(pVM, errCode);
1536 TRPMSetFaultAddress(pVM, exitQualification);
1537
1538 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1539 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1540 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1541 if (rc == VINF_SUCCESS)
1542 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1543 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1544 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1545
1546 TRPMResetTrap(pVM);
1547
1548 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1549 goto ResumeExecution;
1550 }
1551 else
1552 if (rc == VINF_EM_RAW_GUEST_TRAP)
1553 { /* A genuine pagefault.
1554 * Forward the trap to the guest by injecting the exception and resuming execution.
1555 */
1556 Log2(("Forward page fault to the guest\n"));
1557 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1558 /* The error code might have been changed. */
1559 errCode = TRPMGetErrorCode(pVM);
1560
1561 TRPMResetTrap(pVM);
1562
1563 /* Now we must update CR2. */
1564 pCtx->cr2 = exitQualification;
1565 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1566 AssertRC(rc);
1567
1568 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1569 goto ResumeExecution;
1570 }
1571#ifdef VBOX_STRICT
1572 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1573 Log2(("PGMTrap0eHandler failed with %d\n", rc));
1574#endif
1575 /* Need to go back to the recompiler to emulate the instruction. */
1576 TRPMResetTrap(pVM);
1577 break;
1578 }
1579
1580 case X86_XCPT_MF: /* Floating point exception. */
1581 {
1582 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1583 if (!(pCtx->cr0 & X86_CR0_NE))
1584 {
1585 /* old style FPU error reporting needs some extra work. */
1586 /** @todo don't fall back to the recompiler, but do it manually. */
1587 rc = VINF_EM_RAW_EMULATE_INSTR;
1588 break;
1589 }
1590 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1591 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1592 AssertRC(rc);
1593
1594 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1595 goto ResumeExecution;
1596 }
1597
1598#ifdef VBOX_STRICT
1599 case X86_XCPT_GP: /* General protection failure exception.*/
1600 case X86_XCPT_UD: /* Unknown opcode exception. */
1601 case X86_XCPT_DE: /* Debug exception. */
1602 case X86_XCPT_SS: /* Stack segment exception. */
1603 case X86_XCPT_NP: /* Segment not present exception. */
1604 {
1605 switch(vector)
1606 {
1607 case X86_XCPT_DE:
1608 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1609 break;
1610 case X86_XCPT_UD:
1611 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1612 break;
1613 case X86_XCPT_SS:
1614 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1615 break;
1616 case X86_XCPT_NP:
1617 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1618 break;
1619 case X86_XCPT_GP:
1620 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1621 break;
1622 }
1623
1624 Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1625 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1626 AssertRC(rc);
1627
1628 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1629 goto ResumeExecution;
1630 }
1631#endif
1632 default:
1633 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1634 rc = VERR_EM_INTERNAL_ERROR;
1635 break;
1636 } /* switch (vector) */
1637
1638 break;
1639
1640 default:
1641 rc = VERR_EM_INTERNAL_ERROR;
1642 AssertFailed();
1643 break;
1644 }
1645
1646 break;
1647 }
1648
1649 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1650 /* Clear VM-exit on IF=1 change. */
1651 Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1652 pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1653 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1654 AssertRC(rc);
1655 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1656 goto ResumeExecution; /* we check for pending guest interrupts there */
1657
1658 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1659 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1660 /* Skip instruction and continue directly. */
1661 pCtx->rip += cbInstr;
1662 /* Continue execution.*/
1663 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1664 goto ResumeExecution;
1665
1666 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1667 {
1668 Log2(("VMX: Cpuid %x\n", pCtx->eax));
1669 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1670 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1671 if (rc == VINF_SUCCESS)
1672 {
1673 /* Update EIP and continue execution. */
1674 Assert(cbInstr == 2);
1675 pCtx->rip += cbInstr;
1676 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1677 goto ResumeExecution;
1678 }
1679 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1680 rc = VINF_EM_RAW_EMULATE_INSTR;
1681 break;
1682 }
1683
1684 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1685 {
1686 Log2(("VMX: Rdtsc\n"));
1687 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1688 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1689 if (rc == VINF_SUCCESS)
1690 {
1691 /* Update EIP and continue execution. */
1692 Assert(cbInstr == 2);
1693 pCtx->rip += cbInstr;
1694 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1695 goto ResumeExecution;
1696 }
1697 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1698 rc = VINF_EM_RAW_EMULATE_INSTR;
1699 break;
1700 }
1701
1702 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1703 {
1704 Log2(("VMX: invlpg\n"));
1705 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1706 rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1707 if (rc == VINF_SUCCESS)
1708 {
1709 /* Update EIP and continue execution. */
1710 pCtx->rip += cbInstr;
1711 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1712 goto ResumeExecution;
1713 }
1714 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1715 break;
1716 }
1717
1718 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1719 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1720 {
1721 uint32_t cbSize;
1722
1723 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1724 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1725 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1726 if (rc == VINF_SUCCESS)
1727 {
1728 /* EIP has been updated already. */
1729
1730 /* Only resume if successful. */
1731 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1732 goto ResumeExecution;
1733 }
1734 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1735 break;
1736 }
1737
1738 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1739 {
1740 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1741 {
1742 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1743 Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1744 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1745 rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1746 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1747 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1748
1749 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1750 {
1751 case 0:
1752 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1753 break;
1754 case 2:
1755 break;
1756 case 3:
1757 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1758 break;
1759 case 4:
1760 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1761 break;
1762 default:
1763 AssertFailed();
1764 }
1765 /* Check if a sync operation is pending. */
1766 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1767 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1768 {
1769 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1770 AssertRC(rc);
1771 }
1772 break;
1773
1774 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1775 Log2(("VMX: mov x, crx\n"));
1776 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1777 rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1778 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1779 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1780 break;
1781
1782 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1783 Log2(("VMX: clts\n"));
1784 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1785 rc = EMInterpretCLTS(pVM);
1786 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1787 break;
1788
1789 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1790 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1791 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1792 rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1793 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1794 break;
1795 }
1796
1797 /* Update EIP if no error occurred. */
1798 if (VBOX_SUCCESS(rc))
1799 pCtx->rip += cbInstr;
1800
1801 if (rc == VINF_SUCCESS)
1802 {
1803 /* Only resume if successful. */
1804 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1805 goto ResumeExecution;
1806 }
1807 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1808 break;
1809 }
1810
1811 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1812 {
1813 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1814 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1815 {
1816 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1817 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1818 rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1819 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1820 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1821 Log2(("DR7=%08x\n", pCtx->dr7));
1822 }
1823 else
1824 {
1825 Log2(("VMX: mov x, drx\n"));
1826 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1827 rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1828 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1829 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1830 }
1831 /* Update EIP if no error occurred. */
1832 if (VBOX_SUCCESS(rc))
1833 pCtx->rip += cbInstr;
1834
1835 if (rc == VINF_SUCCESS)
1836 {
1837 /* Only resume if successful. */
1838 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1839 goto ResumeExecution;
1840 }
1841 Assert(rc == VERR_EM_INTERPRETER);
1842 break;
1843 }
1844
1845 /** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1846 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1847 {
1848 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1849 uint32_t uPort;
1850 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1851
1852 /** @todo necessary to make the distinction? */
1853 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1854 {
1855 uPort = pCtx->edx & 0xffff;
1856 }
1857 else
1858 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1859
1860 /* paranoia */
1861 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
1862 {
1863 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1864 break;
1865 }
1866
1867 uint32_t cbSize = aIOSize[uIOWidth];
1868
1869 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1870 {
1871 /* ins/outs */
1872 uint32_t prefix = 0;
1873 if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1874 prefix |= PREFIX_REP;
1875
1876 if (fIOWrite)
1877 {
1878 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1879 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1880 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1881 }
1882 else
1883 {
1884 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1885 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1886 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1887 }
1888 }
1889 else
1890 {
1891 /* normal in/out */
1892 uint32_t uAndVal = aIOOpAnd[uIOWidth];
1893
1894 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1895
1896 if (fIOWrite)
1897 {
1898 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1899 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1900 }
1901 else
1902 {
1903 uint32_t u32Val = 0;
1904
1905 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1906 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1907 if (IOM_SUCCESS(rc))
1908 {
1909 /* Write back to the EAX register. */
1910 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1911 }
1912 }
1913 }
1914 /*
1915 * Handled the I/O return codes.
1916 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1917 */
1918 if (IOM_SUCCESS(rc))
1919 {
1920 /* Update EIP and continue execution. */
1921 pCtx->rip += cbInstr;
1922 if (RT_LIKELY(rc == VINF_SUCCESS))
1923 {
1924 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1925 goto ResumeExecution;
1926 }
1927 break;
1928 }
1929
1930#ifdef VBOX_STRICT
1931 if (rc == VINF_IOM_HC_IOPORT_READ)
1932 Assert(!fIOWrite);
1933 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1934 Assert(fIOWrite);
1935 else
1936 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1937#endif
1938 break;
1939 }
1940
1941 default:
1942 /* The rest is handled after syncing the entire CPU state. */
1943 break;
1944 }
1945
1946 /* Note: the guest state isn't entirely synced back at this stage. */
1947
1948 /* Investigate why there was a VM-exit. (part 2) */
1949 switch (exitReason)
1950 {
1951 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1952 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1953 /* Already handled above. */
1954 break;
1955
1956 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1957 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1958 break;
1959
1960 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1961 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1962 rc = VINF_EM_RAW_INTERRUPT;
1963 AssertFailed(); /* Can't happen. Yet. */
1964 break;
1965
1966 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1967 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1968 rc = VINF_EM_RAW_INTERRUPT;
1969 AssertFailed(); /* Can't happen afaik. */
1970 break;
1971
1972 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1973 rc = VERR_EM_INTERPRETER;
1974 break;
1975
1976 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1977 /** Check if external interrupts are pending; if so, don't switch back. */
1978 if ( pCtx->eflags.Bits.u1IF
1979 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
1980 {
1981 pCtx->rip++; /* skip hlt */
1982 goto ResumeExecution;
1983 }
1984
1985 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1986 break;
1987
1988 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1989 AssertFailed(); /* can't happen. */
1990 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1991 break;
1992
1993 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1994 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1995 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1996 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1997 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1998 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1999 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2000 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2001 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2002 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2003 /** @todo inject #UD immediately */
2004 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2005 break;
2006
2007 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2008 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2009 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2010 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2011 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2012 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2013 /* already handled above */
2014 AssertMsg( rc == VINF_PGM_CHANGE_MODE
2015 || rc == VINF_EM_RAW_INTERRUPT
2016 || rc == VERR_EM_INTERPRETER
2017 || rc == VINF_EM_RAW_EMULATE_INSTR
2018 || rc == VINF_PGM_SYNC_CR3
2019 || rc == VINF_IOM_HC_IOPORT_READ
2020 || rc == VINF_IOM_HC_IOPORT_WRITE
2021 || rc == VINF_EM_RAW_GUEST_TRAP
2022 || rc == VINF_TRPM_XCPT_DISPATCHED
2023 || rc == VINF_EM_RESCHEDULE_REM,
2024 ("rc = %d\n", rc));
2025 break;
2026
2027 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2028 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2029 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2030 rc = VERR_EM_INTERPRETER;
2031 break;
2032
2033 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2034 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2035 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2036 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2037 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2038 break;
2039
2040 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2041 Assert(rc == VINF_EM_RAW_INTERRUPT);
2042 break;
2043
2044 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2045 {
2046#ifdef VBOX_STRICT
2047 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2048
2049 VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2050 Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2051
2052 VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2053 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2054
2055 VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2056 Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2057
2058 VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2059 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2060
2061 VMX_LOG_SELREG(CS, "CS");
2062 VMX_LOG_SELREG(DS, "DS");
2063 VMX_LOG_SELREG(ES, "ES");
2064 VMX_LOG_SELREG(FS, "FS");
2065 VMX_LOG_SELREG(GS, "GS");
2066 VMX_LOG_SELREG(SS, "SS");
2067 VMX_LOG_SELREG(TR, "TR");
2068 VMX_LOG_SELREG(LDTR, "LDTR");
2069
2070 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2071 Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2072 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2073 Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2074#endif /* VBOX_STRICT */
2075 rc = VERR_EM_INTERNAL_ERROR;
2076 break;
2077 }
2078
2079 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2080 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2081 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2082 default:
2083 rc = VERR_EM_INTERNAL_ERROR;
2084 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2085 break;
2086
2087 }
2088end:
2089 if (fGuestStateSynced)
2090 {
2091 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2092 VMX_READ_SELREG(LDTR, ldtr);
2093 VMX_READ_SELREG(TR, tr);
2094
2095 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2096 pCtx->gdtr.cbGdt = val;
2097 VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2098 pCtx->gdtr.pGdt = val;
2099
2100 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2101 pCtx->idtr.cbIdt = val;
2102 VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2103 pCtx->idtr.pIdt = val;
2104
2105 /*
2106 * System MSRs
2107 */
2108 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
2109 pCtx->SysEnter.cs = val;
2110 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
2111 pCtx->SysEnter.eip = val;
2112 VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
2113 pCtx->SysEnter.esp = val;
2114
2115 /* 64 bits guest mode? */
2116 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
2117 {
2118 /* Note: we assume that either you can't rely on fs/gs base staying intact when switching in and out of 64 bits mode or that in
2119 * reality it really doesn't matter (as the guest OS restores them manually).
2120 */
2121 VMXReadVMCS(VMX_VMCS_GUEST_FS_BASE, &val);
2122 pCtx->msrFSBASE = val;
2123 VMXReadVMCS(VMX_VMCS_GUEST_GS_BASE, &val);
2124 pCtx->msrGSBASE = val;
2125 }
2126 }
2127
2128 /* Signal changes for the recompiler. */
2129 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2130
2131 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2132 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2133 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2134 {
2135 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2136 /* On the next entry we'll only sync the host context. */
2137 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2138 }
2139 else
2140 {
2141 /* On the next entry we'll sync everything. */
2142 /** @todo we can do better than this */
2143 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2144 }
2145
2146 /* translate into a less severe return code */
2147 if (rc == VERR_EM_INTERPRETER)
2148 rc = VINF_EM_RAW_EMULATE_INSTR;
2149
2150 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2151 Log2(("X"));
2152 return rc;
2153}
2154
2155
2156/**
2157 * Enters the VT-x session
2158 *
2159 * @returns VBox status code.
2160 * @param pVM The VM to operate on.
2161 * @param pCpu CPU info struct
2162 */
2163HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2164{
2165 Assert(pVM->hwaccm.s.vmx.fSupported);
2166
2167 unsigned cr4 = ASMGetCR4();
2168 if (!(cr4 & X86_CR4_VMXE))
2169 {
2170 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2171 return VERR_VMX_X86_CR4_VMXE_CLEARED;
2172 }
2173
2174 /* Activate the VM Control Structure. */
2175 int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2176 if (VBOX_FAILURE(rc))
2177 return rc;
2178
2179 pVM->hwaccm.s.vmx.fResumeVM = false;
2180 return VINF_SUCCESS;
2181}
2182
2183
2184/**
2185 * Leaves the VT-x session
2186 *
2187 * @returns VBox status code.
2188 * @param pVM The VM to operate on.
2189 */
2190HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2191{
2192 Assert(pVM->hwaccm.s.vmx.fSupported);
2193
2194 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2195 int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2196 AssertRC(rc);
2197
2198 return VINF_SUCCESS;
2199}
2200
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