NEMR0Native-win.cpp@ 72466

Last change on this file since 72466 was 72412, checked in by vboxsync, 7 years ago
NEM/win: More code merging. bugref:9044
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1	/* $Id: NEMR0Native-win.cpp 72412 2018-06-01 14:02:49Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-0 Windows backend.
4	*/
5
6	/*
7	* Copyright (C) 2018 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_NEM
23	#include <iprt/nt/nt.h>
24	#include <iprt/nt/hyperv.h>
25	#include <iprt/nt/vid.h>
26	#include <winerror.h>
27
28	#include <VBox/vmm/nem.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/em.h>
31	#include <VBox/vmm/apic.h>
32	#include <VBox/vmm/pdm.h>
33	#include "NEMInternal.h"
34	#include <VBox/vmm/gvm.h>
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/gvmm.h>
37	#include <VBox/param.h>
38
39	#include <iprt/dbg.h>
40	#include <iprt/memobj.h>
41	#include <iprt/string.h>
42
43
44	/* Assert compile context sanity. */
45	#ifndef RT_OS_WINDOWS
46	# error "Windows only file!"
47	#endif
48	#ifndef RT_ARCH_AMD64
49	# error "AMD64 only file!"
50	#endif
51
52
53	/*********************************************************************************************************************************
54	* Internal Functions *
55	*********************************************************************************************************************************/
56	typedef uint32_t DWORD; /* for winerror.h constants */
57
58
59	/*********************************************************************************************************************************
60	* Global Variables *
61	*********************************************************************************************************************************/
62	static uint64_t (*g_pfnHvlInvokeHypercall)(uint64_t uCallInfo, uint64_t HCPhysInput, uint64_t HCPhysOutput);
63
64	/**
65	* WinHvr.sys!WinHvDepositMemory
66	*
67	* This API will try allocates cPages on IdealNode and deposit it to the
68	* hypervisor for use with the given partition. The memory will be freed when
69	* VID.SYS calls WinHvWithdrawAllMemory when the partition is cleanedup.
70	*
71	* Apparently node numbers above 64 has a different meaning.
72	*/
73	static NTSTATUS (g_pfnWinHvDepositMemory)(uintptr_t idPartition, size_t cPages, uintptr_t IdealNode, size_t pcActuallyAdded);
74
75
76	/*********************************************************************************************************************************
77	* Internal Functions *
78	*********************************************************************************************************************************/
79	NEM_TMPL_STATIC int nemR0WinMapPages(PGVM pGVM, PVM pVM, PGVMCPU pGVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
80	uint32_t cPages, uint32_t fFlags);
81	NEM_TMPL_STATIC int nemR0WinUnmapPages(PGVM pGVM, PGVMCPU pGVCpu, RTGCPHYS GCPhys, uint32_t cPages);
82	NEM_TMPL_STATIC int nemR0WinExportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx);
83	NEM_TMPL_STATIC int nemR0WinImportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx, uint64_t fWhat);
84	DECLINLINE(NTSTATUS) nemR0NtPerformIoControl(PGVM pGVM, uint32_t uFunction, void *pvInput, uint32_t cbInput,
85	void *pvOutput, uint32_t cbOutput);
86
87
88	/*
89	* Instantate the code we share with ring-0.
90	*/
91	#include "../VMMAll/NEMAllNativeTemplate-win.cpp.h"
92
93	/**
94	* Worker for NEMR0InitVM that allocates a hypercall page.
95	*
96	* @returns VBox status code.
97	* @param pHypercallData The hypercall data page to initialize.
98	*/
99	static int nemR0InitHypercallData(PNEMR0HYPERCALLDATA pHypercallData)
100	{
101	int rc = RTR0MemObjAllocPage(&pHypercallData->hMemObj, PAGE_SIZE, false /fExecutable/);
102	if (RT_SUCCESS(rc))
103	{
104	pHypercallData->HCPhysPage = RTR0MemObjGetPagePhysAddr(pHypercallData->hMemObj, 0 /iPage/);
105	AssertStmt(pHypercallData->HCPhysPage != NIL_RTHCPHYS, rc = VERR_INTERNAL_ERROR_3);
106	pHypercallData->pbPage = (uint8_t *)RTR0MemObjAddress(pHypercallData->hMemObj);
107	AssertStmt(pHypercallData->pbPage, rc = VERR_INTERNAL_ERROR_3);
108	if (RT_SUCCESS(rc))
109	return VINF_SUCCESS;
110
111	/* bail out */
112	RTR0MemObjFree(pHypercallData->hMemObj, true /fFreeMappings/);
113	}
114	pHypercallData->hMemObj = NIL_RTR0MEMOBJ;
115	pHypercallData->HCPhysPage = NIL_RTHCPHYS;
116	pHypercallData->pbPage = NULL;
117	return rc;
118	}
119
120	/**
121	* Worker for NEMR0CleanupVM and NEMR0InitVM that cleans up a hypercall page.
122	*
123	* @param pHypercallData The hypercall data page to uninitialize.
124	*/
125	static void nemR0DeleteHypercallData(PNEMR0HYPERCALLDATA pHypercallData)
126	{
127	/* Check pbPage here since it's NULL, whereas the hMemObj can be either
128	NIL_RTR0MEMOBJ or 0 (they aren't necessarily the same). */
129	if (pHypercallData->pbPage != NULL)
130	{
131	RTR0MemObjFree(pHypercallData->hMemObj, true /fFreeMappings/);
132	pHypercallData->pbPage = NULL;
133	}
134	pHypercallData->hMemObj = NIL_RTR0MEMOBJ;
135	pHypercallData->HCPhysPage = NIL_RTHCPHYS;
136	}
137
138
139	/**
140	* Called by NEMR3Init to make sure we've got what we need.
141	*
142	* @returns VBox status code.
143	* @param pGVM The ring-0 VM handle.
144	* @param pVM The cross context VM handle.
145	* @thread EMT(0)
146	*/
147	VMMR0_INT_DECL(int) NEMR0InitVM(PGVM pGVM, PVM pVM)
148	{
149	AssertCompile(sizeof(pGVM->nem.s) <= sizeof(pGVM->nem.padding));
150	AssertCompile(sizeof(pGVM->aCpus[0].nem.s) <= sizeof(pGVM->aCpus[0].nem.padding));
151
152	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, 0);
153	AssertRCReturn(rc, rc);
154
155	/*
156	* We want to perform hypercalls here. The NT kernel started to expose a very low
157	* level interface to do this thru somewhere between build 14271 and 16299. Since
158	* we need build 17134 to get anywhere at all, the exact build is not relevant here.
159	*
160	* We also need to deposit memory to the hypervisor for use with partition (page
161	* mapping structures, stuff).
162	*/
163	RTDBGKRNLINFO hKrnlInfo;
164	rc = RTR0DbgKrnlInfoOpen(&hKrnlInfo, 0);
165	if (RT_SUCCESS(rc))
166	{
167	rc = RTR0DbgKrnlInfoQuerySymbol(hKrnlInfo, NULL, "HvlInvokeHypercall", (void **)&g_pfnHvlInvokeHypercall);
168	if (RT_SUCCESS(rc))
169	rc = RTR0DbgKrnlInfoQuerySymbol(hKrnlInfo, "winhvr.sys", "WinHvDepositMemory", (void **)&g_pfnWinHvDepositMemory);
170	RTR0DbgKrnlInfoRelease(hKrnlInfo);
171	if (RT_SUCCESS(rc))
172	{
173	/*
174	* Allocate a page for non-EMT threads to use for hypercalls (update
175	* statistics and such) and a critical section protecting it.
176	*/
177	rc = RTCritSectInit(&pGVM->nem.s.HypercallDataCritSect);
178	if (RT_SUCCESS(rc))
179	{
180	rc = nemR0InitHypercallData(&pGVM->nem.s.HypercallData);
181	if (RT_SUCCESS(rc))
182	{
183	/*
184	* Allocate a page for each VCPU to place hypercall data on.
185	*/
186	for (VMCPUID i = 0; i < pGVM->cCpus; i++)
187	{
188	rc = nemR0InitHypercallData(&pGVM->aCpus[i].nem.s.HypercallData);
189	if (RT_FAILURE(rc))
190	{
191	while (i-- > 0)
192	nemR0DeleteHypercallData(&pGVM->aCpus[i].nem.s.HypercallData);
193	break;
194	}
195	}
196	if (RT_SUCCESS(rc))
197	{
198	/*
199	* So far, so good.
200	*/
201	return rc;
202	}
203
204	/*
205	* Bail out.
206	*/
207	nemR0DeleteHypercallData(&pGVM->nem.s.HypercallData);
208	}
209	RTCritSectDelete(&pGVM->nem.s.HypercallDataCritSect);
210	}
211	}
212	else
213	rc = VERR_NEM_MISSING_KERNEL_API;
214	}
215
216	RT_NOREF(pVM);
217	return rc;
218	}
219
220
221	/**
222	* Perform an I/O control operation on the partition handle (VID.SYS).
223	*
224	* @returns NT status code.
225	* @param pGVM The ring-0 VM structure.
226	* @param uFunction The function to perform.
227	* @param pvInput The input buffer. This must point within the VM
228	* structure so we can easily convert to a ring-3
229	* pointer if necessary.
230	* @param cbInput The size of the input. @a pvInput must be NULL when
231	* zero.
232	* @param pvOutput The output buffer. This must also point within the
233	* VM structure for ring-3 pointer magic.
234	* @param cbOutput The size of the output. @a pvOutput must be NULL
235	* when zero.
236	*/
237	DECLINLINE(NTSTATUS) nemR0NtPerformIoControl(PGVM pGVM, uint32_t uFunction, void *pvInput, uint32_t cbInput,
238	void *pvOutput, uint32_t cbOutput)
239	{
240	#ifdef RT_STRICT
241	/*
242	* Input and output parameters are part of the VM CPU structure.
243	*/
244	PVM pVM = pGVM->pVM;
245	size_t const cbVM = RT_UOFFSETOF(VM, aCpus[pGVM->cCpus]);
246	if (pvInput)
247	AssertReturn(((uintptr_t)pvInput + cbInput) - (uintptr_t)pVM <= cbVM, VERR_INVALID_PARAMETER);
248	if (pvOutput)
249	AssertReturn(((uintptr_t)pvOutput + cbOutput) - (uintptr_t)pVM <= cbVM, VERR_INVALID_PARAMETER);
250	#endif
251
252	int32_t rcNt = STATUS_UNSUCCESSFUL;
253	int rc = SUPR0IoCtlPerform(pGVM->nem.s.pIoCtlCtx, uFunction,
254	pvInput,
255	pvInput ? (uintptr_t)pvInput + pGVM->nem.s.offRing3ConversionDelta : NIL_RTR3PTR,
256	cbInput,
257	pvOutput,
258	pvOutput ? (uintptr_t)pvOutput + pGVM->nem.s.offRing3ConversionDelta : NIL_RTR3PTR,
259	cbOutput,
260	&rcNt);
261	if (RT_SUCCESS(rc) \|\| !NT_SUCCESS((NTSTATUS)rcNt))
262	return (NTSTATUS)rcNt;
263	return STATUS_UNSUCCESSFUL;
264	}
265
266
267	/**
268	* 2nd part of the initialization, after we've got a partition handle.
269	*
270	* @returns VBox status code.
271	* @param pGVM The ring-0 VM handle.
272	* @param pVM The cross context VM handle.
273	* @thread EMT(0)
274	*/
275	VMMR0_INT_DECL(int) NEMR0InitVMPart2(PGVM pGVM, PVM pVM)
276	{
277	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, 0);
278	AssertRCReturn(rc, rc);
279	SUPR0Printf("NEMR0InitVMPart2\n"); LogRel(("2: NEMR0InitVMPart2\n"));
280
281	/*
282	* Copy and validate the I/O control information from ring-3.
283	*/
284	NEMWINIOCTL Copy = pVM->nem.s.IoCtlGetHvPartitionId;
285	AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
286	AssertLogRelReturn(Copy.cbInput == 0, VERR_NEM_INIT_FAILED);
287	AssertLogRelReturn(Copy.cbOutput == sizeof(HV_PARTITION_ID), VERR_NEM_INIT_FAILED);
288	pGVM->nem.s.IoCtlGetHvPartitionId = Copy;
289
290	Copy = pVM->nem.s.IoCtlStartVirtualProcessor;
291	AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
292	AssertLogRelReturn(Copy.cbInput == sizeof(HV_VP_INDEX), VERR_NEM_INIT_FAILED);
293	AssertLogRelReturn(Copy.cbOutput == 0, VERR_NEM_INIT_FAILED);
294	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, VERR_NEM_INIT_FAILED);
295	pGVM->nem.s.IoCtlStartVirtualProcessor = Copy;
296
297	Copy = pVM->nem.s.IoCtlStopVirtualProcessor;
298	AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
299	AssertLogRelReturn(Copy.cbInput == sizeof(HV_VP_INDEX), VERR_NEM_INIT_FAILED);
300	AssertLogRelReturn(Copy.cbOutput == 0, VERR_NEM_INIT_FAILED);
301	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, VERR_NEM_INIT_FAILED);
302	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlStartVirtualProcessor.uFunction, VERR_NEM_INIT_FAILED);
303	pGVM->nem.s.IoCtlStopVirtualProcessor = Copy;
304
305	Copy = pVM->nem.s.IoCtlMessageSlotHandleAndGetNext;
306	AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
307	AssertLogRelReturn(Copy.cbInput == sizeof(VID_IOCTL_INPUT_MESSAGE_SLOT_HANDLE_AND_GET_NEXT), VERR_NEM_INIT_FAILED);
308	AssertLogRelReturn(Copy.cbOutput == 0, VERR_NEM_INIT_FAILED);
309	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, VERR_NEM_INIT_FAILED);
310	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlStartVirtualProcessor.uFunction, VERR_NEM_INIT_FAILED);
311	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlStopVirtualProcessor.uFunction, VERR_NEM_INIT_FAILED);
312	pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext = Copy;
313
314	/*
315	* Setup of an I/O control context for the partition handle for later use.
316	*/
317	rc = SUPR0IoCtlSetupForHandle(pGVM->pSession, pVM->nem.s.hPartitionDevice, 0, &pGVM->nem.s.pIoCtlCtx);
318	AssertLogRelRCReturn(rc, rc);
319	pGVM->nem.s.offRing3ConversionDelta = (uintptr_t)pVM->pVMR3 - (uintptr_t)pGVM->pVM;
320
321	/*
322	* Get the partition ID.
323	*/
324	PVMCPU pVCpu = &pGVM->pVM->aCpus[0];
325	NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, NULL, 0,
326	&pVCpu->nem.s.uIoCtlBuf.idPartition, sizeof(pVCpu->nem.s.uIoCtlBuf.idPartition));
327	AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("IoCtlGetHvPartitionId failed: %#x\n", rcNt), VERR_NEM_INIT_FAILED);
328	pGVM->nem.s.idHvPartition = pVCpu->nem.s.uIoCtlBuf.idPartition;
329	AssertLogRelMsgReturn(pGVM->nem.s.idHvPartition == pVM->nem.s.idHvPartition,
330	("idHvPartition mismatch: r0=%#RX64, r3=%#RX64\n", pGVM->nem.s.idHvPartition, pVM->nem.s.idHvPartition),
331	VERR_NEM_INIT_FAILED);
332
333
334	return rc;
335	}
336
337
338	/**
339	* Cleanup the NEM parts of the VM in ring-0.
340	*
341	* This is always called and must deal the state regardless of whether
342	* NEMR0InitVM() was called or not. So, take care here.
343	*
344	* @param pGVM The ring-0 VM handle.
345	*/
346	VMMR0_INT_DECL(void) NEMR0CleanupVM(PGVM pGVM)
347	{
348	pGVM->nem.s.idHvPartition = HV_PARTITION_ID_INVALID;
349
350	/* Clean up I/O control context. */
351	if (pGVM->nem.s.pIoCtlCtx)
352	{
353	int rc = SUPR0IoCtlCleanup(pGVM->nem.s.pIoCtlCtx);
354	AssertRC(rc);
355	pGVM->nem.s.pIoCtlCtx = NULL;
356	}
357
358	/* Free the hypercall pages. */
359	VMCPUID i = pGVM->cCpus;
360	while (i-- > 0)
361	nemR0DeleteHypercallData(&pGVM->aCpus[i].nem.s.HypercallData);
362
363	/* The non-EMT one too. */
364	if (RTCritSectIsInitialized(&pGVM->nem.s.HypercallDataCritSect))
365	RTCritSectDelete(&pGVM->nem.s.HypercallDataCritSect);
366	nemR0DeleteHypercallData(&pGVM->nem.s.HypercallData);
367	}
368
369
370	#if 0 /* for debugging GPA unmapping. */
371	static int nemR3WinDummyReadGpa(PGVM pGVM, PGVMCPU pGVCpu, RTGCPHYS GCPhys)
372	{
373	PHV_INPUT_READ_GPA pIn = (PHV_INPUT_READ_GPA)pGVCpu->nem.s.pbHypercallData;
374	PHV_OUTPUT_READ_GPA pOut = (PHV_OUTPUT_READ_GPA)(pIn + 1);
375	pIn->PartitionId = pGVM->nem.s.idHvPartition;
376	pIn->VpIndex = pGVCpu->idCpu;
377	pIn->ByteCount = 0x10;
378	pIn->BaseGpa = GCPhys;
379	pIn->ControlFlags.AsUINT64 = 0;
380	pIn->ControlFlags.CacheType = HvCacheTypeX64WriteCombining;
381	memset(pOut, 0xfe, sizeof(*pOut));
382	uint64_t volatile uResult = g_pfnHvlInvokeHypercall(HvCallReadGpa, pGVCpu->nem.s.HCPhysHypercallData,
383	pGVCpu->nem.s.HCPhysHypercallData + sizeof(*pIn));
384	LogRel(("nemR3WinDummyReadGpa: %RGp -> %#RX64; code=%u rsvd=%u abData=%.16Rhxs\n",
385	GCPhys, uResult, pOut->AccessResult.ResultCode, pOut->AccessResult.Reserved, pOut->Data));
386	__debugbreak();
387
388	return uResult != 0 ? VERR_READ_ERROR : VINF_SUCCESS;
389	}
390	#endif
391
392
393	/**
394	* Worker for NEMR0MapPages and others.
395	*/
396	NEM_TMPL_STATIC int nemR0WinMapPages(PGVM pGVM, PVM pVM, PGVMCPU pGVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
397	uint32_t cPages, uint32_t fFlags)
398	{
399	/*
400	* Validate.
401	*/
402	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
403
404	AssertReturn(cPages > 0, VERR_OUT_OF_RANGE);
405	AssertReturn(cPages <= NEM_MAX_MAP_PAGES, VERR_OUT_OF_RANGE);
406	AssertReturn(!(fFlags & ~(HV_MAP_GPA_MAYBE_ACCESS_MASK & ~HV_MAP_GPA_DUNNO_ACCESS)), VERR_INVALID_FLAGS);
407	AssertMsgReturn(!(GCPhysDst & X86_PAGE_OFFSET_MASK), ("GCPhysDst=%RGp\n", GCPhysDst), VERR_OUT_OF_RANGE);
408	AssertReturn(GCPhysDst < _1E, VERR_OUT_OF_RANGE);
409	if (GCPhysSrc != GCPhysDst)
410	{
411	AssertMsgReturn(!(GCPhysSrc & X86_PAGE_OFFSET_MASK), ("GCPhysSrc=%RGp\n", GCPhysSrc), VERR_OUT_OF_RANGE);
412	AssertReturn(GCPhysSrc < _1E, VERR_OUT_OF_RANGE);
413	}
414
415	/*
416	* Compose and make the hypercall.
417	* Ring-3 is not allowed to fill in the host physical addresses of the call.
418	*/
419	for (uint32_t iTries = 0;; iTries++)
420	{
421	HV_INPUT_MAP_GPA_PAGES pMapPages = (HV_INPUT_MAP_GPA_PAGES )pGVCpu->nem.s.HypercallData.pbPage;
422	AssertPtrReturn(pMapPages, VERR_INTERNAL_ERROR_3);
423	pMapPages->TargetPartitionId = pGVM->nem.s.idHvPartition;
424	pMapPages->TargetGpaBase = GCPhysDst >> X86_PAGE_SHIFT;
425	pMapPages->MapFlags = fFlags;
426	pMapPages->u32ExplicitPadding = 0;
427	for (uint32_t iPage = 0; iPage < cPages; iPage++, GCPhysSrc += X86_PAGE_SIZE)
428	{
429	RTHCPHYS HCPhys = NIL_RTGCPHYS;
430	int rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysSrc, &HCPhys);
431	AssertRCReturn(rc, rc);
432	pMapPages->PageList[iPage] = HCPhys >> X86_PAGE_SHIFT;
433	}
434
435	uint64_t uResult = g_pfnHvlInvokeHypercall(HvCallMapGpaPages \| ((uint64_t)cPages << 32),
436	pGVCpu->nem.s.HypercallData.HCPhysPage, 0);
437	Log6(("NEMR0MapPages: %RGp/%RGp L %u prot %#x -> %#RX64\n",
438	GCPhysDst, GCPhysSrc - cPages * X86_PAGE_SIZE, cPages, fFlags, uResult));
439	if (uResult == ((uint64_t)cPages << 32))
440	return VINF_SUCCESS;
441
442	/*
443	* If the partition is out of memory, try donate another 512 pages to
444	* it (2MB). VID.SYS does multiples of 512 pages, nothing smaller.
445	*/
446	if ( uResult != HV_STATUS_INSUFFICIENT_MEMORY
447	\|\| iTries > 16
448	\|\| g_pfnWinHvDepositMemory == NULL)
449	{
450	LogRel(("g_pfnHvlInvokeHypercall/MapGpaPages -> %#RX64\n", uResult));
451	return VERR_NEM_MAP_PAGES_FAILED;
452	}
453
454	size_t cPagesAdded = 0;
455	NTSTATUS rcNt = g_pfnWinHvDepositMemory(pGVM->nem.s.idHvPartition, 512, 0, &cPagesAdded);
456	if (!cPagesAdded)
457	{
458	LogRel(("g_pfnWinHvDepositMemory -> %#x / %#RX64\n", rcNt, uResult));
459	return VERR_NEM_MAP_PAGES_FAILED;
460	}
461	}
462	}
463
464
465	/**
466	* Maps pages into the guest physical address space.
467	*
468	* Generally the caller will be under the PGM lock already, so no extra effort
469	* is needed to make sure all changes happens under it.
470	*
471	* @returns VBox status code.
472	* @param pGVM The ring-0 VM handle.
473	* @param pVM The cross context VM handle.
474	* @param idCpu The calling EMT. Necessary for getting the
475	* hypercall page and arguments.
476	* @thread EMT(idCpu)
477	*/
478	VMMR0_INT_DECL(int) NEMR0MapPages(PGVM pGVM, PVM pVM, VMCPUID idCpu)
479	{
480	/*
481	* Unpack the call.
482	*/
483	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
484	if (RT_SUCCESS(rc))
485	{
486	PVMCPU pVCpu = &pVM->aCpus[idCpu];
487	PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
488
489	RTGCPHYS const GCPhysSrc = pVCpu->nem.s.Hypercall.MapPages.GCPhysSrc;
490	RTGCPHYS const GCPhysDst = pVCpu->nem.s.Hypercall.MapPages.GCPhysDst;
491	uint32_t const cPages = pVCpu->nem.s.Hypercall.MapPages.cPages;
492	HV_MAP_GPA_FLAGS const fFlags = pVCpu->nem.s.Hypercall.MapPages.fFlags;
493
494	/*
495	* Do the work.
496	*/
497	rc = nemR0WinMapPages(pGVM, pVM, pGVCpu, GCPhysSrc, GCPhysDst, cPages, fFlags);
498	}
499	return rc;
500	}
501
502
503	/**
504	* Worker for NEMR0UnmapPages and others.
505	*/
506	NEM_TMPL_STATIC int nemR0WinUnmapPages(PGVM pGVM, PGVMCPU pGVCpu, RTGCPHYS GCPhys, uint32_t cPages)
507	{
508	/*
509	* Validate input.
510	*/
511	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
512
513	AssertReturn(cPages > 0, VERR_OUT_OF_RANGE);
514	AssertReturn(cPages <= NEM_MAX_UNMAP_PAGES, VERR_OUT_OF_RANGE);
515	AssertMsgReturn(!(GCPhys & X86_PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_OUT_OF_RANGE);
516	AssertReturn(GCPhys < _1E, VERR_OUT_OF_RANGE);
517
518	/*
519	* Compose and make the hypercall.
520	*/
521	HV_INPUT_UNMAP_GPA_PAGES pUnmapPages = (HV_INPUT_UNMAP_GPA_PAGES )pGVCpu->nem.s.HypercallData.pbPage;
522	AssertPtrReturn(pUnmapPages, VERR_INTERNAL_ERROR_3);
523	pUnmapPages->TargetPartitionId = pGVM->nem.s.idHvPartition;
524	pUnmapPages->TargetGpaBase = GCPhys >> X86_PAGE_SHIFT;
525	pUnmapPages->fFlags = 0;
526
527	uint64_t uResult = g_pfnHvlInvokeHypercall(HvCallUnmapGpaPages \| ((uint64_t)cPages << 32),
528	pGVCpu->nem.s.HypercallData.HCPhysPage, 0);
529	Log6(("NEMR0UnmapPages: %RGp L %u -> %#RX64\n", GCPhys, cPages, uResult));
530	if (uResult == ((uint64_t)cPages << 32))
531	{
532	#if 1 /* Do we need to do this? Hopefully not... */
533	uint64_t volatile uR = g_pfnHvlInvokeHypercall(HvCallUncommitGpaPages \| ((uint64_t)cPages << 32),
534	pGVCpu->nem.s.HypercallData.HCPhysPage, 0);
535	AssertMsg(uR == ((uint64_t)cPages << 32), ("uR=%#RX64\n", uR)); NOREF(uR);
536	#endif
537	return VINF_SUCCESS;
538	}
539
540	LogRel(("g_pfnHvlInvokeHypercall/UnmapGpaPages -> %#RX64\n", uResult));
541	return VERR_NEM_UNMAP_PAGES_FAILED;
542	}
543
544
545	/**
546	* Unmaps pages from the guest physical address space.
547	*
548	* Generally the caller will be under the PGM lock already, so no extra effort
549	* is needed to make sure all changes happens under it.
550	*
551	* @returns VBox status code.
552	* @param pGVM The ring-0 VM handle.
553	* @param pVM The cross context VM handle.
554	* @param idCpu The calling EMT. Necessary for getting the
555	* hypercall page and arguments.
556	* @thread EMT(idCpu)
557	*/
558	VMMR0_INT_DECL(int) NEMR0UnmapPages(PGVM pGVM, PVM pVM, VMCPUID idCpu)
559	{
560	/*
561	* Unpack the call.
562	*/
563	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
564	if (RT_SUCCESS(rc))
565	{
566	PVMCPU pVCpu = &pVM->aCpus[idCpu];
567	PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
568
569	RTGCPHYS const GCPhys = pVCpu->nem.s.Hypercall.UnmapPages.GCPhys;
570	uint32_t const cPages = pVCpu->nem.s.Hypercall.UnmapPages.cPages;
571
572	/*
573	* Do the work.
574	*/
575	rc = nemR0WinUnmapPages(pGVM, pGVCpu, GCPhys, cPages);
576	}
577	return rc;
578	}
579
580
581	/**
582	* Worker for NEMR0ExportState.
583	*
584	* Intention is to use it internally later.
585	*
586	* @returns VBox status code.
587	* @param pGVM The ring-0 VM handle.
588	* @param pGVCpu The irng-0 VCPU handle.
589	* @param pCtx The CPU context structure to import into.
590	*/
591	NEM_TMPL_STATIC int nemR0WinExportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx)
592	{
593	PVMCPU pVCpu = &pGVM->pVM->aCpus[pGVCpu->idCpu];
594	HV_INPUT_SET_VP_REGISTERS pInput = (HV_INPUT_SET_VP_REGISTERS )pGVCpu->nem.s.HypercallData.pbPage;
595	AssertPtrReturn(pInput, VERR_INTERNAL_ERROR_3);
596
597	pInput->PartitionId = pGVM->nem.s.idHvPartition;
598	pInput->VpIndex = pGVCpu->idCpu;
599	pInput->RsvdZ = 0;
600
601	uint64_t const fWhat = ~pCtx->fExtrn & (CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK);
602	if ( !fWhat
603	&& pVCpu->nem.s.fCurrentInterruptWindows == pVCpu->nem.s.fDesiredInterruptWindows)
604	return VINF_SUCCESS;
605	uintptr_t iReg = 0;
606
607	/* GPRs */
608	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
609	{
610	if (fWhat & CPUMCTX_EXTRN_RAX)
611	{
612	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
613	pInput->Elements[iReg].Name = HvX64RegisterRax;
614	pInput->Elements[iReg].Value.Reg64 = pCtx->rax;
615	iReg++;
616	}
617	if (fWhat & CPUMCTX_EXTRN_RCX)
618	{
619	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
620	pInput->Elements[iReg].Name = HvX64RegisterRcx;
621	pInput->Elements[iReg].Value.Reg64 = pCtx->rcx;
622	iReg++;
623	}
624	if (fWhat & CPUMCTX_EXTRN_RDX)
625	{
626	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
627	pInput->Elements[iReg].Name = HvX64RegisterRdx;
628	pInput->Elements[iReg].Value.Reg64 = pCtx->rdx;
629	iReg++;
630	}
631	if (fWhat & CPUMCTX_EXTRN_RBX)
632	{
633	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
634	pInput->Elements[iReg].Name = HvX64RegisterRbx;
635	pInput->Elements[iReg].Value.Reg64 = pCtx->rbx;
636	iReg++;
637	}
638	if (fWhat & CPUMCTX_EXTRN_RSP)
639	{
640	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
641	pInput->Elements[iReg].Name = HvX64RegisterRsp;
642	pInput->Elements[iReg].Value.Reg64 = pCtx->rsp;
643	iReg++;
644	}
645	if (fWhat & CPUMCTX_EXTRN_RBP)
646	{
647	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
648	pInput->Elements[iReg].Name = HvX64RegisterRbp;
649	pInput->Elements[iReg].Value.Reg64 = pCtx->rbp;
650	iReg++;
651	}
652	if (fWhat & CPUMCTX_EXTRN_RSI)
653	{
654	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
655	pInput->Elements[iReg].Name = HvX64RegisterRsi;
656	pInput->Elements[iReg].Value.Reg64 = pCtx->rsi;
657	iReg++;
658	}
659	if (fWhat & CPUMCTX_EXTRN_RDI)
660	{
661	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
662	pInput->Elements[iReg].Name = HvX64RegisterRdi;
663	pInput->Elements[iReg].Value.Reg64 = pCtx->rdi;
664	iReg++;
665	}
666	if (fWhat & CPUMCTX_EXTRN_R8_R15)
667	{
668	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
669	pInput->Elements[iReg].Name = HvX64RegisterR8;
670	pInput->Elements[iReg].Value.Reg64 = pCtx->r8;
671	iReg++;
672	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
673	pInput->Elements[iReg].Name = HvX64RegisterR9;
674	pInput->Elements[iReg].Value.Reg64 = pCtx->r9;
675	iReg++;
676	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
677	pInput->Elements[iReg].Name = HvX64RegisterR10;
678	pInput->Elements[iReg].Value.Reg64 = pCtx->r10;
679	iReg++;
680	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
681	pInput->Elements[iReg].Name = HvX64RegisterR11;
682	pInput->Elements[iReg].Value.Reg64 = pCtx->r11;
683	iReg++;
684	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
685	pInput->Elements[iReg].Name = HvX64RegisterR12;
686	pInput->Elements[iReg].Value.Reg64 = pCtx->r12;
687	iReg++;
688	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
689	pInput->Elements[iReg].Name = HvX64RegisterR13;
690	pInput->Elements[iReg].Value.Reg64 = pCtx->r13;
691	iReg++;
692	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
693	pInput->Elements[iReg].Name = HvX64RegisterR14;
694	pInput->Elements[iReg].Value.Reg64 = pCtx->r14;
695	iReg++;
696	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
697	pInput->Elements[iReg].Name = HvX64RegisterR15;
698	pInput->Elements[iReg].Value.Reg64 = pCtx->r15;
699	iReg++;
700	}
701	}
702
703	/* RIP & Flags */
704	if (fWhat & CPUMCTX_EXTRN_RIP)
705	{
706	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
707	pInput->Elements[iReg].Name = HvX64RegisterRip;
708	pInput->Elements[iReg].Value.Reg64 = pCtx->rip;
709	iReg++;
710	}
711	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
712	{
713	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
714	pInput->Elements[iReg].Name = HvX64RegisterRflags;
715	pInput->Elements[iReg].Value.Reg64 = pCtx->rflags.u;
716	iReg++;
717	}
718
719	/* Segments */
720	#define COPY_OUT_SEG(a_idx, a_enmName, a_SReg) \
721	do { \
722	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[a_idx]); \
723	pInput->Elements[a_idx].Name = a_enmName; \
724	pInput->Elements[a_idx].Value.Segment.Base = (a_SReg).u64Base; \
725	pInput->Elements[a_idx].Value.Segment.Limit = (a_SReg).u32Limit; \
726	pInput->Elements[a_idx].Value.Segment.Selector = (a_SReg).Sel; \
727	pInput->Elements[a_idx].Value.Segment.Attributes = (a_SReg).Attr.u; \
728	} while (0)
729	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
730	{
731	if (fWhat & CPUMCTX_EXTRN_CS)
732	{
733	COPY_OUT_SEG(iReg, HvX64RegisterCs, pCtx->cs);
734	iReg++;
735	}
736	if (fWhat & CPUMCTX_EXTRN_ES)
737	{
738	COPY_OUT_SEG(iReg, HvX64RegisterEs, pCtx->es);
739	iReg++;
740	}
741	if (fWhat & CPUMCTX_EXTRN_SS)
742	{
743	COPY_OUT_SEG(iReg, HvX64RegisterSs, pCtx->ss);
744	iReg++;
745	}
746	if (fWhat & CPUMCTX_EXTRN_DS)
747	{
748	COPY_OUT_SEG(iReg, HvX64RegisterDs, pCtx->ds);
749	iReg++;
750	}
751	if (fWhat & CPUMCTX_EXTRN_FS)
752	{
753	COPY_OUT_SEG(iReg, HvX64RegisterFs, pCtx->fs);
754	iReg++;
755	}
756	if (fWhat & CPUMCTX_EXTRN_GS)
757	{
758	COPY_OUT_SEG(iReg, HvX64RegisterGs, pCtx->gs);
759	iReg++;
760	}
761	}
762
763	/* Descriptor tables & task segment. */
764	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
765	{
766	if (fWhat & CPUMCTX_EXTRN_LDTR)
767	{
768	COPY_OUT_SEG(iReg, HvX64RegisterLdtr, pCtx->ldtr);
769	iReg++;
770	}
771	if (fWhat & CPUMCTX_EXTRN_TR)
772	{
773	COPY_OUT_SEG(iReg, HvX64RegisterTr, pCtx->tr);
774	iReg++;
775	}
776
777	if (fWhat & CPUMCTX_EXTRN_IDTR)
778	{
779	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
780	pInput->Elements[iReg].Value.Table.Pad[0] = 0;
781	pInput->Elements[iReg].Value.Table.Pad[1] = 0;
782	pInput->Elements[iReg].Value.Table.Pad[2] = 0;
783	pInput->Elements[iReg].Name = HvX64RegisterIdtr;
784	pInput->Elements[iReg].Value.Table.Limit = pCtx->idtr.cbIdt;
785	pInput->Elements[iReg].Value.Table.Base = pCtx->idtr.pIdt;
786	iReg++;
787	}
788	if (fWhat & CPUMCTX_EXTRN_GDTR)
789	{
790	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
791	pInput->Elements[iReg].Value.Table.Pad[0] = 0;
792	pInput->Elements[iReg].Value.Table.Pad[1] = 0;
793	pInput->Elements[iReg].Value.Table.Pad[2] = 0;
794	pInput->Elements[iReg].Name = HvX64RegisterGdtr;
795	pInput->Elements[iReg].Value.Table.Limit = pCtx->gdtr.cbGdt;
796	pInput->Elements[iReg].Value.Table.Base = pCtx->gdtr.pGdt;
797	iReg++;
798	}
799	}
800
801	/* Control registers. */
802	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
803	{
804	if (fWhat & CPUMCTX_EXTRN_CR0)
805	{
806	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
807	pInput->Elements[iReg].Name = HvX64RegisterCr0;
808	pInput->Elements[iReg].Value.Reg64 = pCtx->cr0;
809	iReg++;
810	}
811	if (fWhat & CPUMCTX_EXTRN_CR2)
812	{
813	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
814	pInput->Elements[iReg].Name = HvX64RegisterCr2;
815	pInput->Elements[iReg].Value.Reg64 = pCtx->cr2;
816	iReg++;
817	}
818	if (fWhat & CPUMCTX_EXTRN_CR3)
819	{
820	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
821	pInput->Elements[iReg].Name = HvX64RegisterCr3;
822	pInput->Elements[iReg].Value.Reg64 = pCtx->cr3;
823	iReg++;
824	}
825	if (fWhat & CPUMCTX_EXTRN_CR4)
826	{
827	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
828	pInput->Elements[iReg].Name = HvX64RegisterCr4;
829	pInput->Elements[iReg].Value.Reg64 = pCtx->cr4;
830	iReg++;
831	}
832	}
833	/** @todo CR8/TPR */
834	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
835	pInput->Elements[iReg].Name = HvX64RegisterCr8;
836	pInput->Elements[iReg].Value.Reg64 = CPUMGetGuestCR8(pVCpu);
837	iReg++;
838
839	/** @todo does HvX64RegisterXfem mean XCR0? What about the related MSR. */
840
841	/* Debug registers. */
842	/** @todo fixme. Figure out what the hyper-v version of KVM_SET_GUEST_DEBUG would be. */
843	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
844	{
845	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
846	pInput->Elements[iReg].Name = HvX64RegisterDr0;
847	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR0(pVCpu);
848	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[0];
849	iReg++;
850	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
851	pInput->Elements[iReg].Name = HvX64RegisterDr1;
852	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR1(pVCpu);
853	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[1];
854	iReg++;
855	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
856	pInput->Elements[iReg].Name = HvX64RegisterDr2;
857	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR2(pVCpu);
858	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[2];
859	iReg++;
860	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
861	pInput->Elements[iReg].Name = HvX64RegisterDr3;
862	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR3(pVCpu);
863	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[3];
864	iReg++;
865	}
866	if (fWhat & CPUMCTX_EXTRN_DR6)
867	{
868	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
869	pInput->Elements[iReg].Name = HvX64RegisterDr6;
870	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR6(pVCpu);
871	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[6];
872	iReg++;
873	}
874	if (fWhat & CPUMCTX_EXTRN_DR7)
875	{
876	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
877	pInput->Elements[iReg].Name = HvX64RegisterDr7;
878	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR7(pVCpu);
879	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[7];
880	iReg++;
881	}
882
883	/* Floating point state. */
884	if (fWhat & CPUMCTX_EXTRN_X87)
885	{
886	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
887	pInput->Elements[iReg].Name = HvX64RegisterFpMmx0;
888	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[0].au64[0];
889	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[0].au64[1];
890	iReg++;
891	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
892	pInput->Elements[iReg].Name = HvX64RegisterFpMmx1;
893	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[1].au64[0];
894	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[1].au64[1];
895	iReg++;
896	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
897	pInput->Elements[iReg].Name = HvX64RegisterFpMmx2;
898	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[2].au64[0];
899	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[2].au64[1];
900	iReg++;
901	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
902	pInput->Elements[iReg].Name = HvX64RegisterFpMmx3;
903	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[3].au64[0];
904	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[3].au64[1];
905	iReg++;
906	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
907	pInput->Elements[iReg].Name = HvX64RegisterFpMmx4;
908	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[4].au64[0];
909	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[4].au64[1];
910	iReg++;
911	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
912	pInput->Elements[iReg].Name = HvX64RegisterFpMmx5;
913	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[5].au64[0];
914	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[5].au64[1];
915	iReg++;
916	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
917	pInput->Elements[iReg].Name = HvX64RegisterFpMmx6;
918	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[6].au64[0];
919	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[6].au64[1];
920	iReg++;
921	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
922	pInput->Elements[iReg].Name = HvX64RegisterFpMmx7;
923	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[7].au64[0];
924	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[7].au64[1];
925	iReg++;
926
927	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
928	pInput->Elements[iReg].Name = HvX64RegisterFpControlStatus;
929	pInput->Elements[iReg].Value.FpControlStatus.FpControl = pCtx->pXStateR0->x87.FCW;
930	pInput->Elements[iReg].Value.FpControlStatus.FpStatus = pCtx->pXStateR0->x87.FSW;
931	pInput->Elements[iReg].Value.FpControlStatus.FpTag = pCtx->pXStateR0->x87.FTW;
932	pInput->Elements[iReg].Value.FpControlStatus.Reserved = pCtx->pXStateR0->x87.FTW >> 8;
933	pInput->Elements[iReg].Value.FpControlStatus.LastFpOp = pCtx->pXStateR0->x87.FOP;
934	pInput->Elements[iReg].Value.FpControlStatus.LastFpRip = (pCtx->pXStateR0->x87.FPUIP)
935	\| ((uint64_t)pCtx->pXStateR0->x87.CS << 32)
936	\| ((uint64_t)pCtx->pXStateR0->x87.Rsrvd1 << 48);
937	iReg++;
938	/** @todo we've got trouble if if we try write just SSE w/o X87. */
939	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
940	pInput->Elements[iReg].Name = HvX64RegisterXmmControlStatus;
941	pInput->Elements[iReg].Value.XmmControlStatus.LastFpRdp = (pCtx->pXStateR0->x87.FPUDP)
942	\| ((uint64_t)pCtx->pXStateR0->x87.DS << 32)
943	\| ((uint64_t)pCtx->pXStateR0->x87.Rsrvd2 << 48);
944	pInput->Elements[iReg].Value.XmmControlStatus.XmmStatusControl = pCtx->pXStateR0->x87.MXCSR;
945	pInput->Elements[iReg].Value.XmmControlStatus.XmmStatusControlMask = pCtx->pXStateR0->x87.MXCSR_MASK; /** @todo ??? (Isn't this an output field?) */
946	iReg++;
947	}
948
949	/* Vector state. */
950	if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
951	{
952	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
953	pInput->Elements[iReg].Name = HvX64RegisterXmm0;
954	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Lo;
955	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Hi;
956	iReg++;
957	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
958	pInput->Elements[iReg].Name = HvX64RegisterXmm1;
959	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Lo;
960	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Hi;
961	iReg++;
962	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
963	pInput->Elements[iReg].Name = HvX64RegisterXmm2;
964	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Lo;
965	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Hi;
966	iReg++;
967	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
968	pInput->Elements[iReg].Name = HvX64RegisterXmm3;
969	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Lo;
970	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Hi;
971	iReg++;
972	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
973	pInput->Elements[iReg].Name = HvX64RegisterXmm4;
974	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Lo;
975	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Hi;
976	iReg++;
977	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
978	pInput->Elements[iReg].Name = HvX64RegisterXmm5;
979	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Lo;
980	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Hi;
981	iReg++;
982	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
983	pInput->Elements[iReg].Name = HvX64RegisterXmm6;
984	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Lo;
985	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Hi;
986	iReg++;
987	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
988	pInput->Elements[iReg].Name = HvX64RegisterXmm7;
989	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Lo;
990	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Hi;
991	iReg++;
992	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
993	pInput->Elements[iReg].Name = HvX64RegisterXmm8;
994	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Lo;
995	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Hi;
996	iReg++;
997	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
998	pInput->Elements[iReg].Name = HvX64RegisterXmm9;
999	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Lo;
1000	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Hi;
1001	iReg++;
1002	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
1003	pInput->Elements[iReg].Name = HvX64RegisterXmm10;
1004	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Lo;
1005	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Hi;
1006	iReg++;
1007	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
1008	pInput->Elements[iReg].Name = HvX64RegisterXmm11;
1009	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Lo;
1010	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Hi;
1011	iReg++;
1012	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
1013	pInput->Elements[iReg].Name = HvX64RegisterXmm12;
1014	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Lo;
1015	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Hi;
1016	iReg++;
1017	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
1018	pInput->Elements[iReg].Name = HvX64RegisterXmm13;
1019	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Lo;
1020	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Hi;
1021	iReg++;
1022	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
1023	pInput->Elements[iReg].Name = HvX64RegisterXmm14;
1024	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Lo;
1025	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Hi;
1026	iReg++;
1027	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
1028	pInput->Elements[iReg].Name = HvX64RegisterXmm15;
1029	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Lo;
1030	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Hi;
1031	iReg++;
1032	}
1033
1034	/* MSRs */
1035	// HvX64RegisterTsc - don't touch
1036	if (fWhat & CPUMCTX_EXTRN_EFER)
1037	{
1038	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1039	pInput->Elements[iReg].Name = HvX64RegisterEfer;
1040	pInput->Elements[iReg].Value.Reg64 = pCtx->msrEFER;
1041	iReg++;
1042	}
1043	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1044	{
1045	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1046	pInput->Elements[iReg].Name = HvX64RegisterKernelGsBase;
1047	pInput->Elements[iReg].Value.Reg64 = pCtx->msrKERNELGSBASE;
1048	iReg++;
1049	}
1050	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1051	{
1052	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1053	pInput->Elements[iReg].Name = HvX64RegisterSysenterCs;
1054	pInput->Elements[iReg].Value.Reg64 = pCtx->SysEnter.cs;
1055	iReg++;
1056	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1057	pInput->Elements[iReg].Name = HvX64RegisterSysenterEip;
1058	pInput->Elements[iReg].Value.Reg64 = pCtx->SysEnter.eip;
1059	iReg++;
1060	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1061	pInput->Elements[iReg].Name = HvX64RegisterSysenterEsp;
1062	pInput->Elements[iReg].Value.Reg64 = pCtx->SysEnter.esp;
1063	iReg++;
1064	}
1065	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1066	{
1067	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1068	pInput->Elements[iReg].Name = HvX64RegisterStar;
1069	pInput->Elements[iReg].Value.Reg64 = pCtx->msrSTAR;
1070	iReg++;
1071	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1072	pInput->Elements[iReg].Name = HvX64RegisterLstar;
1073	pInput->Elements[iReg].Value.Reg64 = pCtx->msrLSTAR;
1074	iReg++;
1075	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1076	pInput->Elements[iReg].Name = HvX64RegisterCstar;
1077	pInput->Elements[iReg].Value.Reg64 = pCtx->msrCSTAR;
1078	iReg++;
1079	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1080	pInput->Elements[iReg].Name = HvX64RegisterSfmask;
1081	pInput->Elements[iReg].Value.Reg64 = pCtx->msrSFMASK;
1082	iReg++;
1083	}
1084	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1085	{
1086	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1087	pInput->Elements[iReg].Name = HvX64RegisterApicBase;
1088	pInput->Elements[iReg].Value.Reg64 = APICGetBaseMsrNoCheck(pVCpu);
1089	iReg++;
1090	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1091	pInput->Elements[iReg].Name = HvX64RegisterPat;
1092	pInput->Elements[iReg].Value.Reg64 = pCtx->msrPAT;
1093	iReg++;
1094	#if 0 /** @todo HvX64RegisterMtrrCap is read only? Seems it's not even readable. */
1095	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1096	pInput->Elements[iReg].Name = HvX64RegisterMtrrCap;
1097	pInput->Elements[iReg].Value.Reg64 = CPUMGetGuestIa32MtrrCap(pVCpu);
1098	iReg++;
1099	#endif
1100
1101	PCPUMCTXMSRS pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1102
1103	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1104	pInput->Elements[iReg].Name = HvX64RegisterMtrrDefType;
1105	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrDefType;
1106	iReg++;
1107
1108	/** @todo we dont keep state for HvX64RegisterMtrrPhysBaseX and HvX64RegisterMtrrPhysMaskX */
1109
1110	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1111	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix64k00000;
1112	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix64K_00000;
1113	iReg++;
1114	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1115	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix16k80000;
1116	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix16K_80000;
1117	iReg++;
1118	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1119	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix16kA0000;
1120	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix16K_A0000;
1121	iReg++;
1122	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1123	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix4kC0000;
1124	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix4K_C0000;
1125	iReg++;
1126	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1127	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix4kC8000;
1128	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix4K_C8000;
1129	iReg++;
1130	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1131	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix4kD0000;
1132	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix4K_D0000;
1133	iReg++;
1134	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1135	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix4kD8000;
1136	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix4K_D8000;
1137	iReg++;
1138	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1139	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix4kE0000;
1140	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix4K_E0000;
1141	iReg++;
1142	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1143	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix4kE8000;
1144	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix4K_E8000;
1145	iReg++;
1146	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1147	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix4kF0000;
1148	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix4K_F0000;
1149	iReg++;
1150	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1151	pInput->Elements[iReg].Name = HvX64RegisterMtrrFix4kF8000;
1152	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MtrrFix4K_F8000;
1153	iReg++;
1154	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1155	pInput->Elements[iReg].Name = HvX64RegisterTscAux;
1156	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.TscAux;
1157	iReg++;
1158
1159	#if 0 /** @todo Why can't we write these on Intel systems? Not that we really care... */
1160	const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pGVM->pVM);
1161	if (enmCpuVendor != CPUMCPUVENDOR_AMD)
1162	{
1163	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1164	pInput->Elements[iReg].Name = HvX64RegisterIa32MiscEnable;
1165	pInput->Elements[iReg].Value.Reg64 = pCtxMsrs->msr.MiscEnable;
1166	iReg++;
1167	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1168	pInput->Elements[iReg].Name = HvX64RegisterIa32FeatureControl;
1169	pInput->Elements[iReg].Value.Reg64 = CPUMGetGuestIa32FeatureControl(pVCpu);
1170	iReg++;
1171	}
1172	#endif
1173	}
1174
1175	/* event injection (clear it). */
1176	if (fWhat & CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)
1177	{
1178	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1179	pInput->Elements[iReg].Name = HvRegisterPendingInterruption;
1180	pInput->Elements[iReg].Value.Reg64 = 0;
1181	iReg++;
1182	}
1183
1184	/* Interruptibility state. This can get a little complicated since we get
1185	half of the state via HV_X64_VP_EXECUTION_STATE. */
1186	if ( (fWhat & (CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI))
1187	== (CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI) )
1188	{
1189	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1190	pInput->Elements[iReg].Name = HvRegisterInterruptState;
1191	pInput->Elements[iReg].Value.Reg64 = 0;
1192	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1193	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
1194	pInput->Elements[iReg].Value.InterruptState.InterruptShadow = 1;
1195	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
1196	pInput->Elements[iReg].Value.InterruptState.NmiMasked = 1;
1197	iReg++;
1198	}
1199	else if (fWhat & CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT)
1200	{
1201	if ( pVCpu->nem.s.fLastInterruptShadow
1202	\|\| ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1203	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip))
1204	{
1205	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1206	pInput->Elements[iReg].Name = HvRegisterInterruptState;
1207	pInput->Elements[iReg].Value.Reg64 = 0;
1208	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1209	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
1210	pInput->Elements[iReg].Value.InterruptState.InterruptShadow = 1;
1211	/** @todo Retrieve NMI state, currently assuming it's zero. (yes this may happen on I/O) */
1212	//if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
1213	// pInput->Elements[iReg].Value.InterruptState.NmiMasked = 1;
1214	iReg++;
1215	}
1216	}
1217	else
1218	Assert(!(fWhat & CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI));
1219
1220	/* Interrupt windows. Always set if active as Hyper-V seems to be forgetful. */
1221	uint8_t const fDesiredIntWin = pVCpu->nem.s.fDesiredInterruptWindows;
1222	if ( fDesiredIntWin
1223	\|\| pVCpu->nem.s.fCurrentInterruptWindows != fDesiredIntWin)
1224	{
1225	pVCpu->nem.s.fCurrentInterruptWindows = pVCpu->nem.s.fDesiredInterruptWindows;
1226	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1227	pInput->Elements[iReg].Name = HvX64RegisterDeliverabilityNotifications;
1228	pInput->Elements[iReg].Value.DeliverabilityNotifications.AsUINT64 = fDesiredIntWin;
1229	Assert(pInput->Elements[iReg].Value.DeliverabilityNotifications.NmiNotification == RT_BOOL(fDesiredIntWin & NEM_WIN_INTW_F_NMI));
1230	Assert(pInput->Elements[iReg].Value.DeliverabilityNotifications.InterruptNotification == RT_BOOL(fDesiredIntWin & NEM_WIN_INTW_F_REGULAR));
1231	Assert(pInput->Elements[iReg].Value.DeliverabilityNotifications.InterruptPriority == (fDesiredIntWin & NEM_WIN_INTW_F_PRIO_MASK) >> NEM_WIN_INTW_F_PRIO_SHIFT);
1232	iReg++;
1233	}
1234
1235	/// @todo HvRegisterPendingEvent0
1236	/// @todo HvRegisterPendingEvent1
1237
1238	/*
1239	* Set the registers.
1240	*/
1241	Assert((uintptr_t)&pInput->Elements[iReg] - (uintptr_t)pGVCpu->nem.s.HypercallData.pbPage < PAGE_SIZE); /* max is 127 */
1242
1243	/*
1244	* Make the hypercall.
1245	*/
1246	uint64_t uResult = g_pfnHvlInvokeHypercall(HV_MAKE_CALL_INFO(HvCallSetVpRegisters, iReg),
1247	pGVCpu->nem.s.HypercallData.HCPhysPage, 0 /GCPhysOutput/);
1248	AssertLogRelMsgReturn(uResult == HV_MAKE_CALL_REP_RET(iReg),
1249	("uResult=%RX64 iRegs=%#x\n", uResult, iReg),
1250	VERR_NEM_SET_REGISTERS_FAILED);
1251	//LogFlow(("nemR0WinExportState: uResult=%#RX64 iReg=%zu fWhat=%#018RX64 fExtrn=%#018RX64 -> %#018RX64\n", uResult, iReg, fWhat, pCtx->fExtrn,
1252	// pCtx->fExtrn \| CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK \| CPUMCTX_EXTRN_KEEPER_NEM ));
1253	pCtx->fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK \| CPUMCTX_EXTRN_KEEPER_NEM;
1254	return VINF_SUCCESS;
1255	}
1256
1257
1258	/**
1259	* Export the state to the native API (out of CPUMCTX).
1260	*
1261	* @returns VBox status code
1262	* @param pGVM The ring-0 VM handle.
1263	* @param pVM The cross context VM handle.
1264	* @param idCpu The calling EMT. Necessary for getting the
1265	* hypercall page and arguments.
1266	*/
1267	VMMR0_INT_DECL(int) NEMR0ExportState(PGVM pGVM, PVM pVM, VMCPUID idCpu)
1268	{
1269	/*
1270	* Validate the call.
1271	*/
1272	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
1273	if (RT_SUCCESS(rc))
1274	{
1275	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1276	PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
1277	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
1278
1279	/*
1280	* Call worker.
1281	*/
1282	rc = nemR0WinExportState(pGVM, pGVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1283	}
1284	return rc;
1285	}
1286
1287
1288	/**
1289	* Worker for NEMR0ImportState.
1290	*
1291	* Intention is to use it internally later.
1292	*
1293	* @returns VBox status code.
1294	* @param pGVM The ring-0 VM handle.
1295	* @param pGVCpu The irng-0 VCPU handle.
1296	* @param pCtx The CPU context structure to import into.
1297	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1298	*/
1299	NEM_TMPL_STATIC int nemR0WinImportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx, uint64_t fWhat)
1300	{
1301	HV_INPUT_GET_VP_REGISTERS pInput = (HV_INPUT_GET_VP_REGISTERS )pGVCpu->nem.s.HypercallData.pbPage;
1302	AssertPtrReturn(pInput, VERR_INTERNAL_ERROR_3);
1303
1304	fWhat &= pCtx->fExtrn;
1305
1306	pInput->PartitionId = pGVM->nem.s.idHvPartition;
1307	pInput->VpIndex = pGVCpu->idCpu;
1308	pInput->fFlags = 0;
1309
1310	/* GPRs */
1311	uintptr_t iReg = 0;
1312	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
1313	{
1314	if (fWhat & CPUMCTX_EXTRN_RAX)
1315	pInput->Names[iReg++] = HvX64RegisterRax;
1316	if (fWhat & CPUMCTX_EXTRN_RCX)
1317	pInput->Names[iReg++] = HvX64RegisterRcx;
1318	if (fWhat & CPUMCTX_EXTRN_RDX)
1319	pInput->Names[iReg++] = HvX64RegisterRdx;
1320	if (fWhat & CPUMCTX_EXTRN_RBX)
1321	pInput->Names[iReg++] = HvX64RegisterRbx;
1322	if (fWhat & CPUMCTX_EXTRN_RSP)
1323	pInput->Names[iReg++] = HvX64RegisterRsp;
1324	if (fWhat & CPUMCTX_EXTRN_RBP)
1325	pInput->Names[iReg++] = HvX64RegisterRbp;
1326	if (fWhat & CPUMCTX_EXTRN_RSI)
1327	pInput->Names[iReg++] = HvX64RegisterRsi;
1328	if (fWhat & CPUMCTX_EXTRN_RDI)
1329	pInput->Names[iReg++] = HvX64RegisterRdi;
1330	if (fWhat & CPUMCTX_EXTRN_R8_R15)
1331	{
1332	pInput->Names[iReg++] = HvX64RegisterR8;
1333	pInput->Names[iReg++] = HvX64RegisterR9;
1334	pInput->Names[iReg++] = HvX64RegisterR10;
1335	pInput->Names[iReg++] = HvX64RegisterR11;
1336	pInput->Names[iReg++] = HvX64RegisterR12;
1337	pInput->Names[iReg++] = HvX64RegisterR13;
1338	pInput->Names[iReg++] = HvX64RegisterR14;
1339	pInput->Names[iReg++] = HvX64RegisterR15;
1340	}
1341	}
1342
1343	/* RIP & Flags */
1344	if (fWhat & CPUMCTX_EXTRN_RIP)
1345	pInput->Names[iReg++] = HvX64RegisterRip;
1346	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1347	pInput->Names[iReg++] = HvX64RegisterRflags;
1348
1349	/* Segments */
1350	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1351	{
1352	if (fWhat & CPUMCTX_EXTRN_CS)
1353	pInput->Names[iReg++] = HvX64RegisterCs;
1354	if (fWhat & CPUMCTX_EXTRN_ES)
1355	pInput->Names[iReg++] = HvX64RegisterEs;
1356	if (fWhat & CPUMCTX_EXTRN_SS)
1357	pInput->Names[iReg++] = HvX64RegisterSs;
1358	if (fWhat & CPUMCTX_EXTRN_DS)
1359	pInput->Names[iReg++] = HvX64RegisterDs;
1360	if (fWhat & CPUMCTX_EXTRN_FS)
1361	pInput->Names[iReg++] = HvX64RegisterFs;
1362	if (fWhat & CPUMCTX_EXTRN_GS)
1363	pInput->Names[iReg++] = HvX64RegisterGs;
1364	}
1365
1366	/* Descriptor tables and the task segment. */
1367	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1368	{
1369	if (fWhat & CPUMCTX_EXTRN_LDTR)
1370	pInput->Names[iReg++] = HvX64RegisterLdtr;
1371	if (fWhat & CPUMCTX_EXTRN_TR)
1372	pInput->Names[iReg++] = HvX64RegisterTr;
1373	if (fWhat & CPUMCTX_EXTRN_IDTR)
1374	pInput->Names[iReg++] = HvX64RegisterIdtr;
1375	if (fWhat & CPUMCTX_EXTRN_GDTR)
1376	pInput->Names[iReg++] = HvX64RegisterGdtr;
1377	}
1378
1379	/* Control registers. */
1380	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1381	{
1382	if (fWhat & CPUMCTX_EXTRN_CR0)
1383	pInput->Names[iReg++] = HvX64RegisterCr0;
1384	if (fWhat & CPUMCTX_EXTRN_CR2)
1385	pInput->Names[iReg++] = HvX64RegisterCr2;
1386	if (fWhat & CPUMCTX_EXTRN_CR3)
1387	pInput->Names[iReg++] = HvX64RegisterCr3;
1388	if (fWhat & CPUMCTX_EXTRN_CR4)
1389	pInput->Names[iReg++] = HvX64RegisterCr4;
1390	}
1391	pInput->Names[iReg++] = HvX64RegisterCr8; /// @todo CR8/TPR
1392
1393	/* Debug registers. */
1394	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1395	{
1396	pInput->Names[iReg++] = HvX64RegisterDr0;
1397	pInput->Names[iReg++] = HvX64RegisterDr1;
1398	pInput->Names[iReg++] = HvX64RegisterDr2;
1399	pInput->Names[iReg++] = HvX64RegisterDr3;
1400	}
1401	if (fWhat & CPUMCTX_EXTRN_DR6)
1402	pInput->Names[iReg++] = HvX64RegisterDr6;
1403	if (fWhat & CPUMCTX_EXTRN_DR7)
1404	pInput->Names[iReg++] = HvX64RegisterDr7;
1405
1406	/* Floating point state. */
1407	if (fWhat & CPUMCTX_EXTRN_X87)
1408	{
1409	pInput->Names[iReg++] = HvX64RegisterFpMmx0;
1410	pInput->Names[iReg++] = HvX64RegisterFpMmx1;
1411	pInput->Names[iReg++] = HvX64RegisterFpMmx2;
1412	pInput->Names[iReg++] = HvX64RegisterFpMmx3;
1413	pInput->Names[iReg++] = HvX64RegisterFpMmx4;
1414	pInput->Names[iReg++] = HvX64RegisterFpMmx5;
1415	pInput->Names[iReg++] = HvX64RegisterFpMmx6;
1416	pInput->Names[iReg++] = HvX64RegisterFpMmx7;
1417	pInput->Names[iReg++] = HvX64RegisterFpControlStatus;
1418	}
1419	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX))
1420	pInput->Names[iReg++] = HvX64RegisterXmmControlStatus;
1421
1422	/* Vector state. */
1423	if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
1424	{
1425	pInput->Names[iReg++] = HvX64RegisterXmm0;
1426	pInput->Names[iReg++] = HvX64RegisterXmm1;
1427	pInput->Names[iReg++] = HvX64RegisterXmm2;
1428	pInput->Names[iReg++] = HvX64RegisterXmm3;
1429	pInput->Names[iReg++] = HvX64RegisterXmm4;
1430	pInput->Names[iReg++] = HvX64RegisterXmm5;
1431	pInput->Names[iReg++] = HvX64RegisterXmm6;
1432	pInput->Names[iReg++] = HvX64RegisterXmm7;
1433	pInput->Names[iReg++] = HvX64RegisterXmm8;
1434	pInput->Names[iReg++] = HvX64RegisterXmm9;
1435	pInput->Names[iReg++] = HvX64RegisterXmm10;
1436	pInput->Names[iReg++] = HvX64RegisterXmm11;
1437	pInput->Names[iReg++] = HvX64RegisterXmm12;
1438	pInput->Names[iReg++] = HvX64RegisterXmm13;
1439	pInput->Names[iReg++] = HvX64RegisterXmm14;
1440	pInput->Names[iReg++] = HvX64RegisterXmm15;
1441	}
1442
1443	/* MSRs */
1444	// HvX64RegisterTsc - don't touch
1445	if (fWhat & CPUMCTX_EXTRN_EFER)
1446	pInput->Names[iReg++] = HvX64RegisterEfer;
1447	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1448	pInput->Names[iReg++] = HvX64RegisterKernelGsBase;
1449	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1450	{
1451	pInput->Names[iReg++] = HvX64RegisterSysenterCs;
1452	pInput->Names[iReg++] = HvX64RegisterSysenterEip;
1453	pInput->Names[iReg++] = HvX64RegisterSysenterEsp;
1454	}
1455	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1456	{
1457	pInput->Names[iReg++] = HvX64RegisterStar;
1458	pInput->Names[iReg++] = HvX64RegisterLstar;
1459	pInput->Names[iReg++] = HvX64RegisterCstar;
1460	pInput->Names[iReg++] = HvX64RegisterSfmask;
1461	}
1462
1463	#ifdef LOG_ENABLED
1464	const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pGVM->pVM);
1465	#endif
1466	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1467	{
1468	pInput->Names[iReg++] = HvX64RegisterApicBase; /// @todo APIC BASE
1469	pInput->Names[iReg++] = HvX64RegisterPat;
1470	#if 0 /def LOG_ENABLED/ /** @todo something's wrong with HvX64RegisterMtrrCap? (AMD) */
1471	pInput->Names[iReg++] = HvX64RegisterMtrrCap;
1472	#endif
1473	pInput->Names[iReg++] = HvX64RegisterMtrrDefType;
1474	pInput->Names[iReg++] = HvX64RegisterMtrrFix64k00000;
1475	pInput->Names[iReg++] = HvX64RegisterMtrrFix16k80000;
1476	pInput->Names[iReg++] = HvX64RegisterMtrrFix16kA0000;
1477	pInput->Names[iReg++] = HvX64RegisterMtrrFix4kC0000;
1478	pInput->Names[iReg++] = HvX64RegisterMtrrFix4kC8000;
1479	pInput->Names[iReg++] = HvX64RegisterMtrrFix4kD0000;
1480	pInput->Names[iReg++] = HvX64RegisterMtrrFix4kD8000;
1481	pInput->Names[iReg++] = HvX64RegisterMtrrFix4kE0000;
1482	pInput->Names[iReg++] = HvX64RegisterMtrrFix4kE8000;
1483	pInput->Names[iReg++] = HvX64RegisterMtrrFix4kF0000;
1484	pInput->Names[iReg++] = HvX64RegisterMtrrFix4kF8000;
1485	pInput->Names[iReg++] = HvX64RegisterTscAux;
1486	#if 0 /** @todo why can't we read HvX64RegisterIa32MiscEnable? */
1487	if (enmCpuVendor != CPUMCPUVENDOR_AMD)
1488	pInput->Names[iReg++] = HvX64RegisterIa32MiscEnable;
1489	#endif
1490	#ifdef LOG_ENABLED
1491	if (enmCpuVendor != CPUMCPUVENDOR_AMD)
1492	pInput->Names[iReg++] = HvX64RegisterIa32FeatureControl;
1493	#endif
1494	}
1495
1496	/* Interruptibility. */
1497	if (fWhat & (CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI))
1498	{
1499	pInput->Names[iReg++] = HvRegisterInterruptState;
1500	pInput->Names[iReg++] = HvX64RegisterRip;
1501	}
1502
1503	/* event injection */
1504	pInput->Names[iReg++] = HvRegisterPendingInterruption;
1505	pInput->Names[iReg++] = HvRegisterPendingEvent0;
1506	pInput->Names[iReg++] = HvRegisterPendingEvent1;
1507	size_t const cRegs = iReg;
1508	size_t const cbInput = RT_ALIGN_Z(RT_OFFSETOF(HV_INPUT_GET_VP_REGISTERS, Names[cRegs]), 32);
1509
1510	HV_REGISTER_VALUE paValues = (HV_REGISTER_VALUE )((uint8_t *)pInput + cbInput);
1511	Assert((uintptr_t)&paValues[cRegs] - (uintptr_t)pGVCpu->nem.s.HypercallData.pbPage < PAGE_SIZE); /* (max is around 168 registers) */
1512	RT_BZERO(paValues, cRegs * sizeof(paValues[0]));
1513
1514	/*
1515	* Make the hypercall.
1516	*/
1517	uint64_t uResult = g_pfnHvlInvokeHypercall(HV_MAKE_CALL_INFO(HvCallGetVpRegisters, cRegs),
1518	pGVCpu->nem.s.HypercallData.HCPhysPage,
1519	pGVCpu->nem.s.HypercallData.HCPhysPage + cbInput);
1520	AssertLogRelMsgReturn(uResult == HV_MAKE_CALL_REP_RET(cRegs),
1521	("uResult=%RX64 cRegs=%#x\n", uResult, cRegs),
1522	VERR_NEM_GET_REGISTERS_FAILED);
1523	//LogFlow(("nemR0WinImportState: uResult=%#RX64 iReg=%zu fWhat=%#018RX64 fExtr=%#018RX64\n", uResult, cRegs, fWhat, pCtx->fExtrn));
1524
1525	/*
1526	* Copy information to the CPUM context.
1527	*/
1528	PVMCPU pVCpu = &pGVM->pVM->aCpus[pGVCpu->idCpu];
1529	iReg = 0;
1530
1531	/* GPRs */
1532	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
1533	{
1534	if (fWhat & CPUMCTX_EXTRN_RAX)
1535	{
1536	Assert(pInput->Names[iReg] == HvX64RegisterRax);
1537	pCtx->rax = paValues[iReg++].Reg64;
1538	}
1539	if (fWhat & CPUMCTX_EXTRN_RCX)
1540	{
1541	Assert(pInput->Names[iReg] == HvX64RegisterRcx);
1542	pCtx->rcx = paValues[iReg++].Reg64;
1543	}
1544	if (fWhat & CPUMCTX_EXTRN_RDX)
1545	{
1546	Assert(pInput->Names[iReg] == HvX64RegisterRdx);
1547	pCtx->rdx = paValues[iReg++].Reg64;
1548	}
1549	if (fWhat & CPUMCTX_EXTRN_RBX)
1550	{
1551	Assert(pInput->Names[iReg] == HvX64RegisterRbx);
1552	pCtx->rbx = paValues[iReg++].Reg64;
1553	}
1554	if (fWhat & CPUMCTX_EXTRN_RSP)
1555	{
1556	Assert(pInput->Names[iReg] == HvX64RegisterRsp);
1557	pCtx->rsp = paValues[iReg++].Reg64;
1558	}
1559	if (fWhat & CPUMCTX_EXTRN_RBP)
1560	{
1561	Assert(pInput->Names[iReg] == HvX64RegisterRbp);
1562	pCtx->rbp = paValues[iReg++].Reg64;
1563	}
1564	if (fWhat & CPUMCTX_EXTRN_RSI)
1565	{
1566	Assert(pInput->Names[iReg] == HvX64RegisterRsi);
1567	pCtx->rsi = paValues[iReg++].Reg64;
1568	}
1569	if (fWhat & CPUMCTX_EXTRN_RDI)
1570	{
1571	Assert(pInput->Names[iReg] == HvX64RegisterRdi);
1572	pCtx->rdi = paValues[iReg++].Reg64;
1573	}
1574	if (fWhat & CPUMCTX_EXTRN_R8_R15)
1575	{
1576	Assert(pInput->Names[iReg] == HvX64RegisterR8);
1577	Assert(pInput->Names[iReg + 7] == HvX64RegisterR15);
1578	pCtx->r8 = paValues[iReg++].Reg64;
1579	pCtx->r9 = paValues[iReg++].Reg64;
1580	pCtx->r10 = paValues[iReg++].Reg64;
1581	pCtx->r11 = paValues[iReg++].Reg64;
1582	pCtx->r12 = paValues[iReg++].Reg64;
1583	pCtx->r13 = paValues[iReg++].Reg64;
1584	pCtx->r14 = paValues[iReg++].Reg64;
1585	pCtx->r15 = paValues[iReg++].Reg64;
1586	}
1587	}
1588
1589	/* RIP & Flags */
1590	if (fWhat & CPUMCTX_EXTRN_RIP)
1591	{
1592	Assert(pInput->Names[iReg] == HvX64RegisterRip);
1593	pCtx->rip = paValues[iReg++].Reg64;
1594	}
1595	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1596	{
1597	Assert(pInput->Names[iReg] == HvX64RegisterRflags);
1598	pCtx->rflags.u = paValues[iReg++].Reg64;
1599	}
1600
1601	/* Segments */
1602	#define COPY_BACK_SEG(a_idx, a_enmName, a_SReg) \
1603	do { \
1604	Assert(pInput->Names[a_idx] == a_enmName); \
1605	(a_SReg).u64Base = paValues[a_idx].Segment.Base; \
1606	(a_SReg).u32Limit = paValues[a_idx].Segment.Limit; \
1607	(a_SReg).ValidSel = (a_SReg).Sel = paValues[a_idx].Segment.Selector; \
1608	(a_SReg).Attr.u = paValues[a_idx].Segment.Attributes; \
1609	(a_SReg).fFlags = CPUMSELREG_FLAGS_VALID; \
1610	} while (0)
1611	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1612	{
1613	if (fWhat & CPUMCTX_EXTRN_CS)
1614	{
1615	COPY_BACK_SEG(iReg, HvX64RegisterCs, pCtx->cs);
1616	iReg++;
1617	}
1618	if (fWhat & CPUMCTX_EXTRN_ES)
1619	{
1620	COPY_BACK_SEG(iReg, HvX64RegisterEs, pCtx->es);
1621	iReg++;
1622	}
1623	if (fWhat & CPUMCTX_EXTRN_SS)
1624	{
1625	COPY_BACK_SEG(iReg, HvX64RegisterSs, pCtx->ss);
1626	iReg++;
1627	}
1628	if (fWhat & CPUMCTX_EXTRN_DS)
1629	{
1630	COPY_BACK_SEG(iReg, HvX64RegisterDs, pCtx->ds);
1631	iReg++;
1632	}
1633	if (fWhat & CPUMCTX_EXTRN_FS)
1634	{
1635	COPY_BACK_SEG(iReg, HvX64RegisterFs, pCtx->fs);
1636	iReg++;
1637	}
1638	if (fWhat & CPUMCTX_EXTRN_GS)
1639	{
1640	COPY_BACK_SEG(iReg, HvX64RegisterGs, pCtx->gs);
1641	iReg++;
1642	}
1643	}
1644	/* Descriptor tables and the task segment. */
1645	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1646	{
1647	if (fWhat & CPUMCTX_EXTRN_LDTR)
1648	{
1649	COPY_BACK_SEG(iReg, HvX64RegisterLdtr, pCtx->ldtr);
1650	iReg++;
1651	}
1652	if (fWhat & CPUMCTX_EXTRN_TR)
1653	{
1654	/* AMD-V likes loading TR with in AVAIL state, whereas intel insists on BUSY. So,
1655	avoid to trigger sanity assertions around the code, always fix this. */
1656	COPY_BACK_SEG(iReg, HvX64RegisterTr, pCtx->tr);
1657	switch (pCtx->tr.Attr.n.u4Type)
1658	{
1659	case X86_SEL_TYPE_SYS_386_TSS_BUSY:
1660	case X86_SEL_TYPE_SYS_286_TSS_BUSY:
1661	break;
1662	case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
1663	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1664	break;
1665	case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
1666	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
1667	break;
1668	}
1669	iReg++;
1670	}
1671	if (fWhat & CPUMCTX_EXTRN_IDTR)
1672	{
1673	Assert(pInput->Names[iReg] == HvX64RegisterIdtr);
1674	pCtx->idtr.cbIdt = paValues[iReg].Table.Limit;
1675	pCtx->idtr.pIdt = paValues[iReg].Table.Base;
1676	iReg++;
1677	}
1678	if (fWhat & CPUMCTX_EXTRN_GDTR)
1679	{
1680	Assert(pInput->Names[iReg] == HvX64RegisterGdtr);
1681	pCtx->gdtr.cbGdt = paValues[iReg].Table.Limit;
1682	pCtx->gdtr.pGdt = paValues[iReg].Table.Base;
1683	iReg++;
1684	}
1685	}
1686
1687	/* Control registers. */
1688	bool fMaybeChangedMode = false;
1689	bool fFlushTlb = false;
1690	bool fFlushGlobalTlb = false;
1691	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1692	{
1693	if (fWhat & CPUMCTX_EXTRN_CR0)
1694	{
1695	Assert(pInput->Names[iReg] == HvX64RegisterCr0);
1696	if (pCtx->cr0 != paValues[iReg].Reg64)
1697	{
1698	CPUMSetGuestCR0(pVCpu, paValues[iReg].Reg64);
1699	fMaybeChangedMode = true;
1700	fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
1701	}
1702	iReg++;
1703	}
1704	if (fWhat & CPUMCTX_EXTRN_CR2)
1705	{
1706	Assert(pInput->Names[iReg] == HvX64RegisterCr2);
1707	pCtx->cr2 = paValues[iReg].Reg64;
1708	iReg++;
1709	}
1710	if (fWhat & CPUMCTX_EXTRN_CR3)
1711	{
1712	Assert(pInput->Names[iReg] == HvX64RegisterCr3);
1713	if (pCtx->cr3 != paValues[iReg].Reg64)
1714	{
1715	CPUMSetGuestCR3(pVCpu, paValues[iReg].Reg64);
1716	fFlushTlb = true;
1717	}
1718	iReg++;
1719	}
1720	if (fWhat & CPUMCTX_EXTRN_CR4)
1721	{
1722	Assert(pInput->Names[iReg] == HvX64RegisterCr4);
1723	if (pCtx->cr4 != paValues[iReg].Reg64)
1724	{
1725	CPUMSetGuestCR4(pVCpu, paValues[iReg].Reg64);
1726	fMaybeChangedMode = true;
1727	fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
1728	}
1729	iReg++;
1730	}
1731	}
1732
1733	/// @todo CR8/TPR
1734	Assert(pInput->Names[iReg] == HvX64RegisterCr8);
1735	APICSetTpr(pVCpu, (uint8_t)paValues[iReg].Reg64 << 4);
1736	iReg++;
1737
1738	/* Debug registers. */
1739	/** @todo fixme */
1740	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1741	{
1742	Assert(pInput->Names[iReg] == HvX64RegisterDr0);
1743	Assert(pInput->Names[iReg+3] == HvX64RegisterDr3);
1744	if (pCtx->dr[0] != paValues[iReg].Reg64)
1745	CPUMSetGuestDR0(pVCpu, paValues[iReg].Reg64);
1746	iReg++;
1747	if (pCtx->dr[1] != paValues[iReg].Reg64)
1748	CPUMSetGuestDR1(pVCpu, paValues[iReg].Reg64);
1749	iReg++;
1750	if (pCtx->dr[2] != paValues[iReg].Reg64)
1751	CPUMSetGuestDR2(pVCpu, paValues[iReg].Reg64);
1752	iReg++;
1753	if (pCtx->dr[3] != paValues[iReg].Reg64)
1754	CPUMSetGuestDR3(pVCpu, paValues[iReg].Reg64);
1755	iReg++;
1756	}
1757	if (fWhat & CPUMCTX_EXTRN_DR6)
1758	{
1759	Assert(pInput->Names[iReg] == HvX64RegisterDr6);
1760	if (pCtx->dr[6] != paValues[iReg].Reg64)
1761	CPUMSetGuestDR6(pVCpu, paValues[iReg].Reg64);
1762	iReg++;
1763	}
1764	if (fWhat & CPUMCTX_EXTRN_DR7)
1765	{
1766	Assert(pInput->Names[iReg] == HvX64RegisterDr7);
1767	if (pCtx->dr[7] != paValues[iReg].Reg64)
1768	CPUMSetGuestDR7(pVCpu, paValues[iReg].Reg64);
1769	iReg++;
1770	}
1771
1772	/* Floating point state. */
1773	if (fWhat & CPUMCTX_EXTRN_X87)
1774	{
1775	Assert(pInput->Names[iReg] == HvX64RegisterFpMmx0);
1776	Assert(pInput->Names[iReg + 7] == HvX64RegisterFpMmx7);
1777	pCtx->pXStateR0->x87.aRegs[0].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1778	pCtx->pXStateR0->x87.aRegs[0].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1779	iReg++;
1780	pCtx->pXStateR0->x87.aRegs[1].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1781	pCtx->pXStateR0->x87.aRegs[1].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1782	iReg++;
1783	pCtx->pXStateR0->x87.aRegs[2].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1784	pCtx->pXStateR0->x87.aRegs[2].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1785	iReg++;
1786	pCtx->pXStateR0->x87.aRegs[3].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1787	pCtx->pXStateR0->x87.aRegs[3].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1788	iReg++;
1789	pCtx->pXStateR0->x87.aRegs[4].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1790	pCtx->pXStateR0->x87.aRegs[4].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1791	iReg++;
1792	pCtx->pXStateR0->x87.aRegs[5].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1793	pCtx->pXStateR0->x87.aRegs[5].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1794	iReg++;
1795	pCtx->pXStateR0->x87.aRegs[6].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1796	pCtx->pXStateR0->x87.aRegs[6].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1797	iReg++;
1798	pCtx->pXStateR0->x87.aRegs[7].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1799	pCtx->pXStateR0->x87.aRegs[7].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1800	iReg++;
1801
1802	Assert(pInput->Names[iReg] == HvX64RegisterFpControlStatus);
1803	pCtx->pXStateR0->x87.FCW = paValues[iReg].FpControlStatus.FpControl;
1804	pCtx->pXStateR0->x87.FSW = paValues[iReg].FpControlStatus.FpStatus;
1805	pCtx->pXStateR0->x87.FTW = paValues[iReg].FpControlStatus.FpTag
1806	/\| (paValues[iReg].FpControlStatus.Reserved << 8)/;
1807	pCtx->pXStateR0->x87.FOP = paValues[iReg].FpControlStatus.LastFpOp;
1808	pCtx->pXStateR0->x87.FPUIP = (uint32_t)paValues[iReg].FpControlStatus.LastFpRip;
1809	pCtx->pXStateR0->x87.CS = (uint16_t)(paValues[iReg].FpControlStatus.LastFpRip >> 32);
1810	pCtx->pXStateR0->x87.Rsrvd1 = (uint16_t)(paValues[iReg].FpControlStatus.LastFpRip >> 48);
1811	iReg++;
1812	}
1813
1814	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX))
1815	{
1816	Assert(pInput->Names[iReg] == HvX64RegisterXmmControlStatus);
1817	if (fWhat & CPUMCTX_EXTRN_X87)
1818	{
1819	pCtx->pXStateR0->x87.FPUDP = (uint32_t)paValues[iReg].XmmControlStatus.LastFpRdp;
1820	pCtx->pXStateR0->x87.DS = (uint16_t)(paValues[iReg].XmmControlStatus.LastFpRdp >> 32);
1821	pCtx->pXStateR0->x87.Rsrvd2 = (uint16_t)(paValues[iReg].XmmControlStatus.LastFpRdp >> 48);
1822	}
1823	pCtx->pXStateR0->x87.MXCSR = paValues[iReg].XmmControlStatus.XmmStatusControl;
1824	pCtx->pXStateR0->x87.MXCSR_MASK = paValues[iReg].XmmControlStatus.XmmStatusControlMask; /** @todo ??? (Isn't this an output field?) */
1825	iReg++;
1826	}
1827
1828	/* Vector state. */
1829	if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
1830	{
1831	Assert(pInput->Names[iReg] == HvX64RegisterXmm0);
1832	Assert(pInput->Names[iReg+15] == HvX64RegisterXmm15);
1833	pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1834	pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1835	iReg++;
1836	pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1837	pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1838	iReg++;
1839	pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1840	pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1841	iReg++;
1842	pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1843	pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1844	iReg++;
1845	pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1846	pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1847	iReg++;
1848	pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1849	pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1850	iReg++;
1851	pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1852	pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1853	iReg++;
1854	pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1855	pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1856	iReg++;
1857	pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1858	pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1859	iReg++;
1860	pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1861	pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1862	iReg++;
1863	pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1864	pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1865	iReg++;
1866	pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1867	pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1868	iReg++;
1869	pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1870	pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1871	iReg++;
1872	pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1873	pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1874	iReg++;
1875	pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1876	pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1877	iReg++;
1878	pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1879	pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1880	iReg++;
1881	}
1882
1883
1884	/* MSRs */
1885	// HvX64RegisterTsc - don't touch
1886	if (fWhat & CPUMCTX_EXTRN_EFER)
1887	{
1888	Assert(pInput->Names[iReg] == HvX64RegisterEfer);
1889	if (paValues[iReg].Reg64 != pCtx->msrEFER)
1890	{
1891	Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->msrEFER, paValues[iReg].Reg64));
1892	if ((paValues[iReg].Reg64 ^ pCtx->msrEFER) & MSR_K6_EFER_NXE)
1893	PGMNotifyNxeChanged(pVCpu, RT_BOOL(paValues[iReg].Reg64 & MSR_K6_EFER_NXE));
1894	pCtx->msrEFER = paValues[iReg].Reg64;
1895	fMaybeChangedMode = true;
1896	}
1897	iReg++;
1898	}
1899	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1900	{
1901	Assert(pInput->Names[iReg] == HvX64RegisterKernelGsBase);
1902	if (pCtx->msrKERNELGSBASE != paValues[iReg].Reg64)
1903	Log7(("NEM/%u: MSR KERNELGSBASE changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->msrKERNELGSBASE, paValues[iReg].Reg64));
1904	pCtx->msrKERNELGSBASE = paValues[iReg].Reg64;
1905	iReg++;
1906	}
1907	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1908	{
1909	Assert(pInput->Names[iReg] == HvX64RegisterSysenterCs);
1910	if (pCtx->SysEnter.cs != paValues[iReg].Reg64)
1911	Log7(("NEM/%u: MSR SYSENTER.CS changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->SysEnter.cs, paValues[iReg].Reg64));
1912	pCtx->SysEnter.cs = paValues[iReg].Reg64;
1913	iReg++;
1914
1915	Assert(pInput->Names[iReg] == HvX64RegisterSysenterEip);
1916	if (pCtx->SysEnter.eip != paValues[iReg].Reg64)
1917	Log7(("NEM/%u: MSR SYSENTER.EIP changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->SysEnter.eip, paValues[iReg].Reg64));
1918	pCtx->SysEnter.eip = paValues[iReg].Reg64;
1919	iReg++;
1920
1921	Assert(pInput->Names[iReg] == HvX64RegisterSysenterEsp);
1922	if (pCtx->SysEnter.esp != paValues[iReg].Reg64)
1923	Log7(("NEM/%u: MSR SYSENTER.ESP changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->SysEnter.esp, paValues[iReg].Reg64));
1924	pCtx->SysEnter.esp = paValues[iReg].Reg64;
1925	iReg++;
1926	}
1927	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1928	{
1929	Assert(pInput->Names[iReg] == HvX64RegisterStar);
1930	if (pCtx->msrSTAR != paValues[iReg].Reg64)
1931	Log7(("NEM/%u: MSR STAR changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->msrSTAR, paValues[iReg].Reg64));
1932	pCtx->msrSTAR = paValues[iReg].Reg64;
1933	iReg++;
1934
1935	Assert(pInput->Names[iReg] == HvX64RegisterLstar);
1936	if (pCtx->msrLSTAR != paValues[iReg].Reg64)
1937	Log7(("NEM/%u: MSR LSTAR changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->msrLSTAR, paValues[iReg].Reg64));
1938	pCtx->msrLSTAR = paValues[iReg].Reg64;
1939	iReg++;
1940
1941	Assert(pInput->Names[iReg] == HvX64RegisterCstar);
1942	if (pCtx->msrCSTAR != paValues[iReg].Reg64)
1943	Log7(("NEM/%u: MSR CSTAR changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->msrCSTAR, paValues[iReg].Reg64));
1944	pCtx->msrCSTAR = paValues[iReg].Reg64;
1945	iReg++;
1946
1947	Assert(pInput->Names[iReg] == HvX64RegisterSfmask);
1948	if (pCtx->msrSFMASK != paValues[iReg].Reg64)
1949	Log7(("NEM/%u: MSR SFMASK changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->msrSFMASK, paValues[iReg].Reg64));
1950	pCtx->msrSFMASK = paValues[iReg].Reg64;
1951	iReg++;
1952	}
1953	bool fUpdateApicBase = false;
1954	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1955	{
1956	Assert(pInput->Names[iReg] == HvX64RegisterApicBase);
1957	const uint64_t uOldBase = APICGetBaseMsrNoCheck(pVCpu);
1958	if (paValues[iReg].Reg64 != uOldBase)
1959	{
1960	Log7(("NEM/%u: MSR APICBase changed %RX64 -> %RX64 (%RX64)\n",
1961	pVCpu->idCpu, uOldBase, paValues[iReg].Reg64, paValues[iReg].Reg64 ^ uOldBase));
1962	VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, paValues[iReg].Reg64);
1963	if (rc2 == VINF_CPUM_R3_MSR_WRITE)
1964	{
1965	pVCpu->nem.s.uPendingApicBase = paValues[iReg].Reg64;
1966	fUpdateApicBase = true;
1967	}
1968	else
1969	AssertLogRelMsg(rc2 == VINF_SUCCESS, ("rc2=%Rrc [%#RX64]\n", VBOXSTRICTRC_VAL(rc2), paValues[iReg].Reg64));
1970	}
1971	iReg++;
1972
1973	Assert(pInput->Names[iReg] == HvX64RegisterPat);
1974	if (pCtx->msrPAT != paValues[iReg].Reg64)
1975	Log7(("NEM/%u: MSR PAT changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtx->msrPAT, paValues[iReg].Reg64));
1976	pCtx->msrPAT = paValues[iReg].Reg64;
1977	iReg++;
1978
1979	#if 0 /def LOG_ENABLED/ /** @todo something's wrong with HvX64RegisterMtrrCap? (AMD) */
1980	Assert(pInput->Names[iReg] == HvX64RegisterMtrrCap);
1981	if (paValues[iReg].Reg64 != CPUMGetGuestIa32MtrrCap(pVCpu))
1982	Log7(("NEM/%u: MSR MTRR_CAP changed %RX64 -> %RX64 (!!)\n", pVCpu->idCpu, CPUMGetGuestIa32MtrrCap(pVCpu), paValues[iReg].Reg64));
1983	iReg++;
1984	#endif
1985
1986	PCPUMCTXMSRS pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1987	Assert(pInput->Names[iReg] == HvX64RegisterMtrrDefType);
1988	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrDefType )
1989	Log7(("NEM/%u: MSR MTRR_DEF_TYPE changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrDefType, paValues[iReg].Reg64));
1990	pCtxMsrs->msr.MtrrDefType = paValues[iReg].Reg64;
1991	iReg++;
1992
1993	/** @todo we dont keep state for HvX64RegisterMtrrPhysBaseX and HvX64RegisterMtrrPhysMaskX */
1994
1995	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix64k00000);
1996	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix64K_00000 )
1997	Log7(("NEM/%u: MSR MTRR_FIX16K_00000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix64K_00000, paValues[iReg].Reg64));
1998	pCtxMsrs->msr.MtrrFix64K_00000 = paValues[iReg].Reg64;
1999	iReg++;
2000
2001	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix16k80000);
2002	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix16K_80000 )
2003	Log7(("NEM/%u: MSR MTRR_FIX16K_80000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix16K_80000, paValues[iReg].Reg64));
2004	pCtxMsrs->msr.MtrrFix16K_80000 = paValues[iReg].Reg64;
2005	iReg++;
2006
2007	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix16kA0000);
2008	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix16K_A0000 )
2009	Log7(("NEM/%u: MSR MTRR_FIX16K_A0000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix16K_A0000, paValues[iReg].Reg64));
2010	pCtxMsrs->msr.MtrrFix16K_A0000 = paValues[iReg].Reg64;
2011	iReg++;
2012
2013	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix4kC0000);
2014	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix4K_C0000 )
2015	Log7(("NEM/%u: MSR MTRR_FIX16K_C0000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix4K_C0000, paValues[iReg].Reg64));
2016	pCtxMsrs->msr.MtrrFix4K_C0000 = paValues[iReg].Reg64;
2017	iReg++;
2018
2019	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix4kC8000);
2020	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix4K_C8000 )
2021	Log7(("NEM/%u: MSR MTRR_FIX16K_C8000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix4K_C8000, paValues[iReg].Reg64));
2022	pCtxMsrs->msr.MtrrFix4K_C8000 = paValues[iReg].Reg64;
2023	iReg++;
2024
2025	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix4kD0000);
2026	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix4K_D0000 )
2027	Log7(("NEM/%u: MSR MTRR_FIX16K_D0000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix4K_D0000, paValues[iReg].Reg64));
2028	pCtxMsrs->msr.MtrrFix4K_D0000 = paValues[iReg].Reg64;
2029	iReg++;
2030
2031	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix4kD8000);
2032	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix4K_D8000 )
2033	Log7(("NEM/%u: MSR MTRR_FIX16K_D8000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix4K_D8000, paValues[iReg].Reg64));
2034	pCtxMsrs->msr.MtrrFix4K_D8000 = paValues[iReg].Reg64;
2035	iReg++;
2036
2037	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix4kE0000);
2038	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix4K_E0000 )
2039	Log7(("NEM/%u: MSR MTRR_FIX16K_E0000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix4K_E0000, paValues[iReg].Reg64));
2040	pCtxMsrs->msr.MtrrFix4K_E0000 = paValues[iReg].Reg64;
2041	iReg++;
2042
2043	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix4kE8000);
2044	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix4K_E8000 )
2045	Log7(("NEM/%u: MSR MTRR_FIX16K_E8000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix4K_E8000, paValues[iReg].Reg64));
2046	pCtxMsrs->msr.MtrrFix4K_E8000 = paValues[iReg].Reg64;
2047	iReg++;
2048
2049	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix4kF0000);
2050	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix4K_F0000 )
2051	Log7(("NEM/%u: MSR MTRR_FIX16K_F0000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix4K_F0000, paValues[iReg].Reg64));
2052	pCtxMsrs->msr.MtrrFix4K_F0000 = paValues[iReg].Reg64;
2053	iReg++;
2054
2055	Assert(pInput->Names[iReg] == HvX64RegisterMtrrFix4kF8000);
2056	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MtrrFix4K_F8000 )
2057	Log7(("NEM/%u: MSR MTRR_FIX16K_F8000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix4K_F8000, paValues[iReg].Reg64));
2058	pCtxMsrs->msr.MtrrFix4K_F8000 = paValues[iReg].Reg64;
2059	iReg++;
2060
2061	Assert(pInput->Names[iReg] == HvX64RegisterTscAux);
2062	if (paValues[iReg].Reg64 != pCtxMsrs->msr.TscAux )
2063	Log7(("NEM/%u: MSR TSC_AUX changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.TscAux, paValues[iReg].Reg64));
2064	pCtxMsrs->msr.TscAux = paValues[iReg].Reg64;
2065	iReg++;
2066
2067	#if 0 /** @todo why can't we even read HvX64RegisterIa32MiscEnable? */
2068	if (enmCpuVendor != CPUMCPUVENDOR_AMD)
2069	{
2070	Assert(pInput->Names[iReg] == HvX64RegisterIa32MiscEnable);
2071	if (paValues[iReg].Reg64 != pCtxMsrs->msr.MiscEnable)
2072	Log7(("NEM/%u: MSR MISC_ENABLE changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MiscEnable, paValues[iReg].Reg64));
2073	pCtxMsrs->msr.MiscEnable = paValues[iReg].Reg64;
2074	iReg++;
2075	}
2076	#endif
2077	#ifdef LOG_ENABLED
2078	if (enmCpuVendor != CPUMCPUVENDOR_AMD)
2079	{
2080	Assert(pInput->Names[iReg] == HvX64RegisterIa32FeatureControl);
2081	if (paValues[iReg].Reg64 != CPUMGetGuestIa32FeatureControl(pVCpu))
2082	Log7(("NEM/%u: MSR FEATURE_CONTROL changed %RX64 -> %RX64 (!!)\n", pVCpu->idCpu, CPUMGetGuestIa32FeatureControl(pVCpu), paValues[iReg].Reg64));
2083	iReg++;
2084	}
2085	#endif
2086	}
2087
2088	/* Interruptibility. */
2089	if (fWhat & (CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI))
2090	{
2091	Assert(pInput->Names[iReg] == HvRegisterInterruptState);
2092	Assert(pInput->Names[iReg + 1] == HvX64RegisterRip);
2093
2094	if (!(pCtx->fExtrn & CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT))
2095	{
2096	pVCpu->nem.s.fLastInterruptShadow = paValues[iReg].InterruptState.InterruptShadow;
2097	if (paValues[iReg].InterruptState.InterruptShadow)
2098	EMSetInhibitInterruptsPC(pVCpu, paValues[iReg + 1].Reg64);
2099	else
2100	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2101	}
2102
2103	if (!(pCtx->fExtrn & CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI))
2104	{
2105	if (paValues[iReg].InterruptState.NmiMasked)
2106	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2107	else
2108	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2109	}
2110
2111	fWhat \|= CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI;
2112	iReg += 2;
2113	}
2114
2115	/* Event injection. */
2116	/// @todo HvRegisterPendingInterruption
2117	Assert(pInput->Names[iReg] == HvRegisterPendingInterruption);
2118	if (paValues[iReg].PendingInterruption.InterruptionPending)
2119	{
2120	Log7(("PendingInterruption: type=%u vector=%#x errcd=%RTbool/%#x instr-len=%u nested=%u\n",
2121	paValues[iReg].PendingInterruption.InterruptionType, paValues[iReg].PendingInterruption.InterruptionVector,
2122	paValues[iReg].PendingInterruption.DeliverErrorCode, paValues[iReg].PendingInterruption.ErrorCode,
2123	paValues[iReg].PendingInterruption.InstructionLength, paValues[iReg].PendingInterruption.NestedEvent));
2124	AssertMsg((paValues[iReg].PendingInterruption.AsUINT64 & UINT64_C(0xfc00)) == 0,
2125	("%#RX64\n", paValues[iReg].PendingInterruption.AsUINT64));
2126	}
2127
2128	/// @todo HvRegisterPendingEvent0
2129	/// @todo HvRegisterPendingEvent1
2130
2131	/* Almost done, just update extrn flags and maybe change PGM mode. */
2132	pCtx->fExtrn &= ~fWhat;
2133
2134	/* Typical. */
2135	if (!fMaybeChangedMode && !fFlushTlb && !fUpdateApicBase)
2136	return VINF_SUCCESS;
2137
2138	/*
2139	* Slow.
2140	*/
2141	int rc = VINF_SUCCESS;
2142	if (fMaybeChangedMode)
2143	{
2144	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2145	if (rc == VINF_PGM_CHANGE_MODE)
2146	{
2147	LogFlow(("nemR0WinImportState: -> VERR_NEM_CHANGE_PGM_MODE!\n"));
2148	return VERR_NEM_CHANGE_PGM_MODE;
2149	}
2150	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
2151	}
2152
2153	if (fFlushTlb)
2154	{
2155	LogFlow(("nemR0WinImportState: -> VERR_NEM_FLUSH_TLB!\n"));
2156	rc = VERR_NEM_FLUSH_TLB; /* Calling PGMFlushTLB w/o long jump setup doesn't work, ring-3 does it. */
2157	}
2158
2159	if (fUpdateApicBase && rc == VINF_SUCCESS)
2160	{
2161	LogFlow(("nemR0WinImportState: -> VERR_NEM_UPDATE_APIC_BASE!\n"));
2162	rc = VERR_NEM_UPDATE_APIC_BASE;
2163	}
2164
2165	return rc;
2166	}
2167
2168
2169	/**
2170	* Import the state from the native API (back to CPUMCTX).
2171	*
2172	* @returns VBox status code
2173	* @param pGVM The ring-0 VM handle.
2174	* @param pVM The cross context VM handle.
2175	* @param idCpu The calling EMT. Necessary for getting the
2176	* hypercall page and arguments.
2177	* @param fWhat What to import, CPUMCTX_EXTRN_XXX. Set
2178	* CPUMCTX_EXTERN_ALL for everything.
2179	*/
2180	VMMR0_INT_DECL(int) NEMR0ImportState(PGVM pGVM, PVM pVM, VMCPUID idCpu, uint64_t fWhat)
2181	{
2182	/*
2183	* Validate the call.
2184	*/
2185	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
2186	if (RT_SUCCESS(rc))
2187	{
2188	PVMCPU pVCpu = &pVM->aCpus[idCpu];
2189	PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
2190	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
2191
2192	/*
2193	* Call worker.
2194	*/
2195	rc = nemR0WinImportState(pGVM, pGVCpu, CPUMQueryGuestCtxPtr(pVCpu), fWhat);
2196	}
2197	return rc;
2198	}
2199
2200
2201	VMMR0_INT_DECL(VBOXSTRICTRC) NEMR0RunGuestCode(PGVM pGVM, VMCPUID idCpu)
2202	{
2203	#ifdef NEM_WIN_USE_OUR_OWN_RUN_API
2204	PVM pVM = pGVM->pVM;
2205	return nemHCWinRunGC(pVM, &pVM->aCpus[idCpu], pGVM, &pGVM->aCpus[idCpu]);
2206	#else
2207	RT_NOREF(pGVM, idCpu);
2208	return VERR_NOT_IMPLEMENTED;
2209	#endif
2210	}
2211
2212
2213	/**
2214	* Updates statistics in the VM structure.
2215	*
2216	* @returns VBox status code.
2217	* @param pGVM The ring-0 VM handle.
2218	* @param pVM The cross context VM handle.
2219	* @param idCpu The calling EMT, or NIL. Necessary for getting the hypercall
2220	* page and arguments.
2221	*/
2222	VMMR0_INT_DECL(int) NEMR0UpdateStatistics(PGVM pGVM, PVM pVM, VMCPUID idCpu)
2223	{
2224	/*
2225	* Validate the call.
2226	*/
2227	int rc;
2228	if (idCpu == NIL_VMCPUID)
2229	rc = GVMMR0ValidateGVMandVM(pGVM, pVM);
2230	else
2231	rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
2232	if (RT_SUCCESS(rc))
2233	{
2234	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
2235
2236	PNEMR0HYPERCALLDATA pHypercallData = idCpu != NIL_VMCPUID
2237	? &pGVM->aCpus[idCpu].nem.s.HypercallData
2238	: &pGVM->nem.s.HypercallData;
2239	if ( RT_VALID_PTR(pHypercallData->pbPage)
2240	&& pHypercallData->HCPhysPage != NIL_RTHCPHYS)
2241	{
2242	if (idCpu == NIL_VMCPUID)
2243	rc = RTCritSectEnter(&pGVM->nem.s.HypercallDataCritSect);
2244	if (RT_SUCCESS(rc))
2245	{
2246	/*
2247	* Query the memory statistics for the partition.
2248	*/
2249	HV_INPUT_GET_MEMORY_BALANCE pInput = (HV_INPUT_GET_MEMORY_BALANCE )pHypercallData->pbPage;
2250	pInput->TargetPartitionId = pGVM->nem.s.idHvPartition;
2251	pInput->ProximityDomainInfo.Flags.ProximityPreferred = 0;
2252	pInput->ProximityDomainInfo.Flags.ProxyimityInfoValid = 0;
2253	pInput->ProximityDomainInfo.Flags.Reserved = 0;
2254	pInput->ProximityDomainInfo.Id = 0;
2255
2256	HV_OUTPUT_GET_MEMORY_BALANCE pOutput = (HV_OUTPUT_GET_MEMORY_BALANCE )(pInput + 1);
2257	RT_ZERO(*pOutput);
2258
2259	uint64_t uResult = g_pfnHvlInvokeHypercall(HvCallGetMemoryBalance,
2260	pHypercallData->HCPhysPage,
2261	pHypercallData->HCPhysPage + sizeof(*pInput));
2262	if (uResult == HV_STATUS_SUCCESS)
2263	{
2264	pVM->nem.s.R0Stats.cPagesAvailable = pOutput->PagesAvailable;
2265	pVM->nem.s.R0Stats.cPagesInUse = pOutput->PagesInUse;
2266	rc = VINF_SUCCESS;
2267	}
2268	else
2269	{
2270	LogRel(("HvCallGetMemoryBalance -> %#RX64 (%#RX64 %#RX64)!!\n",
2271	uResult, pOutput->PagesAvailable, pOutput->PagesInUse));
2272	rc = VERR_NEM_IPE_0;
2273	}
2274
2275	if (idCpu == NIL_VMCPUID)
2276	RTCritSectLeave(&pGVM->nem.s.HypercallDataCritSect);
2277	}
2278	}
2279	else
2280	rc = VERR_WRONG_ORDER;
2281	}
2282	return rc;
2283	}
2284

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source: vbox/trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp@ 72466

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