VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp@ 71222

Last change on this file since 71222 was 71222, checked in by vboxsync, 7 years ago

NEM/win,VMM,PGM: Ported NEM runloop to ring-0. bugref:9044
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1/* $Id: NEMR0Native-win.cpp 71222 2018-03-05 22:07:48Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager, native ring-0 Windows backend.
4 */
5
6/*
7 * Copyright (C) 2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_NEM
23#include <iprt/nt/nt.h>
24#include <iprt/nt/hyperv.h>
25#include <iprt/nt/vid.h>
26#include <winerror.h>
27
28#include <VBox/vmm/nem.h>
29#include <VBox/vmm/iem.h>
30#include <VBox/vmm/em.h>
31#include <VBox/vmm/apic.h>
32#include "NEMInternal.h"
33#include <VBox/vmm/gvm.h>
34#include <VBox/vmm/vm.h>
35#include <VBox/vmm/gvmm.h>
36#include <VBox/param.h>
37
38#include <iprt/dbg.h>
39#include <iprt/memobj.h>
40#include <iprt/string.h>
41
42
43/* Assert compile context sanity. */
44#ifndef RT_OS_WINDOWS
45# error "Windows only file!"
46#endif
47#ifndef RT_ARCH_AMD64
48# error "AMD64 only file!"
49#endif
50
51
52/*********************************************************************************************************************************
53* Internal Functions *
54*********************************************************************************************************************************/
55typedef uint32_t DWORD; /* for winerror.h constants */
56
57
58/*********************************************************************************************************************************
59* Global Variables *
60*********************************************************************************************************************************/
61static uint64_t (*g_pfnHvlInvokeHypercall)(uint64_t uCallInfo, uint64_t HCPhysInput, uint64_t HCPhysOutput);
62
63
64/*********************************************************************************************************************************
65* Internal Functions *
66*********************************************************************************************************************************/
67NEM_TMPL_STATIC int nemR0WinMapPages(PGVM pGVM, PVM pVM, PGVMCPU pGVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
68 uint32_t cPages, uint32_t fFlags);
69NEM_TMPL_STATIC int nemR0WinUnmapPages(PGVM pGVM, PGVMCPU pGVCpu, RTGCPHYS GCPhys, uint32_t cPages);
70NEM_TMPL_STATIC int nemR0WinExportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx);
71NEM_TMPL_STATIC int nemR0WinImportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx, uint64_t fWhat);
72DECLINLINE(NTSTATUS) nemR0NtPerformIoControl(PGVM pGVM, uint32_t uFunction, void *pvInput, uint32_t cbInput,
73 void *pvOutput, uint32_t cbOutput);
74
75
76/*
77 * Instantate the code we share with ring-0.
78 */
79#include "../VMMAll/NEMAllNativeTemplate-win.cpp.h"
80
81
82/**
83 * Called by NEMR3Init to make sure we've got what we need.
84 *
85 * @returns VBox status code.
86 * @param pGVM The ring-0 VM handle.
87 * @param pVM The cross context VM handle.
88 * @thread EMT(0)
89 */
90VMMR0_INT_DECL(int) NEMR0InitVM(PGVM pGVM, PVM pVM)
91{
92 AssertCompile(sizeof(pGVM->nem.s) <= sizeof(pGVM->nem.padding));
93 AssertCompile(sizeof(pGVM->aCpus[0].nem.s) <= sizeof(pGVM->aCpus[0].nem.padding));
94
95 int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, 0);
96 AssertRCReturn(rc, rc);
97
98 /*
99 * We want to perform hypercalls here. The NT kernel started to expose a very low
100 * level interface to do this thru somewhere between build 14271 and 16299. Since
101 * we need build 17083 to get anywhere at all, the exact build is not relevant here.
102 */
103 RTDBGKRNLINFO hKrnlInfo;
104 rc = RTR0DbgKrnlInfoOpen(&hKrnlInfo, 0);
105 if (RT_SUCCESS(rc))
106 {
107 rc = RTR0DbgKrnlInfoQuerySymbol(hKrnlInfo, NULL, "HvlInvokeHypercall", (void **)&g_pfnHvlInvokeHypercall);
108 RTR0DbgKrnlInfoRelease(hKrnlInfo);
109 if (RT_SUCCESS(rc))
110 {
111 /*
112 * Allocate a page for each VCPU to place hypercall data on.
113 */
114 for (VMCPUID i = 0; i < pGVM->cCpus; i++)
115 {
116 PGVMCPU pGVCpu = &pGVM->aCpus[i];
117 rc = RTR0MemObjAllocPage(&pGVCpu->nem.s.hHypercallDataMemObj, PAGE_SIZE, false /*fExecutable*/);
118 if (RT_SUCCESS(rc))
119 {
120 pGVCpu->nem.s.HCPhysHypercallData = RTR0MemObjGetPagePhysAddr(pGVCpu->nem.s.hHypercallDataMemObj, 0 /*iPage*/);
121 pGVCpu->nem.s.pbHypercallData = (uint8_t *)RTR0MemObjAddress(pGVCpu->nem.s.hHypercallDataMemObj);
122 AssertStmt(pGVCpu->nem.s.HCPhysHypercallData != NIL_RTHCPHYS, rc = VERR_INTERNAL_ERROR_3);
123 AssertStmt(pGVCpu->nem.s.pbHypercallData, rc = VERR_INTERNAL_ERROR_3);
124 }
125 else
126 pGVCpu->nem.s.hHypercallDataMemObj = NIL_RTR0MEMOBJ;
127 if (RT_FAILURE(rc))
128 {
129 /* bail. */
130 do
131 {
132 RTR0MemObjFree(pGVCpu->nem.s.hHypercallDataMemObj, true /*fFreeMappings*/);
133 pGVCpu->nem.s.hHypercallDataMemObj = NIL_RTR0MEMOBJ;
134 pGVCpu->nem.s.HCPhysHypercallData = NIL_RTHCPHYS;
135 pGVCpu->nem.s.pbHypercallData = NULL;
136 } while (i-- > 0);
137 return rc;
138 }
139 }
140 /*
141 * So far, so good.
142 */
143 return rc;
144 }
145
146 rc = VERR_NEM_MISSING_KERNEL_API;
147 }
148
149 RT_NOREF(pGVM, pVM);
150 return rc;
151}
152
153
154/**
155 * Perform an I/O control operation on the partition handle (VID.SYS).
156 *
157 * @returns NT status code.
158 * @param pGVM The ring-0 VM structure.
159 * @param uFunction The function to perform.
160 * @param pvInput The input buffer. This must point within the VM
161 * structure so we can easily convert to a ring-3
162 * pointer if necessary.
163 * @param cbInput The size of the input. @a pvInput must be NULL when
164 * zero.
165 * @param pvOutput The output buffer. This must also point within the
166 * VM structure for ring-3 pointer magic.
167 * @param cbOutput The size of the output. @a pvOutput must be NULL
168 * when zero.
169 */
170DECLINLINE(NTSTATUS) nemR0NtPerformIoControl(PGVM pGVM, uint32_t uFunction, void *pvInput, uint32_t cbInput,
171 void *pvOutput, uint32_t cbOutput)
172{
173#ifdef RT_STRICT
174 /*
175 * Input and output parameters are part of the VM CPU structure.
176 */
177 PVM pVM = pGVM->pVM;
178 size_t const cbVM = RT_UOFFSETOF(VM, aCpus[pGVM->cCpus]);
179 if (pvInput)
180 AssertReturn(((uintptr_t)pvInput + cbInput) - (uintptr_t)pVM <= cbVM, VERR_INVALID_PARAMETER);
181 if (pvOutput)
182 AssertReturn(((uintptr_t)pvOutput + cbOutput) - (uintptr_t)pVM <= cbVM, VERR_INVALID_PARAMETER);
183#endif
184
185 int32_t rcNt = STATUS_UNSUCCESSFUL;
186 int rc = SUPR0IoCtlPerform(pGVM->nem.s.pIoCtlCtx, uFunction,
187 pvInput,
188 pvInput ? (uintptr_t)pvInput + pGVM->nem.s.offRing3ConversionDelta : NIL_RTR3PTR,
189 cbInput,
190 pvOutput,
191 pvOutput ? (uintptr_t)pvOutput + pGVM->nem.s.offRing3ConversionDelta : NIL_RTR3PTR,
192 cbOutput,
193 &rcNt);
194 if (RT_SUCCESS(rc) || !NT_SUCCESS((NTSTATUS)rcNt))
195 return (NTSTATUS)rcNt;
196 return STATUS_UNSUCCESSFUL;
197}
198
199
200/**
201 * 2nd part of the initialization, after we've got a partition handle.
202 *
203 * @returns VBox status code.
204 * @param pGVM The ring-0 VM handle.
205 * @param pVM The cross context VM handle.
206 * @thread EMT(0)
207 */
208VMMR0_INT_DECL(int) NEMR0InitVMPart2(PGVM pGVM, PVM pVM)
209{
210 int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, 0);
211 AssertRCReturn(rc, rc);
212 SUPR0Printf("NEMR0InitVMPart2\n"); LogRel(("2: NEMR0InitVMPart2\n"));
213
214 /*
215 * Copy and validate the I/O control information from ring-3.
216 */
217 NEMWINIOCTL Copy = pVM->nem.s.IoCtlGetHvPartitionId;
218 AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
219 AssertLogRelReturn(Copy.cbInput == 0, VERR_NEM_INIT_FAILED);
220 AssertLogRelReturn(Copy.cbOutput == sizeof(HV_PARTITION_ID), VERR_NEM_INIT_FAILED);
221 pGVM->nem.s.IoCtlGetHvPartitionId = Copy;
222
223 Copy = pVM->nem.s.IoCtlStartVirtualProcessor;
224 AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
225 AssertLogRelReturn(Copy.cbInput == sizeof(HV_VP_INDEX), VERR_NEM_INIT_FAILED);
226 AssertLogRelReturn(Copy.cbOutput == 0, VERR_NEM_INIT_FAILED);
227 AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, VERR_NEM_INIT_FAILED);
228 pGVM->nem.s.IoCtlStartVirtualProcessor = Copy;
229
230 Copy = pVM->nem.s.IoCtlStopVirtualProcessor;
231 AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
232 AssertLogRelReturn(Copy.cbInput == sizeof(HV_VP_INDEX), VERR_NEM_INIT_FAILED);
233 AssertLogRelReturn(Copy.cbOutput == 0, VERR_NEM_INIT_FAILED);
234 AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, VERR_NEM_INIT_FAILED);
235 AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlStartVirtualProcessor.uFunction, VERR_NEM_INIT_FAILED);
236 pGVM->nem.s.IoCtlStopVirtualProcessor = Copy;
237
238 Copy = pVM->nem.s.IoCtlMessageSlotHandleAndGetNext;
239 AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
240 AssertLogRelReturn(Copy.cbInput == sizeof(VID_IOCTL_INPUT_MESSAGE_SLOT_HANDLE_AND_GET_NEXT), VERR_NEM_INIT_FAILED);
241 AssertLogRelReturn(Copy.cbOutput == 0, VERR_NEM_INIT_FAILED);
242 AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, VERR_NEM_INIT_FAILED);
243 AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlStartVirtualProcessor.uFunction, VERR_NEM_INIT_FAILED);
244 AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlStopVirtualProcessor.uFunction, VERR_NEM_INIT_FAILED);
245 pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext = Copy;
246
247 /*
248 * Setup of an I/O control context for the partition handle for later use.
249 */
250 rc = SUPR0IoCtlSetupForHandle(pGVM->pSession, pVM->nem.s.hPartitionDevice, 0, &pGVM->nem.s.pIoCtlCtx);
251 AssertLogRelRCReturn(rc, rc);
252 pGVM->nem.s.offRing3ConversionDelta = (uintptr_t)pVM->pVMR3 - (uintptr_t)pGVM->pVM;
253
254 /*
255 * Get the partition ID.
256 */
257 PVMCPU pVCpu = &pGVM->pVM->aCpus[0];
258 NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, NULL, 0,
259 &pVCpu->nem.s.uIoCtlBuf.idPartition, sizeof(pVCpu->nem.s.uIoCtlBuf.idPartition));
260 AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("IoCtlGetHvPartitionId failed: %#x\n", rcNt), VERR_NEM_INIT_FAILED);
261 pGVM->nem.s.idHvPartition = pVCpu->nem.s.uIoCtlBuf.idPartition;
262 AssertLogRelMsgReturn(pGVM->nem.s.idHvPartition == pVM->nem.s.idHvPartition,
263 ("idHvPartition mismatch: r0=%#RX64, r3=%#RX64\n", pGVM->nem.s.idHvPartition, pVM->nem.s.idHvPartition),
264 VERR_NEM_INIT_FAILED);
265
266
267 return rc;
268}
269
270
271/**
272 * Cleanup the NEM parts of the VM in ring-0.
273 *
274 * This is always called and must deal the state regardless of whether
275 * NEMR0InitVM() was called or not. So, take care here.
276 *
277 * @param pGVM The ring-0 VM handle.
278 */
279VMMR0_INT_DECL(void) NEMR0CleanupVM(PGVM pGVM)
280{
281 pGVM->nem.s.idHvPartition = HV_PARTITION_ID_INVALID;
282
283 /* Clean up I/O control context. */
284 if (pGVM->nem.s.pIoCtlCtx)
285 {
286 int rc = SUPR0IoCtlCleanup(pGVM->nem.s.pIoCtlCtx);
287 AssertRC(rc);
288 pGVM->nem.s.pIoCtlCtx = NULL;
289 }
290
291 /* Free the hypercall pages. */
292 VMCPUID i = pGVM->cCpus;
293 while (i-- > 0)
294 {
295 PGVMCPU pGVCpu = &pGVM->aCpus[i];
296 if (pGVCpu->nem.s.pbHypercallData)
297 {
298 pGVCpu->nem.s.pbHypercallData = NULL;
299 int rc = RTR0MemObjFree(pGVCpu->nem.s.hHypercallDataMemObj, true /*fFreeMappings*/);
300 AssertRC(rc);
301 }
302 pGVCpu->nem.s.hHypercallDataMemObj = NIL_RTR0MEMOBJ;
303 pGVCpu->nem.s.HCPhysHypercallData = NIL_RTHCPHYS;
304 }
305}
306
307
308#if 0 /* for debugging GPA unmapping. */
309static int nemR3WinDummyReadGpa(PGVM pGVM, PGVMCPU pGVCpu, RTGCPHYS GCPhys)
310{
311 PHV_INPUT_READ_GPA pIn = (PHV_INPUT_READ_GPA)pGVCpu->nem.s.pbHypercallData;
312 PHV_OUTPUT_READ_GPA pOut = (PHV_OUTPUT_READ_GPA)(pIn + 1);
313 pIn->PartitionId = pGVM->nem.s.idHvPartition;
314 pIn->VpIndex = pGVCpu->idCpu;
315 pIn->ByteCount = 0x10;
316 pIn->BaseGpa = GCPhys;
317 pIn->ControlFlags.AsUINT64 = 0;
318 pIn->ControlFlags.CacheType = HvCacheTypeX64WriteCombining;
319 memset(pOut, 0xfe, sizeof(*pOut));
320 uint64_t volatile uResult = g_pfnHvlInvokeHypercall(HvCallReadGpa, pGVCpu->nem.s.HCPhysHypercallData,
321 pGVCpu->nem.s.HCPhysHypercallData + sizeof(*pIn));
322 LogRel(("nemR3WinDummyReadGpa: %RGp -> %#RX64; code=%u rsvd=%u abData=%.16Rhxs\n",
323 GCPhys, uResult, pOut->AccessResult.ResultCode, pOut->AccessResult.Reserved, pOut->Data));
324 __debugbreak();
325
326 return uResult != 0 ? VERR_READ_ERROR : VINF_SUCCESS;
327}
328#endif
329
330
331/**
332 * Worker for NEMR0MapPages and others.
333 */
334NEM_TMPL_STATIC int nemR0WinMapPages(PGVM pGVM, PVM pVM, PGVMCPU pGVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
335 uint32_t cPages, uint32_t fFlags)
336{
337 /*
338 * Validate.
339 */
340 AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
341
342 AssertReturn(cPages > 0, VERR_OUT_OF_RANGE);
343 AssertReturn(cPages <= NEM_MAX_MAP_PAGES, VERR_OUT_OF_RANGE);
344 AssertReturn(!(fFlags & ~(HV_MAP_GPA_MAYBE_ACCESS_MASK & ~HV_MAP_GPA_DUNNO_ACCESS)), VERR_INVALID_FLAGS);
345 AssertMsgReturn(!(GCPhysDst & X86_PAGE_OFFSET_MASK), ("GCPhysDst=%RGp\n", GCPhysDst), VERR_OUT_OF_RANGE);
346 AssertReturn(GCPhysDst < _1E, VERR_OUT_OF_RANGE);
347 if (GCPhysSrc != GCPhysDst)
348 {
349 AssertMsgReturn(!(GCPhysSrc & X86_PAGE_OFFSET_MASK), ("GCPhysSrc=%RGp\n", GCPhysSrc), VERR_OUT_OF_RANGE);
350 AssertReturn(GCPhysSrc < _1E, VERR_OUT_OF_RANGE);
351 }
352
353 /*
354 * Compose and make the hypercall.
355 * Ring-3 is not allowed to fill in the host physical addresses of the call.
356 */
357 HV_INPUT_MAP_GPA_PAGES *pMapPages = (HV_INPUT_MAP_GPA_PAGES *)pGVCpu->nem.s.pbHypercallData;
358 AssertPtrReturn(pMapPages, VERR_INTERNAL_ERROR_3);
359 pMapPages->TargetPartitionId = pGVM->nem.s.idHvPartition;
360 pMapPages->TargetGpaBase = GCPhysDst >> X86_PAGE_SHIFT;
361 pMapPages->MapFlags = fFlags;
362 pMapPages->u32ExplicitPadding = 0;
363 for (uint32_t iPage = 0; iPage < cPages; iPage++, GCPhysSrc += X86_PAGE_SIZE)
364 {
365 RTHCPHYS HCPhys = NIL_RTGCPHYS;
366 int rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysSrc, &HCPhys);
367 AssertRCReturn(rc, rc);
368 pMapPages->PageList[iPage] = HCPhys >> X86_PAGE_SHIFT;
369 }
370
371 uint64_t uResult = g_pfnHvlInvokeHypercall(HvCallMapGpaPages | ((uint64_t)cPages << 32),
372 pGVCpu->nem.s.HCPhysHypercallData, 0);
373 Log6(("NEMR0MapPages: %RGp/%RGp L %u prot %#x -> %#RX64\n",
374 GCPhysDst, GCPhysSrc - cPages * X86_PAGE_SIZE, cPages, fFlags, uResult));
375 if (uResult == ((uint64_t)cPages << 32))
376 return VINF_SUCCESS;
377
378 LogRel(("g_pfnHvlInvokeHypercall/MapGpaPages -> %#RX64\n", uResult));
379 return VERR_NEM_MAP_PAGES_FAILED;
380}
381
382
383/**
384 * Maps pages into the guest physical address space.
385 *
386 * Generally the caller will be under the PGM lock already, so no extra effort
387 * is needed to make sure all changes happens under it.
388 *
389 * @returns VBox status code.
390 * @param pGVM The ring-0 VM handle.
391 * @param pVM The cross context VM handle.
392 * @param idCpu The calling EMT. Necessary for getting the
393 * hypercall page and arguments.
394 * @thread EMT(idCpu)
395 */
396VMMR0_INT_DECL(int) NEMR0MapPages(PGVM pGVM, PVM pVM, VMCPUID idCpu)
397{
398 /*
399 * Unpack the call.
400 */
401 int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
402 if (RT_SUCCESS(rc))
403 {
404 PVMCPU pVCpu = &pVM->aCpus[idCpu];
405 PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
406
407 RTGCPHYS const GCPhysSrc = pVCpu->nem.s.Hypercall.MapPages.GCPhysSrc;
408 RTGCPHYS const GCPhysDst = pVCpu->nem.s.Hypercall.MapPages.GCPhysDst;
409 uint32_t const cPages = pVCpu->nem.s.Hypercall.MapPages.cPages;
410 HV_MAP_GPA_FLAGS const fFlags = pVCpu->nem.s.Hypercall.MapPages.fFlags;
411
412 /*
413 * Do the work.
414 */
415 rc = nemR0WinMapPages(pGVM, pVM, pGVCpu, GCPhysSrc, GCPhysDst, cPages, fFlags);
416 }
417 return rc;
418}
419
420
421/**
422 * Worker for NEMR0UnmapPages and others.
423 */
424NEM_TMPL_STATIC int nemR0WinUnmapPages(PGVM pGVM, PGVMCPU pGVCpu, RTGCPHYS GCPhys, uint32_t cPages)
425{
426 /*
427 * Validate input.
428 */
429 AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
430
431 AssertReturn(cPages > 0, VERR_OUT_OF_RANGE);
432 AssertReturn(cPages <= NEM_MAX_UNMAP_PAGES, VERR_OUT_OF_RANGE);
433 AssertMsgReturn(!(GCPhys & X86_PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_OUT_OF_RANGE);
434 AssertReturn(GCPhys < _1E, VERR_OUT_OF_RANGE);
435
436 /*
437 * Compose and make the hypercall.
438 */
439 HV_INPUT_UNMAP_GPA_PAGES *pUnmapPages = (HV_INPUT_UNMAP_GPA_PAGES *)pGVCpu->nem.s.pbHypercallData;
440 AssertPtrReturn(pUnmapPages, VERR_INTERNAL_ERROR_3);
441 pUnmapPages->TargetPartitionId = pGVM->nem.s.idHvPartition;
442 pUnmapPages->TargetGpaBase = GCPhys >> X86_PAGE_SHIFT;
443 pUnmapPages->fFlags = 0;
444
445 uint64_t uResult = g_pfnHvlInvokeHypercall(HvCallUnmapGpaPages | ((uint64_t)cPages << 32),
446 pGVCpu->nem.s.HCPhysHypercallData, 0);
447 Log6(("NEMR0UnmapPages: %RGp L %u -> %#RX64\n", GCPhys, cPages, uResult));
448 if (uResult == ((uint64_t)cPages << 32))
449 {
450#if 1 /* Do we need to do this? Hopefully not... */
451 uint64_t volatile uR = g_pfnHvlInvokeHypercall(HvCallUncommitGpaPages | ((uint64_t)cPages << 32),
452 pGVCpu->nem.s.HCPhysHypercallData, 0);
453 AssertMsg(uR == ((uint64_t)cPages << 32), ("uR=%#RX64\n", uR));
454#endif
455 return VINF_SUCCESS;
456 }
457
458 LogRel(("g_pfnHvlInvokeHypercall/UnmapGpaPages -> %#RX64\n", uResult));
459 return VERR_NEM_UNMAP_PAGES_FAILED;
460}
461
462
463/**
464 * Unmaps pages from the guest physical address space.
465 *
466 * Generally the caller will be under the PGM lock already, so no extra effort
467 * is needed to make sure all changes happens under it.
468 *
469 * @returns VBox status code.
470 * @param pGVM The ring-0 VM handle.
471 * @param pVM The cross context VM handle.
472 * @param idCpu The calling EMT. Necessary for getting the
473 * hypercall page and arguments.
474 * @thread EMT(idCpu)
475 */
476VMMR0_INT_DECL(int) NEMR0UnmapPages(PGVM pGVM, PVM pVM, VMCPUID idCpu)
477{
478 /*
479 * Unpack the call.
480 */
481 int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
482 if (RT_SUCCESS(rc))
483 {
484 PVMCPU pVCpu = &pVM->aCpus[idCpu];
485 PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
486
487 RTGCPHYS const GCPhys = pVCpu->nem.s.Hypercall.UnmapPages.GCPhys;
488 uint32_t const cPages = pVCpu->nem.s.Hypercall.UnmapPages.cPages;
489
490 /*
491 * Do the work.
492 */
493 rc = nemR0WinUnmapPages(pGVM, pGVCpu, GCPhys, cPages);
494 }
495 return rc;
496}
497
498
499/**
500 * Worker for NEMR0ExportState.
501 *
502 * Intention is to use it internally later.
503 *
504 * @returns VBox status code.
505 * @param pGVM The ring-0 VM handle.
506 * @param pGVCpu The irng-0 VCPU handle.
507 * @param pCtx The CPU context structure to import into.
508 * @param fWhat What to export. To be defined, UINT64_MAX for now.
509 */
510NEM_TMPL_STATIC int nemR0WinExportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx)
511{
512 PVMCPU pVCpu = &pGVM->pVM->aCpus[pGVCpu->idCpu];
513 HV_INPUT_SET_VP_REGISTERS *pInput = (HV_INPUT_SET_VP_REGISTERS *)pGVCpu->nem.s.pbHypercallData;
514 AssertPtrReturn(pInput, VERR_INTERNAL_ERROR_3);
515
516 pInput->PartitionId = pGVM->nem.s.idHvPartition;
517 pInput->VpIndex = pGVCpu->idCpu;
518 pInput->RsvdZ = 0;
519
520 uint64_t const fWhat = ~pCtx->fExtrn & (CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK);
521 if (!fWhat)
522 return VINF_SUCCESS;
523 uintptr_t iReg = 0;
524
525 /* GPRs */
526 if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
527 {
528 if (fWhat & CPUMCTX_EXTRN_RAX)
529 {
530 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
531 pInput->Elements[iReg].Name = HvX64RegisterRax;
532 pInput->Elements[iReg].Value.Reg64 = pCtx->rax;
533 iReg++;
534 }
535 if (fWhat & CPUMCTX_EXTRN_RCX)
536 {
537 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
538 pInput->Elements[iReg].Name = HvX64RegisterRcx;
539 pInput->Elements[iReg].Value.Reg64 = pCtx->rcx;
540 iReg++;
541 }
542 if (fWhat & CPUMCTX_EXTRN_RDX)
543 {
544 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
545 pInput->Elements[iReg].Name = HvX64RegisterRdx;
546 pInput->Elements[iReg].Value.Reg64 = pCtx->rdx;
547 iReg++;
548 }
549 if (fWhat & CPUMCTX_EXTRN_RBX)
550 {
551 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
552 pInput->Elements[iReg].Name = HvX64RegisterRbx;
553 pInput->Elements[iReg].Value.Reg64 = pCtx->rbx;
554 iReg++;
555 }
556 if (fWhat & CPUMCTX_EXTRN_RSP)
557 {
558 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
559 pInput->Elements[iReg].Name = HvX64RegisterRsp;
560 pInput->Elements[iReg].Value.Reg64 = pCtx->rsp;
561 iReg++;
562 }
563 if (fWhat & CPUMCTX_EXTRN_RBP)
564 {
565 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
566 pInput->Elements[iReg].Name = HvX64RegisterRbp;
567 pInput->Elements[iReg].Value.Reg64 = pCtx->rbp;
568 iReg++;
569 }
570 if (fWhat & CPUMCTX_EXTRN_RSI)
571 {
572 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
573 pInput->Elements[iReg].Name = HvX64RegisterRsi;
574 pInput->Elements[iReg].Value.Reg64 = pCtx->rsi;
575 iReg++;
576 }
577 if (fWhat & CPUMCTX_EXTRN_RDI)
578 {
579 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
580 pInput->Elements[iReg].Name = HvX64RegisterRdi;
581 pInput->Elements[iReg].Value.Reg64 = pCtx->rdi;
582 iReg++;
583 }
584 if (fWhat & CPUMCTX_EXTRN_R8_R15)
585 {
586 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
587 pInput->Elements[iReg].Name = HvX64RegisterR8;
588 pInput->Elements[iReg].Value.Reg64 = pCtx->r8;
589 iReg++;
590 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
591 pInput->Elements[iReg].Name = HvX64RegisterR9;
592 pInput->Elements[iReg].Value.Reg64 = pCtx->r9;
593 iReg++;
594 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
595 pInput->Elements[iReg].Name = HvX64RegisterR10;
596 pInput->Elements[iReg].Value.Reg64 = pCtx->r10;
597 iReg++;
598 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
599 pInput->Elements[iReg].Name = HvX64RegisterR11;
600 pInput->Elements[iReg].Value.Reg64 = pCtx->r11;
601 iReg++;
602 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
603 pInput->Elements[iReg].Name = HvX64RegisterR12;
604 pInput->Elements[iReg].Value.Reg64 = pCtx->r12;
605 iReg++;
606 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
607 pInput->Elements[iReg].Name = HvX64RegisterR13;
608 pInput->Elements[iReg].Value.Reg64 = pCtx->r13;
609 iReg++;
610 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
611 pInput->Elements[iReg].Name = HvX64RegisterR14;
612 pInput->Elements[iReg].Value.Reg64 = pCtx->r14;
613 iReg++;
614 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
615 pInput->Elements[iReg].Name = HvX64RegisterR15;
616 pInput->Elements[iReg].Value.Reg64 = pCtx->r15;
617 iReg++;
618 }
619 }
620
621 /* RIP & Flags */
622 if (fWhat & CPUMCTX_EXTRN_RIP)
623 {
624 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
625 pInput->Elements[iReg].Name = HvX64RegisterRip;
626 pInput->Elements[iReg].Value.Reg64 = pCtx->rip;
627 iReg++;
628 }
629 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
630 {
631 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
632 pInput->Elements[iReg].Name = HvX64RegisterRflags;
633 pInput->Elements[iReg].Value.Reg64 = pCtx->rflags.u;
634 iReg++;
635 }
636
637 /* Segments */
638#define COPY_OUT_SEG(a_idx, a_enmName, a_SReg) \
639 do { \
640 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[a_idx]); \
641 pInput->Elements[a_idx].Name = a_enmName; \
642 pInput->Elements[a_idx].Value.Segment.Base = (a_SReg).u64Base; \
643 pInput->Elements[a_idx].Value.Segment.Limit = (a_SReg).u32Limit; \
644 pInput->Elements[a_idx].Value.Segment.Selector = (a_SReg).Sel; \
645 pInput->Elements[a_idx].Value.Segment.Attributes = (a_SReg).Attr.u; \
646 } while (0)
647 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
648 {
649 if (fWhat & CPUMCTX_EXTRN_CS)
650 {
651 COPY_OUT_SEG(iReg, HvX64RegisterCs, pCtx->cs);
652 iReg++;
653 }
654 if (fWhat & CPUMCTX_EXTRN_ES)
655 {
656 COPY_OUT_SEG(iReg, HvX64RegisterEs, pCtx->es);
657 iReg++;
658 }
659 if (fWhat & CPUMCTX_EXTRN_SS)
660 {
661 COPY_OUT_SEG(iReg, HvX64RegisterSs, pCtx->ss);
662 iReg++;
663 }
664 if (fWhat & CPUMCTX_EXTRN_DS)
665 {
666 COPY_OUT_SEG(iReg, HvX64RegisterDs, pCtx->ds);
667 iReg++;
668 }
669 if (fWhat & CPUMCTX_EXTRN_FS)
670 {
671 COPY_OUT_SEG(iReg, HvX64RegisterFs, pCtx->fs);
672 iReg++;
673 }
674 if (fWhat & CPUMCTX_EXTRN_GS)
675 {
676 COPY_OUT_SEG(iReg, HvX64RegisterGs, pCtx->gs);
677 iReg++;
678 }
679 }
680
681 /* Descriptor tables & task segment. */
682 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
683 {
684 if (fWhat & CPUMCTX_EXTRN_LDTR)
685 {
686 COPY_OUT_SEG(iReg, HvX64RegisterLdtr, pCtx->ldtr);
687 iReg++;
688 }
689 if (fWhat & CPUMCTX_EXTRN_TR)
690 {
691 COPY_OUT_SEG(iReg, HvX64RegisterTr, pCtx->tr);
692 iReg++;
693 }
694
695 if (fWhat & CPUMCTX_EXTRN_IDTR)
696 {
697 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
698 pInput->Elements[iReg].Value.Table.Pad[0] = 0;
699 pInput->Elements[iReg].Value.Table.Pad[1] = 0;
700 pInput->Elements[iReg].Value.Table.Pad[2] = 0;
701 pInput->Elements[iReg].Name = HvX64RegisterIdtr;
702 pInput->Elements[iReg].Value.Table.Limit = pCtx->idtr.cbIdt;
703 pInput->Elements[iReg].Value.Table.Base = pCtx->idtr.pIdt;
704 iReg++;
705 }
706 if (fWhat & CPUMCTX_EXTRN_GDTR)
707 {
708 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
709 pInput->Elements[iReg].Value.Table.Pad[0] = 0;
710 pInput->Elements[iReg].Value.Table.Pad[1] = 0;
711 pInput->Elements[iReg].Value.Table.Pad[2] = 0;
712 pInput->Elements[iReg].Name = HvX64RegisterGdtr;
713 pInput->Elements[iReg].Value.Table.Limit = pCtx->gdtr.cbGdt;
714 pInput->Elements[iReg].Value.Table.Base = pCtx->gdtr.pGdt;
715 iReg++;
716 }
717 }
718
719 /* Control registers. */
720 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
721 {
722 if (fWhat & CPUMCTX_EXTRN_CR0)
723 {
724 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
725 pInput->Elements[iReg].Name = HvX64RegisterCr0;
726 pInput->Elements[iReg].Value.Reg64 = pCtx->cr0;
727 iReg++;
728 }
729 if (fWhat & CPUMCTX_EXTRN_CR2)
730 {
731 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
732 pInput->Elements[iReg].Name = HvX64RegisterCr2;
733 pInput->Elements[iReg].Value.Reg64 = pCtx->cr2;
734 iReg++;
735 }
736 if (fWhat & CPUMCTX_EXTRN_CR3)
737 {
738 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
739 pInput->Elements[iReg].Name = HvX64RegisterCr3;
740 pInput->Elements[iReg].Value.Reg64 = pCtx->cr3;
741 iReg++;
742 }
743 if (fWhat & CPUMCTX_EXTRN_CR4)
744 {
745 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
746 pInput->Elements[iReg].Name = HvX64RegisterCr4;
747 pInput->Elements[iReg].Value.Reg64 = pCtx->cr4;
748 iReg++;
749 }
750 }
751 /** @todo CR8/TPR */
752 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
753 pInput->Elements[iReg].Name = HvX64RegisterCr8;
754 pInput->Elements[iReg].Value.Reg64 = CPUMGetGuestCR8(pVCpu);
755 iReg++;
756
757 /** @todo does HvX64RegisterXfem mean XCR0? What about the related MSR. */
758
759 /* Debug registers. */
760/** @todo fixme. Figure out what the hyper-v version of KVM_SET_GUEST_DEBUG would be. */
761 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
762 {
763 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
764 pInput->Elements[iReg].Name = HvX64RegisterDr0;
765 //pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR0(pVCpu);
766 pInput->Elements[iReg].Value.Reg64 = pCtx->dr[0];
767 iReg++;
768 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
769 pInput->Elements[iReg].Name = HvX64RegisterDr1;
770 //pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR1(pVCpu);
771 pInput->Elements[iReg].Value.Reg64 = pCtx->dr[1];
772 iReg++;
773 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
774 pInput->Elements[iReg].Name = HvX64RegisterDr2;
775 //pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR2(pVCpu);
776 pInput->Elements[iReg].Value.Reg64 = pCtx->dr[2];
777 iReg++;
778 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
779 pInput->Elements[iReg].Name = HvX64RegisterDr3;
780 //pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR3(pVCpu);
781 pInput->Elements[iReg].Value.Reg64 = pCtx->dr[3];
782 iReg++;
783 }
784 if (fWhat & CPUMCTX_EXTRN_DR6)
785 {
786 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
787 pInput->Elements[iReg].Name = HvX64RegisterDr6;
788 //pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR6(pVCpu);
789 pInput->Elements[iReg].Value.Reg64 = pCtx->dr[6];
790 iReg++;
791 }
792 if (fWhat & CPUMCTX_EXTRN_DR7)
793 {
794 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
795 pInput->Elements[iReg].Name = HvX64RegisterDr7;
796 //pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR7(pVCpu);
797 pInput->Elements[iReg].Value.Reg64 = pCtx->dr[7];
798 iReg++;
799 }
800
801 /* Floating point state. */
802 if (fWhat & CPUMCTX_EXTRN_X87)
803 {
804 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
805 pInput->Elements[iReg].Name = HvX64RegisterFpMmx0;
806 pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[0].au64[0];
807 pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[0].au64[1];
808 iReg++;
809 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
810 pInput->Elements[iReg].Name = HvX64RegisterFpMmx1;
811 pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[1].au64[0];
812 pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[1].au64[1];
813 iReg++;
814 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
815 pInput->Elements[iReg].Name = HvX64RegisterFpMmx2;
816 pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[2].au64[0];
817 pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[2].au64[1];
818 iReg++;
819 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
820 pInput->Elements[iReg].Name = HvX64RegisterFpMmx3;
821 pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[3].au64[0];
822 pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[3].au64[1];
823 iReg++;
824 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
825 pInput->Elements[iReg].Name = HvX64RegisterFpMmx4;
826 pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[4].au64[0];
827 pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[4].au64[1];
828 iReg++;
829 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
830 pInput->Elements[iReg].Name = HvX64RegisterFpMmx5;
831 pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[5].au64[0];
832 pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[5].au64[1];
833 iReg++;
834 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
835 pInput->Elements[iReg].Name = HvX64RegisterFpMmx6;
836 pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[6].au64[0];
837 pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[6].au64[1];
838 iReg++;
839 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
840 pInput->Elements[iReg].Name = HvX64RegisterFpMmx7;
841 pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[7].au64[0];
842 pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[7].au64[1];
843 iReg++;
844
845 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
846 pInput->Elements[iReg].Name = HvX64RegisterFpControlStatus;
847 pInput->Elements[iReg].Value.FpControlStatus.FpControl = pCtx->pXStateR0->x87.FCW;
848 pInput->Elements[iReg].Value.FpControlStatus.FpStatus = pCtx->pXStateR0->x87.FSW;
849 pInput->Elements[iReg].Value.FpControlStatus.FpTag = pCtx->pXStateR0->x87.FTW;
850 pInput->Elements[iReg].Value.FpControlStatus.Reserved = pCtx->pXStateR0->x87.FTW >> 8;
851 pInput->Elements[iReg].Value.FpControlStatus.LastFpOp = pCtx->pXStateR0->x87.FOP;
852 pInput->Elements[iReg].Value.FpControlStatus.LastFpRip = (pCtx->pXStateR0->x87.FPUIP)
853 | ((uint64_t)pCtx->pXStateR0->x87.CS << 32)
854 | ((uint64_t)pCtx->pXStateR0->x87.Rsrvd1 << 48);
855 iReg++;
856/** @todo we've got trouble if if we try write just SSE w/o X87. */
857 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
858 pInput->Elements[iReg].Name = HvX64RegisterXmmControlStatus;
859 pInput->Elements[iReg].Value.XmmControlStatus.LastFpRdp = (pCtx->pXStateR0->x87.FPUDP)
860 | ((uint64_t)pCtx->pXStateR0->x87.DS << 32)
861 | ((uint64_t)pCtx->pXStateR0->x87.Rsrvd2 << 48);
862 pInput->Elements[iReg].Value.XmmControlStatus.XmmStatusControl = pCtx->pXStateR0->x87.MXCSR;
863 pInput->Elements[iReg].Value.XmmControlStatus.XmmStatusControlMask = pCtx->pXStateR0->x87.MXCSR_MASK; /** @todo ??? (Isn't this an output field?) */
864 iReg++;
865 }
866
867 /* Vector state. */
868 if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
869 {
870 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
871 pInput->Elements[iReg].Name = HvX64RegisterXmm0;
872 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Lo;
873 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Hi;
874 iReg++;
875 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
876 pInput->Elements[iReg].Name = HvX64RegisterXmm1;
877 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Lo;
878 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Hi;
879 iReg++;
880 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
881 pInput->Elements[iReg].Name = HvX64RegisterXmm2;
882 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Lo;
883 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Hi;
884 iReg++;
885 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
886 pInput->Elements[iReg].Name = HvX64RegisterXmm3;
887 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Lo;
888 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Hi;
889 iReg++;
890 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
891 pInput->Elements[iReg].Name = HvX64RegisterXmm4;
892 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Lo;
893 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Hi;
894 iReg++;
895 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
896 pInput->Elements[iReg].Name = HvX64RegisterXmm5;
897 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Lo;
898 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Hi;
899 iReg++;
900 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
901 pInput->Elements[iReg].Name = HvX64RegisterXmm6;
902 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Lo;
903 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Hi;
904 iReg++;
905 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
906 pInput->Elements[iReg].Name = HvX64RegisterXmm7;
907 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Lo;
908 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Hi;
909 iReg++;
910 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
911 pInput->Elements[iReg].Name = HvX64RegisterXmm8;
912 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Lo;
913 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Hi;
914 iReg++;
915 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
916 pInput->Elements[iReg].Name = HvX64RegisterXmm9;
917 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Lo;
918 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Hi;
919 iReg++;
920 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
921 pInput->Elements[iReg].Name = HvX64RegisterXmm10;
922 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Lo;
923 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Hi;
924 iReg++;
925 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
926 pInput->Elements[iReg].Name = HvX64RegisterXmm11;
927 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Lo;
928 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Hi;
929 iReg++;
930 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
931 pInput->Elements[iReg].Name = HvX64RegisterXmm12;
932 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Lo;
933 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Hi;
934 iReg++;
935 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
936 pInput->Elements[iReg].Name = HvX64RegisterXmm13;
937 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Lo;
938 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Hi;
939 iReg++;
940 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
941 pInput->Elements[iReg].Name = HvX64RegisterXmm14;
942 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Lo;
943 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Hi;
944 iReg++;
945 HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
946 pInput->Elements[iReg].Name = HvX64RegisterXmm15;
947 pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Lo;
948 pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Hi;
949 iReg++;
950 }
951
952 /* MSRs */
953 // HvX64RegisterTsc - don't touch
954 /** @todo does HvX64RegisterTsc include TSC_AUX? Is it TSC_AUX? */
955 if (fWhat & CPUMCTX_EXTRN_EFER)
956 {
957 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
958 pInput->Elements[iReg].Name = HvX64RegisterEfer;
959 pInput->Elements[iReg].Value.Reg64 = pCtx->msrEFER;
960 iReg++;
961 }
962 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
963 {
964 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
965 pInput->Elements[iReg].Name = HvX64RegisterKernelGsBase;
966 pInput->Elements[iReg].Value.Reg64 = pCtx->msrKERNELGSBASE;
967 iReg++;
968 }
969 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
970 {
971 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
972 pInput->Elements[iReg].Name = HvX64RegisterSysenterCs;
973 pInput->Elements[iReg].Value.Reg64 = pCtx->SysEnter.cs;
974 iReg++;
975 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
976 pInput->Elements[iReg].Name = HvX64RegisterSysenterEip;
977 pInput->Elements[iReg].Value.Reg64 = pCtx->SysEnter.eip;
978 iReg++;
979 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
980 pInput->Elements[iReg].Name = HvX64RegisterSysenterEsp;
981 pInput->Elements[iReg].Value.Reg64 = pCtx->SysEnter.esp;
982 iReg++;
983 }
984 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
985 {
986 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
987 pInput->Elements[iReg].Name = HvX64RegisterStar;
988 pInput->Elements[iReg].Value.Reg64 = pCtx->msrSTAR;
989 iReg++;
990 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
991 pInput->Elements[iReg].Name = HvX64RegisterLstar;
992 pInput->Elements[iReg].Value.Reg64 = pCtx->msrLSTAR;
993 iReg++;
994 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
995 pInput->Elements[iReg].Name = HvX64RegisterCstar;
996 pInput->Elements[iReg].Value.Reg64 = pCtx->msrCSTAR;
997 iReg++;
998 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
999 pInput->Elements[iReg].Name = HvX64RegisterSfmask;
1000 pInput->Elements[iReg].Value.Reg64 = pCtx->msrSFMASK;
1001 iReg++;
1002 }
1003 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1004 {
1005 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1006 pInput->Elements[iReg].Name = HvX64RegisterApicBase;
1007 pInput->Elements[iReg].Value.Reg64 = APICGetBaseMsrNoCheck(pVCpu);
1008 iReg++;
1009 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1010 pInput->Elements[iReg].Name = HvX64RegisterPat;
1011 pInput->Elements[iReg].Value.Reg64 = pCtx->msrPAT;
1012 iReg++;
1013 }
1014
1015 /* event injection (always clear it). */
1016 if (fWhat & CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)
1017 {
1018 HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1019 pInput->Elements[iReg].Name = HvRegisterPendingInterruption;
1020 pInput->Elements[iReg].Value.Reg64 = 0;
1021 iReg++;
1022 }
1023 /// @todo HvRegisterInterruptState
1024 /// @todo HvRegisterPendingEvent0
1025 /// @todo HvRegisterPendingEvent1
1026
1027 /*
1028 * Set the registers.
1029 */
1030 Assert((uintptr_t)&pInput->Elements[iReg] - (uintptr_t)pGVCpu->nem.s.pbHypercallData < PAGE_SIZE); /* max is 127 */
1031
1032 /*
1033 * Make the hypercall.
1034 */
1035 uint64_t uResult = g_pfnHvlInvokeHypercall(HV_MAKE_CALL_INFO(HvCallSetVpRegisters, iReg),
1036 pGVCpu->nem.s.HCPhysHypercallData, 0 /*GCPhysOutput*/);
1037 AssertLogRelMsgReturn(uResult == HV_MAKE_CALL_REP_RET(iReg),
1038 ("uResult=%RX64 iRegs=%#x\n", uResult, iReg),
1039 VERR_NEM_SET_REGISTERS_FAILED);
1040 //LogFlow(("nemR0WinExportState: uResult=%#RX64 iReg=%zu fWhat=%#018RX64 fExtrn=%#018RX64 -> %#018RX64\n", uResult, iReg, fWhat, pCtx->fExtrn,
1041 // pCtx->fExtrn | CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK | CPUMCTX_EXTRN_KEEPER_NEM ));
1042 pCtx->fExtrn |= CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_NEM_WIN_MASK | CPUMCTX_EXTRN_KEEPER_NEM;
1043 return VINF_SUCCESS;
1044}
1045
1046
1047/**
1048 * Export the state to the native API (out of CPUMCTX).
1049 *
1050 * @returns VBox status code
1051 * @param pGVM The ring-0 VM handle.
1052 * @param pVM The cross context VM handle.
1053 * @param idCpu The calling EMT. Necessary for getting the
1054 * hypercall page and arguments.
1055 */
1056VMMR0_INT_DECL(int) NEMR0ExportState(PGVM pGVM, PVM pVM, VMCPUID idCpu)
1057{
1058 /*
1059 * Validate the call.
1060 */
1061 int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
1062 if (RT_SUCCESS(rc))
1063 {
1064 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1065 PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
1066 AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
1067
1068 /*
1069 * Call worker.
1070 */
1071 rc = nemR0WinExportState(pGVM, pGVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1072 }
1073 return rc;
1074}
1075
1076
1077/**
1078 * Worker for NEMR0ImportState.
1079 *
1080 * Intention is to use it internally later.
1081 *
1082 * @returns VBox status code.
1083 * @param pGVM The ring-0 VM handle.
1084 * @param pGVCpu The irng-0 VCPU handle.
1085 * @param pCtx The CPU context structure to import into.
1086 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1087 */
1088NEM_TMPL_STATIC int nemR0WinImportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx, uint64_t fWhat)
1089{
1090 HV_INPUT_GET_VP_REGISTERS *pInput = (HV_INPUT_GET_VP_REGISTERS *)pGVCpu->nem.s.pbHypercallData;
1091 AssertPtrReturn(pInput, VERR_INTERNAL_ERROR_3);
1092
1093 fWhat &= pCtx->fExtrn;
1094
1095 pInput->PartitionId = pGVM->nem.s.idHvPartition;
1096 pInput->VpIndex = pGVCpu->idCpu;
1097 pInput->fFlags = 0;
1098
1099 /* GPRs */
1100 uintptr_t iReg = 0;
1101 if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
1102 {
1103 if (fWhat & CPUMCTX_EXTRN_RAX)
1104 pInput->Names[iReg++] = HvX64RegisterRax;
1105 if (fWhat & CPUMCTX_EXTRN_RCX)
1106 pInput->Names[iReg++] = HvX64RegisterRcx;
1107 if (fWhat & CPUMCTX_EXTRN_RDX)
1108 pInput->Names[iReg++] = HvX64RegisterRdx;
1109 if (fWhat & CPUMCTX_EXTRN_RBX)
1110 pInput->Names[iReg++] = HvX64RegisterRbx;
1111 if (fWhat & CPUMCTX_EXTRN_RSP)
1112 pInput->Names[iReg++] = HvX64RegisterRsp;
1113 if (fWhat & CPUMCTX_EXTRN_RBP)
1114 pInput->Names[iReg++] = HvX64RegisterRbp;
1115 if (fWhat & CPUMCTX_EXTRN_RSI)
1116 pInput->Names[iReg++] = HvX64RegisterRsi;
1117 if (fWhat & CPUMCTX_EXTRN_RDI)
1118 pInput->Names[iReg++] = HvX64RegisterRdi;
1119 if (fWhat & CPUMCTX_EXTRN_R8_R15)
1120 {
1121 pInput->Names[iReg++] = HvX64RegisterR8;
1122 pInput->Names[iReg++] = HvX64RegisterR9;
1123 pInput->Names[iReg++] = HvX64RegisterR10;
1124 pInput->Names[iReg++] = HvX64RegisterR11;
1125 pInput->Names[iReg++] = HvX64RegisterR12;
1126 pInput->Names[iReg++] = HvX64RegisterR13;
1127 pInput->Names[iReg++] = HvX64RegisterR14;
1128 pInput->Names[iReg++] = HvX64RegisterR15;
1129 }
1130 }
1131
1132 /* RIP & Flags */
1133 if (fWhat & CPUMCTX_EXTRN_RIP)
1134 pInput->Names[iReg++] = HvX64RegisterRip;
1135 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1136 pInput->Names[iReg++] = HvX64RegisterRflags;
1137
1138 /* Segments */
1139 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1140 {
1141 if (fWhat & CPUMCTX_EXTRN_CS)
1142 pInput->Names[iReg++] = HvX64RegisterCs;
1143 if (fWhat & CPUMCTX_EXTRN_ES)
1144 pInput->Names[iReg++] = HvX64RegisterEs;
1145 if (fWhat & CPUMCTX_EXTRN_SS)
1146 pInput->Names[iReg++] = HvX64RegisterSs;
1147 if (fWhat & CPUMCTX_EXTRN_DS)
1148 pInput->Names[iReg++] = HvX64RegisterDs;
1149 if (fWhat & CPUMCTX_EXTRN_FS)
1150 pInput->Names[iReg++] = HvX64RegisterFs;
1151 if (fWhat & CPUMCTX_EXTRN_GS)
1152 pInput->Names[iReg++] = HvX64RegisterGs;
1153 }
1154
1155 /* Descriptor tables and the task segment. */
1156 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1157 {
1158 if (fWhat & CPUMCTX_EXTRN_LDTR)
1159 pInput->Names[iReg++] = HvX64RegisterLdtr;
1160 if (fWhat & CPUMCTX_EXTRN_TR)
1161 pInput->Names[iReg++] = HvX64RegisterTr;
1162 if (fWhat & CPUMCTX_EXTRN_IDTR)
1163 pInput->Names[iReg++] = HvX64RegisterIdtr;
1164 if (fWhat & CPUMCTX_EXTRN_GDTR)
1165 pInput->Names[iReg++] = HvX64RegisterGdtr;
1166 }
1167
1168 /* Control registers. */
1169 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1170 {
1171 if (fWhat & CPUMCTX_EXTRN_CR0)
1172 pInput->Names[iReg++] = HvX64RegisterCr0;
1173 if (fWhat & CPUMCTX_EXTRN_CR2)
1174 pInput->Names[iReg++] = HvX64RegisterCr2;
1175 if (fWhat & CPUMCTX_EXTRN_CR3)
1176 pInput->Names[iReg++] = HvX64RegisterCr3;
1177 if (fWhat & CPUMCTX_EXTRN_CR4)
1178 pInput->Names[iReg++] = HvX64RegisterCr4;
1179 }
1180 pInput->Names[iReg++] = HvX64RegisterCr8; /// @todo CR8/TPR
1181
1182 /* Debug registers. */
1183 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1184 {
1185 pInput->Names[iReg++] = HvX64RegisterDr0;
1186 pInput->Names[iReg++] = HvX64RegisterDr1;
1187 pInput->Names[iReg++] = HvX64RegisterDr2;
1188 pInput->Names[iReg++] = HvX64RegisterDr3;
1189 }
1190 if (fWhat & CPUMCTX_EXTRN_DR6)
1191 pInput->Names[iReg++] = HvX64RegisterDr6;
1192 if (fWhat & CPUMCTX_EXTRN_DR7)
1193 pInput->Names[iReg++] = HvX64RegisterDr7;
1194
1195 /* Floating point state. */
1196 if (fWhat & CPUMCTX_EXTRN_X87)
1197 {
1198 pInput->Names[iReg++] = HvX64RegisterFpMmx0;
1199 pInput->Names[iReg++] = HvX64RegisterFpMmx1;
1200 pInput->Names[iReg++] = HvX64RegisterFpMmx2;
1201 pInput->Names[iReg++] = HvX64RegisterFpMmx3;
1202 pInput->Names[iReg++] = HvX64RegisterFpMmx4;
1203 pInput->Names[iReg++] = HvX64RegisterFpMmx5;
1204 pInput->Names[iReg++] = HvX64RegisterFpMmx6;
1205 pInput->Names[iReg++] = HvX64RegisterFpMmx7;
1206 pInput->Names[iReg++] = HvX64RegisterFpControlStatus;
1207 }
1208 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX))
1209 pInput->Names[iReg++] = HvX64RegisterXmmControlStatus;
1210
1211 /* Vector state. */
1212 if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
1213 {
1214 pInput->Names[iReg++] = HvX64RegisterXmm0;
1215 pInput->Names[iReg++] = HvX64RegisterXmm1;
1216 pInput->Names[iReg++] = HvX64RegisterXmm2;
1217 pInput->Names[iReg++] = HvX64RegisterXmm3;
1218 pInput->Names[iReg++] = HvX64RegisterXmm4;
1219 pInput->Names[iReg++] = HvX64RegisterXmm5;
1220 pInput->Names[iReg++] = HvX64RegisterXmm6;
1221 pInput->Names[iReg++] = HvX64RegisterXmm7;
1222 pInput->Names[iReg++] = HvX64RegisterXmm8;
1223 pInput->Names[iReg++] = HvX64RegisterXmm9;
1224 pInput->Names[iReg++] = HvX64RegisterXmm10;
1225 pInput->Names[iReg++] = HvX64RegisterXmm11;
1226 pInput->Names[iReg++] = HvX64RegisterXmm12;
1227 pInput->Names[iReg++] = HvX64RegisterXmm13;
1228 pInput->Names[iReg++] = HvX64RegisterXmm14;
1229 pInput->Names[iReg++] = HvX64RegisterXmm15;
1230 }
1231
1232 /* MSRs */
1233 // HvX64RegisterTsc - don't touch
1234 if (fWhat & CPUMCTX_EXTRN_EFER)
1235 pInput->Names[iReg++] = HvX64RegisterEfer;
1236 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1237 pInput->Names[iReg++] = HvX64RegisterKernelGsBase;
1238 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1239 {
1240 pInput->Names[iReg++] = HvX64RegisterSysenterCs;
1241 pInput->Names[iReg++] = HvX64RegisterSysenterEip;
1242 pInput->Names[iReg++] = HvX64RegisterSysenterEsp;
1243 }
1244 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1245 {
1246 pInput->Names[iReg++] = HvX64RegisterStar;
1247 pInput->Names[iReg++] = HvX64RegisterLstar;
1248 pInput->Names[iReg++] = HvX64RegisterCstar;
1249 pInput->Names[iReg++] = HvX64RegisterSfmask;
1250 }
1251
1252 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1253 {
1254 pInput->Names[iReg++] = HvX64RegisterApicBase; /// @todo APIC BASE
1255 pInput->Names[iReg++] = HvX64RegisterPat;
1256 }
1257
1258 /* event injection */
1259 pInput->Names[iReg++] = HvRegisterPendingInterruption;
1260 pInput->Names[iReg++] = HvRegisterInterruptState;
1261 pInput->Names[iReg++] = HvRegisterInterruptState;
1262 pInput->Names[iReg++] = HvRegisterPendingEvent0;
1263 pInput->Names[iReg++] = HvRegisterPendingEvent1;
1264 size_t const cRegs = iReg;
1265 size_t const cbInput = RT_ALIGN_Z(RT_OFFSETOF(HV_INPUT_GET_VP_REGISTERS, Names[cRegs]), 32);
1266
1267 HV_REGISTER_VALUE *paValues = (HV_REGISTER_VALUE *)((uint8_t *)pInput + cbInput);
1268 Assert((uintptr_t)&paValues[cRegs] - (uintptr_t)pGVCpu->nem.s.pbHypercallData < PAGE_SIZE); /* (max is around 168 registers) */
1269 RT_BZERO(paValues, cRegs * sizeof(paValues[0]));
1270
1271 /*
1272 * Make the hypercall.
1273 */
1274 uint64_t uResult = g_pfnHvlInvokeHypercall(HV_MAKE_CALL_INFO(HvCallGetVpRegisters, cRegs),
1275 pGVCpu->nem.s.HCPhysHypercallData,
1276 pGVCpu->nem.s.HCPhysHypercallData + cbInput);
1277 AssertLogRelMsgReturn(uResult == HV_MAKE_CALL_REP_RET(cRegs),
1278 ("uResult=%RX64 cRegs=%#x\n", uResult, cRegs),
1279 VERR_NEM_GET_REGISTERS_FAILED);
1280 //LogFlow(("nemR0WinImportState: uResult=%#RX64 iReg=%zu fWhat=%#018RX64 fExtr=%#018RX64\n", uResult, cRegs, fWhat, pCtx->fExtrn));
1281
1282 /*
1283 * Copy information to the CPUM context.
1284 */
1285 PVMCPU pVCpu = &pGVM->pVM->aCpus[pGVCpu->idCpu];
1286 iReg = 0;
1287
1288 /* GPRs */
1289 if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
1290 {
1291 if (fWhat & CPUMCTX_EXTRN_RAX)
1292 {
1293 Assert(pInput->Names[iReg] == HvX64RegisterRax);
1294 pCtx->rax = paValues[iReg++].Reg64;
1295 }
1296 if (fWhat & CPUMCTX_EXTRN_RCX)
1297 {
1298 Assert(pInput->Names[iReg] == HvX64RegisterRcx);
1299 pCtx->rcx = paValues[iReg++].Reg64;
1300 }
1301 if (fWhat & CPUMCTX_EXTRN_RDX)
1302 {
1303 Assert(pInput->Names[iReg] == HvX64RegisterRdx);
1304 pCtx->rdx = paValues[iReg++].Reg64;
1305 }
1306 if (fWhat & CPUMCTX_EXTRN_RBX)
1307 {
1308 Assert(pInput->Names[iReg] == HvX64RegisterRbx);
1309 pCtx->rbx = paValues[iReg++].Reg64;
1310 }
1311 if (fWhat & CPUMCTX_EXTRN_RSP)
1312 {
1313 Assert(pInput->Names[iReg] == HvX64RegisterRsp);
1314 pCtx->rsp = paValues[iReg++].Reg64;
1315 }
1316 if (fWhat & CPUMCTX_EXTRN_RBP)
1317 {
1318 Assert(pInput->Names[iReg] == HvX64RegisterRbp);
1319 pCtx->rbp = paValues[iReg++].Reg64;
1320 }
1321 if (fWhat & CPUMCTX_EXTRN_RSI)
1322 {
1323 Assert(pInput->Names[iReg] == HvX64RegisterRsi);
1324 pCtx->rsi = paValues[iReg++].Reg64;
1325 }
1326 if (fWhat & CPUMCTX_EXTRN_RDI)
1327 {
1328 Assert(pInput->Names[iReg] == HvX64RegisterRdi);
1329 pCtx->rdi = paValues[iReg++].Reg64;
1330 }
1331 if (fWhat & CPUMCTX_EXTRN_R8_R15)
1332 {
1333 Assert(pInput->Names[iReg] == HvX64RegisterR8);
1334 Assert(pInput->Names[iReg + 7] == HvX64RegisterR15);
1335 pCtx->r8 = paValues[iReg++].Reg64;
1336 pCtx->r9 = paValues[iReg++].Reg64;
1337 pCtx->r10 = paValues[iReg++].Reg64;
1338 pCtx->r11 = paValues[iReg++].Reg64;
1339 pCtx->r12 = paValues[iReg++].Reg64;
1340 pCtx->r13 = paValues[iReg++].Reg64;
1341 pCtx->r14 = paValues[iReg++].Reg64;
1342 pCtx->r15 = paValues[iReg++].Reg64;
1343 }
1344 }
1345
1346 /* RIP & Flags */
1347 if (fWhat & CPUMCTX_EXTRN_RIP)
1348 {
1349 Assert(pInput->Names[iReg] == HvX64RegisterRip);
1350 pCtx->rip = paValues[iReg++].Reg64;
1351 }
1352 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1353 {
1354 Assert(pInput->Names[iReg] == HvX64RegisterRflags);
1355 pCtx->rflags.u = paValues[iReg++].Reg64;
1356 }
1357
1358 /* Segments */
1359#define COPY_BACK_SEG(a_idx, a_enmName, a_SReg) \
1360 do { \
1361 Assert(pInput->Names[a_idx] == a_enmName); \
1362 (a_SReg).u64Base = paValues[a_idx].Segment.Base; \
1363 (a_SReg).u32Limit = paValues[a_idx].Segment.Limit; \
1364 (a_SReg).ValidSel = (a_SReg).Sel = paValues[a_idx].Segment.Selector; \
1365 (a_SReg).Attr.u = paValues[a_idx].Segment.Attributes; \
1366 (a_SReg).fFlags = CPUMSELREG_FLAGS_VALID; \
1367 } while (0)
1368 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1369 {
1370 if (fWhat & CPUMCTX_EXTRN_CS)
1371 {
1372 COPY_BACK_SEG(iReg, HvX64RegisterCs, pCtx->cs);
1373 iReg++;
1374 }
1375 if (fWhat & CPUMCTX_EXTRN_ES)
1376 {
1377 COPY_BACK_SEG(iReg, HvX64RegisterEs, pCtx->es);
1378 iReg++;
1379 }
1380 if (fWhat & CPUMCTX_EXTRN_SS)
1381 {
1382 COPY_BACK_SEG(iReg, HvX64RegisterSs, pCtx->ss);
1383 iReg++;
1384 }
1385 if (fWhat & CPUMCTX_EXTRN_DS)
1386 {
1387 COPY_BACK_SEG(iReg, HvX64RegisterDs, pCtx->ds);
1388 iReg++;
1389 }
1390 if (fWhat & CPUMCTX_EXTRN_FS)
1391 {
1392 COPY_BACK_SEG(iReg, HvX64RegisterFs, pCtx->fs);
1393 iReg++;
1394 }
1395 if (fWhat & CPUMCTX_EXTRN_GS)
1396 {
1397 COPY_BACK_SEG(iReg, HvX64RegisterGs, pCtx->gs);
1398 iReg++;
1399 }
1400 }
1401 /* Descriptor tables and the task segment. */
1402 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1403 {
1404 if (fWhat & CPUMCTX_EXTRN_LDTR)
1405 {
1406 COPY_BACK_SEG(iReg, HvX64RegisterLdtr, pCtx->ldtr);
1407 iReg++;
1408 }
1409 if (fWhat & CPUMCTX_EXTRN_TR)
1410 {
1411 COPY_BACK_SEG(iReg, HvX64RegisterTr, pCtx->tr);
1412 iReg++;
1413 }
1414 if (fWhat & CPUMCTX_EXTRN_IDTR)
1415 {
1416 Assert(pInput->Names[iReg] == HvX64RegisterIdtr);
1417 pCtx->idtr.cbIdt = paValues[iReg].Table.Limit;
1418 pCtx->idtr.pIdt = paValues[iReg].Table.Base;
1419 iReg++;
1420 }
1421 if (fWhat & CPUMCTX_EXTRN_GDTR)
1422 {
1423 Assert(pInput->Names[iReg] == HvX64RegisterGdtr);
1424 pCtx->gdtr.cbGdt = paValues[iReg].Table.Limit;
1425 pCtx->gdtr.pGdt = paValues[iReg].Table.Base;
1426 iReg++;
1427 }
1428 }
1429
1430 /* Control registers. */
1431 bool fMaybeChangedMode = false;
1432 bool fFlushTlb = false;
1433 bool fFlushGlobalTlb = false;
1434 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1435 {
1436 if (fWhat & CPUMCTX_EXTRN_CR0)
1437 {
1438 Assert(pInput->Names[iReg] == HvX64RegisterCr0);
1439 if (pCtx->cr0 != paValues[iReg].Reg64)
1440 {
1441 CPUMSetGuestCR0(pVCpu, paValues[iReg].Reg64);
1442 fMaybeChangedMode = true;
1443 fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
1444 }
1445 iReg++;
1446 }
1447 if (fWhat & CPUMCTX_EXTRN_CR2)
1448 {
1449 Assert(pInput->Names[iReg] == HvX64RegisterCr2);
1450 pCtx->cr2 = paValues[iReg].Reg64;
1451 iReg++;
1452 }
1453 if (fWhat & CPUMCTX_EXTRN_CR3)
1454 {
1455 Assert(pInput->Names[iReg] == HvX64RegisterCr3);
1456 if (pCtx->cr3 != paValues[iReg].Reg64)
1457 {
1458 CPUMSetGuestCR3(pVCpu, paValues[iReg].Reg64);
1459 fFlushTlb = true;
1460 }
1461 iReg++;
1462 }
1463 if (fWhat & CPUMCTX_EXTRN_CR4)
1464 {
1465 Assert(pInput->Names[iReg] == HvX64RegisterCr4);
1466 if (pCtx->cr4 != paValues[iReg].Reg64)
1467 {
1468 CPUMSetGuestCR4(pVCpu, paValues[iReg].Reg64);
1469 fMaybeChangedMode = true;
1470 fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
1471 }
1472 iReg++;
1473 }
1474 }
1475
1476 /// @todo CR8/TPR
1477 Assert(pInput->Names[iReg] == HvX64RegisterCr8);
1478 APICSetTpr(pVCpu, (uint8_t)paValues[iReg].Reg64 << 4);
1479 iReg++;
1480
1481 /* Debug registers. */
1482/** @todo fixme */
1483 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1484 {
1485 Assert(pInput->Names[iReg] == HvX64RegisterDr0);
1486 Assert(pInput->Names[iReg+3] == HvX64RegisterDr3);
1487 if (pCtx->dr[0] != paValues[iReg].Reg64)
1488 CPUMSetGuestDR0(pVCpu, paValues[iReg].Reg64);
1489 iReg++;
1490 if (pCtx->dr[1] != paValues[iReg].Reg64)
1491 CPUMSetGuestDR1(pVCpu, paValues[iReg].Reg64);
1492 iReg++;
1493 if (pCtx->dr[2] != paValues[iReg].Reg64)
1494 CPUMSetGuestDR2(pVCpu, paValues[iReg].Reg64);
1495 iReg++;
1496 if (pCtx->dr[3] != paValues[iReg].Reg64)
1497 CPUMSetGuestDR3(pVCpu, paValues[iReg].Reg64);
1498 iReg++;
1499 }
1500 if (fWhat & CPUMCTX_EXTRN_DR6)
1501 {
1502 Assert(pInput->Names[iReg] == HvX64RegisterDr6);
1503 if (pCtx->dr[6] != paValues[iReg].Reg64)
1504 CPUMSetGuestDR6(pVCpu, paValues[iReg].Reg64);
1505 iReg++;
1506 }
1507 if (fWhat & CPUMCTX_EXTRN_DR7)
1508 {
1509 Assert(pInput->Names[iReg] == HvX64RegisterDr7);
1510 if (pCtx->dr[7] != paValues[iReg].Reg64)
1511 CPUMSetGuestDR6(pVCpu, paValues[iReg].Reg64);
1512 iReg++;
1513 }
1514
1515 /* Floating point state. */
1516 if (fWhat & CPUMCTX_EXTRN_X87)
1517 {
1518 Assert(pInput->Names[iReg] == HvX64RegisterFpMmx0);
1519 Assert(pInput->Names[iReg + 7] == HvX64RegisterFpMmx7);
1520 pCtx->pXStateR0->x87.aRegs[0].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1521 pCtx->pXStateR0->x87.aRegs[0].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1522 iReg++;
1523 pCtx->pXStateR0->x87.aRegs[1].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1524 pCtx->pXStateR0->x87.aRegs[1].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1525 iReg++;
1526 pCtx->pXStateR0->x87.aRegs[2].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1527 pCtx->pXStateR0->x87.aRegs[2].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1528 iReg++;
1529 pCtx->pXStateR0->x87.aRegs[3].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1530 pCtx->pXStateR0->x87.aRegs[3].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1531 iReg++;
1532 pCtx->pXStateR0->x87.aRegs[4].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1533 pCtx->pXStateR0->x87.aRegs[4].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1534 iReg++;
1535 pCtx->pXStateR0->x87.aRegs[5].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1536 pCtx->pXStateR0->x87.aRegs[5].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1537 iReg++;
1538 pCtx->pXStateR0->x87.aRegs[6].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1539 pCtx->pXStateR0->x87.aRegs[6].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1540 iReg++;
1541 pCtx->pXStateR0->x87.aRegs[7].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1542 pCtx->pXStateR0->x87.aRegs[7].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1543 iReg++;
1544
1545 Assert(pInput->Names[iReg] == HvX64RegisterFpControlStatus);
1546 pCtx->pXStateR0->x87.FCW = paValues[iReg].FpControlStatus.FpControl;
1547 pCtx->pXStateR0->x87.FSW = paValues[iReg].FpControlStatus.FpStatus;
1548 pCtx->pXStateR0->x87.FTW = paValues[iReg].FpControlStatus.FpTag
1549 /*| (paValues[iReg].FpControlStatus.Reserved << 8)*/;
1550 pCtx->pXStateR0->x87.FOP = paValues[iReg].FpControlStatus.LastFpOp;
1551 pCtx->pXStateR0->x87.FPUIP = (uint32_t)paValues[iReg].FpControlStatus.LastFpRip;
1552 pCtx->pXStateR0->x87.CS = (uint16_t)(paValues[iReg].FpControlStatus.LastFpRip >> 32);
1553 pCtx->pXStateR0->x87.Rsrvd1 = (uint16_t)(paValues[iReg].FpControlStatus.LastFpRip >> 48);
1554 iReg++;
1555 }
1556
1557 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX))
1558 {
1559 Assert(pInput->Names[iReg] == HvX64RegisterXmmControlStatus);
1560 if (fWhat & CPUMCTX_EXTRN_X87)
1561 {
1562 pCtx->pXStateR0->x87.FPUDP = (uint32_t)paValues[iReg].XmmControlStatus.LastFpRdp;
1563 pCtx->pXStateR0->x87.DS = (uint16_t)(paValues[iReg].XmmControlStatus.LastFpRdp >> 32);
1564 pCtx->pXStateR0->x87.Rsrvd2 = (uint16_t)(paValues[iReg].XmmControlStatus.LastFpRdp >> 48);
1565 }
1566 pCtx->pXStateR0->x87.MXCSR = paValues[iReg].XmmControlStatus.XmmStatusControl;
1567 pCtx->pXStateR0->x87.MXCSR_MASK = paValues[iReg].XmmControlStatus.XmmStatusControlMask; /** @todo ??? (Isn't this an output field?) */
1568 iReg++;
1569 }
1570
1571 /* Vector state. */
1572 if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
1573 {
1574 Assert(pInput->Names[iReg] == HvX64RegisterXmm0);
1575 Assert(pInput->Names[iReg+15] == HvX64RegisterXmm15);
1576 pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1577 pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1578 iReg++;
1579 pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1580 pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1581 iReg++;
1582 pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1583 pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1584 iReg++;
1585 pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1586 pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1587 iReg++;
1588 pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1589 pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1590 iReg++;
1591 pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1592 pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1593 iReg++;
1594 pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1595 pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1596 iReg++;
1597 pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1598 pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1599 iReg++;
1600 pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1601 pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1602 iReg++;
1603 pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1604 pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1605 iReg++;
1606 pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1607 pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1608 iReg++;
1609 pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1610 pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1611 iReg++;
1612 pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1613 pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1614 iReg++;
1615 pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1616 pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1617 iReg++;
1618 pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1619 pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1620 iReg++;
1621 pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1622 pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1623 iReg++;
1624 }
1625
1626
1627 /* MSRs */
1628 // HvX64RegisterTsc - don't touch
1629 if (fWhat & CPUMCTX_EXTRN_EFER)
1630 {
1631 Assert(pInput->Names[iReg] == HvX64RegisterEfer);
1632 if (paValues[iReg].Reg64 != pCtx->msrEFER)
1633 {
1634 pCtx->msrEFER = paValues[iReg].Reg64;
1635 fMaybeChangedMode = true;
1636 }
1637 iReg++;
1638 }
1639 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1640 {
1641 Assert(pInput->Names[iReg] == HvX64RegisterKernelGsBase);
1642 pCtx->msrKERNELGSBASE = paValues[iReg].Reg64;
1643 iReg++;
1644 }
1645 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1646 {
1647 Assert(pInput->Names[iReg] == HvX64RegisterSysenterCs);
1648 pCtx->SysEnter.cs = paValues[iReg].Reg64;
1649 iReg++;
1650 Assert(pInput->Names[iReg] == HvX64RegisterSysenterEip);
1651 pCtx->SysEnter.eip = paValues[iReg].Reg64;
1652 iReg++;
1653 Assert(pInput->Names[iReg] == HvX64RegisterSysenterEsp);
1654 pCtx->SysEnter.esp = paValues[iReg].Reg64;
1655 iReg++;
1656 }
1657 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1658 {
1659 Assert(pInput->Names[iReg] == HvX64RegisterStar);
1660 pCtx->msrSTAR = paValues[iReg].Reg64;
1661 iReg++;
1662 Assert(pInput->Names[iReg] == HvX64RegisterLstar);
1663 pCtx->msrLSTAR = paValues[iReg].Reg64;
1664 iReg++;
1665 Assert(pInput->Names[iReg] == HvX64RegisterCstar);
1666 pCtx->msrCSTAR = paValues[iReg].Reg64;
1667 iReg++;
1668 Assert(pInput->Names[iReg] == HvX64RegisterSfmask);
1669 pCtx->msrSFMASK = paValues[iReg].Reg64;
1670 iReg++;
1671 }
1672 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1673 {
1674 Assert(pInput->Names[iReg] == HvX64RegisterApicBase);
1675 if (paValues[iReg].Reg64 != APICGetBaseMsrNoCheck(pVCpu))
1676 {
1677 VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, paValues[iReg].Reg64);
1678 Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
1679 }
1680 iReg++;
1681
1682 Assert(pInput->Names[iReg] == HvX64RegisterPat);
1683 pCtx->msrPAT = paValues[iReg].Reg64;
1684 iReg++;
1685 }
1686
1687 /* Event injection. */
1688 /// @todo HvRegisterPendingInterruption
1689 Assert(pInput->Names[iReg] == HvRegisterPendingInterruption);
1690 if (paValues[iReg].PendingInterruption.InterruptionPending)
1691 {
1692 Log7(("PendingInterruption: type=%u vector=%#x errcd=%RTbool/%#x instr-len=%u nested=%u\n",
1693 paValues[iReg].PendingInterruption.InterruptionType, paValues[iReg].PendingInterruption.InterruptionVector,
1694 paValues[iReg].PendingInterruption.DeliverErrorCode, paValues[iReg].PendingInterruption.ErrorCode,
1695 paValues[iReg].PendingInterruption.InstructionLength, paValues[iReg].PendingInterruption.NestedEvent));
1696 AssertMsg((paValues[iReg].PendingInterruption.AsUINT64 & UINT64_C(0xfc00)) == 0,
1697 ("%#RX64\n", paValues[iReg].PendingInterruption.AsUINT64));
1698 }
1699
1700 /// @todo HvRegisterInterruptState
1701 /// @todo HvRegisterPendingEvent0
1702 /// @todo HvRegisterPendingEvent1
1703
1704 /* Almost done, just update extrn flags and maybe change PGM mode. */
1705 pCtx->fExtrn &= ~fWhat;
1706
1707 /* Typical. */
1708 if (!fMaybeChangedMode && !fFlushTlb)
1709 return VINF_SUCCESS;
1710
1711 /*
1712 * Slow.
1713 */
1714 int rc = VINF_SUCCESS;
1715 if (fMaybeChangedMode)
1716 {
1717 rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
1718 if (rc == VINF_PGM_CHANGE_MODE)
1719 {
1720 LogFlow(("nemR0WinImportState: -> VERR_NEM_CHANGE_PGM_MODE!\n"));
1721 return VERR_NEM_CHANGE_PGM_MODE;
1722 }
1723 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
1724 }
1725
1726 if (fFlushTlb)
1727 {
1728 LogFlow(("nemR0WinImportState: -> VERR_NEM_FLUSH_TLB!\n"));
1729 rc = VERR_NEM_FLUSH_TLB; /* Calling PGMFlushTLB w/o long jump setup doesn't work, ring-3 does it. */
1730 }
1731
1732 return rc;
1733}
1734
1735
1736/**
1737 * Import the state from the native API (back to CPUMCTX).
1738 *
1739 * @returns VBox status code
1740 * @param pGVM The ring-0 VM handle.
1741 * @param pVM The cross context VM handle.
1742 * @param idCpu The calling EMT. Necessary for getting the
1743 * hypercall page and arguments.
1744 * @param fWhat What to import, CPUMCTX_EXTRN_XXX. Set
1745 * CPUMCTX_EXTERN_ALL for everything.
1746 */
1747VMMR0_INT_DECL(int) NEMR0ImportState(PGVM pGVM, PVM pVM, VMCPUID idCpu, uint64_t fWhat)
1748{
1749 /*
1750 * Validate the call.
1751 */
1752 int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
1753 if (RT_SUCCESS(rc))
1754 {
1755 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1756 PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
1757 AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
1758
1759 /*
1760 * Call worker.
1761 */
1762 rc = nemR0WinImportState(pGVM, pGVCpu, CPUMQueryGuestCtxPtr(pVCpu), fWhat);
1763 }
1764 return rc;
1765}
1766
1767
1768VMMR0_INT_DECL(VBOXSTRICTRC) NEMR0RunGuestCode(PGVM pGVM, VMCPUID idCpu)
1769{
1770 PVM pVM = pGVM->pVM;
1771 return nemHCWinRunGC(pVM, &pVM->aCpus[idCpu], pGVM, &pGVM->aCpus[idCpu]);
1772}
1773
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