NEMR0Native-win.cpp@ 72300

Last change on this file since 72300 was 72300, checked in by vboxsync, 7 years ago

NEM,STAM: Partition memory statistics for NEM. bugref:9044

STAM: Redid the way we handle statistics requiring fetching data from ring-0 (or elsewhere) by introducing a refresh group concept. We'll refresh the statistics for a group if needed and only once per enumeration/query. There's a new registration API for these.
NEM: Added memory balance statistics for the partition. Some failed fumbling thru VID.DLL/SYS, before realizing that hypercall is the only way to get at them.
NEM: Added a hypervisor input/output page buffer for non-EMT threads so we can get statistics. Put the related data and code into separate structure to save duplication.

Property svn:eol-style set to native
Property svn:keywords set to Author Date Id Revision

File size: 84.3 KB

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1	/* $Id: NEMR0Native-win.cpp 72300 2018-05-23 15:13:06Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-0 Windows backend.
4	*/
5
6	/*
7	* Copyright (C) 2018 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_NEM
23	#include <iprt/nt/nt.h>
24	#include <iprt/nt/hyperv.h>
25	#include <iprt/nt/vid.h>
26	#include <winerror.h>
27
28	#include <VBox/vmm/nem.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/em.h>
31	#include <VBox/vmm/apic.h>
32	#include <VBox/vmm/pdm.h>
33	#include "NEMInternal.h"
34	#include <VBox/vmm/gvm.h>
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/gvmm.h>
37	#include <VBox/param.h>
38
39	#include <iprt/dbg.h>
40	#include <iprt/memobj.h>
41	#include <iprt/string.h>
42
43
44	/* Assert compile context sanity. */
45	#ifndef RT_OS_WINDOWS
46	# error "Windows only file!"
47	#endif
48	#ifndef RT_ARCH_AMD64
49	# error "AMD64 only file!"
50	#endif
51
52
53	/*********************************************************************************************************************************
54	* Internal Functions *
55	*********************************************************************************************************************************/
56	typedef uint32_t DWORD; /* for winerror.h constants */
57
58
59	/*********************************************************************************************************************************
60	* Global Variables *
61	*********************************************************************************************************************************/
62	static uint64_t (*g_pfnHvlInvokeHypercall)(uint64_t uCallInfo, uint64_t HCPhysInput, uint64_t HCPhysOutput);
63
64	/**
65	* WinHvr.sys!WinHvDepositMemory
66	*
67	* This API will try allocates cPages on IdealNode and deposit it to the
68	* hypervisor for use with the given partition. The memory will be freed when
69	* VID.SYS calls WinHvWithdrawAllMemory when the partition is cleanedup.
70	*
71	* Apparently node numbers above 64 has a different meaning.
72	*/
73	static NTSTATUS (g_pfnWinHvDepositMemory)(uintptr_t idPartition, size_t cPages, uintptr_t IdealNode, size_t pcActuallyAdded);
74
75
76	/*********************************************************************************************************************************
77	* Internal Functions *
78	*********************************************************************************************************************************/
79	NEM_TMPL_STATIC int nemR0WinMapPages(PGVM pGVM, PVM pVM, PGVMCPU pGVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
80	uint32_t cPages, uint32_t fFlags);
81	NEM_TMPL_STATIC int nemR0WinUnmapPages(PGVM pGVM, PGVMCPU pGVCpu, RTGCPHYS GCPhys, uint32_t cPages);
82	NEM_TMPL_STATIC int nemR0WinExportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx);
83	NEM_TMPL_STATIC int nemR0WinImportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx, uint64_t fWhat);
84	DECLINLINE(NTSTATUS) nemR0NtPerformIoControl(PGVM pGVM, uint32_t uFunction, void *pvInput, uint32_t cbInput,
85	void *pvOutput, uint32_t cbOutput);
86
87
88	/*
89	* Instantate the code we share with ring-0.
90	*/
91	#include "../VMMAll/NEMAllNativeTemplate-win.cpp.h"
92
93	/**
94	* Worker for NEMR0InitVM that allocates a hypercall page.
95	*
96	* @returns VBox status code.
97	* @param pHypercallData The hypercall data page to initialize.
98	*/
99	static int nemR0InitHypercallData(PNEMR0HYPERCALLDATA pHypercallData)
100	{
101	int rc = RTR0MemObjAllocPage(&pHypercallData->hMemObj, PAGE_SIZE, false /fExecutable/);
102	if (RT_SUCCESS(rc))
103	{
104	pHypercallData->HCPhysPage = RTR0MemObjGetPagePhysAddr(pHypercallData->hMemObj, 0 /iPage/);
105	AssertStmt(pHypercallData->HCPhysPage != NIL_RTHCPHYS, rc = VERR_INTERNAL_ERROR_3);
106	pHypercallData->pbPage = (uint8_t *)RTR0MemObjAddress(pHypercallData->hMemObj);
107	AssertStmt(pHypercallData->pbPage, rc = VERR_INTERNAL_ERROR_3);
108	if (RT_SUCCESS(rc))
109	return VINF_SUCCESS;
110
111	/* bail out */
112	RTR0MemObjFree(pHypercallData->hMemObj, true /fFreeMappings/);
113	}
114	pHypercallData->hMemObj = NIL_RTR0MEMOBJ;
115	pHypercallData->HCPhysPage = NIL_RTHCPHYS;
116	pHypercallData->pbPage = NULL;
117	return rc;
118	}
119
120	/**
121	* Worker for NEMR0CleanupVM and NEMR0InitVM that cleans up a hypercall page.
122	*
123	* @param pHypercallData The hypercall data page to uninitialize.
124	*/
125	static void nemR0DeleteHypercallData(PNEMR0HYPERCALLDATA pHypercallData)
126	{
127	/* Check pbPage here since it's NULL, whereas the hMemObj can be either
128	NIL_RTR0MEMOBJ or 0 (they aren't necessarily the same). */
129	if (pHypercallData->pbPage != NULL)
130	{
131	RTR0MemObjFree(pHypercallData->hMemObj, true /fFreeMappings/);
132	pHypercallData->pbPage = NULL;
133	}
134	pHypercallData->hMemObj = NIL_RTR0MEMOBJ;
135	pHypercallData->HCPhysPage = NIL_RTHCPHYS;
136	}
137
138
139	/**
140	* Called by NEMR3Init to make sure we've got what we need.
141	*
142	* @returns VBox status code.
143	* @param pGVM The ring-0 VM handle.
144	* @param pVM The cross context VM handle.
145	* @thread EMT(0)
146	*/
147	VMMR0_INT_DECL(int) NEMR0InitVM(PGVM pGVM, PVM pVM)
148	{
149	AssertCompile(sizeof(pGVM->nem.s) <= sizeof(pGVM->nem.padding));
150	AssertCompile(sizeof(pGVM->aCpus[0].nem.s) <= sizeof(pGVM->aCpus[0].nem.padding));
151
152	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, 0);
153	AssertRCReturn(rc, rc);
154
155	/*
156	* We want to perform hypercalls here. The NT kernel started to expose a very low
157	* level interface to do this thru somewhere between build 14271 and 16299. Since
158	* we need build 17134 to get anywhere at all, the exact build is not relevant here.
159	*
160	* We also need to deposit memory to the hypervisor for use with partition (page
161	* mapping structures, stuff).
162	*/
163	RTDBGKRNLINFO hKrnlInfo;
164	rc = RTR0DbgKrnlInfoOpen(&hKrnlInfo, 0);
165	if (RT_SUCCESS(rc))
166	{
167	rc = RTR0DbgKrnlInfoQuerySymbol(hKrnlInfo, NULL, "HvlInvokeHypercall", (void **)&g_pfnHvlInvokeHypercall);
168	if (RT_SUCCESS(rc))
169	rc = RTR0DbgKrnlInfoQuerySymbol(hKrnlInfo, "winhvr.sys", "WinHvDepositMemory", (void **)&g_pfnWinHvDepositMemory);
170	RTR0DbgKrnlInfoRelease(hKrnlInfo);
171	if (RT_SUCCESS(rc))
172	{
173	/*
174	* Allocate a page for non-EMT threads to use for hypercalls (update
175	* statistics and such) and a critical section protecting it.
176	*/
177	rc = RTCritSectInit(&pGVM->nem.s.HypercallDataCritSect);
178	if (RT_SUCCESS(rc))
179	{
180	rc = nemR0InitHypercallData(&pGVM->nem.s.HypercallData);
181	if (RT_SUCCESS(rc))
182	{
183	/*
184	* Allocate a page for each VCPU to place hypercall data on.
185	*/
186	for (VMCPUID i = 0; i < pGVM->cCpus; i++)
187	{
188	rc = nemR0InitHypercallData(&pGVM->aCpus[i].nem.s.HypercallData);
189	if (RT_FAILURE(rc))
190	{
191	while (i-- > 0)
192	nemR0DeleteHypercallData(&pGVM->aCpus[i].nem.s.HypercallData);
193	break;
194	}
195	}
196	if (RT_SUCCESS(rc))
197	{
198	/*
199	* So far, so good.
200	*/
201	return rc;
202	}
203
204	/*
205	* Bail out.
206	*/
207	nemR0DeleteHypercallData(&pGVM->nem.s.HypercallData);
208	}
209	RTCritSectDelete(&pGVM->nem.s.HypercallDataCritSect);
210	}
211	}
212	else
213	rc = VERR_NEM_MISSING_KERNEL_API;
214	}
215
216	RT_NOREF(pVM);
217	return rc;
218	}
219
220
221	/**
222	* Perform an I/O control operation on the partition handle (VID.SYS).
223	*
224	* @returns NT status code.
225	* @param pGVM The ring-0 VM structure.
226	* @param uFunction The function to perform.
227	* @param pvInput The input buffer. This must point within the VM
228	* structure so we can easily convert to a ring-3
229	* pointer if necessary.
230	* @param cbInput The size of the input. @a pvInput must be NULL when
231	* zero.
232	* @param pvOutput The output buffer. This must also point within the
233	* VM structure for ring-3 pointer magic.
234	* @param cbOutput The size of the output. @a pvOutput must be NULL
235	* when zero.
236	*/
237	DECLINLINE(NTSTATUS) nemR0NtPerformIoControl(PGVM pGVM, uint32_t uFunction, void *pvInput, uint32_t cbInput,
238	void *pvOutput, uint32_t cbOutput)
239	{
240	#ifdef RT_STRICT
241	/*
242	* Input and output parameters are part of the VM CPU structure.
243	*/
244	PVM pVM = pGVM->pVM;
245	size_t const cbVM = RT_UOFFSETOF(VM, aCpus[pGVM->cCpus]);
246	if (pvInput)
247	AssertReturn(((uintptr_t)pvInput + cbInput) - (uintptr_t)pVM <= cbVM, VERR_INVALID_PARAMETER);
248	if (pvOutput)
249	AssertReturn(((uintptr_t)pvOutput + cbOutput) - (uintptr_t)pVM <= cbVM, VERR_INVALID_PARAMETER);
250	#endif
251
252	int32_t rcNt = STATUS_UNSUCCESSFUL;
253	int rc = SUPR0IoCtlPerform(pGVM->nem.s.pIoCtlCtx, uFunction,
254	pvInput,
255	pvInput ? (uintptr_t)pvInput + pGVM->nem.s.offRing3ConversionDelta : NIL_RTR3PTR,
256	cbInput,
257	pvOutput,
258	pvOutput ? (uintptr_t)pvOutput + pGVM->nem.s.offRing3ConversionDelta : NIL_RTR3PTR,
259	cbOutput,
260	&rcNt);
261	if (RT_SUCCESS(rc) \|\| !NT_SUCCESS((NTSTATUS)rcNt))
262	return (NTSTATUS)rcNt;
263	return STATUS_UNSUCCESSFUL;
264	}
265
266
267	/**
268	* 2nd part of the initialization, after we've got a partition handle.
269	*
270	* @returns VBox status code.
271	* @param pGVM The ring-0 VM handle.
272	* @param pVM The cross context VM handle.
273	* @thread EMT(0)
274	*/
275	VMMR0_INT_DECL(int) NEMR0InitVMPart2(PGVM pGVM, PVM pVM)
276	{
277	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, 0);
278	AssertRCReturn(rc, rc);
279	SUPR0Printf("NEMR0InitVMPart2\n"); LogRel(("2: NEMR0InitVMPart2\n"));
280
281	/*
282	* Copy and validate the I/O control information from ring-3.
283	*/
284	NEMWINIOCTL Copy = pVM->nem.s.IoCtlGetHvPartitionId;
285	AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
286	AssertLogRelReturn(Copy.cbInput == 0, VERR_NEM_INIT_FAILED);
287	AssertLogRelReturn(Copy.cbOutput == sizeof(HV_PARTITION_ID), VERR_NEM_INIT_FAILED);
288	pGVM->nem.s.IoCtlGetHvPartitionId = Copy;
289
290	Copy = pVM->nem.s.IoCtlStartVirtualProcessor;
291	AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
292	AssertLogRelReturn(Copy.cbInput == sizeof(HV_VP_INDEX), VERR_NEM_INIT_FAILED);
293	AssertLogRelReturn(Copy.cbOutput == 0, VERR_NEM_INIT_FAILED);
294	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, VERR_NEM_INIT_FAILED);
295	pGVM->nem.s.IoCtlStartVirtualProcessor = Copy;
296
297	Copy = pVM->nem.s.IoCtlStopVirtualProcessor;
298	AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
299	AssertLogRelReturn(Copy.cbInput == sizeof(HV_VP_INDEX), VERR_NEM_INIT_FAILED);
300	AssertLogRelReturn(Copy.cbOutput == 0, VERR_NEM_INIT_FAILED);
301	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, VERR_NEM_INIT_FAILED);
302	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlStartVirtualProcessor.uFunction, VERR_NEM_INIT_FAILED);
303	pGVM->nem.s.IoCtlStopVirtualProcessor = Copy;
304
305	Copy = pVM->nem.s.IoCtlMessageSlotHandleAndGetNext;
306	AssertLogRelReturn(Copy.uFunction != 0, VERR_NEM_INIT_FAILED);
307	AssertLogRelReturn(Copy.cbInput == sizeof(VID_IOCTL_INPUT_MESSAGE_SLOT_HANDLE_AND_GET_NEXT), VERR_NEM_INIT_FAILED);
308	AssertLogRelReturn(Copy.cbOutput == 0, VERR_NEM_INIT_FAILED);
309	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, VERR_NEM_INIT_FAILED);
310	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlStartVirtualProcessor.uFunction, VERR_NEM_INIT_FAILED);
311	AssertLogRelReturn(Copy.uFunction != pGVM->nem.s.IoCtlStopVirtualProcessor.uFunction, VERR_NEM_INIT_FAILED);
312	pGVM->nem.s.IoCtlMessageSlotHandleAndGetNext = Copy;
313
314	/*
315	* Setup of an I/O control context for the partition handle for later use.
316	*/
317	rc = SUPR0IoCtlSetupForHandle(pGVM->pSession, pVM->nem.s.hPartitionDevice, 0, &pGVM->nem.s.pIoCtlCtx);
318	AssertLogRelRCReturn(rc, rc);
319	pGVM->nem.s.offRing3ConversionDelta = (uintptr_t)pVM->pVMR3 - (uintptr_t)pGVM->pVM;
320
321	/*
322	* Get the partition ID.
323	*/
324	PVMCPU pVCpu = &pGVM->pVM->aCpus[0];
325	NTSTATUS rcNt = nemR0NtPerformIoControl(pGVM, pGVM->nem.s.IoCtlGetHvPartitionId.uFunction, NULL, 0,
326	&pVCpu->nem.s.uIoCtlBuf.idPartition, sizeof(pVCpu->nem.s.uIoCtlBuf.idPartition));
327	AssertLogRelMsgReturn(NT_SUCCESS(rcNt), ("IoCtlGetHvPartitionId failed: %#x\n", rcNt), VERR_NEM_INIT_FAILED);
328	pGVM->nem.s.idHvPartition = pVCpu->nem.s.uIoCtlBuf.idPartition;
329	AssertLogRelMsgReturn(pGVM->nem.s.idHvPartition == pVM->nem.s.idHvPartition,
330	("idHvPartition mismatch: r0=%#RX64, r3=%#RX64\n", pGVM->nem.s.idHvPartition, pVM->nem.s.idHvPartition),
331	VERR_NEM_INIT_FAILED);
332
333
334	return rc;
335	}
336
337
338	/**
339	* Cleanup the NEM parts of the VM in ring-0.
340	*
341	* This is always called and must deal the state regardless of whether
342	* NEMR0InitVM() was called or not. So, take care here.
343	*
344	* @param pGVM The ring-0 VM handle.
345	*/
346	VMMR0_INT_DECL(void) NEMR0CleanupVM(PGVM pGVM)
347	{
348	pGVM->nem.s.idHvPartition = HV_PARTITION_ID_INVALID;
349
350	/* Clean up I/O control context. */
351	if (pGVM->nem.s.pIoCtlCtx)
352	{
353	int rc = SUPR0IoCtlCleanup(pGVM->nem.s.pIoCtlCtx);
354	AssertRC(rc);
355	pGVM->nem.s.pIoCtlCtx = NULL;
356	}
357
358	/* Free the hypercall pages. */
359	VMCPUID i = pGVM->cCpus;
360	while (i-- > 0)
361	nemR0DeleteHypercallData(&pGVM->aCpus[i].nem.s.HypercallData);
362
363	/* The non-EMT one too. */
364	if (RTCritSectIsInitialized(&pGVM->nem.s.HypercallDataCritSect))
365	RTCritSectDelete(&pGVM->nem.s.HypercallDataCritSect);
366	nemR0DeleteHypercallData(&pGVM->nem.s.HypercallData);
367	}
368
369
370	#if 0 /* for debugging GPA unmapping. */
371	static int nemR3WinDummyReadGpa(PGVM pGVM, PGVMCPU pGVCpu, RTGCPHYS GCPhys)
372	{
373	PHV_INPUT_READ_GPA pIn = (PHV_INPUT_READ_GPA)pGVCpu->nem.s.pbHypercallData;
374	PHV_OUTPUT_READ_GPA pOut = (PHV_OUTPUT_READ_GPA)(pIn + 1);
375	pIn->PartitionId = pGVM->nem.s.idHvPartition;
376	pIn->VpIndex = pGVCpu->idCpu;
377	pIn->ByteCount = 0x10;
378	pIn->BaseGpa = GCPhys;
379	pIn->ControlFlags.AsUINT64 = 0;
380	pIn->ControlFlags.CacheType = HvCacheTypeX64WriteCombining;
381	memset(pOut, 0xfe, sizeof(*pOut));
382	uint64_t volatile uResult = g_pfnHvlInvokeHypercall(HvCallReadGpa, pGVCpu->nem.s.HCPhysHypercallData,
383	pGVCpu->nem.s.HCPhysHypercallData + sizeof(*pIn));
384	LogRel(("nemR3WinDummyReadGpa: %RGp -> %#RX64; code=%u rsvd=%u abData=%.16Rhxs\n",
385	GCPhys, uResult, pOut->AccessResult.ResultCode, pOut->AccessResult.Reserved, pOut->Data));
386	__debugbreak();
387
388	return uResult != 0 ? VERR_READ_ERROR : VINF_SUCCESS;
389	}
390	#endif
391
392
393	/**
394	* Worker for NEMR0MapPages and others.
395	*/
396	NEM_TMPL_STATIC int nemR0WinMapPages(PGVM pGVM, PVM pVM, PGVMCPU pGVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
397	uint32_t cPages, uint32_t fFlags)
398	{
399	/*
400	* Validate.
401	*/
402	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
403
404	AssertReturn(cPages > 0, VERR_OUT_OF_RANGE);
405	AssertReturn(cPages <= NEM_MAX_MAP_PAGES, VERR_OUT_OF_RANGE);
406	AssertReturn(!(fFlags & ~(HV_MAP_GPA_MAYBE_ACCESS_MASK & ~HV_MAP_GPA_DUNNO_ACCESS)), VERR_INVALID_FLAGS);
407	AssertMsgReturn(!(GCPhysDst & X86_PAGE_OFFSET_MASK), ("GCPhysDst=%RGp\n", GCPhysDst), VERR_OUT_OF_RANGE);
408	AssertReturn(GCPhysDst < _1E, VERR_OUT_OF_RANGE);
409	if (GCPhysSrc != GCPhysDst)
410	{
411	AssertMsgReturn(!(GCPhysSrc & X86_PAGE_OFFSET_MASK), ("GCPhysSrc=%RGp\n", GCPhysSrc), VERR_OUT_OF_RANGE);
412	AssertReturn(GCPhysSrc < _1E, VERR_OUT_OF_RANGE);
413	}
414
415	/*
416	* Compose and make the hypercall.
417	* Ring-3 is not allowed to fill in the host physical addresses of the call.
418	*/
419	HV_INPUT_MAP_GPA_PAGES pMapPages = (HV_INPUT_MAP_GPA_PAGES )pGVCpu->nem.s.HypercallData.pbPage;
420	AssertPtrReturn(pMapPages, VERR_INTERNAL_ERROR_3);
421	pMapPages->TargetPartitionId = pGVM->nem.s.idHvPartition;
422	pMapPages->TargetGpaBase = GCPhysDst >> X86_PAGE_SHIFT;
423	pMapPages->MapFlags = fFlags;
424	pMapPages->u32ExplicitPadding = 0;
425	for (uint32_t iPage = 0; iPage < cPages; iPage++, GCPhysSrc += X86_PAGE_SIZE)
426	{
427	RTHCPHYS HCPhys = NIL_RTGCPHYS;
428	int rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysSrc, &HCPhys);
429	AssertRCReturn(rc, rc);
430	pMapPages->PageList[iPage] = HCPhys >> X86_PAGE_SHIFT;
431	}
432
433	uint64_t uResult = g_pfnHvlInvokeHypercall(HvCallMapGpaPages \| ((uint64_t)cPages << 32),
434	pGVCpu->nem.s.HypercallData.HCPhysPage, 0);
435	Log6(("NEMR0MapPages: %RGp/%RGp L %u prot %#x -> %#RX64\n",
436	GCPhysDst, GCPhysSrc - cPages * X86_PAGE_SIZE, cPages, fFlags, uResult));
437	if (uResult == ((uint64_t)cPages << 32))
438	return VINF_SUCCESS;
439
440	LogRel(("g_pfnHvlInvokeHypercall/MapGpaPages -> %#RX64\n", uResult));
441	return VERR_NEM_MAP_PAGES_FAILED;
442	}
443
444
445	/**
446	* Maps pages into the guest physical address space.
447	*
448	* Generally the caller will be under the PGM lock already, so no extra effort
449	* is needed to make sure all changes happens under it.
450	*
451	* @returns VBox status code.
452	* @param pGVM The ring-0 VM handle.
453	* @param pVM The cross context VM handle.
454	* @param idCpu The calling EMT. Necessary for getting the
455	* hypercall page and arguments.
456	* @thread EMT(idCpu)
457	*/
458	VMMR0_INT_DECL(int) NEMR0MapPages(PGVM pGVM, PVM pVM, VMCPUID idCpu)
459	{
460	/*
461	* Unpack the call.
462	*/
463	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
464	if (RT_SUCCESS(rc))
465	{
466	PVMCPU pVCpu = &pVM->aCpus[idCpu];
467	PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
468
469	RTGCPHYS const GCPhysSrc = pVCpu->nem.s.Hypercall.MapPages.GCPhysSrc;
470	RTGCPHYS const GCPhysDst = pVCpu->nem.s.Hypercall.MapPages.GCPhysDst;
471	uint32_t const cPages = pVCpu->nem.s.Hypercall.MapPages.cPages;
472	HV_MAP_GPA_FLAGS const fFlags = pVCpu->nem.s.Hypercall.MapPages.fFlags;
473
474	/*
475	* Do the work.
476	*/
477	rc = nemR0WinMapPages(pGVM, pVM, pGVCpu, GCPhysSrc, GCPhysDst, cPages, fFlags);
478	}
479	return rc;
480	}
481
482
483	/**
484	* Worker for NEMR0UnmapPages and others.
485	*/
486	NEM_TMPL_STATIC int nemR0WinUnmapPages(PGVM pGVM, PGVMCPU pGVCpu, RTGCPHYS GCPhys, uint32_t cPages)
487	{
488	/*
489	* Validate input.
490	*/
491	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
492
493	AssertReturn(cPages > 0, VERR_OUT_OF_RANGE);
494	AssertReturn(cPages <= NEM_MAX_UNMAP_PAGES, VERR_OUT_OF_RANGE);
495	AssertMsgReturn(!(GCPhys & X86_PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_OUT_OF_RANGE);
496	AssertReturn(GCPhys < _1E, VERR_OUT_OF_RANGE);
497
498	/*
499	* Compose and make the hypercall.
500	*/
501	HV_INPUT_UNMAP_GPA_PAGES pUnmapPages = (HV_INPUT_UNMAP_GPA_PAGES )pGVCpu->nem.s.HypercallData.pbPage;
502	AssertPtrReturn(pUnmapPages, VERR_INTERNAL_ERROR_3);
503	pUnmapPages->TargetPartitionId = pGVM->nem.s.idHvPartition;
504	pUnmapPages->TargetGpaBase = GCPhys >> X86_PAGE_SHIFT;
505	pUnmapPages->fFlags = 0;
506
507	uint64_t uResult = g_pfnHvlInvokeHypercall(HvCallUnmapGpaPages \| ((uint64_t)cPages << 32),
508	pGVCpu->nem.s.HypercallData.HCPhysPage, 0);
509	Log6(("NEMR0UnmapPages: %RGp L %u -> %#RX64\n", GCPhys, cPages, uResult));
510	if (uResult == ((uint64_t)cPages << 32))
511	{
512	#if 1 /* Do we need to do this? Hopefully not... */
513	uint64_t volatile uR = g_pfnHvlInvokeHypercall(HvCallUncommitGpaPages \| ((uint64_t)cPages << 32),
514	pGVCpu->nem.s.HypercallData.HCPhysPage, 0);
515	AssertMsg(uR == ((uint64_t)cPages << 32), ("uR=%#RX64\n", uR)); NOREF(uR);
516	#endif
517	return VINF_SUCCESS;
518	}
519
520	LogRel(("g_pfnHvlInvokeHypercall/UnmapGpaPages -> %#RX64\n", uResult));
521	return VERR_NEM_UNMAP_PAGES_FAILED;
522	}
523
524
525	/**
526	* Unmaps pages from the guest physical address space.
527	*
528	* Generally the caller will be under the PGM lock already, so no extra effort
529	* is needed to make sure all changes happens under it.
530	*
531	* @returns VBox status code.
532	* @param pGVM The ring-0 VM handle.
533	* @param pVM The cross context VM handle.
534	* @param idCpu The calling EMT. Necessary for getting the
535	* hypercall page and arguments.
536	* @thread EMT(idCpu)
537	*/
538	VMMR0_INT_DECL(int) NEMR0UnmapPages(PGVM pGVM, PVM pVM, VMCPUID idCpu)
539	{
540	/*
541	* Unpack the call.
542	*/
543	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
544	if (RT_SUCCESS(rc))
545	{
546	PVMCPU pVCpu = &pVM->aCpus[idCpu];
547	PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
548
549	RTGCPHYS const GCPhys = pVCpu->nem.s.Hypercall.UnmapPages.GCPhys;
550	uint32_t const cPages = pVCpu->nem.s.Hypercall.UnmapPages.cPages;
551
552	/*
553	* Do the work.
554	*/
555	rc = nemR0WinUnmapPages(pGVM, pGVCpu, GCPhys, cPages);
556	}
557	return rc;
558	}
559
560
561	/**
562	* Worker for NEMR0ExportState.
563	*
564	* Intention is to use it internally later.
565	*
566	* @returns VBox status code.
567	* @param pGVM The ring-0 VM handle.
568	* @param pGVCpu The irng-0 VCPU handle.
569	* @param pCtx The CPU context structure to import into.
570	*/
571	NEM_TMPL_STATIC int nemR0WinExportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx)
572	{
573	PVMCPU pVCpu = &pGVM->pVM->aCpus[pGVCpu->idCpu];
574	HV_INPUT_SET_VP_REGISTERS pInput = (HV_INPUT_SET_VP_REGISTERS )pGVCpu->nem.s.HypercallData.pbPage;
575	AssertPtrReturn(pInput, VERR_INTERNAL_ERROR_3);
576
577	pInput->PartitionId = pGVM->nem.s.idHvPartition;
578	pInput->VpIndex = pGVCpu->idCpu;
579	pInput->RsvdZ = 0;
580
581	uint64_t const fWhat = ~pCtx->fExtrn & (CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK);
582	if ( !fWhat
583	&& pVCpu->nem.s.fCurrentInterruptWindows == pVCpu->nem.s.fDesiredInterruptWindows)
584	return VINF_SUCCESS;
585	uintptr_t iReg = 0;
586
587	/* GPRs */
588	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
589	{
590	if (fWhat & CPUMCTX_EXTRN_RAX)
591	{
592	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
593	pInput->Elements[iReg].Name = HvX64RegisterRax;
594	pInput->Elements[iReg].Value.Reg64 = pCtx->rax;
595	iReg++;
596	}
597	if (fWhat & CPUMCTX_EXTRN_RCX)
598	{
599	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
600	pInput->Elements[iReg].Name = HvX64RegisterRcx;
601	pInput->Elements[iReg].Value.Reg64 = pCtx->rcx;
602	iReg++;
603	}
604	if (fWhat & CPUMCTX_EXTRN_RDX)
605	{
606	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
607	pInput->Elements[iReg].Name = HvX64RegisterRdx;
608	pInput->Elements[iReg].Value.Reg64 = pCtx->rdx;
609	iReg++;
610	}
611	if (fWhat & CPUMCTX_EXTRN_RBX)
612	{
613	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
614	pInput->Elements[iReg].Name = HvX64RegisterRbx;
615	pInput->Elements[iReg].Value.Reg64 = pCtx->rbx;
616	iReg++;
617	}
618	if (fWhat & CPUMCTX_EXTRN_RSP)
619	{
620	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
621	pInput->Elements[iReg].Name = HvX64RegisterRsp;
622	pInput->Elements[iReg].Value.Reg64 = pCtx->rsp;
623	iReg++;
624	}
625	if (fWhat & CPUMCTX_EXTRN_RBP)
626	{
627	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
628	pInput->Elements[iReg].Name = HvX64RegisterRbp;
629	pInput->Elements[iReg].Value.Reg64 = pCtx->rbp;
630	iReg++;
631	}
632	if (fWhat & CPUMCTX_EXTRN_RSI)
633	{
634	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
635	pInput->Elements[iReg].Name = HvX64RegisterRsi;
636	pInput->Elements[iReg].Value.Reg64 = pCtx->rsi;
637	iReg++;
638	}
639	if (fWhat & CPUMCTX_EXTRN_RDI)
640	{
641	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
642	pInput->Elements[iReg].Name = HvX64RegisterRdi;
643	pInput->Elements[iReg].Value.Reg64 = pCtx->rdi;
644	iReg++;
645	}
646	if (fWhat & CPUMCTX_EXTRN_R8_R15)
647	{
648	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
649	pInput->Elements[iReg].Name = HvX64RegisterR8;
650	pInput->Elements[iReg].Value.Reg64 = pCtx->r8;
651	iReg++;
652	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
653	pInput->Elements[iReg].Name = HvX64RegisterR9;
654	pInput->Elements[iReg].Value.Reg64 = pCtx->r9;
655	iReg++;
656	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
657	pInput->Elements[iReg].Name = HvX64RegisterR10;
658	pInput->Elements[iReg].Value.Reg64 = pCtx->r10;
659	iReg++;
660	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
661	pInput->Elements[iReg].Name = HvX64RegisterR11;
662	pInput->Elements[iReg].Value.Reg64 = pCtx->r11;
663	iReg++;
664	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
665	pInput->Elements[iReg].Name = HvX64RegisterR12;
666	pInput->Elements[iReg].Value.Reg64 = pCtx->r12;
667	iReg++;
668	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
669	pInput->Elements[iReg].Name = HvX64RegisterR13;
670	pInput->Elements[iReg].Value.Reg64 = pCtx->r13;
671	iReg++;
672	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
673	pInput->Elements[iReg].Name = HvX64RegisterR14;
674	pInput->Elements[iReg].Value.Reg64 = pCtx->r14;
675	iReg++;
676	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
677	pInput->Elements[iReg].Name = HvX64RegisterR15;
678	pInput->Elements[iReg].Value.Reg64 = pCtx->r15;
679	iReg++;
680	}
681	}
682
683	/* RIP & Flags */
684	if (fWhat & CPUMCTX_EXTRN_RIP)
685	{
686	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
687	pInput->Elements[iReg].Name = HvX64RegisterRip;
688	pInput->Elements[iReg].Value.Reg64 = pCtx->rip;
689	iReg++;
690	}
691	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
692	{
693	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
694	pInput->Elements[iReg].Name = HvX64RegisterRflags;
695	pInput->Elements[iReg].Value.Reg64 = pCtx->rflags.u;
696	iReg++;
697	}
698
699	/* Segments */
700	#define COPY_OUT_SEG(a_idx, a_enmName, a_SReg) \
701	do { \
702	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[a_idx]); \
703	pInput->Elements[a_idx].Name = a_enmName; \
704	pInput->Elements[a_idx].Value.Segment.Base = (a_SReg).u64Base; \
705	pInput->Elements[a_idx].Value.Segment.Limit = (a_SReg).u32Limit; \
706	pInput->Elements[a_idx].Value.Segment.Selector = (a_SReg).Sel; \
707	pInput->Elements[a_idx].Value.Segment.Attributes = (a_SReg).Attr.u; \
708	} while (0)
709	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
710	{
711	if (fWhat & CPUMCTX_EXTRN_CS)
712	{
713	COPY_OUT_SEG(iReg, HvX64RegisterCs, pCtx->cs);
714	iReg++;
715	}
716	if (fWhat & CPUMCTX_EXTRN_ES)
717	{
718	COPY_OUT_SEG(iReg, HvX64RegisterEs, pCtx->es);
719	iReg++;
720	}
721	if (fWhat & CPUMCTX_EXTRN_SS)
722	{
723	COPY_OUT_SEG(iReg, HvX64RegisterSs, pCtx->ss);
724	iReg++;
725	}
726	if (fWhat & CPUMCTX_EXTRN_DS)
727	{
728	COPY_OUT_SEG(iReg, HvX64RegisterDs, pCtx->ds);
729	iReg++;
730	}
731	if (fWhat & CPUMCTX_EXTRN_FS)
732	{
733	COPY_OUT_SEG(iReg, HvX64RegisterFs, pCtx->fs);
734	iReg++;
735	}
736	if (fWhat & CPUMCTX_EXTRN_GS)
737	{
738	COPY_OUT_SEG(iReg, HvX64RegisterGs, pCtx->gs);
739	iReg++;
740	}
741	}
742
743	/* Descriptor tables & task segment. */
744	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
745	{
746	if (fWhat & CPUMCTX_EXTRN_LDTR)
747	{
748	COPY_OUT_SEG(iReg, HvX64RegisterLdtr, pCtx->ldtr);
749	iReg++;
750	}
751	if (fWhat & CPUMCTX_EXTRN_TR)
752	{
753	COPY_OUT_SEG(iReg, HvX64RegisterTr, pCtx->tr);
754	iReg++;
755	}
756
757	if (fWhat & CPUMCTX_EXTRN_IDTR)
758	{
759	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
760	pInput->Elements[iReg].Value.Table.Pad[0] = 0;
761	pInput->Elements[iReg].Value.Table.Pad[1] = 0;
762	pInput->Elements[iReg].Value.Table.Pad[2] = 0;
763	pInput->Elements[iReg].Name = HvX64RegisterIdtr;
764	pInput->Elements[iReg].Value.Table.Limit = pCtx->idtr.cbIdt;
765	pInput->Elements[iReg].Value.Table.Base = pCtx->idtr.pIdt;
766	iReg++;
767	}
768	if (fWhat & CPUMCTX_EXTRN_GDTR)
769	{
770	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
771	pInput->Elements[iReg].Value.Table.Pad[0] = 0;
772	pInput->Elements[iReg].Value.Table.Pad[1] = 0;
773	pInput->Elements[iReg].Value.Table.Pad[2] = 0;
774	pInput->Elements[iReg].Name = HvX64RegisterGdtr;
775	pInput->Elements[iReg].Value.Table.Limit = pCtx->gdtr.cbGdt;
776	pInput->Elements[iReg].Value.Table.Base = pCtx->gdtr.pGdt;
777	iReg++;
778	}
779	}
780
781	/* Control registers. */
782	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
783	{
784	if (fWhat & CPUMCTX_EXTRN_CR0)
785	{
786	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
787	pInput->Elements[iReg].Name = HvX64RegisterCr0;
788	pInput->Elements[iReg].Value.Reg64 = pCtx->cr0;
789	iReg++;
790	}
791	if (fWhat & CPUMCTX_EXTRN_CR2)
792	{
793	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
794	pInput->Elements[iReg].Name = HvX64RegisterCr2;
795	pInput->Elements[iReg].Value.Reg64 = pCtx->cr2;
796	iReg++;
797	}
798	if (fWhat & CPUMCTX_EXTRN_CR3)
799	{
800	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
801	pInput->Elements[iReg].Name = HvX64RegisterCr3;
802	pInput->Elements[iReg].Value.Reg64 = pCtx->cr3;
803	iReg++;
804	}
805	if (fWhat & CPUMCTX_EXTRN_CR4)
806	{
807	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
808	pInput->Elements[iReg].Name = HvX64RegisterCr4;
809	pInput->Elements[iReg].Value.Reg64 = pCtx->cr4;
810	iReg++;
811	}
812	}
813	/** @todo CR8/TPR */
814	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
815	pInput->Elements[iReg].Name = HvX64RegisterCr8;
816	pInput->Elements[iReg].Value.Reg64 = CPUMGetGuestCR8(pVCpu);
817	iReg++;
818
819	/** @todo does HvX64RegisterXfem mean XCR0? What about the related MSR. */
820
821	/* Debug registers. */
822	/** @todo fixme. Figure out what the hyper-v version of KVM_SET_GUEST_DEBUG would be. */
823	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
824	{
825	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
826	pInput->Elements[iReg].Name = HvX64RegisterDr0;
827	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR0(pVCpu);
828	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[0];
829	iReg++;
830	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
831	pInput->Elements[iReg].Name = HvX64RegisterDr1;
832	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR1(pVCpu);
833	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[1];
834	iReg++;
835	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
836	pInput->Elements[iReg].Name = HvX64RegisterDr2;
837	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR2(pVCpu);
838	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[2];
839	iReg++;
840	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
841	pInput->Elements[iReg].Name = HvX64RegisterDr3;
842	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR3(pVCpu);
843	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[3];
844	iReg++;
845	}
846	if (fWhat & CPUMCTX_EXTRN_DR6)
847	{
848	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
849	pInput->Elements[iReg].Name = HvX64RegisterDr6;
850	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR6(pVCpu);
851	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[6];
852	iReg++;
853	}
854	if (fWhat & CPUMCTX_EXTRN_DR7)
855	{
856	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
857	pInput->Elements[iReg].Name = HvX64RegisterDr7;
858	//pInput->Elements[iReg].Value.Reg64 = CPUMGetHyperDR7(pVCpu);
859	pInput->Elements[iReg].Value.Reg64 = pCtx->dr[7];
860	iReg++;
861	}
862
863	/* Floating point state. */
864	if (fWhat & CPUMCTX_EXTRN_X87)
865	{
866	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
867	pInput->Elements[iReg].Name = HvX64RegisterFpMmx0;
868	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[0].au64[0];
869	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[0].au64[1];
870	iReg++;
871	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
872	pInput->Elements[iReg].Name = HvX64RegisterFpMmx1;
873	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[1].au64[0];
874	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[1].au64[1];
875	iReg++;
876	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
877	pInput->Elements[iReg].Name = HvX64RegisterFpMmx2;
878	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[2].au64[0];
879	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[2].au64[1];
880	iReg++;
881	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
882	pInput->Elements[iReg].Name = HvX64RegisterFpMmx3;
883	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[3].au64[0];
884	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[3].au64[1];
885	iReg++;
886	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
887	pInput->Elements[iReg].Name = HvX64RegisterFpMmx4;
888	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[4].au64[0];
889	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[4].au64[1];
890	iReg++;
891	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
892	pInput->Elements[iReg].Name = HvX64RegisterFpMmx5;
893	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[5].au64[0];
894	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[5].au64[1];
895	iReg++;
896	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
897	pInput->Elements[iReg].Name = HvX64RegisterFpMmx6;
898	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[6].au64[0];
899	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[6].au64[1];
900	iReg++;
901	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
902	pInput->Elements[iReg].Name = HvX64RegisterFpMmx7;
903	pInput->Elements[iReg].Value.Fp.AsUINT128.Low64 = pCtx->pXStateR0->x87.aRegs[7].au64[0];
904	pInput->Elements[iReg].Value.Fp.AsUINT128.High64 = pCtx->pXStateR0->x87.aRegs[7].au64[1];
905	iReg++;
906
907	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
908	pInput->Elements[iReg].Name = HvX64RegisterFpControlStatus;
909	pInput->Elements[iReg].Value.FpControlStatus.FpControl = pCtx->pXStateR0->x87.FCW;
910	pInput->Elements[iReg].Value.FpControlStatus.FpStatus = pCtx->pXStateR0->x87.FSW;
911	pInput->Elements[iReg].Value.FpControlStatus.FpTag = pCtx->pXStateR0->x87.FTW;
912	pInput->Elements[iReg].Value.FpControlStatus.Reserved = pCtx->pXStateR0->x87.FTW >> 8;
913	pInput->Elements[iReg].Value.FpControlStatus.LastFpOp = pCtx->pXStateR0->x87.FOP;
914	pInput->Elements[iReg].Value.FpControlStatus.LastFpRip = (pCtx->pXStateR0->x87.FPUIP)
915	\| ((uint64_t)pCtx->pXStateR0->x87.CS << 32)
916	\| ((uint64_t)pCtx->pXStateR0->x87.Rsrvd1 << 48);
917	iReg++;
918	/** @todo we've got trouble if if we try write just SSE w/o X87. */
919	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
920	pInput->Elements[iReg].Name = HvX64RegisterXmmControlStatus;
921	pInput->Elements[iReg].Value.XmmControlStatus.LastFpRdp = (pCtx->pXStateR0->x87.FPUDP)
922	\| ((uint64_t)pCtx->pXStateR0->x87.DS << 32)
923	\| ((uint64_t)pCtx->pXStateR0->x87.Rsrvd2 << 48);
924	pInput->Elements[iReg].Value.XmmControlStatus.XmmStatusControl = pCtx->pXStateR0->x87.MXCSR;
925	pInput->Elements[iReg].Value.XmmControlStatus.XmmStatusControlMask = pCtx->pXStateR0->x87.MXCSR_MASK; /** @todo ??? (Isn't this an output field?) */
926	iReg++;
927	}
928
929	/* Vector state. */
930	if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
931	{
932	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
933	pInput->Elements[iReg].Name = HvX64RegisterXmm0;
934	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Lo;
935	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Hi;
936	iReg++;
937	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
938	pInput->Elements[iReg].Name = HvX64RegisterXmm1;
939	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Lo;
940	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Hi;
941	iReg++;
942	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
943	pInput->Elements[iReg].Name = HvX64RegisterXmm2;
944	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Lo;
945	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Hi;
946	iReg++;
947	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
948	pInput->Elements[iReg].Name = HvX64RegisterXmm3;
949	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Lo;
950	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Hi;
951	iReg++;
952	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
953	pInput->Elements[iReg].Name = HvX64RegisterXmm4;
954	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Lo;
955	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Hi;
956	iReg++;
957	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
958	pInput->Elements[iReg].Name = HvX64RegisterXmm5;
959	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Lo;
960	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Hi;
961	iReg++;
962	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
963	pInput->Elements[iReg].Name = HvX64RegisterXmm6;
964	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Lo;
965	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Hi;
966	iReg++;
967	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
968	pInput->Elements[iReg].Name = HvX64RegisterXmm7;
969	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Lo;
970	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Hi;
971	iReg++;
972	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
973	pInput->Elements[iReg].Name = HvX64RegisterXmm8;
974	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Lo;
975	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Hi;
976	iReg++;
977	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
978	pInput->Elements[iReg].Name = HvX64RegisterXmm9;
979	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Lo;
980	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Hi;
981	iReg++;
982	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
983	pInput->Elements[iReg].Name = HvX64RegisterXmm10;
984	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Lo;
985	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Hi;
986	iReg++;
987	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
988	pInput->Elements[iReg].Name = HvX64RegisterXmm11;
989	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Lo;
990	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Hi;
991	iReg++;
992	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
993	pInput->Elements[iReg].Name = HvX64RegisterXmm12;
994	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Lo;
995	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Hi;
996	iReg++;
997	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
998	pInput->Elements[iReg].Name = HvX64RegisterXmm13;
999	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Lo;
1000	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Hi;
1001	iReg++;
1002	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
1003	pInput->Elements[iReg].Name = HvX64RegisterXmm14;
1004	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Lo;
1005	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Hi;
1006	iReg++;
1007	HV_REGISTER_ASSOC_ZERO_PADDING(&pInput->Elements[iReg]);
1008	pInput->Elements[iReg].Name = HvX64RegisterXmm15;
1009	pInput->Elements[iReg].Value.Reg128.Low64 = pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Lo;
1010	pInput->Elements[iReg].Value.Reg128.High64 = pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Hi;
1011	iReg++;
1012	}
1013
1014	/* MSRs */
1015	// HvX64RegisterTsc - don't touch
1016	/** @todo does HvX64RegisterTsc include TSC_AUX? Is it TSC_AUX? */
1017	if (fWhat & CPUMCTX_EXTRN_EFER)
1018	{
1019	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1020	pInput->Elements[iReg].Name = HvX64RegisterEfer;
1021	pInput->Elements[iReg].Value.Reg64 = pCtx->msrEFER;
1022	iReg++;
1023	}
1024	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1025	{
1026	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1027	pInput->Elements[iReg].Name = HvX64RegisterKernelGsBase;
1028	pInput->Elements[iReg].Value.Reg64 = pCtx->msrKERNELGSBASE;
1029	iReg++;
1030	}
1031	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1032	{
1033	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1034	pInput->Elements[iReg].Name = HvX64RegisterSysenterCs;
1035	pInput->Elements[iReg].Value.Reg64 = pCtx->SysEnter.cs;
1036	iReg++;
1037	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1038	pInput->Elements[iReg].Name = HvX64RegisterSysenterEip;
1039	pInput->Elements[iReg].Value.Reg64 = pCtx->SysEnter.eip;
1040	iReg++;
1041	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1042	pInput->Elements[iReg].Name = HvX64RegisterSysenterEsp;
1043	pInput->Elements[iReg].Value.Reg64 = pCtx->SysEnter.esp;
1044	iReg++;
1045	}
1046	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1047	{
1048	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1049	pInput->Elements[iReg].Name = HvX64RegisterStar;
1050	pInput->Elements[iReg].Value.Reg64 = pCtx->msrSTAR;
1051	iReg++;
1052	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1053	pInput->Elements[iReg].Name = HvX64RegisterLstar;
1054	pInput->Elements[iReg].Value.Reg64 = pCtx->msrLSTAR;
1055	iReg++;
1056	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1057	pInput->Elements[iReg].Name = HvX64RegisterCstar;
1058	pInput->Elements[iReg].Value.Reg64 = pCtx->msrCSTAR;
1059	iReg++;
1060	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1061	pInput->Elements[iReg].Name = HvX64RegisterSfmask;
1062	pInput->Elements[iReg].Value.Reg64 = pCtx->msrSFMASK;
1063	iReg++;
1064	}
1065	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1066	{
1067	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1068	pInput->Elements[iReg].Name = HvX64RegisterApicBase;
1069	pInput->Elements[iReg].Value.Reg64 = APICGetBaseMsrNoCheck(pVCpu);
1070	iReg++;
1071	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1072	pInput->Elements[iReg].Name = HvX64RegisterPat;
1073	pInput->Elements[iReg].Value.Reg64 = pCtx->msrPAT;
1074	iReg++;
1075	}
1076
1077	/* event injection (always clear it). */
1078	if (fWhat & CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT)
1079	{
1080	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1081	pInput->Elements[iReg].Name = HvRegisterPendingInterruption;
1082	pInput->Elements[iReg].Value.Reg64 = 0;
1083	iReg++;
1084	}
1085
1086	/* Interruptibility state. This can get a little complicated since we get
1087	half of the state via HV_X64_VP_EXECUTION_STATE. */
1088	if ( (fWhat & (CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI))
1089	== (CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI) )
1090	{
1091	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1092	pInput->Elements[iReg].Name = HvRegisterInterruptState;
1093	pInput->Elements[iReg].Value.Reg64 = 0;
1094	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1095	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
1096	pInput->Elements[iReg].Value.InterruptState.InterruptShadow = 1;
1097	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
1098	pInput->Elements[iReg].Value.InterruptState.NmiMasked = 1;
1099	iReg++;
1100	}
1101	else if (fWhat & CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT)
1102	{
1103	if ( pVCpu->nem.s.fLastInterruptShadow
1104	\|\| ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1105	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip))
1106	{
1107	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1108	pInput->Elements[iReg].Name = HvRegisterInterruptState;
1109	pInput->Elements[iReg].Value.Reg64 = 0;
1110	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1111	&& EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
1112	pInput->Elements[iReg].Value.InterruptState.InterruptShadow = 1;
1113	/** @todo Retrieve NMI state, currently assuming it's zero. (yes this may happen on I/O) */
1114	//if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
1115	// pInput->Elements[iReg].Value.InterruptState.NmiMasked = 1;
1116	iReg++;
1117	}
1118	}
1119	else
1120	Assert(!(fWhat & CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI));
1121
1122	/* Interrupt windows. Always set if active as Hyper-V seems to be forgetful. */
1123	uint8_t const fDesiredIntWin = pVCpu->nem.s.fDesiredInterruptWindows;
1124	if ( fDesiredIntWin
1125	\|\| pVCpu->nem.s.fCurrentInterruptWindows != fDesiredIntWin)
1126	{
1127	pVCpu->nem.s.fCurrentInterruptWindows = pVCpu->nem.s.fDesiredInterruptWindows;
1128	HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
1129	pInput->Elements[iReg].Name = HvX64RegisterDeliverabilityNotifications;
1130	pInput->Elements[iReg].Value.DeliverabilityNotifications.AsUINT64 = fDesiredIntWin;
1131	Assert(pInput->Elements[iReg].Value.DeliverabilityNotifications.NmiNotification == RT_BOOL(fDesiredIntWin & NEM_WIN_INTW_F_NMI));
1132	Assert(pInput->Elements[iReg].Value.DeliverabilityNotifications.InterruptNotification == RT_BOOL(fDesiredIntWin & NEM_WIN_INTW_F_REGULAR));
1133	Assert(pInput->Elements[iReg].Value.DeliverabilityNotifications.InterruptPriority == (fDesiredIntWin & NEM_WIN_INTW_F_PRIO_MASK) >> NEM_WIN_INTW_F_PRIO_SHIFT);
1134	iReg++;
1135	}
1136
1137	/// @todo HvRegisterPendingEvent0
1138	/// @todo HvRegisterPendingEvent1
1139
1140	/*
1141	* Set the registers.
1142	*/
1143	Assert((uintptr_t)&pInput->Elements[iReg] - (uintptr_t)pGVCpu->nem.s.HypercallData.pbPage < PAGE_SIZE); /* max is 127 */
1144
1145	/*
1146	* Make the hypercall.
1147	*/
1148	uint64_t uResult = g_pfnHvlInvokeHypercall(HV_MAKE_CALL_INFO(HvCallSetVpRegisters, iReg),
1149	pGVCpu->nem.s.HypercallData.HCPhysPage, 0 /GCPhysOutput/);
1150	AssertLogRelMsgReturn(uResult == HV_MAKE_CALL_REP_RET(iReg),
1151	("uResult=%RX64 iRegs=%#x\n", uResult, iReg),
1152	VERR_NEM_SET_REGISTERS_FAILED);
1153	//LogFlow(("nemR0WinExportState: uResult=%#RX64 iReg=%zu fWhat=%#018RX64 fExtrn=%#018RX64 -> %#018RX64\n", uResult, iReg, fWhat, pCtx->fExtrn,
1154	// pCtx->fExtrn \| CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK \| CPUMCTX_EXTRN_KEEPER_NEM ));
1155	pCtx->fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_NEM_WIN_MASK \| CPUMCTX_EXTRN_KEEPER_NEM;
1156	return VINF_SUCCESS;
1157	}
1158
1159
1160	/**
1161	* Export the state to the native API (out of CPUMCTX).
1162	*
1163	* @returns VBox status code
1164	* @param pGVM The ring-0 VM handle.
1165	* @param pVM The cross context VM handle.
1166	* @param idCpu The calling EMT. Necessary for getting the
1167	* hypercall page and arguments.
1168	*/
1169	VMMR0_INT_DECL(int) NEMR0ExportState(PGVM pGVM, PVM pVM, VMCPUID idCpu)
1170	{
1171	/*
1172	* Validate the call.
1173	*/
1174	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
1175	if (RT_SUCCESS(rc))
1176	{
1177	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1178	PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
1179	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
1180
1181	/*
1182	* Call worker.
1183	*/
1184	rc = nemR0WinExportState(pGVM, pGVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1185	}
1186	return rc;
1187	}
1188
1189
1190	/**
1191	* Worker for NEMR0ImportState.
1192	*
1193	* Intention is to use it internally later.
1194	*
1195	* @returns VBox status code.
1196	* @param pGVM The ring-0 VM handle.
1197	* @param pGVCpu The irng-0 VCPU handle.
1198	* @param pCtx The CPU context structure to import into.
1199	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1200	*/
1201	NEM_TMPL_STATIC int nemR0WinImportState(PGVM pGVM, PGVMCPU pGVCpu, PCPUMCTX pCtx, uint64_t fWhat)
1202	{
1203	HV_INPUT_GET_VP_REGISTERS pInput = (HV_INPUT_GET_VP_REGISTERS )pGVCpu->nem.s.HypercallData.pbPage;
1204	AssertPtrReturn(pInput, VERR_INTERNAL_ERROR_3);
1205
1206	fWhat &= pCtx->fExtrn;
1207
1208	pInput->PartitionId = pGVM->nem.s.idHvPartition;
1209	pInput->VpIndex = pGVCpu->idCpu;
1210	pInput->fFlags = 0;
1211
1212	/* GPRs */
1213	uintptr_t iReg = 0;
1214	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
1215	{
1216	if (fWhat & CPUMCTX_EXTRN_RAX)
1217	pInput->Names[iReg++] = HvX64RegisterRax;
1218	if (fWhat & CPUMCTX_EXTRN_RCX)
1219	pInput->Names[iReg++] = HvX64RegisterRcx;
1220	if (fWhat & CPUMCTX_EXTRN_RDX)
1221	pInput->Names[iReg++] = HvX64RegisterRdx;
1222	if (fWhat & CPUMCTX_EXTRN_RBX)
1223	pInput->Names[iReg++] = HvX64RegisterRbx;
1224	if (fWhat & CPUMCTX_EXTRN_RSP)
1225	pInput->Names[iReg++] = HvX64RegisterRsp;
1226	if (fWhat & CPUMCTX_EXTRN_RBP)
1227	pInput->Names[iReg++] = HvX64RegisterRbp;
1228	if (fWhat & CPUMCTX_EXTRN_RSI)
1229	pInput->Names[iReg++] = HvX64RegisterRsi;
1230	if (fWhat & CPUMCTX_EXTRN_RDI)
1231	pInput->Names[iReg++] = HvX64RegisterRdi;
1232	if (fWhat & CPUMCTX_EXTRN_R8_R15)
1233	{
1234	pInput->Names[iReg++] = HvX64RegisterR8;
1235	pInput->Names[iReg++] = HvX64RegisterR9;
1236	pInput->Names[iReg++] = HvX64RegisterR10;
1237	pInput->Names[iReg++] = HvX64RegisterR11;
1238	pInput->Names[iReg++] = HvX64RegisterR12;
1239	pInput->Names[iReg++] = HvX64RegisterR13;
1240	pInput->Names[iReg++] = HvX64RegisterR14;
1241	pInput->Names[iReg++] = HvX64RegisterR15;
1242	}
1243	}
1244
1245	/* RIP & Flags */
1246	if (fWhat & CPUMCTX_EXTRN_RIP)
1247	pInput->Names[iReg++] = HvX64RegisterRip;
1248	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1249	pInput->Names[iReg++] = HvX64RegisterRflags;
1250
1251	/* Segments */
1252	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1253	{
1254	if (fWhat & CPUMCTX_EXTRN_CS)
1255	pInput->Names[iReg++] = HvX64RegisterCs;
1256	if (fWhat & CPUMCTX_EXTRN_ES)
1257	pInput->Names[iReg++] = HvX64RegisterEs;
1258	if (fWhat & CPUMCTX_EXTRN_SS)
1259	pInput->Names[iReg++] = HvX64RegisterSs;
1260	if (fWhat & CPUMCTX_EXTRN_DS)
1261	pInput->Names[iReg++] = HvX64RegisterDs;
1262	if (fWhat & CPUMCTX_EXTRN_FS)
1263	pInput->Names[iReg++] = HvX64RegisterFs;
1264	if (fWhat & CPUMCTX_EXTRN_GS)
1265	pInput->Names[iReg++] = HvX64RegisterGs;
1266	}
1267
1268	/* Descriptor tables and the task segment. */
1269	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1270	{
1271	if (fWhat & CPUMCTX_EXTRN_LDTR)
1272	pInput->Names[iReg++] = HvX64RegisterLdtr;
1273	if (fWhat & CPUMCTX_EXTRN_TR)
1274	pInput->Names[iReg++] = HvX64RegisterTr;
1275	if (fWhat & CPUMCTX_EXTRN_IDTR)
1276	pInput->Names[iReg++] = HvX64RegisterIdtr;
1277	if (fWhat & CPUMCTX_EXTRN_GDTR)
1278	pInput->Names[iReg++] = HvX64RegisterGdtr;
1279	}
1280
1281	/* Control registers. */
1282	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1283	{
1284	if (fWhat & CPUMCTX_EXTRN_CR0)
1285	pInput->Names[iReg++] = HvX64RegisterCr0;
1286	if (fWhat & CPUMCTX_EXTRN_CR2)
1287	pInput->Names[iReg++] = HvX64RegisterCr2;
1288	if (fWhat & CPUMCTX_EXTRN_CR3)
1289	pInput->Names[iReg++] = HvX64RegisterCr3;
1290	if (fWhat & CPUMCTX_EXTRN_CR4)
1291	pInput->Names[iReg++] = HvX64RegisterCr4;
1292	}
1293	pInput->Names[iReg++] = HvX64RegisterCr8; /// @todo CR8/TPR
1294
1295	/* Debug registers. */
1296	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1297	{
1298	pInput->Names[iReg++] = HvX64RegisterDr0;
1299	pInput->Names[iReg++] = HvX64RegisterDr1;
1300	pInput->Names[iReg++] = HvX64RegisterDr2;
1301	pInput->Names[iReg++] = HvX64RegisterDr3;
1302	}
1303	if (fWhat & CPUMCTX_EXTRN_DR6)
1304	pInput->Names[iReg++] = HvX64RegisterDr6;
1305	if (fWhat & CPUMCTX_EXTRN_DR7)
1306	pInput->Names[iReg++] = HvX64RegisterDr7;
1307
1308	/* Floating point state. */
1309	if (fWhat & CPUMCTX_EXTRN_X87)
1310	{
1311	pInput->Names[iReg++] = HvX64RegisterFpMmx0;
1312	pInput->Names[iReg++] = HvX64RegisterFpMmx1;
1313	pInput->Names[iReg++] = HvX64RegisterFpMmx2;
1314	pInput->Names[iReg++] = HvX64RegisterFpMmx3;
1315	pInput->Names[iReg++] = HvX64RegisterFpMmx4;
1316	pInput->Names[iReg++] = HvX64RegisterFpMmx5;
1317	pInput->Names[iReg++] = HvX64RegisterFpMmx6;
1318	pInput->Names[iReg++] = HvX64RegisterFpMmx7;
1319	pInput->Names[iReg++] = HvX64RegisterFpControlStatus;
1320	}
1321	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX))
1322	pInput->Names[iReg++] = HvX64RegisterXmmControlStatus;
1323
1324	/* Vector state. */
1325	if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
1326	{
1327	pInput->Names[iReg++] = HvX64RegisterXmm0;
1328	pInput->Names[iReg++] = HvX64RegisterXmm1;
1329	pInput->Names[iReg++] = HvX64RegisterXmm2;
1330	pInput->Names[iReg++] = HvX64RegisterXmm3;
1331	pInput->Names[iReg++] = HvX64RegisterXmm4;
1332	pInput->Names[iReg++] = HvX64RegisterXmm5;
1333	pInput->Names[iReg++] = HvX64RegisterXmm6;
1334	pInput->Names[iReg++] = HvX64RegisterXmm7;
1335	pInput->Names[iReg++] = HvX64RegisterXmm8;
1336	pInput->Names[iReg++] = HvX64RegisterXmm9;
1337	pInput->Names[iReg++] = HvX64RegisterXmm10;
1338	pInput->Names[iReg++] = HvX64RegisterXmm11;
1339	pInput->Names[iReg++] = HvX64RegisterXmm12;
1340	pInput->Names[iReg++] = HvX64RegisterXmm13;
1341	pInput->Names[iReg++] = HvX64RegisterXmm14;
1342	pInput->Names[iReg++] = HvX64RegisterXmm15;
1343	}
1344
1345	/* MSRs */
1346	// HvX64RegisterTsc - don't touch
1347	if (fWhat & CPUMCTX_EXTRN_EFER)
1348	pInput->Names[iReg++] = HvX64RegisterEfer;
1349	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1350	pInput->Names[iReg++] = HvX64RegisterKernelGsBase;
1351	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1352	{
1353	pInput->Names[iReg++] = HvX64RegisterSysenterCs;
1354	pInput->Names[iReg++] = HvX64RegisterSysenterEip;
1355	pInput->Names[iReg++] = HvX64RegisterSysenterEsp;
1356	}
1357	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1358	{
1359	pInput->Names[iReg++] = HvX64RegisterStar;
1360	pInput->Names[iReg++] = HvX64RegisterLstar;
1361	pInput->Names[iReg++] = HvX64RegisterCstar;
1362	pInput->Names[iReg++] = HvX64RegisterSfmask;
1363	}
1364
1365	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1366	{
1367	pInput->Names[iReg++] = HvX64RegisterApicBase; /// @todo APIC BASE
1368	pInput->Names[iReg++] = HvX64RegisterPat;
1369	}
1370
1371	/* Interruptibility. */
1372	if (fWhat & (CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI))
1373	{
1374	pInput->Names[iReg++] = HvRegisterInterruptState;
1375	pInput->Names[iReg++] = HvX64RegisterRip;
1376	}
1377
1378	/* event injection */
1379	pInput->Names[iReg++] = HvRegisterPendingInterruption;
1380	pInput->Names[iReg++] = HvRegisterPendingEvent0;
1381	pInput->Names[iReg++] = HvRegisterPendingEvent1;
1382	size_t const cRegs = iReg;
1383	size_t const cbInput = RT_ALIGN_Z(RT_OFFSETOF(HV_INPUT_GET_VP_REGISTERS, Names[cRegs]), 32);
1384
1385	HV_REGISTER_VALUE paValues = (HV_REGISTER_VALUE )((uint8_t *)pInput + cbInput);
1386	Assert((uintptr_t)&paValues[cRegs] - (uintptr_t)pGVCpu->nem.s.HypercallData.pbPage < PAGE_SIZE); /* (max is around 168 registers) */
1387	RT_BZERO(paValues, cRegs * sizeof(paValues[0]));
1388
1389	/*
1390	* Make the hypercall.
1391	*/
1392	uint64_t uResult = g_pfnHvlInvokeHypercall(HV_MAKE_CALL_INFO(HvCallGetVpRegisters, cRegs),
1393	pGVCpu->nem.s.HypercallData.HCPhysPage,
1394	pGVCpu->nem.s.HypercallData.HCPhysPage + cbInput);
1395	AssertLogRelMsgReturn(uResult == HV_MAKE_CALL_REP_RET(cRegs),
1396	("uResult=%RX64 cRegs=%#x\n", uResult, cRegs),
1397	VERR_NEM_GET_REGISTERS_FAILED);
1398	//LogFlow(("nemR0WinImportState: uResult=%#RX64 iReg=%zu fWhat=%#018RX64 fExtr=%#018RX64\n", uResult, cRegs, fWhat, pCtx->fExtrn));
1399
1400	/*
1401	* Copy information to the CPUM context.
1402	*/
1403	PVMCPU pVCpu = &pGVM->pVM->aCpus[pGVCpu->idCpu];
1404	iReg = 0;
1405
1406	/* GPRs */
1407	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
1408	{
1409	if (fWhat & CPUMCTX_EXTRN_RAX)
1410	{
1411	Assert(pInput->Names[iReg] == HvX64RegisterRax);
1412	pCtx->rax = paValues[iReg++].Reg64;
1413	}
1414	if (fWhat & CPUMCTX_EXTRN_RCX)
1415	{
1416	Assert(pInput->Names[iReg] == HvX64RegisterRcx);
1417	pCtx->rcx = paValues[iReg++].Reg64;
1418	}
1419	if (fWhat & CPUMCTX_EXTRN_RDX)
1420	{
1421	Assert(pInput->Names[iReg] == HvX64RegisterRdx);
1422	pCtx->rdx = paValues[iReg++].Reg64;
1423	}
1424	if (fWhat & CPUMCTX_EXTRN_RBX)
1425	{
1426	Assert(pInput->Names[iReg] == HvX64RegisterRbx);
1427	pCtx->rbx = paValues[iReg++].Reg64;
1428	}
1429	if (fWhat & CPUMCTX_EXTRN_RSP)
1430	{
1431	Assert(pInput->Names[iReg] == HvX64RegisterRsp);
1432	pCtx->rsp = paValues[iReg++].Reg64;
1433	}
1434	if (fWhat & CPUMCTX_EXTRN_RBP)
1435	{
1436	Assert(pInput->Names[iReg] == HvX64RegisterRbp);
1437	pCtx->rbp = paValues[iReg++].Reg64;
1438	}
1439	if (fWhat & CPUMCTX_EXTRN_RSI)
1440	{
1441	Assert(pInput->Names[iReg] == HvX64RegisterRsi);
1442	pCtx->rsi = paValues[iReg++].Reg64;
1443	}
1444	if (fWhat & CPUMCTX_EXTRN_RDI)
1445	{
1446	Assert(pInput->Names[iReg] == HvX64RegisterRdi);
1447	pCtx->rdi = paValues[iReg++].Reg64;
1448	}
1449	if (fWhat & CPUMCTX_EXTRN_R8_R15)
1450	{
1451	Assert(pInput->Names[iReg] == HvX64RegisterR8);
1452	Assert(pInput->Names[iReg + 7] == HvX64RegisterR15);
1453	pCtx->r8 = paValues[iReg++].Reg64;
1454	pCtx->r9 = paValues[iReg++].Reg64;
1455	pCtx->r10 = paValues[iReg++].Reg64;
1456	pCtx->r11 = paValues[iReg++].Reg64;
1457	pCtx->r12 = paValues[iReg++].Reg64;
1458	pCtx->r13 = paValues[iReg++].Reg64;
1459	pCtx->r14 = paValues[iReg++].Reg64;
1460	pCtx->r15 = paValues[iReg++].Reg64;
1461	}
1462	}
1463
1464	/* RIP & Flags */
1465	if (fWhat & CPUMCTX_EXTRN_RIP)
1466	{
1467	Assert(pInput->Names[iReg] == HvX64RegisterRip);
1468	pCtx->rip = paValues[iReg++].Reg64;
1469	}
1470	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1471	{
1472	Assert(pInput->Names[iReg] == HvX64RegisterRflags);
1473	pCtx->rflags.u = paValues[iReg++].Reg64;
1474	}
1475
1476	/* Segments */
1477	#define COPY_BACK_SEG(a_idx, a_enmName, a_SReg) \
1478	do { \
1479	Assert(pInput->Names[a_idx] == a_enmName); \
1480	(a_SReg).u64Base = paValues[a_idx].Segment.Base; \
1481	(a_SReg).u32Limit = paValues[a_idx].Segment.Limit; \
1482	(a_SReg).ValidSel = (a_SReg).Sel = paValues[a_idx].Segment.Selector; \
1483	(a_SReg).Attr.u = paValues[a_idx].Segment.Attributes; \
1484	(a_SReg).fFlags = CPUMSELREG_FLAGS_VALID; \
1485	} while (0)
1486	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1487	{
1488	if (fWhat & CPUMCTX_EXTRN_CS)
1489	{
1490	COPY_BACK_SEG(iReg, HvX64RegisterCs, pCtx->cs);
1491	iReg++;
1492	}
1493	if (fWhat & CPUMCTX_EXTRN_ES)
1494	{
1495	COPY_BACK_SEG(iReg, HvX64RegisterEs, pCtx->es);
1496	iReg++;
1497	}
1498	if (fWhat & CPUMCTX_EXTRN_SS)
1499	{
1500	COPY_BACK_SEG(iReg, HvX64RegisterSs, pCtx->ss);
1501	iReg++;
1502	}
1503	if (fWhat & CPUMCTX_EXTRN_DS)
1504	{
1505	COPY_BACK_SEG(iReg, HvX64RegisterDs, pCtx->ds);
1506	iReg++;
1507	}
1508	if (fWhat & CPUMCTX_EXTRN_FS)
1509	{
1510	COPY_BACK_SEG(iReg, HvX64RegisterFs, pCtx->fs);
1511	iReg++;
1512	}
1513	if (fWhat & CPUMCTX_EXTRN_GS)
1514	{
1515	COPY_BACK_SEG(iReg, HvX64RegisterGs, pCtx->gs);
1516	iReg++;
1517	}
1518	}
1519	/* Descriptor tables and the task segment. */
1520	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1521	{
1522	if (fWhat & CPUMCTX_EXTRN_LDTR)
1523	{
1524	COPY_BACK_SEG(iReg, HvX64RegisterLdtr, pCtx->ldtr);
1525	iReg++;
1526	}
1527	if (fWhat & CPUMCTX_EXTRN_TR)
1528	{
1529	/* AMD-V likes loading TR with in AVAIL state, whereas intel insists on BUSY. So,
1530	avoid to trigger sanity assertions around the code, always fix this. */
1531	COPY_BACK_SEG(iReg, HvX64RegisterTr, pCtx->tr);
1532	switch (pCtx->tr.Attr.n.u4Type)
1533	{
1534	case X86_SEL_TYPE_SYS_386_TSS_BUSY:
1535	case X86_SEL_TYPE_SYS_286_TSS_BUSY:
1536	break;
1537	case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
1538	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1539	break;
1540	case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
1541	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
1542	break;
1543	}
1544	iReg++;
1545	}
1546	if (fWhat & CPUMCTX_EXTRN_IDTR)
1547	{
1548	Assert(pInput->Names[iReg] == HvX64RegisterIdtr);
1549	pCtx->idtr.cbIdt = paValues[iReg].Table.Limit;
1550	pCtx->idtr.pIdt = paValues[iReg].Table.Base;
1551	iReg++;
1552	}
1553	if (fWhat & CPUMCTX_EXTRN_GDTR)
1554	{
1555	Assert(pInput->Names[iReg] == HvX64RegisterGdtr);
1556	pCtx->gdtr.cbGdt = paValues[iReg].Table.Limit;
1557	pCtx->gdtr.pGdt = paValues[iReg].Table.Base;
1558	iReg++;
1559	}
1560	}
1561
1562	/* Control registers. */
1563	bool fMaybeChangedMode = false;
1564	bool fFlushTlb = false;
1565	bool fFlushGlobalTlb = false;
1566	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1567	{
1568	if (fWhat & CPUMCTX_EXTRN_CR0)
1569	{
1570	Assert(pInput->Names[iReg] == HvX64RegisterCr0);
1571	if (pCtx->cr0 != paValues[iReg].Reg64)
1572	{
1573	CPUMSetGuestCR0(pVCpu, paValues[iReg].Reg64);
1574	fMaybeChangedMode = true;
1575	fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
1576	}
1577	iReg++;
1578	}
1579	if (fWhat & CPUMCTX_EXTRN_CR2)
1580	{
1581	Assert(pInput->Names[iReg] == HvX64RegisterCr2);
1582	pCtx->cr2 = paValues[iReg].Reg64;
1583	iReg++;
1584	}
1585	if (fWhat & CPUMCTX_EXTRN_CR3)
1586	{
1587	Assert(pInput->Names[iReg] == HvX64RegisterCr3);
1588	if (pCtx->cr3 != paValues[iReg].Reg64)
1589	{
1590	CPUMSetGuestCR3(pVCpu, paValues[iReg].Reg64);
1591	fFlushTlb = true;
1592	}
1593	iReg++;
1594	}
1595	if (fWhat & CPUMCTX_EXTRN_CR4)
1596	{
1597	Assert(pInput->Names[iReg] == HvX64RegisterCr4);
1598	if (pCtx->cr4 != paValues[iReg].Reg64)
1599	{
1600	CPUMSetGuestCR4(pVCpu, paValues[iReg].Reg64);
1601	fMaybeChangedMode = true;
1602	fFlushTlb = fFlushGlobalTlb = true; /// @todo fix this
1603	}
1604	iReg++;
1605	}
1606	}
1607
1608	/// @todo CR8/TPR
1609	Assert(pInput->Names[iReg] == HvX64RegisterCr8);
1610	APICSetTpr(pVCpu, (uint8_t)paValues[iReg].Reg64 << 4);
1611	iReg++;
1612
1613	/* Debug registers. */
1614	/** @todo fixme */
1615	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1616	{
1617	Assert(pInput->Names[iReg] == HvX64RegisterDr0);
1618	Assert(pInput->Names[iReg+3] == HvX64RegisterDr3);
1619	if (pCtx->dr[0] != paValues[iReg].Reg64)
1620	CPUMSetGuestDR0(pVCpu, paValues[iReg].Reg64);
1621	iReg++;
1622	if (pCtx->dr[1] != paValues[iReg].Reg64)
1623	CPUMSetGuestDR1(pVCpu, paValues[iReg].Reg64);
1624	iReg++;
1625	if (pCtx->dr[2] != paValues[iReg].Reg64)
1626	CPUMSetGuestDR2(pVCpu, paValues[iReg].Reg64);
1627	iReg++;
1628	if (pCtx->dr[3] != paValues[iReg].Reg64)
1629	CPUMSetGuestDR3(pVCpu, paValues[iReg].Reg64);
1630	iReg++;
1631	}
1632	if (fWhat & CPUMCTX_EXTRN_DR6)
1633	{
1634	Assert(pInput->Names[iReg] == HvX64RegisterDr6);
1635	if (pCtx->dr[6] != paValues[iReg].Reg64)
1636	CPUMSetGuestDR6(pVCpu, paValues[iReg].Reg64);
1637	iReg++;
1638	}
1639	if (fWhat & CPUMCTX_EXTRN_DR7)
1640	{
1641	Assert(pInput->Names[iReg] == HvX64RegisterDr7);
1642	if (pCtx->dr[7] != paValues[iReg].Reg64)
1643	CPUMSetGuestDR6(pVCpu, paValues[iReg].Reg64);
1644	iReg++;
1645	}
1646
1647	/* Floating point state. */
1648	if (fWhat & CPUMCTX_EXTRN_X87)
1649	{
1650	Assert(pInput->Names[iReg] == HvX64RegisterFpMmx0);
1651	Assert(pInput->Names[iReg + 7] == HvX64RegisterFpMmx7);
1652	pCtx->pXStateR0->x87.aRegs[0].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1653	pCtx->pXStateR0->x87.aRegs[0].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1654	iReg++;
1655	pCtx->pXStateR0->x87.aRegs[1].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1656	pCtx->pXStateR0->x87.aRegs[1].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1657	iReg++;
1658	pCtx->pXStateR0->x87.aRegs[2].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1659	pCtx->pXStateR0->x87.aRegs[2].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1660	iReg++;
1661	pCtx->pXStateR0->x87.aRegs[3].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1662	pCtx->pXStateR0->x87.aRegs[3].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1663	iReg++;
1664	pCtx->pXStateR0->x87.aRegs[4].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1665	pCtx->pXStateR0->x87.aRegs[4].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1666	iReg++;
1667	pCtx->pXStateR0->x87.aRegs[5].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1668	pCtx->pXStateR0->x87.aRegs[5].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1669	iReg++;
1670	pCtx->pXStateR0->x87.aRegs[6].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1671	pCtx->pXStateR0->x87.aRegs[6].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1672	iReg++;
1673	pCtx->pXStateR0->x87.aRegs[7].au64[0] = paValues[iReg].Fp.AsUINT128.Low64;
1674	pCtx->pXStateR0->x87.aRegs[7].au64[1] = paValues[iReg].Fp.AsUINT128.High64;
1675	iReg++;
1676
1677	Assert(pInput->Names[iReg] == HvX64RegisterFpControlStatus);
1678	pCtx->pXStateR0->x87.FCW = paValues[iReg].FpControlStatus.FpControl;
1679	pCtx->pXStateR0->x87.FSW = paValues[iReg].FpControlStatus.FpStatus;
1680	pCtx->pXStateR0->x87.FTW = paValues[iReg].FpControlStatus.FpTag
1681	/\| (paValues[iReg].FpControlStatus.Reserved << 8)/;
1682	pCtx->pXStateR0->x87.FOP = paValues[iReg].FpControlStatus.LastFpOp;
1683	pCtx->pXStateR0->x87.FPUIP = (uint32_t)paValues[iReg].FpControlStatus.LastFpRip;
1684	pCtx->pXStateR0->x87.CS = (uint16_t)(paValues[iReg].FpControlStatus.LastFpRip >> 32);
1685	pCtx->pXStateR0->x87.Rsrvd1 = (uint16_t)(paValues[iReg].FpControlStatus.LastFpRip >> 48);
1686	iReg++;
1687	}
1688
1689	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX))
1690	{
1691	Assert(pInput->Names[iReg] == HvX64RegisterXmmControlStatus);
1692	if (fWhat & CPUMCTX_EXTRN_X87)
1693	{
1694	pCtx->pXStateR0->x87.FPUDP = (uint32_t)paValues[iReg].XmmControlStatus.LastFpRdp;
1695	pCtx->pXStateR0->x87.DS = (uint16_t)(paValues[iReg].XmmControlStatus.LastFpRdp >> 32);
1696	pCtx->pXStateR0->x87.Rsrvd2 = (uint16_t)(paValues[iReg].XmmControlStatus.LastFpRdp >> 48);
1697	}
1698	pCtx->pXStateR0->x87.MXCSR = paValues[iReg].XmmControlStatus.XmmStatusControl;
1699	pCtx->pXStateR0->x87.MXCSR_MASK = paValues[iReg].XmmControlStatus.XmmStatusControlMask; /** @todo ??? (Isn't this an output field?) */
1700	iReg++;
1701	}
1702
1703	/* Vector state. */
1704	if (fWhat & CPUMCTX_EXTRN_SSE_AVX)
1705	{
1706	Assert(pInput->Names[iReg] == HvX64RegisterXmm0);
1707	Assert(pInput->Names[iReg+15] == HvX64RegisterXmm15);
1708	pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1709	pCtx->pXStateR0->x87.aXMM[0].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1710	iReg++;
1711	pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1712	pCtx->pXStateR0->x87.aXMM[1].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1713	iReg++;
1714	pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1715	pCtx->pXStateR0->x87.aXMM[2].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1716	iReg++;
1717	pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1718	pCtx->pXStateR0->x87.aXMM[3].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1719	iReg++;
1720	pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1721	pCtx->pXStateR0->x87.aXMM[4].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1722	iReg++;
1723	pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1724	pCtx->pXStateR0->x87.aXMM[5].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1725	iReg++;
1726	pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1727	pCtx->pXStateR0->x87.aXMM[6].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1728	iReg++;
1729	pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1730	pCtx->pXStateR0->x87.aXMM[7].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1731	iReg++;
1732	pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1733	pCtx->pXStateR0->x87.aXMM[8].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1734	iReg++;
1735	pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1736	pCtx->pXStateR0->x87.aXMM[9].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1737	iReg++;
1738	pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1739	pCtx->pXStateR0->x87.aXMM[10].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1740	iReg++;
1741	pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1742	pCtx->pXStateR0->x87.aXMM[11].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1743	iReg++;
1744	pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1745	pCtx->pXStateR0->x87.aXMM[12].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1746	iReg++;
1747	pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1748	pCtx->pXStateR0->x87.aXMM[13].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1749	iReg++;
1750	pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1751	pCtx->pXStateR0->x87.aXMM[14].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1752	iReg++;
1753	pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Lo = paValues[iReg].Reg128.Low64;
1754	pCtx->pXStateR0->x87.aXMM[15].uXmm.s.Hi = paValues[iReg].Reg128.High64;
1755	iReg++;
1756	}
1757
1758
1759	/* MSRs */
1760	// HvX64RegisterTsc - don't touch
1761	if (fWhat & CPUMCTX_EXTRN_EFER)
1762	{
1763	Assert(pInput->Names[iReg] == HvX64RegisterEfer);
1764	if (paValues[iReg].Reg64 != pCtx->msrEFER)
1765	{
1766	pCtx->msrEFER = paValues[iReg].Reg64;
1767	fMaybeChangedMode = true;
1768	}
1769	iReg++;
1770	}
1771	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1772	{
1773	Assert(pInput->Names[iReg] == HvX64RegisterKernelGsBase);
1774	pCtx->msrKERNELGSBASE = paValues[iReg].Reg64;
1775	iReg++;
1776	}
1777	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1778	{
1779	Assert(pInput->Names[iReg] == HvX64RegisterSysenterCs);
1780	pCtx->SysEnter.cs = paValues[iReg].Reg64;
1781	iReg++;
1782	Assert(pInput->Names[iReg] == HvX64RegisterSysenterEip);
1783	pCtx->SysEnter.eip = paValues[iReg].Reg64;
1784	iReg++;
1785	Assert(pInput->Names[iReg] == HvX64RegisterSysenterEsp);
1786	pCtx->SysEnter.esp = paValues[iReg].Reg64;
1787	iReg++;
1788	}
1789	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1790	{
1791	Assert(pInput->Names[iReg] == HvX64RegisterStar);
1792	pCtx->msrSTAR = paValues[iReg].Reg64;
1793	iReg++;
1794	Assert(pInput->Names[iReg] == HvX64RegisterLstar);
1795	pCtx->msrLSTAR = paValues[iReg].Reg64;
1796	iReg++;
1797	Assert(pInput->Names[iReg] == HvX64RegisterCstar);
1798	pCtx->msrCSTAR = paValues[iReg].Reg64;
1799	iReg++;
1800	Assert(pInput->Names[iReg] == HvX64RegisterSfmask);
1801	pCtx->msrSFMASK = paValues[iReg].Reg64;
1802	iReg++;
1803	}
1804	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1805	{
1806	Assert(pInput->Names[iReg] == HvX64RegisterApicBase);
1807	if (paValues[iReg].Reg64 != APICGetBaseMsrNoCheck(pVCpu))
1808	{
1809	VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, paValues[iReg].Reg64);
1810	Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
1811	}
1812	iReg++;
1813
1814	Assert(pInput->Names[iReg] == HvX64RegisterPat);
1815	pCtx->msrPAT = paValues[iReg].Reg64;
1816	iReg++;
1817	}
1818
1819	/* Interruptibility. */
1820	if (fWhat & (CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI))
1821	{
1822	Assert(pInput->Names[iReg] == HvRegisterInterruptState);
1823	Assert(pInput->Names[iReg + 1] == HvX64RegisterRip);
1824
1825	if (!(pCtx->fExtrn & CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT))
1826	{
1827	pVCpu->nem.s.fLastInterruptShadow = paValues[iReg].InterruptState.InterruptShadow;
1828	if (paValues[iReg].InterruptState.InterruptShadow)
1829	{
1830	EMSetInhibitInterruptsPC(pVCpu, paValues[iReg + 1].Reg64);
1831	VMCPU_FF_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1832	}
1833	else
1834	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1835	}
1836
1837	if (!(pCtx->fExtrn & CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI))
1838	{
1839	if (paValues[iReg].InterruptState.NmiMasked)
1840	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
1841	else
1842	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
1843	}
1844
1845	fWhat \|= CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT \| CPUMCTX_EXTRN_NEM_WIN_INHIBIT_NMI;
1846	iReg += 2;
1847	}
1848
1849	/* Event injection. */
1850	/// @todo HvRegisterPendingInterruption
1851	Assert(pInput->Names[iReg] == HvRegisterPendingInterruption);
1852	if (paValues[iReg].PendingInterruption.InterruptionPending)
1853	{
1854	Log7(("PendingInterruption: type=%u vector=%#x errcd=%RTbool/%#x instr-len=%u nested=%u\n",
1855	paValues[iReg].PendingInterruption.InterruptionType, paValues[iReg].PendingInterruption.InterruptionVector,
1856	paValues[iReg].PendingInterruption.DeliverErrorCode, paValues[iReg].PendingInterruption.ErrorCode,
1857	paValues[iReg].PendingInterruption.InstructionLength, paValues[iReg].PendingInterruption.NestedEvent));
1858	AssertMsg((paValues[iReg].PendingInterruption.AsUINT64 & UINT64_C(0xfc00)) == 0,
1859	("%#RX64\n", paValues[iReg].PendingInterruption.AsUINT64));
1860	}
1861
1862	/// @todo HvRegisterPendingEvent0
1863	/// @todo HvRegisterPendingEvent1
1864
1865	/* Almost done, just update extrn flags and maybe change PGM mode. */
1866	pCtx->fExtrn &= ~fWhat;
1867
1868	/* Typical. */
1869	if (!fMaybeChangedMode && !fFlushTlb)
1870	return VINF_SUCCESS;
1871
1872	/*
1873	* Slow.
1874	*/
1875	int rc = VINF_SUCCESS;
1876	if (fMaybeChangedMode)
1877	{
1878	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
1879	if (rc == VINF_PGM_CHANGE_MODE)
1880	{
1881	LogFlow(("nemR0WinImportState: -> VERR_NEM_CHANGE_PGM_MODE!\n"));
1882	return VERR_NEM_CHANGE_PGM_MODE;
1883	}
1884	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
1885	}
1886
1887	if (fFlushTlb)
1888	{
1889	LogFlow(("nemR0WinImportState: -> VERR_NEM_FLUSH_TLB!\n"));
1890	rc = VERR_NEM_FLUSH_TLB; /* Calling PGMFlushTLB w/o long jump setup doesn't work, ring-3 does it. */
1891	}
1892
1893	return rc;
1894	}
1895
1896
1897	/**
1898	* Import the state from the native API (back to CPUMCTX).
1899	*
1900	* @returns VBox status code
1901	* @param pGVM The ring-0 VM handle.
1902	* @param pVM The cross context VM handle.
1903	* @param idCpu The calling EMT. Necessary for getting the
1904	* hypercall page and arguments.
1905	* @param fWhat What to import, CPUMCTX_EXTRN_XXX. Set
1906	* CPUMCTX_EXTERN_ALL for everything.
1907	*/
1908	VMMR0_INT_DECL(int) NEMR0ImportState(PGVM pGVM, PVM pVM, VMCPUID idCpu, uint64_t fWhat)
1909	{
1910	/*
1911	* Validate the call.
1912	*/
1913	int rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
1914	if (RT_SUCCESS(rc))
1915	{
1916	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1917	PGVMCPU pGVCpu = &pGVM->aCpus[idCpu];
1918	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
1919
1920	/*
1921	* Call worker.
1922	*/
1923	rc = nemR0WinImportState(pGVM, pGVCpu, CPUMQueryGuestCtxPtr(pVCpu), fWhat);
1924	}
1925	return rc;
1926	}
1927
1928
1929	VMMR0_INT_DECL(VBOXSTRICTRC) NEMR0RunGuestCode(PGVM pGVM, VMCPUID idCpu)
1930	{
1931	#ifdef NEM_WIN_USE_OUR_OWN_RUN_API
1932	PVM pVM = pGVM->pVM;
1933	return nemHCWinRunGC(pVM, &pVM->aCpus[idCpu], pGVM, &pGVM->aCpus[idCpu]);
1934	#else
1935	RT_NOREF(pGVM, idCpu);
1936	return VERR_NOT_IMPLEMENTED;
1937	#endif
1938	}
1939
1940
1941	/**
1942	* Updates statistics in the VM structure.
1943	*
1944	* @returns VBox status code.
1945	* @param pGVM The ring-0 VM handle.
1946	* @param pVM The cross context VM handle.
1947	* @param idCpu The calling EMT, or NIL. Necessary for getting the hypercall
1948	* page and arguments.
1949	*/
1950	VMMR0_INT_DECL(int) NEMR0UpdateStatistics(PGVM pGVM, PVM pVM, VMCPUID idCpu)
1951	{
1952	/*
1953	* Validate the call.
1954	*/
1955	int rc;
1956	if (idCpu == NIL_VMCPUID)
1957	rc = GVMMR0ValidateGVMandVM(pGVM, pVM);
1958	else
1959	rc = GVMMR0ValidateGVMandVMandEMT(pGVM, pVM, idCpu);
1960	if (RT_SUCCESS(rc))
1961	{
1962	AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
1963
1964	PNEMR0HYPERCALLDATA pHypercallData = idCpu != NIL_VMCPUID
1965	? &pGVM->aCpus[idCpu].nem.s.HypercallData
1966	: &pGVM->nem.s.HypercallData;
1967	if ( RT_VALID_PTR(pHypercallData->pbPage)
1968	&& pHypercallData->HCPhysPage != NIL_RTHCPHYS)
1969	{
1970	if (idCpu == NIL_VMCPUID)
1971	rc = RTCritSectEnter(&pGVM->nem.s.HypercallDataCritSect);
1972	if (RT_SUCCESS(rc))
1973	{
1974	/*
1975	* Query the memory statistics for the partition.
1976	*/
1977	HV_INPUT_GET_MEMORY_BALANCE pInput = (HV_INPUT_GET_MEMORY_BALANCE )pHypercallData->pbPage;
1978	pInput->TargetPartitionId = pGVM->nem.s.idHvPartition;
1979	pInput->ProximityDomainInfo.Flags.ProximityPreferred = 0;
1980	pInput->ProximityDomainInfo.Flags.ProxyimityInfoValid = 0;
1981	pInput->ProximityDomainInfo.Flags.Reserved = 0;
1982	pInput->ProximityDomainInfo.Id = 0;
1983
1984	HV_OUTPUT_GET_MEMORY_BALANCE pOutput = (HV_OUTPUT_GET_MEMORY_BALANCE )(pInput + 1);
1985	RT_ZERO(*pOutput);
1986
1987	uint64_t uResult = g_pfnHvlInvokeHypercall(HvCallGetMemoryBalance,
1988	pHypercallData->HCPhysPage,
1989	pHypercallData->HCPhysPage + sizeof(*pInput));
1990	if (uResult == HV_STATUS_SUCCESS)
1991	{
1992	pVM->nem.s.R0Stats.cPagesAvailable = pOutput->PagesAvailable;
1993	pVM->nem.s.R0Stats.cPagesInUse = pOutput->PagesInUse;
1994	rc = VINF_SUCCESS;
1995	}
1996	else
1997	{
1998	LogRel(("HvCallGetMemoryBalance -> %#RX64 (%#RX64 %#RX64)!!\n",
1999	uResult, pOutput->PagesAvailable, pOutput->PagesInUse));
2000	rc = VINF_NEM_IPE_0;
2001	}
2002
2003	if (idCpu == NIL_VMCPUID)
2004	RTCritSectLeave(&pGVM->nem.s.HypercallDataCritSect);
2005	}
2006	}
2007	else
2008	rc = VERR_WRONG_ORDER;
2009	}
2010	return rc;
2011	}
2012

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source: vbox/trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp@ 72300

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